diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3508-drm-amd-display-add-eDP-1.2-polling-for-T7.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3508-drm-amd-display-add-eDP-1.2-polling-for-T7.patch | 117 |
1 files changed, 117 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3508-drm-amd-display-add-eDP-1.2-polling-for-T7.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3508-drm-amd-display-add-eDP-1.2-polling-for-T7.patch new file mode 100644 index 00000000..7a7ae7e3 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3508-drm-amd-display-add-eDP-1.2-polling-for-T7.patch @@ -0,0 +1,117 @@ +From ecdd25f858fe0f589c56e94908e361b4be70bc43 Mon Sep 17 00:00:00 2001 +From: Charlene Liu <charlene.liu@amd.com> +Date: Thu, 18 Jan 2018 19:09:06 -0500 +Subject: [PATCH 3508/4131] drm/amd/display: add eDP 1.2+ polling for T7 + +Signed-off-by: Charlene Liu <charlene.liu@amd.com> +Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> +Acked-by: Harry Wentland <harry.wentland@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 22 ++++++++++++++++++++++ + .../drm/amd/display/dc/dce/dce_stream_encoder.c | 6 +++++- + .../amd/display/dc/dce110/dce110_hw_sequencer.c | 9 +++++---- + drivers/gpu/drm/amd/display/dc/inc/link_hwss.h | 1 + + 4 files changed, 33 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +index 524f4aa..bae9b05 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +@@ -123,6 +123,28 @@ bool edp_receiver_ready_T9(struct dc_link *link) + } while (++tries < 50); + return result; + } ++bool edp_receiver_ready_T7(struct dc_link *link) ++{ ++ unsigned int tries = 0; ++ unsigned char sinkstatus = 0; ++ unsigned char edpRev = 0; ++ enum dc_status result = DC_OK; ++ ++ result = core_link_read_dpcd(link, DP_EDP_DPCD_REV, &edpRev, sizeof(edpRev)); ++ if (result == DC_OK && edpRev < DP_EDP_12) ++ return true; ++ /* start from eDP version 1.2, SINK_STAUS indicate the sink is ready.*/ ++ do { ++ sinkstatus = 0; ++ result = core_link_read_dpcd(link, DP_SINK_STATUS, &sinkstatus, sizeof(sinkstatus)); ++ if (sinkstatus == 1) ++ break; ++ if (result != DC_OK) ++ break; ++ udelay(25); //MAx T7 is 50ms ++ } while (++tries < 300); ++ return result; ++} + + void dp_disable_link_phy(struct dc_link *link, enum signal_type signal) + { +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c +index 83bae20..8146b90 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c +@@ -920,6 +920,7 @@ static void dce110_stream_encoder_dp_blank( + { + struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); + uint32_t retries = 0; ++ uint32_t reg1 = 0; + uint32_t max_retries = DP_BLANK_MAX_RETRY * 10; + + /* Note: For CZ, we are changing driver default to disable +@@ -928,7 +929,10 @@ static void dce110_stream_encoder_dp_blank( + * handful of panels that cannot handle disable stream at + * HBLANK and will result in a white line flash across the + * screen on stream disable. */ +- ++ REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, ®1); ++ if ((reg1 & 0x1) == 0) ++ /*stream not enabled*/ ++ return; + /* Specify the video stream disable point + * (2 = start of the next vertical blank) */ + REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2); +diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +index 364b88a..bc1c454 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +@@ -927,9 +927,13 @@ void hwss_edp_backlight_control( + * Enable it in the future if necessary. + */ + /* dc_service_sleep_in_milliseconds(50); */ ++ /*edp 1.2*/ ++ if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) ++ edp_receiver_ready_T7(link); + link_transmitter_control(ctx->dc_bios, &cntl); + /*edp 1.2*/ +- edp_receiver_ready_T9(link); ++ if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF) ++ edp_receiver_ready_T9(link); + } + + void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option) +@@ -976,9 +980,6 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx, int option) + */ + } + +- /* blank at encoder level */ +- if (dc_is_dp_signal(pipe_ctx->stream->signal)) +- pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc); + + link->link_enc->funcs->connect_dig_be_to_fe( + link->link_enc, +diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h +index 46bb201..30be7bb 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h +@@ -52,6 +52,7 @@ void dp_enable_link_phy( + + void dp_receiver_power_ctrl(struct dc_link *link, bool on); + bool edp_receiver_ready_T9(struct dc_link *link); ++bool edp_receiver_ready_T7(struct dc_link *link); + + void dp_disable_link_phy(struct dc_link *link, enum signal_type signal); + +-- +2.7.4 + |