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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3322-drm-amdgpu-fix-DW-estimation-on-VI.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3322-drm-amdgpu-fix-DW-estimation-on-VI.patch67
1 files changed, 67 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3322-drm-amdgpu-fix-DW-estimation-on-VI.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3322-drm-amdgpu-fix-DW-estimation-on-VI.patch
new file mode 100644
index 00000000..0d65f2f7
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3322-drm-amdgpu-fix-DW-estimation-on-VI.patch
@@ -0,0 +1,67 @@
+From ed4705627f879c1ce428a3558278b002c1543704 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Tue, 30 Jan 2018 16:02:38 +0100
+Subject: [PATCH 3322/4131] drm/amdgpu: fix DW estimation on VI
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Forgot to update that during recent changes.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+
+Conflicts:
+ drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+
+Change-Id: Ie67b373ed6def5379d9906f77497cafabc3316aa
+---
+ drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 2 +-
+ drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 4 +++-
+ 2 files changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+index 3c2195c..7278003 100644
+--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+@@ -1636,7 +1636,7 @@ static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
+ 6 + /* sdma_v3_0_ring_emit_hdp_flush */
+ 3 + /* sdma_v3_0_ring_emit_hdp_invalidate */
+ 6 + /* sdma_v3_0_ring_emit_pipeline_sync */
+- 12 + /* sdma_v3_0_ring_emit_vm_flush */
++ VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v3_0_ring_emit_vm_flush */
+ 10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */
+ .emit_ib_size = 7 + 6, /* sdma_v3_0_ring_emit_ib */
+ .emit_ib = sdma_v3_0_ring_emit_ib,
+diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+index 84c558d..4213734 100644
+--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+@@ -1558,6 +1558,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
+ .emit_frame_size =
+ 2 + /* uvd_v6_0_ring_emit_hdp_flush */
+ 2 + /* uvd_v6_0_ring_emit_hdp_invalidate */
++ 6 + 6 + /* hdp flush / invalidate */
+ 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
+ 14, /* uvd_v6_0_ring_emit_fence x1 no user fence */
+ .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
+@@ -1571,6 +1572,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = {
+ .pad_ib = amdgpu_ring_generic_pad_ib,
+ .begin_use = amdgpu_uvd_ring_begin_use,
+ .end_use = amdgpu_uvd_ring_end_use,
++ .emit_wreg = uvd_v6_0_ring_emit_wreg,
+ };
+
+ static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
+@@ -1585,7 +1587,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = {
+ 2 + /* uvd_v6_0_ring_emit_hdp_flush */
+ 2 + /* uvd_v6_0_ring_emit_hdp_invalidate */
+ 10 + /* uvd_v6_0_ring_emit_pipeline_sync */
+- 20 + /* uvd_v6_0_ring_emit_vm_flush */
++ VI_FLUSH_GPU_TLB_NUM_WREG * 6 + 8 + /* uvd_v6_0_ring_emit_vm_flush */
+ 14 + 14, /* uvd_v6_0_ring_emit_fence x2 vm fence */
+ .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */
+ .emit_ib = uvd_v6_0_ring_emit_ib,
+--
+2.7.4
+