diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3321-drm-amd-pp-Fix-sysfs-pp_dpm_pcie-bug-on-CI-VI.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3321-drm-amd-pp-Fix-sysfs-pp_dpm_pcie-bug-on-CI-VI.patch | 95 |
1 files changed, 95 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3321-drm-amd-pp-Fix-sysfs-pp_dpm_pcie-bug-on-CI-VI.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3321-drm-amd-pp-Fix-sysfs-pp_dpm_pcie-bug-on-CI-VI.patch new file mode 100644 index 00000000..0339cc4b --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3321-drm-amd-pp-Fix-sysfs-pp_dpm_pcie-bug-on-CI-VI.patch @@ -0,0 +1,95 @@ +From 01cc19bd59074a31a0cbec2a0022c0a3f62e6d85 Mon Sep 17 00:00:00 2001 +From: Rex Zhu <Rex.Zhu@amd.com> +Date: Thu, 25 Jan 2018 18:42:08 +0800 +Subject: [PATCH 3321/4131] drm/amd/pp: Fix sysfs pp_dpm_pcie bug on CI/VI + +when echo "01">pp_dpm_pcie +the pcie dpm will fix in highest link speed. +But user should expect auto speed between +level 0 and level1 + +Change-Id: I9d6650b1600a809b9b4977cba19c368dd5dc06f3 +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 17 ++++++++++------- + drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 17 ++++++++++------- + 2 files changed, 20 insertions(+), 14 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c +index 5f61e70..f82f40f 100644 +--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c ++++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c +@@ -6642,6 +6642,9 @@ static int ci_dpm_force_clock_level(void *handle, + if (adev->pm.dpm.forced_level != AMD_DPM_FORCED_LEVEL_MANUAL) + return -EINVAL; + ++ if (mask == 0) ++ return -EINVAL; ++ + switch (type) { + case PP_SCLK: + if (!pi->sclk_dpm_key_disabled) +@@ -6660,15 +6663,15 @@ static int ci_dpm_force_clock_level(void *handle, + case PP_PCIE: + { + uint32_t tmp = mask & pi->dpm_level_enable_mask.pcie_dpm_enable_mask; +- uint32_t level = 0; + +- while (tmp >>= 1) +- level++; +- +- if (!pi->pcie_dpm_key_disabled) +- amdgpu_ci_send_msg_to_smc_with_parameter(adev, ++ if (!pi->pcie_dpm_key_disabled) { ++ if (fls(tmp) != ffs(tmp)) ++ amdgpu_ci_send_msg_to_smc(adev, PPSMC_MSG_PCIeDPM_UnForceLevel); ++ else ++ amdgpu_ci_send_msg_to_smc_with_parameter(adev, + PPSMC_MSG_PCIeDPM_ForceLevel, +- level); ++ fls(tmp) - 1); ++ } + break; + } + default: +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +index e446cf0..dffa670 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +@@ -4299,6 +4299,9 @@ static int smu7_force_clock_level(struct pp_hwmgr *hwmgr, + { + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); + ++ if (mask == 0) ++ return -EINVAL; ++ + switch (type) { + case PP_SCLK: + if (!data->sclk_dpm_key_disabled) +@@ -4315,15 +4318,15 @@ static int smu7_force_clock_level(struct pp_hwmgr *hwmgr, + case PP_PCIE: + { + uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask; +- uint32_t level = 0; + +- while (tmp >>= 1) +- level++; +- +- if (!data->pcie_dpm_key_disabled) +- smum_send_msg_to_smc_with_parameter(hwmgr, ++ if (!data->pcie_dpm_key_disabled) { ++ if (fls(tmp) != ffs(tmp)) ++ smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PCIeDPM_UnForceLevel); ++ else ++ smum_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_PCIeDPM_ForceLevel, +- level); ++ fls(tmp) - 1); ++ } + break; + } + default: +-- +2.7.4 + |