diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3316-Revert-drm-amdgpu-remove-now-superflous-_hdp-operati.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3316-Revert-drm-amdgpu-remove-now-superflous-_hdp-operati.patch | 808 |
1 files changed, 808 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3316-Revert-drm-amdgpu-remove-now-superflous-_hdp-operati.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3316-Revert-drm-amdgpu-remove-now-superflous-_hdp-operati.patch new file mode 100644 index 00000000..9e698cb0 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3316-Revert-drm-amdgpu-remove-now-superflous-_hdp-operati.patch @@ -0,0 +1,808 @@ +From d26a7965dbf9d601958f9e9cc2b98c3256b98b3b Mon Sep 17 00:00:00 2001 +From: Jim Qu <Jim.Qu@amd.com> +Date: Thu, 1 Feb 2018 15:08:01 +0800 +Subject: [PATCH 3316/4131] Revert "drm/amdgpu: remove now superflous *_hdp + operation" + +This reverts commit cccee96b9e3ab89fec51fcc1bce769989dde1f74. +--- + drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + + drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 7 +++++- + drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 + + drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 10 +++++++- + drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 39 ++++++++++++++++++++++++++++++-- + drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 26 +++++++++++++++++++-- + drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 19 ++++++++++++++-- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 14 ++++++++++-- + drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 10 +++++++- + drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 11 ++++++++- + drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 13 ++++++++++- + drivers/gpu/drm/amd/amdgpu/si_dma.c | 19 +++++++++++++++- + drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 30 ++++++++++++++++++++++++ + drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 30 ++++++++++++++++++++++++ + drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 35 +++++++++++++++++++++++++++- + drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 37 ++++++++++++++++++++++++++++-- + drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 18 ++++++++++++++- + 17 files changed, 302 insertions(+), 18 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +index 81e6aa2..4a00efb 100755 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +@@ -1851,6 +1851,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) + #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) + #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) + #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) ++#define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r)) + #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r)) + #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d)) + #define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d)) +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +index 5d79b43..1b2b7c1 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +@@ -233,7 +233,12 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, + #ifdef CONFIG_X86_64 + if (!(adev->flags & AMD_IS_APU)) + #endif +- amdgpu_asic_invalidate_hdp(adev, ring); ++ { ++ if (ring->funcs->emit_hdp_invalidate) ++ amdgpu_ring_emit_hdp_invalidate(ring); ++ else ++ amdgpu_asic_invalidate_hdp(adev, ring); ++ } + + r = amdgpu_fence_emit(ring, f); + if (r) { +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +index 115d523..668a1ed 100755 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +@@ -129,6 +129,7 @@ struct amdgpu_ring_funcs { + void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid, + unsigned pasid, uint64_t pd_addr); + void (*emit_hdp_flush)(struct amdgpu_ring *ring); ++ void (*emit_hdp_invalidate)(struct amdgpu_ring *ring); + void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, + uint32_t gds_base, uint32_t gds_size, + uint32_t gws_base, uint32_t gws_size, +diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +index d6a6871..6766f8c 100644 +--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c ++++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +@@ -261,6 +261,13 @@ static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring) + amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ + } + ++static void cik_sdma_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) ++{ ++ amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); ++ amdgpu_ring_write(ring, mmHDP_DEBUG0); ++ amdgpu_ring_write(ring, 1); ++} ++ + /** + * cik_sdma_ring_emit_fence - emit a fence on the DMA ring + * +@@ -1270,7 +1277,7 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { + .set_wptr = cik_sdma_ring_set_wptr, + .emit_frame_size = + 6 + /* cik_sdma_ring_emit_hdp_flush */ +- 3 + /* hdp invalidate */ ++ 3 + /* cik_sdma_ring_emit_hdp_invalidate */ + 6 + /* cik_sdma_ring_emit_pipeline_sync */ + CIK_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* cik_sdma_ring_emit_vm_flush */ + 9 + 9 + 9, /* cik_sdma_ring_emit_fence x3 for user fence, vm fence */ +@@ -1280,6 +1287,7 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { + .emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync, + .emit_vm_flush = cik_sdma_ring_emit_vm_flush, + .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush, ++ .emit_hdp_invalidate = cik_sdma_ring_emit_hdp_invalidate, + .test_ring = cik_sdma_ring_test_ring, + .test_ib = cik_sdma_ring_test_ib, + .insert_nop = cik_sdma_ring_insert_nop, +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +index 3517fd9..e6c3a24 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +@@ -1809,6 +1809,17 @@ static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring) + return r; + } + ++static void gfx_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) ++{ ++ /* flush hdp cache */ ++ amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); ++ amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | ++ WRITE_DATA_DST_SEL(0))); ++ amdgpu_ring_write(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL); ++ amdgpu_ring_write(ring, 0); ++ amdgpu_ring_write(ring, 0x1); ++} ++ + static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) + { + amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); +@@ -1816,6 +1827,24 @@ static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) + EVENT_INDEX(0)); + } + ++/** ++ * gfx_v6_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp ++ * ++ * @adev: amdgpu_device pointer ++ * @ridx: amdgpu ring index ++ * ++ * Emits an hdp invalidate on the cp. ++ */ ++static void gfx_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) ++{ ++ amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); ++ amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | ++ WRITE_DATA_DST_SEL(0))); ++ amdgpu_ring_write(ring, mmHDP_DEBUG0); ++ amdgpu_ring_write(ring, 0); ++ amdgpu_ring_write(ring, 0x1); ++} ++ + static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, + u64 seq, unsigned flags) + { +@@ -3478,7 +3507,8 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { + .get_wptr = gfx_v6_0_ring_get_wptr, + .set_wptr = gfx_v6_0_ring_set_wptr_gfx, + .emit_frame_size = +- 5 + 5 + /* hdp flush / invalidate */ ++ 5 + /* gfx_v6_0_ring_emit_hdp_flush */ ++ 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */ + 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ + 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */ + SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v6_0_ring_emit_vm_flush */ +@@ -3488,6 +3518,8 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { + .emit_fence = gfx_v6_0_ring_emit_fence, + .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, + .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush, ++ .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush, ++ .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate, + .test_ring = gfx_v6_0_ring_test_ring, + .test_ib = gfx_v6_0_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, +@@ -3503,7 +3535,8 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = { + .get_wptr = gfx_v6_0_ring_get_wptr, + .set_wptr = gfx_v6_0_ring_set_wptr_compute, + .emit_frame_size = +- 5 + 5 + /* hdp flush / invalidate */ ++ 5 + /* gfx_v6_0_ring_emit_hdp_flush */ ++ 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */ + 7 + /* gfx_v6_0_ring_emit_pipeline_sync */ + SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v6_0_ring_emit_vm_flush */ + 14 + 14 + 14, /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ +@@ -3512,6 +3545,8 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = { + .emit_fence = gfx_v6_0_ring_emit_fence, + .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, + .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush, ++ .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush, ++ .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate, + .test_ring = gfx_v6_0_ring_test_ring, + .test_ib = gfx_v6_0_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +index ff71f7c..aeeced9 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +@@ -2147,6 +2147,26 @@ static void gfx_v7_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) + EVENT_INDEX(0)); + } + ++ ++/** ++ * gfx_v7_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp ++ * ++ * @adev: amdgpu_device pointer ++ * @ridx: amdgpu ring index ++ * ++ * Emits an hdp invalidate on the cp. ++ */ ++static void gfx_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) ++{ ++ amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); ++ amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | ++ WRITE_DATA_DST_SEL(0) | ++ WR_CONFIRM)); ++ amdgpu_ring_write(ring, mmHDP_DEBUG0); ++ amdgpu_ring_write(ring, 0); ++ amdgpu_ring_write(ring, 1); ++} ++ + /** + * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring + * +@@ -5064,7 +5084,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { + .emit_frame_size = + 20 + /* gfx_v7_0_ring_emit_gds_switch */ + 7 + /* gfx_v7_0_ring_emit_hdp_flush */ +- 5 + /* hdp invalidate */ ++ 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */ + 12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */ + 7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */ + CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v7_0_ring_emit_vm_flush */ +@@ -5076,6 +5096,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { + .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush, + .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch, + .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush, ++ .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate, + .test_ring = gfx_v7_0_ring_test_ring, + .test_ib = gfx_v7_0_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, +@@ -5095,7 +5116,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = { + .emit_frame_size = + 20 + /* gfx_v7_0_ring_emit_gds_switch */ + 7 + /* gfx_v7_0_ring_emit_hdp_flush */ +- 5 + /* hdp invalidate */ ++ 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */ + 7 + /* gfx_v7_0_ring_emit_pipeline_sync */ + CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v7_0_ring_emit_vm_flush */ + 7 + 7 + 7, /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */ +@@ -5106,6 +5127,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = { + .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush, + .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch, + .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush, ++ .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate, + .test_ring = gfx_v7_0_ring_test_ring, + .test_ib = gfx_v7_0_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +index 8a334aa..918cefc 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +@@ -6233,6 +6233,19 @@ static void gfx_v8_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) + EVENT_INDEX(0)); + } + ++ ++static void gfx_v8_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) ++{ ++ amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); ++ amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | ++ WRITE_DATA_DST_SEL(0) | ++ WR_CONFIRM)); ++ amdgpu_ring_write(ring, mmHDP_DEBUG0); ++ amdgpu_ring_write(ring, 0); ++ amdgpu_ring_write(ring, 1); ++ ++} ++ + static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, + struct amdgpu_ib *ib, + unsigned vmid, bool ctx_switch) +@@ -6877,6 +6890,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { + .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush, + .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch, + .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush, ++ .emit_hdp_invalidate = gfx_v8_0_ring_emit_hdp_invalidate, + .test_ring = gfx_v8_0_ring_test_ring, + .test_ib = gfx_v8_0_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, +@@ -6899,7 +6913,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = { + .emit_frame_size = + 20 + /* gfx_v8_0_ring_emit_gds_switch */ + 7 + /* gfx_v8_0_ring_emit_hdp_flush */ +- 5 + /* hdp_invalidate */ ++ 5 + /* gfx_v8_0_ring_emit_hdp_invalidate */ + 7 + /* gfx_v8_0_ring_emit_pipeline_sync */ + VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v8_0_ring_emit_vm_flush */ + 7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_compute x3 for user fence, vm fence */ +@@ -6910,6 +6924,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = { + .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush, + .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch, + .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush, ++ .emit_hdp_invalidate = gfx_v8_0_ring_emit_hdp_invalidate, + .test_ring = gfx_v8_0_ring_test_ring, + .test_ib = gfx_v8_0_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, +@@ -6929,7 +6944,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_kiq = { + .emit_frame_size = + 20 + /* gfx_v8_0_ring_emit_gds_switch */ + 7 + /* gfx_v8_0_ring_emit_hdp_flush */ +- 5 + /* hdp_invalidate */ ++ 5 + /* gfx_v8_0_ring_emit_hdp_invalidate */ + 7 + /* gfx_v8_0_ring_emit_pipeline_sync */ + 17 + /* gfx_v8_0_ring_emit_vm_flush */ + 7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_kiq x3 for user fence, vm fence */ +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index 61728ab..7fd44fcc 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -3591,6 +3591,14 @@ static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) + ref_and_mask, ref_and_mask, 0x20); + } + ++static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) ++{ ++ struct amdgpu_device *adev = ring->adev; ++ ++ gfx_v9_0_write_data_to_reg(ring, 0, true, ++ SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); ++} ++ + static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, + struct amdgpu_ib *ib, + unsigned vmid, bool ctx_switch) +@@ -4317,6 +4325,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = { + .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, + .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, + .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, ++ .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate, + .test_ring = gfx_v9_0_ring_test_ring, + .test_ib = gfx_v9_0_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, +@@ -4341,7 +4350,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { + .emit_frame_size = + 20 + /* gfx_v9_0_ring_emit_gds_switch */ + 7 + /* gfx_v9_0_ring_emit_hdp_flush */ +- 5 + /* hdp invalidate */ ++ 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */ + 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ + SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9 + /* gfx_v9_0_ring_emit_vm_flush */ + 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */ +@@ -4352,6 +4361,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { + .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, + .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, + .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, ++ .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate, + .test_ring = gfx_v9_0_ring_test_ring, + .test_ib = gfx_v9_0_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, +@@ -4372,7 +4382,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = { + .emit_frame_size = + 20 + /* gfx_v9_0_ring_emit_gds_switch */ + 7 + /* gfx_v9_0_ring_emit_hdp_flush */ +- 5 + /* hdp invalidate */ ++ 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */ + 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ + SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9 + /* gfx_v9_0_ring_emit_vm_flush */ + 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */ +diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +index 4a05c85..5e9bea0 100644 +--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c ++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +@@ -289,6 +289,13 @@ static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring) + SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ + } + ++static void sdma_v2_4_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) ++{ ++ amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | ++ SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); ++ amdgpu_ring_write(ring, mmHDP_DEBUG0); ++ amdgpu_ring_write(ring, 1); ++} + /** + * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring + * +@@ -1193,7 +1200,7 @@ static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { + .set_wptr = sdma_v2_4_ring_set_wptr, + .emit_frame_size = + 6 + /* sdma_v2_4_ring_emit_hdp_flush */ +- 3 + /* hdp invalidate */ ++ 3 + /* sdma_v2_4_ring_emit_hdp_invalidate */ + 6 + /* sdma_v2_4_ring_emit_pipeline_sync */ + VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v2_4_ring_emit_vm_flush */ + 10 + 10 + 10, /* sdma_v2_4_ring_emit_fence x3 for user fence, vm fence */ +@@ -1203,6 +1210,7 @@ static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { + .emit_pipeline_sync = sdma_v2_4_ring_emit_pipeline_sync, + .emit_vm_flush = sdma_v2_4_ring_emit_vm_flush, + .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush, ++ .emit_hdp_invalidate = sdma_v2_4_ring_emit_hdp_invalidate, + .test_ring = sdma_v2_4_ring_test_ring, + .test_ib = sdma_v2_4_ring_test_ib, + .insert_nop = sdma_v2_4_ring_insert_nop, +diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +index 586c55b..3c2195c 100644 +--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +@@ -460,6 +460,14 @@ static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) + SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ + } + ++static void sdma_v3_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) ++{ ++ amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | ++ SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); ++ amdgpu_ring_write(ring, mmHDP_DEBUG0); ++ amdgpu_ring_write(ring, 1); ++} ++ + /** + * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring + * +@@ -1626,7 +1634,7 @@ static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { + .set_wptr = sdma_v3_0_ring_set_wptr, + .emit_frame_size = + 6 + /* sdma_v3_0_ring_emit_hdp_flush */ +- 3 + /* hdp invalidate */ ++ 3 + /* sdma_v3_0_ring_emit_hdp_invalidate */ + 6 + /* sdma_v3_0_ring_emit_pipeline_sync */ + 12 + /* sdma_v3_0_ring_emit_vm_flush */ + 10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */ +@@ -1636,6 +1644,7 @@ static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { + .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync, + .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush, + .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush, ++ .emit_hdp_invalidate = sdma_v3_0_ring_emit_hdp_invalidate, + .test_ring = sdma_v3_0_ring_test_ring, + .test_ib = sdma_v3_0_ring_test_ib, + .insert_nop = sdma_v3_0_ring_insert_nop, +diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +index 4344490..54a58b2 100644 +--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +@@ -375,6 +375,16 @@ static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) + SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ + } + ++static void sdma_v4_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) ++{ ++ struct amdgpu_device *adev = ring->adev; ++ ++ amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | ++ SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); ++ amdgpu_ring_write(ring, SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE)); ++ amdgpu_ring_write(ring, 1); ++} ++ + /** + * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring + * +@@ -1573,7 +1583,7 @@ static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = { + .set_wptr = sdma_v4_0_ring_set_wptr, + .emit_frame_size = + 6 + /* sdma_v4_0_ring_emit_hdp_flush */ +- 3 + /* hdp invalidate */ ++ 3 + /* sdma_v4_0_ring_emit_hdp_invalidate */ + 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ + SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v4_0_ring_emit_vm_flush */ + 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ +@@ -1583,6 +1593,7 @@ static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = { + .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, + .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, + .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, ++ .emit_hdp_invalidate = sdma_v4_0_ring_emit_hdp_invalidate, + .test_ring = sdma_v4_0_ring_test_ring, + .test_ib = sdma_v4_0_ring_test_ib, + .insert_nop = sdma_v4_0_ring_insert_nop, +diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c +index 2db5bfb..0275e6f 100644 +--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c ++++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c +@@ -75,6 +75,20 @@ static void si_dma_ring_emit_ib(struct amdgpu_ring *ring, + + } + ++static void si_dma_ring_emit_hdp_flush(struct amdgpu_ring *ring) ++{ ++ amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0)); ++ amdgpu_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL)); ++ amdgpu_ring_write(ring, 1); ++} ++ ++static void si_dma_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) ++{ ++ amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0)); ++ amdgpu_ring_write(ring, (0xf << 16) | (HDP_DEBUG0)); ++ amdgpu_ring_write(ring, 1); ++} ++ + /** + * si_dma_ring_emit_fence - emit a fence on the DMA ring + * +@@ -758,7 +772,8 @@ static const struct amdgpu_ring_funcs si_dma_ring_funcs = { + .get_wptr = si_dma_ring_get_wptr, + .set_wptr = si_dma_ring_set_wptr, + .emit_frame_size = +- 3 + 3 + /* hdp flush / invalidate */ ++ 3 + /* si_dma_ring_emit_hdp_flush */ ++ 3 + /* si_dma_ring_emit_hdp_invalidate */ + 6 + /* si_dma_ring_emit_pipeline_sync */ + SI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* si_dma_ring_emit_vm_flush */ + 9 + 9 + 9, /* si_dma_ring_emit_fence x3 for user fence, vm fence */ +@@ -767,6 +782,8 @@ static const struct amdgpu_ring_funcs si_dma_ring_funcs = { + .emit_fence = si_dma_ring_emit_fence, + .emit_pipeline_sync = si_dma_ring_emit_pipeline_sync, + .emit_vm_flush = si_dma_ring_emit_vm_flush, ++ .emit_hdp_flush = si_dma_ring_emit_hdp_flush, ++ .emit_hdp_invalidate = si_dma_ring_emit_hdp_invalidate, + .test_ring = si_dma_ring_test_ring, + .test_ib = si_dma_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, +diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +index 948bb943..8ab10c2 100644 +--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c ++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +@@ -464,6 +464,32 @@ static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq + } + + /** ++ * uvd_v4_2_ring_emit_hdp_flush - emit an hdp flush ++ * ++ * @ring: amdgpu_ring pointer ++ * ++ * Emits an hdp flush. ++ */ ++static void uvd_v4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) ++{ ++ amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0)); ++ amdgpu_ring_write(ring, 0); ++} ++ ++/** ++ * uvd_v4_2_ring_hdp_invalidate - emit an hdp invalidate ++ * ++ * @ring: amdgpu_ring pointer ++ * ++ * Emits an hdp invalidate. ++ */ ++static void uvd_v4_2_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) ++{ ++ amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0)); ++ amdgpu_ring_write(ring, 1); ++} ++ ++/** + * uvd_v4_2_ring_test_ring - register write test + * + * @ring: amdgpu_ring pointer +@@ -739,10 +765,14 @@ static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { + .set_wptr = uvd_v4_2_ring_set_wptr, + .parse_cs = amdgpu_uvd_ring_parse_cs, + .emit_frame_size = ++ 2 + /* uvd_v4_2_ring_emit_hdp_flush */ ++ 2 + /* uvd_v4_2_ring_emit_hdp_invalidate */ + 14, /* uvd_v4_2_ring_emit_fence x1 no user fence */ + .emit_ib_size = 4, /* uvd_v4_2_ring_emit_ib */ + .emit_ib = uvd_v4_2_ring_emit_ib, + .emit_fence = uvd_v4_2_ring_emit_fence, ++ .emit_hdp_flush = uvd_v4_2_ring_emit_hdp_flush, ++ .emit_hdp_invalidate = uvd_v4_2_ring_emit_hdp_invalidate, + .test_ring = uvd_v4_2_ring_test_ring, + .test_ib = amdgpu_uvd_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, +diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +index 6445d55..c1fe30c 100644 +--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +@@ -479,6 +479,32 @@ static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq + } + + /** ++ * uvd_v5_0_ring_emit_hdp_flush - emit an hdp flush ++ * ++ * @ring: amdgpu_ring pointer ++ * ++ * Emits an hdp flush. ++ */ ++static void uvd_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) ++{ ++ amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0)); ++ amdgpu_ring_write(ring, 0); ++} ++ ++/** ++ * uvd_v5_0_ring_hdp_invalidate - emit an hdp invalidate ++ * ++ * @ring: amdgpu_ring pointer ++ * ++ * Emits an hdp invalidate. ++ */ ++static void uvd_v5_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) ++{ ++ amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0)); ++ amdgpu_ring_write(ring, 1); ++} ++ ++/** + * uvd_v5_0_ring_test_ring - register write test + * + * @ring: amdgpu_ring pointer +@@ -847,10 +873,14 @@ static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { + .set_wptr = uvd_v5_0_ring_set_wptr, + .parse_cs = amdgpu_uvd_ring_parse_cs, + .emit_frame_size = ++ 2 + /* uvd_v5_0_ring_emit_hdp_flush */ ++ 2 + /* uvd_v5_0_ring_emit_hdp_invalidate */ + 14, /* uvd_v5_0_ring_emit_fence x1 no user fence */ + .emit_ib_size = 6, /* uvd_v5_0_ring_emit_ib */ + .emit_ib = uvd_v5_0_ring_emit_ib, + .emit_fence = uvd_v5_0_ring_emit_fence, ++ .emit_hdp_flush = uvd_v5_0_ring_emit_hdp_flush, ++ .emit_hdp_invalidate = uvd_v5_0_ring_emit_hdp_invalidate, + .test_ring = uvd_v5_0_ring_test_ring, + .test_ib = amdgpu_uvd_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, +diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +index ac76a76..84c558d 100644 +--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +@@ -964,6 +964,32 @@ static void uvd_v6_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, + } + + /** ++ * uvd_v6_0_ring_emit_hdp_flush - emit an hdp flush ++ * ++ * @ring: amdgpu_ring pointer ++ * ++ * Emits an hdp flush. ++ */ ++static void uvd_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) ++{ ++ amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0)); ++ amdgpu_ring_write(ring, 0); ++} ++ ++/** ++ * uvd_v6_0_ring_hdp_invalidate - emit an hdp invalidate ++ * ++ * @ring: amdgpu_ring pointer ++ * ++ * Emits an hdp invalidate. ++ */ ++static void uvd_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) ++{ ++ amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0)); ++ amdgpu_ring_write(ring, 1); ++} ++ ++/** + * uvd_v6_0_ring_test_ring - register write test + * + * @ring: amdgpu_ring pointer +@@ -1530,11 +1556,15 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = { + .set_wptr = uvd_v6_0_ring_set_wptr, + .parse_cs = amdgpu_uvd_ring_parse_cs, + .emit_frame_size = ++ 2 + /* uvd_v6_0_ring_emit_hdp_flush */ ++ 2 + /* uvd_v6_0_ring_emit_hdp_invalidate */ + 10 + /* uvd_v6_0_ring_emit_pipeline_sync */ + 14, /* uvd_v6_0_ring_emit_fence x1 no user fence */ + .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */ + .emit_ib = uvd_v6_0_ring_emit_ib, + .emit_fence = uvd_v6_0_ring_emit_fence, ++ .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush, ++ .emit_hdp_invalidate = uvd_v6_0_ring_emit_hdp_invalidate, + .test_ring = uvd_v6_0_ring_test_ring, + .test_ib = amdgpu_uvd_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, +@@ -1552,7 +1582,8 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = { + .get_wptr = uvd_v6_0_ring_get_wptr, + .set_wptr = uvd_v6_0_ring_set_wptr, + .emit_frame_size = +- 6 + 6 + /* hdp flush / invalidate */ ++ 2 + /* uvd_v6_0_ring_emit_hdp_flush */ ++ 2 + /* uvd_v6_0_ring_emit_hdp_invalidate */ + 10 + /* uvd_v6_0_ring_emit_pipeline_sync */ + 20 + /* uvd_v6_0_ring_emit_vm_flush */ + 14 + 14, /* uvd_v6_0_ring_emit_fence x2 vm fence */ +@@ -1561,6 +1592,8 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = { + .emit_fence = uvd_v6_0_ring_emit_fence, + .emit_vm_flush = uvd_v6_0_ring_emit_vm_flush, + .emit_pipeline_sync = uvd_v6_0_ring_emit_pipeline_sync, ++ .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush, ++ .emit_hdp_invalidate = uvd_v6_0_ring_emit_hdp_invalidate, + .test_ring = uvd_v6_0_ring_test_ring, + .test_ib = amdgpu_uvd_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, +diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +index d317c76..241e730 100644 +--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +@@ -1136,6 +1136,37 @@ static void uvd_v7_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, + } + + /** ++ * uvd_v7_0_ring_emit_hdp_flush - emit an hdp flush ++ * ++ * @ring: amdgpu_ring pointer ++ * ++ * Emits an hdp flush. ++ */ ++static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) ++{ ++ struct amdgpu_device *adev = ring->adev; ++ ++ amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(NBIF, 0, ++ mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0)); ++ amdgpu_ring_write(ring, 0); ++} ++ ++/** ++ * uvd_v7_0_ring_hdp_invalidate - emit an hdp invalidate ++ * ++ * @ring: amdgpu_ring pointer ++ * ++ * Emits an hdp invalidate. ++ */ ++static void uvd_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) ++{ ++ struct amdgpu_device *adev = ring->adev; ++ ++ amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 0)); ++ amdgpu_ring_write(ring, 1); ++} ++ ++/** + * uvd_v7_0_ring_test_ring - register write test + * + * @ring: amdgpu_ring pointer +@@ -1662,13 +1693,16 @@ static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = { + .get_wptr = uvd_v7_0_ring_get_wptr, + .set_wptr = uvd_v7_0_ring_set_wptr, + .emit_frame_size = +- 6 + 6 + /* hdp flush / invalidate */ ++ 2 + /* uvd_v7_0_ring_emit_hdp_flush */ ++ 2 + /* uvd_v7_0_ring_emit_hdp_invalidate */ + SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 16 + /* uvd_v7_0_ring_emit_vm_flush */ + 14 + 14, /* uvd_v7_0_ring_emit_fence x2 vm fence */ + .emit_ib_size = 8, /* uvd_v7_0_ring_emit_ib */ + .emit_ib = uvd_v7_0_ring_emit_ib, + .emit_fence = uvd_v7_0_ring_emit_fence, + .emit_vm_flush = uvd_v7_0_ring_emit_vm_flush, ++ .emit_hdp_flush = uvd_v7_0_ring_emit_hdp_flush, ++ .emit_hdp_invalidate = uvd_v7_0_ring_emit_hdp_invalidate, + .test_ring = uvd_v7_0_ring_test_ring, + .test_ib = amdgpu_uvd_ring_test_ib, + .insert_nop = uvd_v7_0_ring_insert_nop, +@@ -1688,7 +1722,6 @@ static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = { + .get_wptr = uvd_v7_0_enc_ring_get_wptr, + .set_wptr = uvd_v7_0_enc_ring_set_wptr, + .emit_frame_size = +- 3 + 3 + /* hdp flush / invalidate */ + SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 8 + /* uvd_v7_0_enc_ring_emit_vm_flush */ + 5 + 5 + /* uvd_v7_0_enc_ring_emit_fence x2 vm fence */ + 1, /* uvd_v7_0_enc_ring_insert_end */ +diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +index d8bfeb2..bdc0052 100644 +--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +@@ -832,6 +832,21 @@ static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 + } + + /** ++ * vcn_v1_0_dec_ring_hdp_invalidate - emit an hdp invalidate ++ * ++ * @ring: amdgpu_ring pointer ++ * ++ * Emits an hdp invalidate. ++ */ ++static void vcn_v1_0_dec_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) ++{ ++ struct amdgpu_device *adev = ring->adev; ++ ++ amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 0)); ++ amdgpu_ring_write(ring, 1); ++} ++ ++/** + * vcn_v1_0_dec_ring_emit_ib - execute indirect buffer + * + * @ring: amdgpu_ring pointer +@@ -1103,7 +1118,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = { + .get_wptr = vcn_v1_0_dec_ring_get_wptr, + .set_wptr = vcn_v1_0_dec_ring_set_wptr, + .emit_frame_size = +- 6 + 6 + /* hdp invalidate / flush */ ++ 2 + /* vcn_v1_0_dec_ring_emit_hdp_invalidate */ + SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 16 + /* vcn_v1_0_dec_ring_emit_vm_flush */ + 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */ + 6, +@@ -1111,6 +1126,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = { + .emit_ib = vcn_v1_0_dec_ring_emit_ib, + .emit_fence = vcn_v1_0_dec_ring_emit_fence, + .emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush, ++ .emit_hdp_invalidate = vcn_v1_0_dec_ring_emit_hdp_invalidate, + .test_ring = amdgpu_vcn_dec_ring_test_ring, + .test_ib = amdgpu_vcn_dec_ring_test_ib, + .insert_nop = vcn_v1_0_ring_insert_nop, +-- +2.7.4 + |