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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3298-Revert-drm-amdgpu-fill-only-the-lower-range-with-ATS.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3298-Revert-drm-amdgpu-fill-only-the-lower-range-with-ATS.patch195
1 files changed, 195 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3298-Revert-drm-amdgpu-fill-only-the-lower-range-with-ATS.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3298-Revert-drm-amdgpu-fill-only-the-lower-range-with-ATS.patch
new file mode 100644
index 00000000..b3d87612
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3298-Revert-drm-amdgpu-fill-only-the-lower-range-with-ATS.patch
@@ -0,0 +1,195 @@
+From bbaeb447fbbac8f2d1b3821039e736ce604e6576 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Mon, 29 Jan 2018 14:31:50 +0100
+Subject: [PATCH 3298/4131] Revert "drm/amdgpu: fill only the lower range with
+ ATS entries"
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This reverts commit 63c2b9e9f4f6f3207a410ab062f7020e95a36bd2.
+
+Change-Id: I4d604b54ecc23044b1682c40aa8b5e42d8c2bb41
+Signed-off-by: Christian König <christian.koenig@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 83 ++++++++++++----------------------
+ 1 file changed, 29 insertions(+), 54 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index 56e1866..0c669d7 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -267,34 +267,24 @@ bool amdgpu_vm_ready(struct amdgpu_vm *vm)
+ * Root PD needs to be reserved when calling this.
+ */
+ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
+- struct amdgpu_vm *vm, struct amdgpu_bo *bo,
+- unsigned level, bool pte_support_ats)
++ struct amdgpu_vm *vm,
++ struct amdgpu_bo *bo,
++ unsigned level)
+ {
+ struct ttm_operation_ctx ctx = { true, false };
+ struct dma_fence *fence = NULL;
+- unsigned entries, ats_entries;
+- uint64_t addr, ats_value;
++ uint64_t addr, init_value;
+ struct amdgpu_ring *ring;
+ struct amdgpu_job *job;
++ unsigned entries;
+ int r;
+
+- addr = amdgpu_bo_gpu_offset(bo);
+- entries = amdgpu_bo_size(bo) / 8;
+-
+- if (pte_support_ats) {
+- if (level == adev->vm_manager.root_level) {
+- ats_entries = amdgpu_vm_level_shift(adev, level);
+- ats_entries += AMDGPU_GPU_PAGE_SHIFT;
+- ats_entries = AMDGPU_VA_HOLE_START >> ats_entries;
+- ats_entries = min(ats_entries, entries);
+- entries -= ats_entries;
+- } else {
+- ats_entries = entries;
+- entries = 0;
+- }
++ if (vm->pte_support_ats) {
++ init_value = AMDGPU_PTE_DEFAULT_ATC;
++ if (level != AMDGPU_VM_PTB)
++ init_value |= AMDGPU_PDE_PTE;
+ } else {
+- ats_entries = 0;
+- ats_value = 0;
++ init_value = 0;
+ }
+
+ ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
+@@ -307,26 +297,15 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
+ if (r)
+ goto error;
+
++ addr = amdgpu_bo_gpu_offset(bo);
++ entries = amdgpu_bo_size(bo) / 8;
++
+ r = amdgpu_job_alloc_with_ib(adev, 64, &job);
+ if (r)
+ goto error;
+
+- if (ats_entries) {
+- uint64_t ats_value;
+-
+- ats_value = AMDGPU_PTE_DEFAULT_ATC;
+- if (level != AMDGPU_VM_PTB)
+- ats_value |= AMDGPU_PDE_PTE;
+-
+- amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0,
+- ats_entries, 0, ats_value);
+- addr += ats_entries * 8;
+- }
+-
+- if (entries)
+- amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0,
+- entries, 0, 0);
+-
++ amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0,
++ entries, 0, init_value);
+ amdgpu_ring_pad_ib(ring, &job->ibs[0]);
+
+ WARN_ON(job->ibs[0].length_dw > 64);
+@@ -360,7 +339,7 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
+ struct amdgpu_vm *vm,
+ struct amdgpu_vm_pt *parent,
+ uint64_t saddr, uint64_t eaddr,
+- unsigned level, bool ats)
++ unsigned level)
+ {
+ unsigned shift = amdgpu_vm_level_shift(adev, level);
+ unsigned pt_idx, from, to;
+@@ -415,7 +394,7 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
+ if (r)
+ return r;
+
+- r = amdgpu_vm_clear_bo(adev, vm, pt, level, ats);
++ r = amdgpu_vm_clear_bo(adev, vm, pt, level);
+ if (r) {
+ amdgpu_bo_unref(&pt);
+ return r;
+@@ -447,7 +426,7 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
+ uint64_t sub_eaddr = (pt_idx == to) ? eaddr :
+ ((1 << shift) - 1);
+ r = amdgpu_vm_alloc_levels(adev, vm, entry, sub_saddr,
+- sub_eaddr, level, ats);
++ sub_eaddr, level);
+ if (r)
+ return r;
+ }
+@@ -470,29 +449,26 @@ int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
+ struct amdgpu_vm *vm,
+ uint64_t saddr, uint64_t size)
+ {
++ uint64_t last_pfn;
+ uint64_t eaddr;
+- bool ats = false;
+
+ /* validate the parameters */
+ if (saddr & AMDGPU_GPU_PAGE_MASK || size & AMDGPU_GPU_PAGE_MASK)
+ return -EINVAL;
+
+ eaddr = saddr + size - 1;
+-
+- if (vm->pte_support_ats)
+- ats = saddr < AMDGPU_VA_HOLE_START;
+-
+- saddr /= AMDGPU_GPU_PAGE_SIZE;
+- eaddr /= AMDGPU_GPU_PAGE_SIZE;
+-
+- if (eaddr >= adev->vm_manager.max_pfn) {
++ last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE;
++ if (last_pfn >= adev->vm_manager.max_pfn) {
+ dev_err(adev->dev, "va above limit (0x%08llX >= 0x%08llX)\n",
+- eaddr, adev->vm_manager.max_pfn);
++ last_pfn, adev->vm_manager.max_pfn);
+ return -EINVAL;
+ }
+
++ saddr /= AMDGPU_GPU_PAGE_SIZE;
++ eaddr /= AMDGPU_GPU_PAGE_SIZE;
++
+ return amdgpu_vm_alloc_levels(adev, vm, &vm->root, saddr, eaddr,
+- adev->vm_manager.root_level, ats);
++ adev->vm_manager.root_level);
+ }
+
+ /**
+@@ -1716,16 +1692,16 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
+ struct dma_fence **fence)
+ {
+ struct amdgpu_bo_va_mapping *mapping;
+- uint64_t init_pte_value = 0;
+ struct dma_fence *f = NULL;
+ int r;
++ uint64_t init_pte_value = 0;
+
+ while (!list_empty(&vm->freed)) {
+ mapping = list_first_entry(&vm->freed,
+ struct amdgpu_bo_va_mapping, list);
+ list_del(&mapping->list);
+
+- if (vm->pte_support_ats && mapping->start < AMDGPU_VA_HOLE_START)
++ if (vm->pte_support_ats)
+ init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
+
+ r = amdgpu_vm_bo_update_mapping(adev, NULL, NULL, vm,
+@@ -2421,8 +2397,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
+ goto error_free_root;
+
+ r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo,
+- adev->vm_manager.root_level,
+- vm->pte_support_ats);
++ adev->vm_manager.root_level);
+ if (r)
+ goto error_unreserve;
+
+--
+2.7.4
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-05-01 05:34:15 +0000