diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3273-drm-amd-pp-Change-activity_target-for-performance-op.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3273-drm-amd-pp-Change-activity_target-for-performance-op.patch | 102 |
1 files changed, 102 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3273-drm-amd-pp-Change-activity_target-for-performance-op.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3273-drm-amd-pp-Change-activity_target-for-performance-op.patch new file mode 100644 index 00000000..3647093b --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3273-drm-amd-pp-Change-activity_target-for-performance-op.patch @@ -0,0 +1,102 @@ +From 776e174e654a5159717d83670a8b749fab533f02 Mon Sep 17 00:00:00 2001 +From: Rex Zhu <Rex.Zhu@amd.com> +Date: Tue, 23 Jan 2018 16:28:09 +0800 +Subject: [PATCH 3273/4131] drm/amd/pp: Change activity_target for performance + optimization on Polaris + +And not support perDPM level optimization on Polaris, so +delete sclk activity_target array. + +Change-Id: I253b707751aa921cb8e4f5d06feb8ac6e1bcd0ce +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> +--- + drivers/gpu/drm/amd/powerplay/hwmgr/smu7_dyn_defaults.h | 2 +- + drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 1 + + drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h | 1 + + drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c | 6 +----- + drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h | 1 - + 5 files changed, 4 insertions(+), 7 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_dyn_defaults.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_dyn_defaults.h +index f967613..3477d4d 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_dyn_defaults.h ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_dyn_defaults.h +@@ -50,6 +50,6 @@ + #define SMU7_CGULVCONTROL_DFLT 0x00007450 + #define SMU7_TARGETACTIVITY_DFLT 50 + #define SMU7_MCLK_TARGETACTIVITY_DFLT 10 +- ++#define SMU7_SCLK_TARGETACTIVITY_DFLT 30 + #endif + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +index 77e28e1..f7380a84 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +@@ -1485,6 +1485,7 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr) + data->dll_default_on = false; + data->mclk_dpm0_activity_target = 0xa; + data->mclk_activity_target = SMU7_MCLK_TARGETACTIVITY_DFLT; ++ data->sclk_activity_target = SMU7_SCLK_TARGETACTIVITY_DFLT; + data->vddc_vddgfx_delta = 300; + data->static_screen_threshold = SMU7_STATICSCREENTHRESHOLD_DFLT; + data->static_screen_threshold_unit = SMU7_STATICSCREENTHRESHOLDUNIT_DFLT; +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h +index 1ce84cc..a626a3e 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h +@@ -290,6 +290,7 @@ struct smu7_hwmgr { + bool use_pcie_performance_levels; + bool use_pcie_power_saving_levels; + uint32_t mclk_activity_target; ++ uint16_t sclk_activity_target; + uint32_t mclk_dpm0_activity_target; + uint32_t low_sclk_interrupt_threshold; + uint32_t last_mclk_dpm_enable_mask; +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c +index a760a82..356f60e 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c +@@ -366,7 +366,6 @@ static bool polaris10_is_hw_avfs_present(struct pp_hwmgr *hwmgr) + static int polaris10_smu_init(struct pp_hwmgr *hwmgr) + { + struct polaris10_smumgr *smu_data; +- int i; + + smu_data = kzalloc(sizeof(struct polaris10_smumgr), GFP_KERNEL); + if (smu_data == NULL) +@@ -377,9 +376,6 @@ static int polaris10_smu_init(struct pp_hwmgr *hwmgr) + if (smu7_init(hwmgr)) + return -EINVAL; + +- for (i = 0; i < SMU74_MAX_LEVELS_GRAPHICS; i++) +- smu_data->activity_target[i] = PPPOLARIS10_TARGETACTIVITY_DFLT; +- + return 0; + } + +@@ -1037,7 +1033,7 @@ static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) + + result = polaris10_populate_single_graphic_level(hwmgr, + dpm_table->sclk_table.dpm_levels[i].value, +- (uint16_t)smu_data->activity_target[i], ++ hw_data->sclk_activity_target, + &(smu_data->smc_state_table.GraphicsLevel[i])); + if (result) + return result; +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h +index 5e19c24..1ec425d 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h +@@ -59,7 +59,6 @@ struct polaris10_smumgr { + struct SMU74_Discrete_PmFuses power_tune_table; + struct polaris10_range_table range_table[NUM_SCLK_RANGE]; + const struct polaris10_pt_defaults *power_tune_defaults; +- uint32_t activity_target[SMU74_MAX_LEVELS_GRAPHICS]; + uint32_t bif_sclk_table[SMU74_MAX_LEVELS_LINK]; + }; + +-- +2.7.4 + |