diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3256-drm-amd-display-Add-timing-generator-count-to-resour.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3256-drm-amd-display-Add-timing-generator-count-to-resour.patch | 157 |
1 files changed, 157 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3256-drm-amd-display-Add-timing-generator-count-to-resour.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3256-drm-amd-display-Add-timing-generator-count-to-resour.patch new file mode 100644 index 00000000..a91af250 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3256-drm-amd-display-Add-timing-generator-count-to-resour.patch @@ -0,0 +1,157 @@ +From e9fd195731df6fa17c16d07f250525078f5da245 Mon Sep 17 00:00:00 2001 +From: Yongqiang Sun <yongqiang.sun@amd.com> +Date: Fri, 5 Jan 2018 13:53:06 -0500 +Subject: [PATCH 3256/4131] drm/amd/display: Add timing generator count to + resource pool. + +Use tg count in resource pool for further reference. + +Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Harry Wentland <harry.wentland@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c | 1 + + drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 2 +- + drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 1 + + drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | 1 + + drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c | 3 +++ + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 6 +++--- + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 1 + + drivers/gpu/drm/amd/display/dc/inc/core_types.h | 1 + + 8 files changed, 12 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +index 84dad36..9485161 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +@@ -849,6 +849,7 @@ static bool construct( + *************************************************/ + pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; + pool->base.pipe_count = res_cap.num_timing_generator; ++ pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; + dc->caps.max_downscale_ratio = 200; + dc->caps.i2c_speed_in_khz = 40; + dc->caps.max_cursor_size = 128; +diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +index 9adb5e9..cb2e0ce 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +@@ -1152,7 +1152,7 @@ static bool construct( + + pool->base.pipe_count = pool->base.res_cap->num_timing_generator; + pool->base.underlay_pipe_index = pool->base.pipe_count; +- ++ pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; + dc->caps.max_downscale_ratio = 150; + dc->caps.i2c_speed_in_khz = 100; + dc->caps.max_cursor_size = 128; +diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +index 98d9cd0..c0757dd 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +@@ -1100,6 +1100,7 @@ static bool construct( + *************************************************/ + pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; + pool->base.pipe_count = pool->base.res_cap->num_timing_generator; ++ pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; + dc->caps.max_downscale_ratio = 200; + dc->caps.i2c_speed_in_khz = 100; + dc->caps.max_cursor_size = 128; +diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +index a8725ac..4659a4b 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +@@ -831,6 +831,7 @@ static bool construct( + + /* TODO: Fill more data from GreenlandAsicCapability.cpp */ + pool->base.pipe_count = res_cap.num_timing_generator; ++ pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; + pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; + + dc->caps.max_downscale_ratio = 200; +diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +index 25d7eb1..a36c14d 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +@@ -790,6 +790,7 @@ static bool dce80_construct( + *************************************************/ + pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; + pool->base.pipe_count = res_cap.num_timing_generator; ++ pool->base.timing_generator_count = res_cap.num_timing_generator; + dc->caps.max_downscale_ratio = 200; + dc->caps.i2c_speed_in_khz = 40; + dc->caps.max_cursor_size = 128; +@@ -955,6 +956,7 @@ static bool dce81_construct( + *************************************************/ + pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; + pool->base.pipe_count = res_cap_81.num_timing_generator; ++ pool->base.timing_generator_count = res_cap_81.num_timing_generator; + dc->caps.max_downscale_ratio = 200; + dc->caps.i2c_speed_in_khz = 40; + dc->caps.max_cursor_size = 128; +@@ -1120,6 +1122,7 @@ static bool dce83_construct( + *************************************************/ + pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; + pool->base.pipe_count = res_cap_83.num_timing_generator; ++ pool->base.timing_generator_count = res_cap_83.num_timing_generator; + dc->caps.max_downscale_ratio = 200; + dc->caps.i2c_speed_in_khz = 40; + dc->caps.max_cursor_size = 128; +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index c6a4fa2..e1a8eba 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -133,7 +133,7 @@ void dcn10_log_hw_state(struct dc *dc) + DTN_INFO("[%d]:\t %xh \t %xh \t %d \t %d \t " + "%xh \t %xh \t %xh \t " + "%d \t %d \t %d \t %xh \t", +- i, ++ hubp->inst, + s.pixel_format, + s.inuse_addr_hi, + s.viewport_width, +@@ -155,7 +155,7 @@ void dcn10_log_hw_state(struct dc *dc) + DTN_INFO("OTG:\t v_bs \t v_be \t v_ss \t v_se \t vpol \t vmax \t vmin \t " + "h_bs \t h_be \t h_ss \t h_se \t hpol \t htot \t vtot \t underflow\n"); + +- for (i = 0; i < pool->res_cap->num_timing_generator; i++) { ++ for (i = 0; i < pool->timing_generator_count; i++) { + struct timing_generator *tg = pool->timing_generators[i]; + struct dcn_otg_state s = {0}; + +@@ -168,7 +168,7 @@ void dcn10_log_hw_state(struct dc *dc) + DTN_INFO("[%d]:\t %d \t %d \t %d \t %d \t " + "%d \t %d \t %d \t %d \t %d \t %d \t " + "%d \t %d \t %d \t %d \t %d \t ", +- i, ++ tg->inst, + s.v_blank_start, + s.v_blank_end, + s.v_sync_a_start, +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +index 66af05b..ed616f5e 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +@@ -1445,6 +1445,7 @@ static bool construct( + + /* valid pipe num */ + pool->base.pipe_count = j; ++ pool->base.timing_generator_count = j; + + /* within dml lib, it is hard code to 4. If ASIC pipe is fused, + * the value may be changed +diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h +index 59d2699..5509e13 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h +@@ -153,6 +153,7 @@ struct resource_pool { + unsigned int underlay_pipe_index; + unsigned int stream_enc_count; + unsigned int ref_clock_inKhz; ++ unsigned int timing_generator_count; + + /* + * reserved clock source for DP +-- +2.7.4 + |