diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3230-drm-amdgpu-remove-now-superflous-_hdp-operation.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3230-drm-amdgpu-remove-now-superflous-_hdp-operation.patch | 814 |
1 files changed, 814 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3230-drm-amdgpu-remove-now-superflous-_hdp-operation.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3230-drm-amdgpu-remove-now-superflous-_hdp-operation.patch new file mode 100644 index 00000000..1ced6107 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3230-drm-amdgpu-remove-now-superflous-_hdp-operation.patch @@ -0,0 +1,814 @@ +From 8bf54f9336f1d653ae96f48a06929a58753aa72e Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com> +Date: Fri, 19 Jan 2018 15:19:16 +0100 +Subject: [PATCH 3230/4131] drm/amdgpu: remove now superflous *_hdp operation +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +All HDP invalidation and most flush can now be replaced by the generic +ASIC function. + +Signed-off-by: Christian König <christian.koenig@amd.com> +Acked-by: Chunming Zhou <david1.zhou@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 - + drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 7 +----- + drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 - + drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 10 +------- + drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 39 ++------------------------------ + drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 26 ++------------------- + drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 19 ++-------------- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 14 ++---------- + drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 10 +------- + drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 11 +-------- + drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 13 +---------- + drivers/gpu/drm/amd/amdgpu/si_dma.c | 19 +--------------- + drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 30 ------------------------ + drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 30 ------------------------ + drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 35 +--------------------------- + drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 37 ++---------------------------- + drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 18 +-------------- + 17 files changed, 18 insertions(+), 302 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +index 6b57458..42c0aa5 100755 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +@@ -1858,7 +1858,6 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) + #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) + #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) + #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) +-#define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r)) + #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r)) + #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d)) + #define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d)) +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +index 1b2b7c1..5d79b43 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +@@ -233,12 +233,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, + #ifdef CONFIG_X86_64 + if (!(adev->flags & AMD_IS_APU)) + #endif +- { +- if (ring->funcs->emit_hdp_invalidate) +- amdgpu_ring_emit_hdp_invalidate(ring); +- else +- amdgpu_asic_invalidate_hdp(adev, ring); +- } ++ amdgpu_asic_invalidate_hdp(adev, ring); + + r = amdgpu_fence_emit(ring, f); + if (r) { +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +index 668a1ed..115d523 100755 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +@@ -129,7 +129,6 @@ struct amdgpu_ring_funcs { + void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid, + unsigned pasid, uint64_t pd_addr); + void (*emit_hdp_flush)(struct amdgpu_ring *ring); +- void (*emit_hdp_invalidate)(struct amdgpu_ring *ring); + void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, + uint32_t gds_base, uint32_t gds_size, + uint32_t gws_base, uint32_t gws_size, +diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +index 730690b..b1644ea 100644 +--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c ++++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +@@ -261,13 +261,6 @@ static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring) + amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ + } + +-static void cik_sdma_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) +-{ +- amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); +- amdgpu_ring_write(ring, mmHDP_DEBUG0); +- amdgpu_ring_write(ring, 1); +-} +- + /** + * cik_sdma_ring_emit_fence - emit a fence on the DMA ring + * +@@ -1277,7 +1270,7 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { + .set_wptr = cik_sdma_ring_set_wptr, + .emit_frame_size = + 6 + /* cik_sdma_ring_emit_hdp_flush */ +- 3 + /* cik_sdma_ring_emit_hdp_invalidate */ ++ 3 + /* hdp invalidate */ + 6 + /* cik_sdma_ring_emit_pipeline_sync */ + CIK_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* cik_sdma_ring_emit_vm_flush */ + 9 + 9 + 9, /* cik_sdma_ring_emit_fence x3 for user fence, vm fence */ +@@ -1287,7 +1280,6 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { + .emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync, + .emit_vm_flush = cik_sdma_ring_emit_vm_flush, + .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush, +- .emit_hdp_invalidate = cik_sdma_ring_emit_hdp_invalidate, + .test_ring = cik_sdma_ring_test_ring, + .test_ib = cik_sdma_ring_test_ib, + .insert_nop = cik_sdma_ring_insert_nop, +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +index e6c3a24..3517fd9 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +@@ -1809,17 +1809,6 @@ static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring) + return r; + } + +-static void gfx_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) +-{ +- /* flush hdp cache */ +- amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); +- amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | +- WRITE_DATA_DST_SEL(0))); +- amdgpu_ring_write(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL); +- amdgpu_ring_write(ring, 0); +- amdgpu_ring_write(ring, 0x1); +-} +- + static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) + { + amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); +@@ -1827,24 +1816,6 @@ static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) + EVENT_INDEX(0)); + } + +-/** +- * gfx_v6_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp +- * +- * @adev: amdgpu_device pointer +- * @ridx: amdgpu ring index +- * +- * Emits an hdp invalidate on the cp. +- */ +-static void gfx_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) +-{ +- amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); +- amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | +- WRITE_DATA_DST_SEL(0))); +- amdgpu_ring_write(ring, mmHDP_DEBUG0); +- amdgpu_ring_write(ring, 0); +- amdgpu_ring_write(ring, 0x1); +-} +- + static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, + u64 seq, unsigned flags) + { +@@ -3507,8 +3478,7 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { + .get_wptr = gfx_v6_0_ring_get_wptr, + .set_wptr = gfx_v6_0_ring_set_wptr_gfx, + .emit_frame_size = +- 5 + /* gfx_v6_0_ring_emit_hdp_flush */ +- 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */ ++ 5 + 5 + /* hdp flush / invalidate */ + 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ + 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */ + SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v6_0_ring_emit_vm_flush */ +@@ -3518,8 +3488,6 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { + .emit_fence = gfx_v6_0_ring_emit_fence, + .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, + .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush, +- .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush, +- .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate, + .test_ring = gfx_v6_0_ring_test_ring, + .test_ib = gfx_v6_0_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, +@@ -3535,8 +3503,7 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = { + .get_wptr = gfx_v6_0_ring_get_wptr, + .set_wptr = gfx_v6_0_ring_set_wptr_compute, + .emit_frame_size = +- 5 + /* gfx_v6_0_ring_emit_hdp_flush */ +- 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */ ++ 5 + 5 + /* hdp flush / invalidate */ + 7 + /* gfx_v6_0_ring_emit_pipeline_sync */ + SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v6_0_ring_emit_vm_flush */ + 14 + 14 + 14, /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ +@@ -3545,8 +3512,6 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = { + .emit_fence = gfx_v6_0_ring_emit_fence, + .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, + .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush, +- .emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush, +- .emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate, + .test_ring = gfx_v6_0_ring_test_ring, + .test_ib = gfx_v6_0_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +index aeeced9..ff71f7c 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +@@ -2147,26 +2147,6 @@ static void gfx_v7_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) + EVENT_INDEX(0)); + } + +- +-/** +- * gfx_v7_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp +- * +- * @adev: amdgpu_device pointer +- * @ridx: amdgpu ring index +- * +- * Emits an hdp invalidate on the cp. +- */ +-static void gfx_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) +-{ +- amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); +- amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | +- WRITE_DATA_DST_SEL(0) | +- WR_CONFIRM)); +- amdgpu_ring_write(ring, mmHDP_DEBUG0); +- amdgpu_ring_write(ring, 0); +- amdgpu_ring_write(ring, 1); +-} +- + /** + * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring + * +@@ -5084,7 +5064,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { + .emit_frame_size = + 20 + /* gfx_v7_0_ring_emit_gds_switch */ + 7 + /* gfx_v7_0_ring_emit_hdp_flush */ +- 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */ ++ 5 + /* hdp invalidate */ + 12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */ + 7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */ + CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v7_0_ring_emit_vm_flush */ +@@ -5096,7 +5076,6 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { + .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush, + .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch, + .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush, +- .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate, + .test_ring = gfx_v7_0_ring_test_ring, + .test_ib = gfx_v7_0_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, +@@ -5116,7 +5095,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = { + .emit_frame_size = + 20 + /* gfx_v7_0_ring_emit_gds_switch */ + 7 + /* gfx_v7_0_ring_emit_hdp_flush */ +- 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */ ++ 5 + /* hdp invalidate */ + 7 + /* gfx_v7_0_ring_emit_pipeline_sync */ + CIK_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v7_0_ring_emit_vm_flush */ + 7 + 7 + 7, /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */ +@@ -5127,7 +5106,6 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = { + .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush, + .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch, + .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush, +- .emit_hdp_invalidate = gfx_v7_0_ring_emit_hdp_invalidate, + .test_ring = gfx_v7_0_ring_test_ring, + .test_ib = gfx_v7_0_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +index 4c6f5fc..21b30b9 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +@@ -6233,19 +6233,6 @@ static void gfx_v8_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) + EVENT_INDEX(0)); + } + +- +-static void gfx_v8_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) +-{ +- amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); +- amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | +- WRITE_DATA_DST_SEL(0) | +- WR_CONFIRM)); +- amdgpu_ring_write(ring, mmHDP_DEBUG0); +- amdgpu_ring_write(ring, 0); +- amdgpu_ring_write(ring, 1); +- +-} +- + static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, + struct amdgpu_ib *ib, + unsigned vmid, bool ctx_switch) +@@ -6890,7 +6877,6 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { + .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush, + .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch, + .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush, +- .emit_hdp_invalidate = gfx_v8_0_ring_emit_hdp_invalidate, + .test_ring = gfx_v8_0_ring_test_ring, + .test_ib = gfx_v8_0_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, +@@ -6913,7 +6899,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = { + .emit_frame_size = + 20 + /* gfx_v8_0_ring_emit_gds_switch */ + 7 + /* gfx_v8_0_ring_emit_hdp_flush */ +- 5 + /* gfx_v8_0_ring_emit_hdp_invalidate */ ++ 5 + /* hdp_invalidate */ + 7 + /* gfx_v8_0_ring_emit_pipeline_sync */ + VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v8_0_ring_emit_vm_flush */ + 7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_compute x3 for user fence, vm fence */ +@@ -6924,7 +6910,6 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = { + .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush, + .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch, + .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush, +- .emit_hdp_invalidate = gfx_v8_0_ring_emit_hdp_invalidate, + .test_ring = gfx_v8_0_ring_test_ring, + .test_ib = gfx_v8_0_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, +@@ -6944,7 +6929,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_kiq = { + .emit_frame_size = + 20 + /* gfx_v8_0_ring_emit_gds_switch */ + 7 + /* gfx_v8_0_ring_emit_hdp_flush */ +- 5 + /* gfx_v8_0_ring_emit_hdp_invalidate */ ++ 5 + /* hdp_invalidate */ + 7 + /* gfx_v8_0_ring_emit_pipeline_sync */ + 17 + /* gfx_v8_0_ring_emit_vm_flush */ + 7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_kiq x3 for user fence, vm fence */ +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index dd519e9..9c4544d 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -3591,14 +3591,6 @@ static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) + ref_and_mask, ref_and_mask, 0x20); + } + +-static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) +-{ +- struct amdgpu_device *adev = ring->adev; +- +- gfx_v9_0_write_data_to_reg(ring, 0, true, +- SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); +-} +- + static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, + struct amdgpu_ib *ib, + unsigned vmid, bool ctx_switch) +@@ -4325,7 +4317,6 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = { + .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, + .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, + .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, +- .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate, + .test_ring = gfx_v9_0_ring_test_ring, + .test_ib = gfx_v9_0_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, +@@ -4350,7 +4341,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { + .emit_frame_size = + 20 + /* gfx_v9_0_ring_emit_gds_switch */ + 7 + /* gfx_v9_0_ring_emit_hdp_flush */ +- 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */ ++ 5 + /* hdp invalidate */ + 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ + SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9 + /* gfx_v9_0_ring_emit_vm_flush */ + 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */ +@@ -4361,7 +4352,6 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { + .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush, + .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch, + .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush, +- .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate, + .test_ring = gfx_v9_0_ring_test_ring, + .test_ib = gfx_v9_0_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, +@@ -4382,7 +4372,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = { + .emit_frame_size = + 20 + /* gfx_v9_0_ring_emit_gds_switch */ + 7 + /* gfx_v9_0_ring_emit_hdp_flush */ +- 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */ ++ 5 + /* hdp invalidate */ + 7 + /* gfx_v9_0_ring_emit_pipeline_sync */ + SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9 + /* gfx_v9_0_ring_emit_vm_flush */ + 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */ +diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +index 439cff2..6316d0f 100644 +--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c ++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +@@ -289,13 +289,6 @@ static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring) + SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ + } + +-static void sdma_v2_4_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) +-{ +- amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | +- SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); +- amdgpu_ring_write(ring, mmHDP_DEBUG0); +- amdgpu_ring_write(ring, 1); +-} + /** + * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring + * +@@ -1200,7 +1193,7 @@ static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { + .set_wptr = sdma_v2_4_ring_set_wptr, + .emit_frame_size = + 6 + /* sdma_v2_4_ring_emit_hdp_flush */ +- 3 + /* sdma_v2_4_ring_emit_hdp_invalidate */ ++ 3 + /* hdp invalidate */ + 6 + /* sdma_v2_4_ring_emit_pipeline_sync */ + VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v2_4_ring_emit_vm_flush */ + 10 + 10 + 10, /* sdma_v2_4_ring_emit_fence x3 for user fence, vm fence */ +@@ -1210,7 +1203,6 @@ static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { + .emit_pipeline_sync = sdma_v2_4_ring_emit_pipeline_sync, + .emit_vm_flush = sdma_v2_4_ring_emit_vm_flush, + .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush, +- .emit_hdp_invalidate = sdma_v2_4_ring_emit_hdp_invalidate, + .test_ring = sdma_v2_4_ring_test_ring, + .test_ib = sdma_v2_4_ring_test_ib, + .insert_nop = sdma_v2_4_ring_insert_nop, +diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +index 2b2677a..e337c10 100644 +--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +@@ -460,14 +460,6 @@ static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) + SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ + } + +-static void sdma_v3_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) +-{ +- amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | +- SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); +- amdgpu_ring_write(ring, mmHDP_DEBUG0); +- amdgpu_ring_write(ring, 1); +-} +- + /** + * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring + * +@@ -1634,7 +1626,7 @@ static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { + .set_wptr = sdma_v3_0_ring_set_wptr, + .emit_frame_size = + 6 + /* sdma_v3_0_ring_emit_hdp_flush */ +- 3 + /* sdma_v3_0_ring_emit_hdp_invalidate */ ++ 3 + /* hdp invalidate */ + 6 + /* sdma_v3_0_ring_emit_pipeline_sync */ + 12 + /* sdma_v3_0_ring_emit_vm_flush */ + 10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */ +@@ -1644,7 +1636,6 @@ static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { + .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync, + .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush, + .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush, +- .emit_hdp_invalidate = sdma_v3_0_ring_emit_hdp_invalidate, + .test_ring = sdma_v3_0_ring_test_ring, + .test_ib = sdma_v3_0_ring_test_ib, + .insert_nop = sdma_v3_0_ring_insert_nop, +diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +index 34a5548..36fc45a 100644 +--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +@@ -375,16 +375,6 @@ static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) + SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ + } + +-static void sdma_v4_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) +-{ +- struct amdgpu_device *adev = ring->adev; +- +- amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | +- SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); +- amdgpu_ring_write(ring, SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE)); +- amdgpu_ring_write(ring, 1); +-} +- + /** + * sdma_v4_0_ring_emit_fence - emit a fence on the DMA ring + * +@@ -1583,7 +1573,7 @@ static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = { + .set_wptr = sdma_v4_0_ring_set_wptr, + .emit_frame_size = + 6 + /* sdma_v4_0_ring_emit_hdp_flush */ +- 3 + /* sdma_v4_0_ring_emit_hdp_invalidate */ ++ 3 + /* hdp invalidate */ + 6 + /* sdma_v4_0_ring_emit_pipeline_sync */ + SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v4_0_ring_emit_vm_flush */ + 10 + 10 + 10, /* sdma_v4_0_ring_emit_fence x3 for user fence, vm fence */ +@@ -1593,7 +1583,6 @@ static const struct amdgpu_ring_funcs sdma_v4_0_ring_funcs = { + .emit_pipeline_sync = sdma_v4_0_ring_emit_pipeline_sync, + .emit_vm_flush = sdma_v4_0_ring_emit_vm_flush, + .emit_hdp_flush = sdma_v4_0_ring_emit_hdp_flush, +- .emit_hdp_invalidate = sdma_v4_0_ring_emit_hdp_invalidate, + .test_ring = sdma_v4_0_ring_test_ring, + .test_ib = sdma_v4_0_ring_test_ib, + .insert_nop = sdma_v4_0_ring_insert_nop, +diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c +index 8f9509f..e59521b 100644 +--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c ++++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c +@@ -75,20 +75,6 @@ static void si_dma_ring_emit_ib(struct amdgpu_ring *ring, + + } + +-static void si_dma_ring_emit_hdp_flush(struct amdgpu_ring *ring) +-{ +- amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0)); +- amdgpu_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL)); +- amdgpu_ring_write(ring, 1); +-} +- +-static void si_dma_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) +-{ +- amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0)); +- amdgpu_ring_write(ring, (0xf << 16) | (HDP_DEBUG0)); +- amdgpu_ring_write(ring, 1); +-} +- + /** + * si_dma_ring_emit_fence - emit a fence on the DMA ring + * +@@ -772,8 +758,7 @@ static const struct amdgpu_ring_funcs si_dma_ring_funcs = { + .get_wptr = si_dma_ring_get_wptr, + .set_wptr = si_dma_ring_set_wptr, + .emit_frame_size = +- 3 + /* si_dma_ring_emit_hdp_flush */ +- 3 + /* si_dma_ring_emit_hdp_invalidate */ ++ 3 + 3 + /* hdp flush / invalidate */ + 6 + /* si_dma_ring_emit_pipeline_sync */ + SI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* si_dma_ring_emit_vm_flush */ + 9 + 9 + 9, /* si_dma_ring_emit_fence x3 for user fence, vm fence */ +@@ -782,8 +767,6 @@ static const struct amdgpu_ring_funcs si_dma_ring_funcs = { + .emit_fence = si_dma_ring_emit_fence, + .emit_pipeline_sync = si_dma_ring_emit_pipeline_sync, + .emit_vm_flush = si_dma_ring_emit_vm_flush, +- .emit_hdp_flush = si_dma_ring_emit_hdp_flush, +- .emit_hdp_invalidate = si_dma_ring_emit_hdp_invalidate, + .test_ring = si_dma_ring_test_ring, + .test_ib = si_dma_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, +diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +index 8ab10c2..948bb943 100644 +--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c ++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +@@ -464,32 +464,6 @@ static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq + } + + /** +- * uvd_v4_2_ring_emit_hdp_flush - emit an hdp flush +- * +- * @ring: amdgpu_ring pointer +- * +- * Emits an hdp flush. +- */ +-static void uvd_v4_2_ring_emit_hdp_flush(struct amdgpu_ring *ring) +-{ +- amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0)); +- amdgpu_ring_write(ring, 0); +-} +- +-/** +- * uvd_v4_2_ring_hdp_invalidate - emit an hdp invalidate +- * +- * @ring: amdgpu_ring pointer +- * +- * Emits an hdp invalidate. +- */ +-static void uvd_v4_2_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) +-{ +- amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0)); +- amdgpu_ring_write(ring, 1); +-} +- +-/** + * uvd_v4_2_ring_test_ring - register write test + * + * @ring: amdgpu_ring pointer +@@ -765,14 +739,10 @@ static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { + .set_wptr = uvd_v4_2_ring_set_wptr, + .parse_cs = amdgpu_uvd_ring_parse_cs, + .emit_frame_size = +- 2 + /* uvd_v4_2_ring_emit_hdp_flush */ +- 2 + /* uvd_v4_2_ring_emit_hdp_invalidate */ + 14, /* uvd_v4_2_ring_emit_fence x1 no user fence */ + .emit_ib_size = 4, /* uvd_v4_2_ring_emit_ib */ + .emit_ib = uvd_v4_2_ring_emit_ib, + .emit_fence = uvd_v4_2_ring_emit_fence, +- .emit_hdp_flush = uvd_v4_2_ring_emit_hdp_flush, +- .emit_hdp_invalidate = uvd_v4_2_ring_emit_hdp_invalidate, + .test_ring = uvd_v4_2_ring_test_ring, + .test_ib = amdgpu_uvd_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, +diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +index c1fe30c..6445d55 100644 +--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +@@ -479,32 +479,6 @@ static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq + } + + /** +- * uvd_v5_0_ring_emit_hdp_flush - emit an hdp flush +- * +- * @ring: amdgpu_ring pointer +- * +- * Emits an hdp flush. +- */ +-static void uvd_v5_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) +-{ +- amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0)); +- amdgpu_ring_write(ring, 0); +-} +- +-/** +- * uvd_v5_0_ring_hdp_invalidate - emit an hdp invalidate +- * +- * @ring: amdgpu_ring pointer +- * +- * Emits an hdp invalidate. +- */ +-static void uvd_v5_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) +-{ +- amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0)); +- amdgpu_ring_write(ring, 1); +-} +- +-/** + * uvd_v5_0_ring_test_ring - register write test + * + * @ring: amdgpu_ring pointer +@@ -873,14 +847,10 @@ static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { + .set_wptr = uvd_v5_0_ring_set_wptr, + .parse_cs = amdgpu_uvd_ring_parse_cs, + .emit_frame_size = +- 2 + /* uvd_v5_0_ring_emit_hdp_flush */ +- 2 + /* uvd_v5_0_ring_emit_hdp_invalidate */ + 14, /* uvd_v5_0_ring_emit_fence x1 no user fence */ + .emit_ib_size = 6, /* uvd_v5_0_ring_emit_ib */ + .emit_ib = uvd_v5_0_ring_emit_ib, + .emit_fence = uvd_v5_0_ring_emit_fence, +- .emit_hdp_flush = uvd_v5_0_ring_emit_hdp_flush, +- .emit_hdp_invalidate = uvd_v5_0_ring_emit_hdp_invalidate, + .test_ring = uvd_v5_0_ring_test_ring, + .test_ib = amdgpu_uvd_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, +diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +index 84c558d..ac76a76 100644 +--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +@@ -964,32 +964,6 @@ static void uvd_v6_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, + } + + /** +- * uvd_v6_0_ring_emit_hdp_flush - emit an hdp flush +- * +- * @ring: amdgpu_ring pointer +- * +- * Emits an hdp flush. +- */ +-static void uvd_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) +-{ +- amdgpu_ring_write(ring, PACKET0(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0)); +- amdgpu_ring_write(ring, 0); +-} +- +-/** +- * uvd_v6_0_ring_hdp_invalidate - emit an hdp invalidate +- * +- * @ring: amdgpu_ring pointer +- * +- * Emits an hdp invalidate. +- */ +-static void uvd_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) +-{ +- amdgpu_ring_write(ring, PACKET0(mmHDP_DEBUG0, 0)); +- amdgpu_ring_write(ring, 1); +-} +- +-/** + * uvd_v6_0_ring_test_ring - register write test + * + * @ring: amdgpu_ring pointer +@@ -1556,15 +1530,11 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = { + .set_wptr = uvd_v6_0_ring_set_wptr, + .parse_cs = amdgpu_uvd_ring_parse_cs, + .emit_frame_size = +- 2 + /* uvd_v6_0_ring_emit_hdp_flush */ +- 2 + /* uvd_v6_0_ring_emit_hdp_invalidate */ + 10 + /* uvd_v6_0_ring_emit_pipeline_sync */ + 14, /* uvd_v6_0_ring_emit_fence x1 no user fence */ + .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */ + .emit_ib = uvd_v6_0_ring_emit_ib, + .emit_fence = uvd_v6_0_ring_emit_fence, +- .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush, +- .emit_hdp_invalidate = uvd_v6_0_ring_emit_hdp_invalidate, + .test_ring = uvd_v6_0_ring_test_ring, + .test_ib = amdgpu_uvd_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, +@@ -1582,8 +1552,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = { + .get_wptr = uvd_v6_0_ring_get_wptr, + .set_wptr = uvd_v6_0_ring_set_wptr, + .emit_frame_size = +- 2 + /* uvd_v6_0_ring_emit_hdp_flush */ +- 2 + /* uvd_v6_0_ring_emit_hdp_invalidate */ ++ 6 + 6 + /* hdp flush / invalidate */ + 10 + /* uvd_v6_0_ring_emit_pipeline_sync */ + 20 + /* uvd_v6_0_ring_emit_vm_flush */ + 14 + 14, /* uvd_v6_0_ring_emit_fence x2 vm fence */ +@@ -1592,8 +1561,6 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = { + .emit_fence = uvd_v6_0_ring_emit_fence, + .emit_vm_flush = uvd_v6_0_ring_emit_vm_flush, + .emit_pipeline_sync = uvd_v6_0_ring_emit_pipeline_sync, +- .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush, +- .emit_hdp_invalidate = uvd_v6_0_ring_emit_hdp_invalidate, + .test_ring = uvd_v6_0_ring_test_ring, + .test_ib = amdgpu_uvd_ring_test_ib, + .insert_nop = amdgpu_ring_insert_nop, +diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +index 241e730..d317c76 100644 +--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +@@ -1136,37 +1136,6 @@ static void uvd_v7_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, + } + + /** +- * uvd_v7_0_ring_emit_hdp_flush - emit an hdp flush +- * +- * @ring: amdgpu_ring pointer +- * +- * Emits an hdp flush. +- */ +-static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) +-{ +- struct amdgpu_device *adev = ring->adev; +- +- amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(NBIF, 0, +- mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0)); +- amdgpu_ring_write(ring, 0); +-} +- +-/** +- * uvd_v7_0_ring_hdp_invalidate - emit an hdp invalidate +- * +- * @ring: amdgpu_ring pointer +- * +- * Emits an hdp invalidate. +- */ +-static void uvd_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) +-{ +- struct amdgpu_device *adev = ring->adev; +- +- amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 0)); +- amdgpu_ring_write(ring, 1); +-} +- +-/** + * uvd_v7_0_ring_test_ring - register write test + * + * @ring: amdgpu_ring pointer +@@ -1693,16 +1662,13 @@ static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = { + .get_wptr = uvd_v7_0_ring_get_wptr, + .set_wptr = uvd_v7_0_ring_set_wptr, + .emit_frame_size = +- 2 + /* uvd_v7_0_ring_emit_hdp_flush */ +- 2 + /* uvd_v7_0_ring_emit_hdp_invalidate */ ++ 6 + 6 + /* hdp flush / invalidate */ + SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 16 + /* uvd_v7_0_ring_emit_vm_flush */ + 14 + 14, /* uvd_v7_0_ring_emit_fence x2 vm fence */ + .emit_ib_size = 8, /* uvd_v7_0_ring_emit_ib */ + .emit_ib = uvd_v7_0_ring_emit_ib, + .emit_fence = uvd_v7_0_ring_emit_fence, + .emit_vm_flush = uvd_v7_0_ring_emit_vm_flush, +- .emit_hdp_flush = uvd_v7_0_ring_emit_hdp_flush, +- .emit_hdp_invalidate = uvd_v7_0_ring_emit_hdp_invalidate, + .test_ring = uvd_v7_0_ring_test_ring, + .test_ib = amdgpu_uvd_ring_test_ib, + .insert_nop = uvd_v7_0_ring_insert_nop, +@@ -1722,6 +1688,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = { + .get_wptr = uvd_v7_0_enc_ring_get_wptr, + .set_wptr = uvd_v7_0_enc_ring_set_wptr, + .emit_frame_size = ++ 3 + 3 + /* hdp flush / invalidate */ + SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 8 + /* uvd_v7_0_enc_ring_emit_vm_flush */ + 5 + 5 + /* uvd_v7_0_enc_ring_emit_fence x2 vm fence */ + 1, /* uvd_v7_0_enc_ring_insert_end */ +diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +index bdc0052..d8bfeb2 100644 +--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +@@ -832,21 +832,6 @@ static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 + } + + /** +- * vcn_v1_0_dec_ring_hdp_invalidate - emit an hdp invalidate +- * +- * @ring: amdgpu_ring pointer +- * +- * Emits an hdp invalidate. +- */ +-static void vcn_v1_0_dec_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) +-{ +- struct amdgpu_device *adev = ring->adev; +- +- amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 0)); +- amdgpu_ring_write(ring, 1); +-} +- +-/** + * vcn_v1_0_dec_ring_emit_ib - execute indirect buffer + * + * @ring: amdgpu_ring pointer +@@ -1118,7 +1103,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = { + .get_wptr = vcn_v1_0_dec_ring_get_wptr, + .set_wptr = vcn_v1_0_dec_ring_set_wptr, + .emit_frame_size = +- 2 + /* vcn_v1_0_dec_ring_emit_hdp_invalidate */ ++ 6 + 6 + /* hdp invalidate / flush */ + SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 16 + /* vcn_v1_0_dec_ring_emit_vm_flush */ + 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */ + 6, +@@ -1126,7 +1111,6 @@ static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = { + .emit_ib = vcn_v1_0_dec_ring_emit_ib, + .emit_fence = vcn_v1_0_dec_ring_emit_fence, + .emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush, +- .emit_hdp_invalidate = vcn_v1_0_dec_ring_emit_hdp_invalidate, + .test_ring = amdgpu_vcn_dec_ring_test_ring, + .test_ib = amdgpu_vcn_dec_ring_test_ib, + .insert_nop = vcn_v1_0_ring_insert_nop, +-- +2.7.4 + |