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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3228-drm-amdgpu-add-optional-ring-to-_hdp-callbacks.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3228-drm-amdgpu-add-optional-ring-to-_hdp-callbacks.patch305
1 files changed, 305 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3228-drm-amdgpu-add-optional-ring-to-_hdp-callbacks.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3228-drm-amdgpu-add-optional-ring-to-_hdp-callbacks.patch
new file mode 100644
index 00000000..a1e15429
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3228-drm-amdgpu-add-optional-ring-to-_hdp-callbacks.patch
@@ -0,0 +1,305 @@
+From 91ce76a217a2db0041bc3288f71dd13c91b16c55 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Fri, 19 Jan 2018 14:17:40 +0100
+Subject: [PATCH 3228/4131] drm/amdgpu: add optional ring to *_hdp callbacks
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This adds an optional ring to the invalidate_hdp and flush_hdp
+callbacks. If the ring isn't specified or the emit_wreg function not
+available the HDP operation will be done with the CPU otherwise by
+writing on the ring.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Acked-by: Chunming Zhou <david1.zhou@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h | 11 ++++++-----
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 4 ++--
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 ++--
+ drivers/gpu/drm/amd/amdgpu/cik.c | 21 +++++++++++++++------
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +-
+ drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 11 +++++++++--
+ drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 9 +++++++--
+ drivers/gpu/drm/amd/amdgpu/si.c | 21 +++++++++++++++------
+ drivers/gpu/drm/amd/amdgpu/soc15.c | 13 +++++++++----
+ drivers/gpu/drm/amd/amdgpu/vi.c | 21 +++++++++++++++------
+ 10 files changed, 81 insertions(+), 36 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+index 434f246..6b57458 100755
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+@@ -1237,9 +1237,10 @@ struct amdgpu_asic_funcs {
+ /* get config memsize register */
+ u32 (*get_config_memsize)(struct amdgpu_device *adev);
+ /* flush hdp write queue */
+- void (*flush_hdp)(struct amdgpu_device *adev);
++ void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
+ /* invalidate hdp read cache */
+- void (*invalidate_hdp)(struct amdgpu_device *adev);
++ void (*invalidate_hdp)(struct amdgpu_device *adev,
++ struct amdgpu_ring *ring);
+ };
+
+ /*
+@@ -1422,7 +1423,7 @@ struct amdgpu_nbio_funcs {
+ u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);
+ u32 (*get_rev_id)(struct amdgpu_device *adev);
+ void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);
+- void (*hdp_flush)(struct amdgpu_device *adev);
++ void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring);
+ u32 (*get_memsize)(struct amdgpu_device *adev);
+ void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,
+ bool use_doorbell, int doorbell_index);
+@@ -1835,8 +1836,8 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
+ #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
+ #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
+ #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
+-#define amdgpu_asic_flush_hdp(adev) (adev)->asic_funcs->flush_hdp((adev))
+-#define amdgpu_asic_invalidate_hdp(adev) (adev)->asic_funcs->invalidate_hdp((adev))
++#define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r))
++#define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r))
+ #define amdgpu_gmc_flush_gpu_tlb(adev, vmid) (adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid))
+ #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, pasid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (pasid), (addr))
+ #define amdgpu_gmc_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gmc.gmc_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+index 18d2387..56b0b30 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+@@ -247,7 +247,7 @@ int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
+ }
+ }
+ mb();
+- amdgpu_asic_flush_hdp(adev);
++ amdgpu_asic_flush_hdp(adev, NULL);
+ amdgpu_gmc_flush_gpu_tlb(adev, 0);
+ return 0;
+ }
+@@ -330,7 +330,7 @@ int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
+ return r;
+
+ mb();
+- amdgpu_asic_flush_hdp(adev);
++ amdgpu_asic_flush_hdp(adev, NULL);
+ amdgpu_gmc_flush_gpu_tlb(adev, 0);
+ return 0;
+ }
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index 5cca5af..59abde3 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -859,7 +859,7 @@ int amdgpu_vm_update_directories(struct amdgpu_device *adev,
+ if (vm->use_cpu_for_update) {
+ /* Flush HDP */
+ mb();
+- amdgpu_asic_flush_hdp(adev);
++ amdgpu_asic_flush_hdp(adev, NULL);
+ } else if (params.ib->length_dw == 0) {
+ amdgpu_job_free(job);
+ } else {
+@@ -1467,7 +1467,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
+ if (vm->use_cpu_for_update) {
+ /* Flush HDP */
+ mb();
+- amdgpu_asic_flush_hdp(adev);
++ amdgpu_asic_flush_hdp(adev, NULL);
+ }
+
+ spin_lock(&vm->status_lock);
+diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
+index 204ce80..4324184 100644
+--- a/drivers/gpu/drm/amd/amdgpu/cik.c
++++ b/drivers/gpu/drm/amd/amdgpu/cik.c
+@@ -1715,16 +1715,25 @@ static void cik_detect_hw_virtualization(struct amdgpu_device *adev)
+ adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
+ }
+
+-static void cik_flush_hdp(struct amdgpu_device *adev)
++static void cik_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
+ {
+- WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
+- RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL);
++ if (!ring || !ring->funcs->emit_wreg) {
++ WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
++ RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL);
++ } else {
++ amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
++ }
+ }
+
+-static void cik_invalidate_hdp(struct amdgpu_device *adev)
++static void cik_invalidate_hdp(struct amdgpu_device *adev,
++ struct amdgpu_ring *ring)
+ {
+- WREG32(mmHDP_DEBUG0, 1);
+- RREG32(mmHDP_DEBUG0);
++ if (!ring || !ring->funcs->emit_wreg) {
++ WREG32(mmHDP_DEBUG0, 1);
++ RREG32(mmHDP_DEBUG0);
++ } else {
++ amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1);
++ }
+ }
+
+ static const struct amdgpu_asic_funcs cik_asic_funcs =
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index bd17336..44eb22a 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -1012,7 +1012,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
+ WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
+
+ /* After HDP is initialized, flush HDP.*/
+- adev->nbio_funcs->hdp_flush(adev);
++ adev->nbio_funcs->hdp_flush(adev, NULL);
+
+ if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
+ value = false;
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+index d4da663d..2daeef6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+@@ -53,9 +53,16 @@ static void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable)
+ WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
+ }
+
+-static void nbio_v6_1_hdp_flush(struct amdgpu_device *adev)
++static void nbio_v6_1_hdp_flush(struct amdgpu_device *adev,
++ struct amdgpu_ring *ring)
+ {
+- WREG32_SOC15_NO_KIQ(NBIO, 0, mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL, 0);
++ if (!ring || !ring->funcs->emit_wreg)
++ WREG32_SOC15_NO_KIQ(NBIO, 0,
++ mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL,
++ 0);
++ else
++ amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
++ NBIO, 0, mmBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL), 0);
+ }
+
+ static u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev)
+diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+index 17a9131..cd10c76 100644
+--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
+@@ -53,9 +53,14 @@ static void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable)
+ WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
+ }
+
+-static void nbio_v7_0_hdp_flush(struct amdgpu_device *adev)
++static void nbio_v7_0_hdp_flush(struct amdgpu_device *adev,
++ struct amdgpu_ring *ring)
+ {
+- WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
++ if (!ring || !ring->funcs->emit_wreg)
++ WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
++ else
++ amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
++ NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
+ }
+
+ static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
+diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
+index 44ead2d..f606b71 100644
+--- a/drivers/gpu/drm/amd/amdgpu/si.c
++++ b/drivers/gpu/drm/amd/amdgpu/si.c
+@@ -1296,16 +1296,25 @@ static void si_set_pcie_lanes(struct amdgpu_device *adev, int lanes)
+ WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
+ }
+
+-static void si_flush_hdp(struct amdgpu_device *adev)
++static void si_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
+ {
+- WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
+- RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL);
++ if (!ring || !ring->funcs->emit_wreg) {
++ WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
++ RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL);
++ } else {
++ amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
++ }
+ }
+
+-static void si_invalidate_hdp(struct amdgpu_device *adev)
++static void si_invalidate_hdp(struct amdgpu_device *adev,
++ struct amdgpu_ring *ring)
+ {
+- WREG32(mmHDP_DEBUG0, 1);
+- RREG32(mmHDP_DEBUG0);
++ if (!ring || !ring->funcs->emit_wreg) {
++ WREG32(mmHDP_DEBUG0, 1);
++ RREG32(mmHDP_DEBUG0);
++ } else {
++ amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1);
++ }
+ }
+
+ static const struct amdgpu_asic_funcs si_asic_funcs =
+diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
+index ad39ffd..04a471b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
+@@ -583,14 +583,19 @@ static uint32_t soc15_get_rev_id(struct amdgpu_device *adev)
+ return adev->nbio_funcs->get_rev_id(adev);
+ }
+
+-static void soc15_flush_hdp(struct amdgpu_device *adev)
++static void soc15_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
+ {
+- adev->nbio_funcs->hdp_flush(adev);
++ adev->nbio_funcs->hdp_flush(adev, ring);
+ }
+
+-static void soc15_invalidate_hdp(struct amdgpu_device *adev)
++static void soc15_invalidate_hdp(struct amdgpu_device *adev,
++ struct amdgpu_ring *ring)
+ {
+- WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
++ if (!ring || !ring->funcs->emit_wreg)
++ WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
++ else
++ amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
++ HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
+ }
+
+ static const struct amdgpu_asic_funcs soc15_asic_funcs =
+diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
+index 58572e7..ae21f3f 100644
+--- a/drivers/gpu/drm/amd/amdgpu/vi.c
++++ b/drivers/gpu/drm/amd/amdgpu/vi.c
+@@ -899,16 +899,25 @@ static uint32_t vi_get_rev_id(struct amdgpu_device *adev)
+ >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT;
+ }
+
+-static void vi_flush_hdp(struct amdgpu_device *adev)
++static void vi_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
+ {
+- WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
+- RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL);
++ if (!ring || !ring->funcs->emit_wreg) {
++ WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
++ RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL);
++ } else {
++ amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
++ }
+ }
+
+-static void vi_invalidate_hdp(struct amdgpu_device *adev)
++static void vi_invalidate_hdp(struct amdgpu_device *adev,
++ struct amdgpu_ring *ring)
+ {
+- WREG32(mmHDP_DEBUG0, 1);
+- RREG32(mmHDP_DEBUG0);
++ if (!ring || !ring->funcs->emit_wreg) {
++ WREG32(mmHDP_DEBUG0, 1);
++ RREG32(mmHDP_DEBUG0);
++ } else {
++ amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1);
++ }
+ }
+
+ static const struct amdgpu_asic_funcs vi_asic_funcs =
+--
+2.7.4
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-05-01 04:30:20 +0000