1 files changed, 209 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3215-drm-amd-dc-include-new-ip-and-ip_offset-headers.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3215-drm-amd-dc-include-new-ip-and-ip_offset-headers.patch
new file mode 100644
index 00000000..5aa273e6
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3215-drm-amd-dc-include-new-ip-and-ip_offset-headers.patch
@@ -0,0 +1,209 @@
+From 66187520b5029e01b73af0c9711d850567b53d80 Mon Sep 17 00:00:00 2001
+From: Hawking Zhang <Hawking.Zhang@amd.com>
+Date: Mon, 15 Jan 2018 15:43:23 +0800
+Subject: [PATCH 3215/4131] drm/amd/dc: include new ip and ip_offset headers
+
+Change-Id: I886747dbfea9eec4f3f7f8af8ce99f04c2a8f1b7
+Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
+Acked-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c                | 3 ++-
+ drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c      | 3 ++-
+ drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c          | 3 ++-
+ drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c  | 3 ++-
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c            | 3 ++-
+ drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c   | 3 ++-
+ drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c | 3 ++-
+ drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c     | 3 ++-
+ drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c   | 3 ++-
+ drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c     | 3 ++-
+ drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c       | 3 ++-
+ drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c   | 3 ++-
+ drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c     | 3 ++-
+ 13 files changed, 26 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+index 6f67892..7bf1d67 100644
+--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+@@ -61,7 +61,8 @@
+ 
+ #include "dcn/dcn_1_0_offset.h"
+ #include "dcn/dcn_1_0_sh_mask.h"
+-#include "soc15ip.h"
++#include "soc15_hw_ip.h"
++#include "vega10_ip_offset.h"
+ 
+ #include "soc15_common.h"
+ #endif
+diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
+index 75d0297..e96ff86 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
+@@ -33,7 +33,8 @@
+ 
+ #include "dce/dce_12_0_offset.h"
+ #include "dce/dce_12_0_sh_mask.h"
+-#include "soc15ip.h"
++#include "soc15_hw_ip.h"
++#include "vega10_ip_offset.h"
+ #include "reg_helper.h"
+ 
+ #define CTX \
+diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+index 5aab01d..a8725ac 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+@@ -56,7 +56,8 @@
+ 
+ #include "dce/dce_12_0_offset.h"
+ #include "dce/dce_12_0_sh_mask.h"
+-#include "soc15ip.h"
++#include "soc15_hw_ip.h"
++#include "vega10_ip_offset.h"
+ #include "nbio/nbio_6_1_offset.h"
+ #include "reg_helper.h"
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+index 0aa60e5..7bee781 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+@@ -27,7 +27,8 @@
+ 
+ #include "dce/dce_12_0_offset.h"
+ #include "dce/dce_12_0_sh_mask.h"
+-#include "soc15ip.h"
++#include "soc15_hw_ip.h"
++#include "vega10_ip_offset.h"
+ 
+ #include "dc_types.h"
+ #include "dc_bios_types.h"
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+index 4610d9c..66af05b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+@@ -50,7 +50,8 @@
+ #include "dcn10_hubp.h"
+ #include "dcn10_hubbub.h"
+ 
+-#include "soc15ip.h"
++#include "soc15_hw_ip.h"
++#include "vega10_ip_offset.h"
+ 
+ #include "dcn/dcn_1_0_offset.h"
+ #include "dcn/dcn_1_0_sh_mask.h"
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c
+index 0c2314e..ea3f888 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c
+@@ -36,7 +36,8 @@
+ 
+ #include "dce/dce_12_0_offset.h"
+ #include "dce/dce_12_0_sh_mask.h"
+-#include "soc15ip.h"
++#include "soc15_hw_ip.h"
++#include "vega10_ip_offset.h"
+ 
+ #define block HPD
+ #define reg_num 0
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
+index a225b02..39ef5c7 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
+@@ -35,7 +35,8 @@
+ 
+ #include "dce/dce_12_0_offset.h"
+ #include "dce/dce_12_0_sh_mask.h"
+-#include "soc15ip.h"
++#include "soc15_hw_ip.h"
++#include "vega10_ip_offset.h"
+ 
+ /* begin *********************
+  * macros to expend register list macro defined in HW object header file */
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c
+index 5235f69..32aa47a 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c
+@@ -36,7 +36,8 @@
+ 
+ #include "dcn/dcn_1_0_offset.h"
+ #include "dcn/dcn_1_0_sh_mask.h"
+-#include "soc15ip.h"
++#include "soc15_hw_ip.h"
++#include "vega10_ip_offset.h"
+ 
+ #define block HPD
+ #define reg_num 0
+diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
+index 3478648..fecc8688 100644
+--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
++++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c
+@@ -35,7 +35,8 @@
+ 
+ #include "dcn/dcn_1_0_offset.h"
+ #include "dcn/dcn_1_0_sh_mask.h"
+-#include "soc15ip.h"
++#include "soc15_hw_ip.h"
++#include "vega10_ip_offset.h"
+ 
+ /* begin *********************
+  * macros to expend register list macro defined in HW object header file */
+diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c
+index a401636..0e7b182 100644
+--- a/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c
++++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c
+@@ -38,7 +38,8 @@
+ 
+ #include "dce/dce_12_0_offset.h"
+ #include "dce/dce_12_0_sh_mask.h"
+-#include "soc15ip.h"
++#include "soc15_hw_ip.h"
++#include "vega10_ip_offset.h"
+ 
+ /* begin *********************
+  * macros to expend register list macro defined in HW object header file */
+diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c b/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c
+index bed7cc3..e44a890 100644
+--- a/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c
++++ b/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c
+@@ -38,7 +38,8 @@
+ 
+ #include "dcn/dcn_1_0_offset.h"
+ #include "dcn/dcn_1_0_sh_mask.h"
+-#include "soc15ip.h"
++#include "soc15_hw_ip.h"
++#include "vega10_ip_offset.h"
+ 
+ /* begin *********************
+  * macros to expend register list macro defined in HW object header file */
+diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
+index 66d5258..1ea7256 100644
+--- a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
++++ b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
+@@ -32,7 +32,8 @@
+ 
+ #include "dce/dce_12_0_offset.h"
+ #include "dce/dce_12_0_sh_mask.h"
+-#include "soc15ip.h"
++#include "soc15_hw_ip.h"
++#include "vega10_ip_offset.h"
+ 
+ #include "ivsrcid/ivsrcid_vislands30.h"
+ 
+diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
+index 7f7db66..e04ae49 100644
+--- a/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
++++ b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c
+@@ -31,7 +31,8 @@
+ 
+ #include "dcn/dcn_1_0_offset.h"
+ #include "dcn/dcn_1_0_sh_mask.h"
+-#include "soc15ip.h"
++#include "soc15_hw_ip.h"
++#include "vega10_ip_offset.h"
+ 
+ #include "irq_service_dcn10.h"
+ 
+-- 
+2.7.4
+