diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3198-drm-amdgpu-wire-up-emit_wreg-for-UVD-v7.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3198-drm-amdgpu-wire-up-emit_wreg-for-UVD-v7.patch | 99 |
1 files changed, 99 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3198-drm-amdgpu-wire-up-emit_wreg-for-UVD-v7.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3198-drm-amdgpu-wire-up-emit_wreg-for-UVD-v7.patch new file mode 100644 index 00000000..d289988e --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3198-drm-amdgpu-wire-up-emit_wreg-for-UVD-v7.patch @@ -0,0 +1,99 @@ +From 0e81a05cea3041ae4838a2d0d0e52ebb8965c53d Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com> +Date: Fri, 12 Jan 2018 16:34:44 +0100 +Subject: [PATCH 3198/4131] drm/amdgpu: wire up emit_wreg for UVD v7 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Needed for vm_flush unification. + +Signed-off-by: Christian König <christian.koenig@amd.com> +Acked-by: Chunming Zhou <david1.zhou@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 24 +++++++++++++++++------- + 1 file changed, 17 insertions(+), 7 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +index 44f1a3d..42c4296 100644 +--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +@@ -1255,17 +1255,17 @@ static void uvd_v7_0_enc_ring_emit_ib(struct amdgpu_ring *ring, + amdgpu_ring_write(ring, ib->length_dw); + } + +-static void uvd_v7_0_vm_reg_write(struct amdgpu_ring *ring, +- uint32_t data0, uint32_t data1) ++static void uvd_v7_0_ring_emit_wreg(struct amdgpu_ring *ring, ++ uint32_t reg, uint32_t val) + { + struct amdgpu_device *adev = ring->adev; + + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); +- amdgpu_ring_write(ring, data0); ++ amdgpu_ring_write(ring, reg << 2); + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); +- amdgpu_ring_write(ring, data1); ++ amdgpu_ring_write(ring, val); + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); + amdgpu_ring_write(ring, 8); +@@ -1305,11 +1305,11 @@ static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, + + data0 = (hub->ctx0_ptb_addr_hi32 + vmid * 2) << 2; + data1 = upper_32_bits(pd_addr); +- uvd_v7_0_vm_reg_write(ring, data0, data1); ++ uvd_v7_0_ring_emit_wreg(ring, data0, data1); + + data0 = (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2; + data1 = lower_32_bits(pd_addr); +- uvd_v7_0_vm_reg_write(ring, data0, data1); ++ uvd_v7_0_ring_emit_wreg(ring, data0, data1); + + data0 = (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2; + data1 = lower_32_bits(pd_addr); +@@ -1319,7 +1319,7 @@ static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, + /* flush TLB */ + data0 = (hub->vm_inv_eng0_req + eng) << 2; + data1 = req; +- uvd_v7_0_vm_reg_write(ring, data0, data1); ++ uvd_v7_0_ring_emit_wreg(ring, data0, data1); + + /* wait for flush */ + data0 = (hub->vm_inv_eng0_ack + eng) << 2; +@@ -1380,6 +1380,14 @@ static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, + amdgpu_ring_write(ring, 1 << vmid); + } + ++static void uvd_v7_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, ++ uint32_t reg, uint32_t val) ++{ ++ amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE); ++ amdgpu_ring_write(ring, reg << 2); ++ amdgpu_ring_write(ring, val); ++} ++ + #if 0 + static bool uvd_v7_0_is_idle(void *handle) + { +@@ -1730,6 +1738,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = { + .pad_ib = amdgpu_ring_generic_pad_ib, + .begin_use = amdgpu_uvd_ring_begin_use, + .end_use = amdgpu_uvd_ring_end_use, ++ .emit_wreg = uvd_v7_0_ring_emit_wreg, + }; + + static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = { +@@ -1756,6 +1765,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = { + .pad_ib = amdgpu_ring_generic_pad_ib, + .begin_use = amdgpu_uvd_ring_begin_use, + .end_use = amdgpu_uvd_ring_end_use, ++ .emit_wreg = uvd_v7_0_enc_ring_emit_wreg, + }; + + static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev) +-- +2.7.4 + |