diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3175-drm-amd-pp-Add-OD-driver-clock-voltage-display-on-sm.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3175-drm-amd-pp-Add-OD-driver-clock-voltage-display-on-sm.patch | 69 |
1 files changed, 69 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3175-drm-amd-pp-Add-OD-driver-clock-voltage-display-on-sm.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3175-drm-amd-pp-Add-OD-driver-clock-voltage-display-on-sm.patch new file mode 100644 index 00000000..d08cac93 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3175-drm-amd-pp-Add-OD-driver-clock-voltage-display-on-sm.patch @@ -0,0 +1,69 @@ +From e2fd84efdb8e247bfe7b099a0fdf8761e428ca76 Mon Sep 17 00:00:00 2001 +From: Rex Zhu <Rex.Zhu@amd.com> +Date: Mon, 15 Jan 2018 18:01:35 +0800 +Subject: [PATCH 3175/4131] drm/amd/pp: Add OD driver clock/voltage display on + smu7 + +Change-Id: If3b5a34363ecab35d82c76c1d9a29c857442b96b +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> +--- + drivers/gpu/drm/amd/include/kgd_pp_interface.h | 2 ++ + drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 21 +++++++++++++++++++++ + 2 files changed, 23 insertions(+) + +diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h +index 68f2c84..103837c 100644 +--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h ++++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h +@@ -107,6 +107,8 @@ enum pp_clock_type { + PP_SCLK, + PP_MCLK, + PP_PCIE, ++ OD_SCLK, ++ OD_MCLK, + }; + + enum amd_pp_sensors { +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +index 8e0591b..a64a7c2 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +@@ -4358,6 +4358,9 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr, + struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); + struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); + struct smu7_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table); ++ struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table); ++ struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels); ++ struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels); + int i, now, size = 0; + uint32_t clock, pcie_speed; + +@@ -4410,6 +4413,24 @@ static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr, + (pcie_table->dpm_levels[i].value == 2) ? "8.0GT/s, x16" : "", + (i == now) ? "*" : ""); + break; ++ case OD_SCLK: ++ if (hwmgr->od_enabled) { ++ size = sprintf(buf, "%s: \n", "OD_SCLK"); ++ for (i = 0; i < odn_sclk_table->num_of_pl; i++) ++ size += sprintf(buf + size, "%d: %10uMhz %10u mV\n", ++ i, odn_sclk_table->entries[i].clock / 100, ++ odn_sclk_table->entries[i].vddc); ++ } ++ break; ++ case OD_MCLK: ++ if (hwmgr->od_enabled) { ++ size = sprintf(buf, "%s: \n", "OD_MCLK"); ++ for (i = 0; i < odn_mclk_table->num_of_pl; i++) ++ size += sprintf(buf + size, "%d: %10uMhz %10u mV\n", ++ i, odn_mclk_table->entries[i].clock / 100, ++ odn_mclk_table->entries[i].vddc); ++ } ++ break; + default: + break; + } +-- +2.7.4 + |