diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3173-drm-amd-pp-Add-a-new-pp-feature-mask-bit-for-OD-feat.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3173-drm-amd-pp-Add-a-new-pp-feature-mask-bit-for-OD-feat.patch | 122 |
1 files changed, 122 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3173-drm-amd-pp-Add-a-new-pp-feature-mask-bit-for-OD-feat.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3173-drm-amd-pp-Add-a-new-pp-feature-mask-bit-for-OD-feat.patch new file mode 100644 index 00000000..2ae9d49e --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3173-drm-amd-pp-Add-a-new-pp-feature-mask-bit-for-OD-feat.patch @@ -0,0 +1,122 @@ +From 4aa708f5813fc6cf47a2183c1e6924ca03808062 Mon Sep 17 00:00:00 2001 +From: Rex Zhu <Rex.Zhu@amd.com> +Date: Thu, 4 Jan 2018 16:42:06 +0800 +Subject: [PATCH 3173/4131] drm/amd/pp: Add a new pp feature mask bit for OD + feature + +when this bit was set on module load, +driver will allow the user over/under gpu +clock and voltage through sysfs. + +by default, this bit was not set. + +Change-Id: I491c468eb0a8c1ab1accf0f390a9bc73c23301ca +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +- + drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 3 +++ + drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 6 ++---- + drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 7 ++----- + drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 2 ++ + 5 files changed, 10 insertions(+), 10 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +index 3f9a5fc..daa24ce 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +@@ -121,7 +121,7 @@ uint amdgpu_pg_mask = 0xffffffff; + uint amdgpu_sdma_phase_quantum = 32; + char *amdgpu_disable_cu = NULL; + char *amdgpu_virtual_display = NULL; +-uint amdgpu_pp_feature_mask = 0xffffffff; ++uint amdgpu_pp_feature_mask = 0x3fff; + int amdgpu_ngg = 0; + int amdgpu_prim_buf_per_se = 0; + int amdgpu_pos_buf_per_se = 0; +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c +index e35bdc5..2690446 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c +@@ -935,6 +935,9 @@ int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr) + PHM_PlatformCaps_CAC); + } + ++ if (hwmgr->feature_mask & PP_OVERDRIVE_MASK) ++ hwmgr->od_enabled = true; ++ + return 0; + } + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +index ac27219..0a93020 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +@@ -3575,8 +3575,7 @@ static int smu7_populate_and_upload_sclk_mclk_dpm_levels( + dpm_table->sclk_table.dpm_levels + [dpm_table->sclk_table.count - 1].value = sclk; + +- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) || +- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) { ++ if (hwmgr->od_enabled) { + /* Need to do calculation based on the golden DPM table + * as the Heatmap GPU Clock axis is also based on the default values + */ +@@ -3621,8 +3620,7 @@ static int smu7_populate_and_upload_sclk_mclk_dpm_levels( + dpm_table->mclk_table.dpm_levels + [dpm_table->mclk_table.count - 1].value = mclk; + +- if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinACSupport) || +- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_OD6PlusinDCSupport)) { ++ if (hwmgr->od_enabled) { + + PP_ASSERT_WITH_CODE( + (golden_dpm_table->mclk_table.dpm_levels +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +index e10597e..72f6b42 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +@@ -3399,8 +3399,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels( + dpm_table-> + gfx_table.dpm_levels[dpm_table->gfx_table.count - 1]. + value = sclk; +- if (PP_CAP(PHM_PlatformCaps_OD6PlusinACSupport) || +- PP_CAP(PHM_PlatformCaps_OD6PlusinDCSupport)) { ++ if (hwmgr->od_enabled) { + /* Need to do calculation based on the golden DPM table + * as the Heatmap GPU Clock axis is also based on + * the default values +@@ -3454,9 +3453,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels( + mem_table.dpm_levels[dpm_table->mem_table.count - 1]. + value = mclk; + +- if (PP_CAP(PHM_PlatformCaps_OD6PlusinACSupport) || +- PP_CAP(PHM_PlatformCaps_OD6PlusinDCSupport)) { +- ++ if (hwmgr->od_enabled) { + PP_ASSERT_WITH_CODE( + golden_dpm_table->mem_table.dpm_levels + [golden_dpm_table->mem_table.count - 1].value, +diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +index 6d8183d..7caab09 100644 +--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h ++++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +@@ -84,6 +84,7 @@ enum PP_FEATURE_MASK { + PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800, + PP_SOCCLK_DPM_MASK = 0x1000, + PP_DCEFCLK_DPM_MASK = 0x2000, ++ PP_OVERDRIVE_MASK = 0x4000, + }; + + enum PHM_BackEnd_Magic { +@@ -755,6 +756,7 @@ struct pp_hwmgr { + uint32_t power_profile_mode; + uint32_t pstate_sclk; + uint32_t pstate_mclk; ++ bool od_enabled; + }; + + struct cgs_irq_src_funcs { +-- +2.7.4 + |