diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3169-drm-amd-pp-Store-stable-Pstate-clocks.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3169-drm-amd-pp-Store-stable-Pstate-clocks.patch | 133 |
1 files changed, 133 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3169-drm-amd-pp-Store-stable-Pstate-clocks.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3169-drm-amd-pp-Store-stable-Pstate-clocks.patch new file mode 100644 index 00000000..fbbb7fca --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3169-drm-amd-pp-Store-stable-Pstate-clocks.patch @@ -0,0 +1,133 @@ +From 3054737b9a2a71b2aa5cdffeeac16ae980dcad5a Mon Sep 17 00:00:00 2001 +From: Rex Zhu <Rex.Zhu@amd.com> +Date: Fri, 5 Jan 2018 19:02:48 +0800 +Subject: [PATCH 3169/4131] drm/amd/pp: Store stable Pstate clocks + +User can use to calculate profiling ratios when +set UMD Pstate. + +Change-Id: I6e98983c95b08a7441c628da8913095d68bdc9d3 +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> +--- + drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 2 ++ + drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 3 +++ + drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 14 ++++++++++++-- + drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 5 +++++ + drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 2 ++ + 5 files changed, 24 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c +index e574af1..f68dd08 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c +@@ -1189,6 +1189,8 @@ static int cz_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr) + + cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk; + cz_hwmgr->sclk_dpm.hard_min_clk = table->entries[0].clk; ++ hwmgr->pstate_sclk = table->entries[0].clk; ++ hwmgr->pstate_mclk = 0; + + level = cz_get_max_sclk_level(hwmgr) - 1; + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c +index 2e0ea41..8e10cc8 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c +@@ -452,6 +452,9 @@ static int rv_hwmgr_backend_init(struct pp_hwmgr *hwmgr) + + hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; + ++ hwmgr->pstate_sclk = RAVEN_UMD_PSTATE_GFXCLK; ++ hwmgr->pstate_mclk = RAVEN_UMD_PSTATE_FCLK; ++ + return result; + } + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +index 284c21f..ac27219 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +@@ -2579,8 +2579,10 @@ static int smu7_get_profiling_clk(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_le + break; + } + } +- if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ++ if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { + *sclk_mask = 0; ++ tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].clk; ++ } + + if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) + *sclk_mask = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1; +@@ -2595,8 +2597,10 @@ static int smu7_get_profiling_clk(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_le + break; + } + } +- if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ++ if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { + *sclk_mask = 0; ++ tmp_sclk = table_info->vdd_dep_on_sclk->entries[0].clk; ++ } + + if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) + *sclk_mask = table_info->vdd_dep_on_sclk->count - 1; +@@ -2608,6 +2612,9 @@ static int smu7_get_profiling_clk(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_le + *mclk_mask = golden_dpm_table->mclk_table.count - 1; + + *pcie_mask = data->dpm_table.pcie_speed_table.count - 1; ++ hwmgr->pstate_sclk = tmp_sclk; ++ hwmgr->pstate_mclk = tmp_mclk; ++ + return 0; + } + +@@ -2619,6 +2626,9 @@ static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr, + uint32_t mclk_mask = 0; + uint32_t pcie_mask = 0; + ++ if (hwmgr->pstate_sclk == 0) ++ smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask); ++ + switch (level) { + case AMD_DPM_FORCED_LEVEL_HIGH: + ret = smu7_force_dpm_highest(hwmgr); +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +index 62e7f91..547670e 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +@@ -4181,6 +4181,8 @@ static int vega10_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_fo + *sclk_mask = VEGA10_UMD_PSTATE_GFXCLK_LEVEL; + *soc_mask = VEGA10_UMD_PSTATE_SOCCLK_LEVEL; + *mclk_mask = VEGA10_UMD_PSTATE_MCLK_LEVEL; ++ hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[VEGA10_UMD_PSTATE_GFXCLK_LEVEL].clk; ++ hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[VEGA10_UMD_PSTATE_MCLK_LEVEL].clk; + } + + if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { +@@ -4222,6 +4224,9 @@ static int vega10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, + uint32_t mclk_mask = 0; + uint32_t soc_mask = 0; + ++ if (hwmgr->pstate_sclk == 0) ++ vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); ++ + switch (level) { + case AMD_DPM_FORCED_LEVEL_HIGH: + ret = vega10_force_dpm_highest(hwmgr); +diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +index 800d773..6d8183d 100644 +--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h ++++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +@@ -753,6 +753,8 @@ struct pp_hwmgr { + enum amd_pp_profile_type current_power_profile; + bool en_umd_pstate; + uint32_t power_profile_mode; ++ uint32_t pstate_sclk; ++ uint32_t pstate_mclk; + }; + + struct cgs_irq_src_funcs { +-- +2.7.4 + |