diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3162-drm-amd-pp-Export-registers-for-read-vddc-on-VI-Vega.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3162-drm-amd-pp-Export-registers-for-read-vddc-on-VI-Vega.patch | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3162-drm-amd-pp-Export-registers-for-read-vddc-on-VI-Vega.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3162-drm-amd-pp-Export-registers-for-read-vddc-on-VI-Vega.patch new file mode 100644 index 00000000..d7ac96d6 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3162-drm-amd-pp-Export-registers-for-read-vddc-on-VI-Vega.patch @@ -0,0 +1,70 @@ +From cd75c6849864972c97c2a222be3e638517de1c03 Mon Sep 17 00:00:00 2001 +From: Rex Zhu <Rex.Zhu@amd.com> +Date: Tue, 2 Jan 2018 14:06:05 +0800 +Subject: [PATCH 3162/4131] drm/amd/pp: Export registers for read vddc on + VI/Vega10 + +Change-Id: I34d323c240e65b47c3558eb7042255b61078e2bb +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> +--- + drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h | 1 + + drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h | 6 ++++-- + drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_offset.h | 3 +++ + drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_sh_mask.h | 3 +++ + 4 files changed, 11 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h +index b89347e..f35aba7 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_d.h +@@ -1246,5 +1246,6 @@ + #define ixGC_CAC_OVRD_CU 0xe7 + #define ixCURRENT_PG_STATUS 0xc020029c + #define ixCURRENT_PG_STATUS_APU 0xd020029c ++#define ixPWR_SVI2_STATUS 0xC0200294 + + #endif /* SMU_7_1_3_D_H */ +diff --git a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h +index 654c109..481ee65 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h +@@ -6078,6 +6078,8 @@ + #define GC_CAC_OVRD_CU__OVRRD_VALUE__SHIFT 0x10 + #define CURRENT_PG_STATUS__VCE_PG_STATUS_MASK 0x00000002 + #define CURRENT_PG_STATUS__UVD_PG_STATUS_MASK 0x00000004 +- +- ++#define PWR_SVI2_STATUS__PLANE1_VID_MASK 0x000000ff ++#define PWR_SVI2_STATUS__PLANE1_VID__SHIFT 0x00000000 ++#define PWR_SVI2_STATUS__PLANE2_VID_MASK 0x0000ff00 ++#define PWR_SVI2_STATUS__PLANE2_VID__SHIFT 0x00000008 + #endif /* SMU_7_1_3_SH_MASK_H */ +diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_offset.h +index c1006fe..efd2704 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_offset.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_offset.h +@@ -172,4 +172,7 @@ + #define mmROM_SW_DATA_64 0x006d + #define mmROM_SW_DATA_64_BASE_IDX 0 + ++#define mmSMUSVI0_PLANE0_CURRENTVID_BASE_IDX 0 ++#define mmSMUSVI0_PLANE0_CURRENTVID 0x0013 ++ + #endif +diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_sh_mask.h +index a0be5c9..2487ab9 100644 +--- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_sh_mask.h ++++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_9_0_sh_mask.h +@@ -254,5 +254,8 @@ + //ROM_SW_DATA_64 + #define ROM_SW_DATA_64__ROM_SW_DATA__SHIFT 0x0 + #define ROM_SW_DATA_64__ROM_SW_DATA_MASK 0xFFFFFFFFL ++/* SMUSVI0_PLANE0_CURRENTVID */ ++#define SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID__SHIFT 0x18 ++#define SMUSVI0_PLANE0_CURRENTVID__CURRENT_SVI0_PLANE0_VID_MASK 0xFF000000L + + #endif +-- +2.7.4 + |