diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3151-drm-amdgpu-move-struct-amdgpu_mc-into-amdgpu_gmc.h.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3151-drm-amdgpu-move-struct-amdgpu_mc-into-amdgpu_gmc.h.patch | 3153 |
1 files changed, 3153 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3151-drm-amdgpu-move-struct-amdgpu_mc-into-amdgpu_gmc.h.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3151-drm-amdgpu-move-struct-amdgpu_mc-into-amdgpu_gmc.h.patch new file mode 100644 index 00000000..0b41dca1 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3151-drm-amdgpu-move-struct-amdgpu_mc-into-amdgpu_gmc.h.patch @@ -0,0 +1,3153 @@ +From cd5b59da08276f2c68c1fedf09d24a67076f1cba Mon Sep 17 00:00:00 2001 +From: Christian Koenig <christian.koenig@amd.com> +Date: Fri, 12 Jan 2018 14:52:22 +0100 +Subject: [PATCH 3151/4131] drm/amdgpu: move struct amdgpu_mc into amdgpu_gmc.h +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +And rename it to amdgpu_gmc as well. + +Signed-off-by: Christian König <christian.koenig@amd.com> +Reviewed-by: Samuel Li <Samuel.Li@amd.com> + +Conflicts: + drivers/gpu/drm/amd/amdgpu/amdgpu.h + drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c + drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c + drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c + drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c + drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c + drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c + +Change-Id: I925adce2ead6cb35eb6128071213a82b66a329fc +--- + drivers/gpu/drm/amd/amdgpu/amdgpu.h | 89 +---------- + drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 16 +- + drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 16 +- + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12 +- + drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 10 +- + drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 14 +- + drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h | 3 - + drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 4 +- + drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 110 ++++++++++++++ + drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 2 +- + drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 18 +-- + drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 30 ++-- + drivers/gpu/drm/amd/amdgpu/amdgpu_test.c | 12 +- + drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 46 +++--- + drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 19 ++- + drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 6 +- + drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 12 +- + drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 4 +- + drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 2 +- + drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 2 +- + drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 2 +- + drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 2 +- + drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 2 +- + drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 2 +- + drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 6 +- + drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 24 +-- + drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 109 +++++++------- + drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 139 +++++++++--------- + drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 170 +++++++++++----------- + drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 110 +++++++------- + drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 24 +-- + drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 4 +- + drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 4 +- + drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 8 +- + drivers/gpu/drm/amd/amdgpu/si_dma.c | 4 +- + drivers/gpu/drm/amd/amdgpu/si_dpm.c | 18 +-- + drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 8 +- + drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 4 +- + drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 8 +- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +- + 41 files changed, 552 insertions(+), 529 deletions(-) + create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +index db8ed3e..a40653f 100755 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +@@ -68,6 +68,7 @@ + #include "amdgpu_uvd.h" + #include "amdgpu_vce.h" + #include "amdgpu_vcn.h" ++#include "amdgpu_gmc.h" + #include "amdgpu_dm.h" + #include "amdgpu_mn.h" + #include "amdgpu_virt.h" +@@ -335,28 +336,6 @@ struct amdgpu_vm_pte_funcs { + uint32_t incr, uint64_t flags); + }; + +-/* provided by the gmc block */ +-struct amdgpu_gart_funcs { +- /* flush the vm tlb via mmio */ +- void (*flush_gpu_tlb)(struct amdgpu_device *adev, +- uint32_t vmid); +- /* write pte/pde updates using the cpu */ +- int (*set_pte_pde)(struct amdgpu_device *adev, +- void *cpu_pt_addr, /* cpu addr of page table */ +- uint32_t gpu_page_idx, /* pte/pde to update */ +- uint64_t addr, /* addr to write into pte/pde */ +- uint64_t flags); /* access flags */ +- /* enable/disable PRT support */ +- void (*set_prt)(struct amdgpu_device *adev, bool enable); +- /* set pte flags based per asic */ +- uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev, +- uint32_t flags); +- /* get the pde for a given mc addr */ +- void (*get_vm_pde)(struct amdgpu_device *adev, int level, +- u64 *dst, u64 *flags); +- uint32_t (*get_invalidate_req)(unsigned int vmid); +-}; +- + /* provided by the ih block */ + struct amdgpu_ih_funcs { + /* ring read/write ptr handling, called from interrupt context */ +@@ -508,58 +487,6 @@ int amdgpu_fence_slab_init(void); + void amdgpu_fence_slab_fini(void); + + /* +- * VMHUB structures, functions & helpers +- */ +-struct amdgpu_vmhub { +- uint32_t ctx0_ptb_addr_lo32; +- uint32_t ctx0_ptb_addr_hi32; +- uint32_t vm_inv_eng0_req; +- uint32_t vm_inv_eng0_ack; +- uint32_t vm_context0_cntl; +- uint32_t vm_l2_pro_fault_status; +- uint32_t vm_l2_pro_fault_cntl; +-}; +- +-/* +- * GPU MC structures, functions & helpers +- */ +-struct amdgpu_mc { +- resource_size_t aper_size; +- resource_size_t aper_base; +- /* for some chips with <= 32MB we need to lie +- * about vram size near mc fb location */ +- u64 mc_vram_size; +- u64 visible_vram_size; +- u64 gart_size; +- u64 gart_start; +- u64 gart_end; +- u64 vram_start; +- u64 vram_end; +- unsigned vram_width; +- u64 real_vram_size; +- int vram_mtrr; +- u64 mc_mask; +- const struct firmware *fw; /* MC firmware */ +- uint32_t fw_version; +- struct amdgpu_irq_src vm_fault; +- uint32_t vram_type; +- uint32_t srbm_soft_reset; +- bool prt_warning; +- uint64_t stolen_size; +- /* apertures */ +- u64 shared_aperture_start; +- u64 shared_aperture_end; +- u64 private_aperture_start; +- u64 private_aperture_end; +- /* protects concurrent invalidation */ +- spinlock_t invalidate_lock; +- bool translate_further; +- +- struct kfd_vm_fault_info *vm_fault_info; +- atomic_t vm_fault_info_updated; +-}; +- +-/* + * GPU doorbell structures, functions & helpers + */ + typedef enum _AMDGPU_DOORBELL_ASSIGNMENT +@@ -1640,7 +1567,7 @@ struct amdgpu_device { + struct amdgpu_clock clock; + + /* MC */ +- struct amdgpu_mc mc; ++ struct amdgpu_gmc gmc; + struct amdgpu_gart gart; + struct amdgpu_dummy_page dummy_page; + struct amdgpu_vm_manager vm_manager; +@@ -1909,13 +1836,13 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) + #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) + #define amdgpu_asic_flush_hdp(adev) (adev)->asic_funcs->flush_hdp((adev)) + #define amdgpu_asic_invalidate_hdp(adev) (adev)->asic_funcs->invalidate_hdp((adev)) +-#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) +-#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) +-#define amdgpu_gart_get_vm_pde(adev, level, dst, flags) (adev)->gart.gart_funcs->get_vm_pde((adev), (level), (dst), (flags)) ++#define amdgpu_gmc_flush_gpu_tlb(adev, vmid) (adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid)) ++#define amdgpu_gmc_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gmc.gmc_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) ++#define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags)) ++#define amdgpu_gmc_get_pte_flags(adev, flags) (adev)->gmc.gmc_funcs->get_vm_pte_flags((adev),(flags)) + #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) + #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) + #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) +-#define amdgpu_vm_get_pte_flags(adev, flags) (adev)->gart.gart_funcs->get_vm_pte_flags((adev),(flags)) + #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) + #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) + #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t)) +@@ -1972,9 +1899,9 @@ void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, + void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain); + bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); + void amdgpu_device_vram_location(struct amdgpu_device *adev, +- struct amdgpu_mc *mc, u64 base); ++ struct amdgpu_gmc *mc, u64 base); + void amdgpu_device_gart_location(struct amdgpu_device *adev, +- struct amdgpu_mc *mc); ++ struct amdgpu_gmc *mc); + int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); + void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); + int amdgpu_ttm_init(struct amdgpu_device *adev); +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +index 0725615..af33709 100755 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +@@ -388,22 +388,22 @@ void get_local_mem_info(struct kgd_dev *kgd, + + address_mask = adev->dev->dma_mask ? ~*adev->dev->dma_mask : + ~((1ULL << 32) - 1); +- aper_limit = adev->mc.aper_base + adev->mc.aper_size; ++ aper_limit = adev->gmc.aper_base + adev->gmc.aper_size; + + memset(mem_info, 0, sizeof(*mem_info)); +- if (!(adev->mc.aper_base & address_mask || ++ if (!(adev->gmc.aper_base & address_mask || + aper_limit & address_mask)) { +- mem_info->local_mem_size_public = adev->mc.visible_vram_size; +- mem_info->local_mem_size_private = adev->mc.real_vram_size - +- adev->mc.visible_vram_size; ++ mem_info->local_mem_size_public = adev->gmc.visible_vram_size; ++ mem_info->local_mem_size_private = adev->gmc.real_vram_size - ++ adev->gmc.visible_vram_size; + } else { + mem_info->local_mem_size_public = 0; +- mem_info->local_mem_size_private = adev->mc.real_vram_size; ++ mem_info->local_mem_size_private = adev->gmc.real_vram_size; + } +- mem_info->vram_width = adev->mc.vram_width; ++ mem_info->vram_width = adev->gmc.vram_width; + + pr_debug("Address base: %pap limit %pap public 0x%llx private 0x%llx\n", +- &adev->mc.aper_base, &aper_limit, ++ &adev->gmc.aper_base, &aper_limit, + mem_info->local_mem_size_public, + mem_info->local_mem_size_private); + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +index 9947e1a..58abb55 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +@@ -267,7 +267,7 @@ static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev, + return; + } + +- total_vram = adev->mc.real_vram_size - adev->vram_pin_size; ++ total_vram = adev->gmc.real_vram_size - adev->vram_pin_size; + used_vram = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); + free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram; + +@@ -312,8 +312,8 @@ static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev, + *max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us); + + /* Do the same for visible VRAM if half of it is free */ +- if (adev->mc.visible_vram_size < adev->mc.real_vram_size) { +- u64 total_vis_vram = adev->mc.visible_vram_size; ++ if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size) { ++ u64 total_vis_vram = adev->gmc.visible_vram_size; + u64 used_vis_vram = + amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); + +@@ -364,7 +364,7 @@ static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p, + * to move it. Don't move anything if the threshold is zero. + */ + if (p->bytes_moved < p->bytes_moved_threshold) { +- if (adev->mc.visible_vram_size < adev->mc.real_vram_size && ++ if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size && + (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) { + /* And don't move a CPU_ACCESS_REQUIRED BO to limited + * visible VRAM if we've depleted our allowance to do +@@ -389,9 +389,9 @@ static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p, + initial_bytes_moved; + p->bytes_moved += bytes_moved; + +- if (adev->mc.visible_vram_size < adev->mc.real_vram_size && ++ if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size && + bo->tbo.mem.mem_type == TTM_PL_VRAM && +- bo->tbo.mem.start < adev->mc.visible_vram_size >> PAGE_SHIFT) ++ bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT) + p->bytes_moved_vis += bytes_moved; + + if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) { +@@ -444,9 +444,9 @@ static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p, + /* Good we can try to move this BO somewhere else */ + amdgpu_ttm_placement_from_domain(bo, other); + update_bytes_moved_vis = +- adev->mc.visible_vram_size < adev->mc.real_vram_size && ++ adev->gmc.visible_vram_size < adev->gmc.real_vram_size && + bo->tbo.mem.mem_type == TTM_PL_VRAM && +- bo->tbo.mem.start < adev->mc.visible_vram_size >> PAGE_SHIFT; ++ bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT; + initial_bytes_moved = atomic64_read(&adev->num_bytes_moved); + r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); + bytes_moved = atomic64_read(&adev->num_bytes_moved) - +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +index 26343af..c0a513a 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +@@ -543,7 +543,7 @@ void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb) + * as parameter. + */ + void amdgpu_device_vram_location(struct amdgpu_device *adev, +- struct amdgpu_mc *mc, u64 base) ++ struct amdgpu_gmc *mc, u64 base) + { + uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; + +@@ -569,11 +569,11 @@ void amdgpu_device_vram_location(struct amdgpu_device *adev, + * FIXME: when reducing GTT size align new size on power of 2. + */ + void amdgpu_device_gart_location(struct amdgpu_device *adev, +- struct amdgpu_mc *mc) ++ struct amdgpu_gmc *mc) + { + u64 size_af, size_bf; + +- size_af = adev->mc.mc_mask - mc->vram_end; ++ size_af = adev->gmc.mc_mask - mc->vram_end; + size_bf = mc->vram_start; + if (size_bf > size_af) { + if (mc->gart_size > size_bf) { +@@ -608,7 +608,7 @@ void amdgpu_device_gart_location(struct amdgpu_device *adev, + */ + int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) + { +- u64 space_needed = roundup_pow_of_two(adev->mc.real_vram_size); ++ u64 space_needed = roundup_pow_of_two(adev->gmc.real_vram_size); + u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1; + struct pci_bus *root; + struct resource *res; +@@ -1796,14 +1796,14 @@ int amdgpu_device_init(struct amdgpu_device *adev, + adev->flags = flags; + adev->asic_type = flags & AMD_ASIC_MASK; + adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; +- adev->mc.gart_size = 512 * 1024 * 1024; ++ adev->gmc.gart_size = 512 * 1024 * 1024; + adev->accel_working = false; + adev->num_rings = 0; + adev->mman.buffer_funcs = NULL; + adev->mman.buffer_funcs_ring = NULL; + adev->vm_manager.vm_pte_funcs = NULL; + adev->vm_manager.vm_pte_num_rings = 0; +- adev->gart.gart_funcs = NULL; ++ adev->gmc.gmc_funcs = NULL; + adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS); + bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +index 577645d..34cb5c1 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +@@ -245,8 +245,8 @@ static int amdgpufb_create(struct drm_fb_helper *helper, + info->flags = FBINFO_DEFAULT | FBINFO_CAN_FORCE_OUTPUT; + info->fbops = &amdgpufb_ops; + +- tmp = amdgpu_bo_gpu_offset(abo) - adev->mc.vram_start; +- info->fix.smem_start = adev->mc.aper_base + tmp; ++ tmp = amdgpu_bo_gpu_offset(abo) - adev->gmc.vram_start; ++ info->fix.smem_start = adev->gmc.aper_base + tmp; + info->fix.smem_len = amdgpu_bo_size(abo); + info->screen_base = amdgpu_bo_kptr(abo); + info->screen_size = amdgpu_bo_size(abo); +@@ -255,7 +255,7 @@ static int amdgpufb_create(struct drm_fb_helper *helper, + + /* setup aperture base/size for vesafb takeover */ + info->apertures->ranges[0].base = adev->ddev->mode_config.fb_base; +- info->apertures->ranges[0].size = adev->mc.aper_size; ++ info->apertures->ranges[0].size = adev->gmc.aper_size; + + /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */ + +@@ -265,7 +265,7 @@ static int amdgpufb_create(struct drm_fb_helper *helper, + } + + DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start); +- DRM_INFO("vram apper at 0x%lX\n", (unsigned long)adev->mc.aper_base); ++ DRM_INFO("vram apper at 0x%lX\n", (unsigned long)adev->gmc.aper_base); + DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(abo)); + DRM_INFO("fb depth is %d\n", fb->format->depth); + DRM_INFO(" pitch is %d\n", fb->pitches[0]); +@@ -352,7 +352,7 @@ int amdgpu_fbdev_init(struct amdgpu_device *adev) + return 0; + + /* select 8 bpp console on low vram cards */ +- if (adev->mc.real_vram_size <= (32*1024*1024)) ++ if (adev->gmc.real_vram_size <= (32*1024*1024)) + bpp_sel = 8; + + rfbdev = kzalloc(sizeof(struct amdgpu_fbdev), GFP_KERNEL); +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c +index d0617f1..18d2387 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c +@@ -241,14 +241,14 @@ int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, + continue; + + for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) { +- amdgpu_gart_set_pte_pde(adev, adev->gart.ptr, +- t, page_base, flags); ++ amdgpu_gmc_set_pte_pde(adev, adev->gart.ptr, ++ t, page_base, flags); + page_base += AMDGPU_GPU_PAGE_SIZE; + } + } + mb(); + amdgpu_asic_flush_hdp(adev); +- amdgpu_gart_flush_gpu_tlb(adev, 0); ++ amdgpu_gmc_flush_gpu_tlb(adev, 0); + return 0; + } + +@@ -280,7 +280,7 @@ int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset, + for (i = 0; i < pages; i++) { + page_base = dma_addr[i]; + for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) { +- amdgpu_gart_set_pte_pde(adev, dst, t, page_base, flags); ++ amdgpu_gmc_set_pte_pde(adev, dst, t, page_base, flags); + page_base += AMDGPU_GPU_PAGE_SIZE; + } + } +@@ -331,7 +331,7 @@ int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, + + mb(); + amdgpu_asic_flush_hdp(adev); +- amdgpu_gart_flush_gpu_tlb(adev, 0); ++ amdgpu_gmc_flush_gpu_tlb(adev, 0); + return 0; + } + +@@ -359,8 +359,8 @@ int amdgpu_gart_init(struct amdgpu_device *adev) + if (r) + return r; + /* Compute table size */ +- adev->gart.num_cpu_pages = adev->mc.gart_size / PAGE_SIZE; +- adev->gart.num_gpu_pages = adev->mc.gart_size / AMDGPU_GPU_PAGE_SIZE; ++ adev->gart.num_cpu_pages = adev->gmc.gart_size / PAGE_SIZE; ++ adev->gart.num_gpu_pages = adev->gmc.gart_size / AMDGPU_GPU_PAGE_SIZE; + DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n", + adev->gart.num_cpu_pages, adev->gart.num_gpu_pages); + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h +index d4a4330..456295c 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h +@@ -31,7 +31,6 @@ + */ + struct amdgpu_device; + struct amdgpu_bo; +-struct amdgpu_gart_funcs; + + #define AMDGPU_GPU_PAGE_SIZE 4096 + #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1) +@@ -52,8 +51,6 @@ struct amdgpu_gart { + + /* Asic default pte flags */ + uint64_t gart_pte_flags; +- +- const struct amdgpu_gart_funcs *gart_funcs; + }; + + int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +index 11d1fb7..2378a2e 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +@@ -805,7 +805,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, + if (r) + goto error_backoff; + +- va_flags = amdgpu_vm_get_pte_flags(adev, args->flags); ++ va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags); + r = amdgpu_vm_bo_map(adev, bo_va, args->va_address, + args->offset_in_bo, args->map_size, + va_flags); +@@ -825,7 +825,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, + if (r) + goto error_backoff; + +- va_flags = amdgpu_vm_get_pte_flags(adev, args->flags); ++ va_flags = amdgpu_gmc_get_pte_flags(adev, args->flags); + r = amdgpu_vm_bo_replace_map(adev, bo_va, args->va_address, + args->offset_in_bo, args->map_size, + va_flags); +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h +new file mode 100644 +index 0000000..2229a14 +--- /dev/null ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h +@@ -0,0 +1,110 @@ ++/* ++ * Copyright 2018 Advanced Micro Devices, Inc. ++ * All Rights Reserved. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the ++ * "Software"), to deal in the Software without restriction, including ++ * without limitation the rights to use, copy, modify, merge, publish, ++ * distribute, sub license, and/or sell copies of the Software, and to ++ * permit persons to whom the Software is furnished to do so, subject to ++ * the following conditions: ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, ++ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR ++ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE ++ * USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ * The above copyright notice and this permission notice (including the ++ * next paragraph) shall be included in all copies or substantial portions ++ * of the Software. ++ * ++ */ ++#ifndef __AMDGPU_GMC_H__ ++#define __AMDGPU_GMC_H__ ++ ++#include <linux/types.h> ++ ++#include "amdgpu_irq.h" ++ ++struct firmware; ++ ++/* ++ * VMHUB structures, functions & helpers ++ */ ++struct amdgpu_vmhub { ++ uint32_t ctx0_ptb_addr_lo32; ++ uint32_t ctx0_ptb_addr_hi32; ++ uint32_t vm_inv_eng0_req; ++ uint32_t vm_inv_eng0_ack; ++ uint32_t vm_context0_cntl; ++ uint32_t vm_l2_pro_fault_status; ++ uint32_t vm_l2_pro_fault_cntl; ++}; ++ ++/* ++ * GPU MC structures, functions & helpers ++ */ ++struct amdgpu_gmc_funcs { ++ /* flush the vm tlb via mmio */ ++ void (*flush_gpu_tlb)(struct amdgpu_device *adev, ++ uint32_t vmid); ++ /* write pte/pde updates using the cpu */ ++ int (*set_pte_pde)(struct amdgpu_device *adev, ++ void *cpu_pt_addr, /* cpu addr of page table */ ++ uint32_t gpu_page_idx, /* pte/pde to update */ ++ uint64_t addr, /* addr to write into pte/pde */ ++ uint64_t flags); /* access flags */ ++ /* enable/disable PRT support */ ++ void (*set_prt)(struct amdgpu_device *adev, bool enable); ++ /* set pte flags based per asic */ ++ uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev, ++ uint32_t flags); ++ /* get the pde for a given mc addr */ ++ void (*get_vm_pde)(struct amdgpu_device *adev, int level, ++ u64 *dst, u64 *flags); ++ uint32_t (*get_invalidate_req)(unsigned int vmid); ++}; ++ ++struct amdgpu_gmc { ++ resource_size_t aper_size; ++ resource_size_t aper_base; ++ /* for some chips with <= 32MB we need to lie ++ * about vram size near mc fb location */ ++ u64 mc_vram_size; ++ u64 visible_vram_size; ++ u64 gart_size; ++ u64 gart_start; ++ u64 gart_end; ++ u64 vram_start; ++ u64 vram_end; ++ unsigned vram_width; ++ u64 real_vram_size; ++ int vram_mtrr; ++ u64 mc_mask; ++ const struct firmware *fw; /* MC firmware */ ++ uint32_t fw_version; ++ struct amdgpu_irq_src vm_fault; ++ uint32_t vram_type; ++ uint32_t srbm_soft_reset; ++ bool prt_warning; ++ uint64_t stolen_size; ++ /* apertures */ ++ u64 shared_aperture_start; ++ u64 shared_aperture_end; ++ u64 private_aperture_start; ++ u64 private_aperture_end; ++ /* protects concurrent invalidation */ ++ spinlock_t invalidate_lock; ++ bool translate_further; ++ ++ struct kfd_vm_fault_info *vm_fault_info; ++ atomic_t vm_fault_info_updated; ++ ++ const struct amdgpu_gmc_funcs *gmc_funcs; ++}; ++ ++#endif +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c +index 73135b9..eeb9e77 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c +@@ -56,7 +56,7 @@ static int amdgpu_gtt_mgr_init(struct ttm_mem_type_manager *man, + return -ENOMEM; + + start = AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS; +- size = (adev->mc.gart_size >> PAGE_SHIFT) - start; ++ size = (adev->gmc.gart_size >> PAGE_SHIFT) - start; + drm_mm_init(&mgr->mm, start, size); + spin_lock_init(&mgr->lock); + atomic64_set(&mgr->available, p_size); +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +index 1481a4a..99c9df2 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +@@ -214,7 +214,7 @@ static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info, + fw_info->feature = 0; + break; + case AMDGPU_INFO_FW_GMC: +- fw_info->ver = adev->mc.fw_version; ++ fw_info->ver = adev->gmc.fw_version; + fw_info->feature = 0; + break; + case AMDGPU_INFO_FW_GFX_ME: +@@ -510,9 +510,9 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file + case AMDGPU_INFO_VRAM_GTT: { + struct drm_amdgpu_info_vram_gtt vram_gtt; + +- vram_gtt.vram_size = adev->mc.real_vram_size; ++ vram_gtt.vram_size = adev->gmc.real_vram_size; + vram_gtt.vram_size -= adev->vram_pin_size; +- vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size; ++ vram_gtt.vram_cpu_accessible_size = adev->gmc.visible_vram_size; + vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - adev->invisible_pin_size); + vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size; + vram_gtt.gtt_size *= PAGE_SIZE; +@@ -524,17 +524,17 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file + struct drm_amdgpu_memory_info mem; + + memset(&mem, 0, sizeof(mem)); +- mem.vram.total_heap_size = adev->mc.real_vram_size; ++ mem.vram.total_heap_size = adev->gmc.real_vram_size; + mem.vram.usable_heap_size = +- adev->mc.real_vram_size - adev->vram_pin_size; ++ adev->gmc.real_vram_size - adev->vram_pin_size; + mem.vram.heap_usage = + amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); + mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4; + + mem.cpu_accessible_vram.total_heap_size = +- adev->mc.visible_vram_size; ++ adev->gmc.visible_vram_size; + mem.cpu_accessible_vram.usable_heap_size = +- adev->mc.visible_vram_size - ++ adev->gmc.visible_vram_size - + (adev->vram_pin_size - adev->invisible_pin_size); + mem.cpu_accessible_vram.heap_usage = + amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); +@@ -639,8 +639,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file + sizeof(adev->gfx.cu_info.ao_cu_bitmap)); + memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0], + sizeof(adev->gfx.cu_info.bitmap)); +- dev_info.vram_type = adev->mc.vram_type; +- dev_info.vram_bit_width = adev->mc.vram_width; ++ dev_info.vram_type = adev->gmc.vram_type; ++ dev_info.vram_bit_width = adev->gmc.vram_width; + dev_info.vce_harvest_config = adev->vce.harvest_config; + dev_info.gc_double_offchip_lds_buf = + adev->gfx.config.double_offchip_lds_buf; +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +index 99a7000..6119703 100755 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +@@ -105,7 +105,7 @@ void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain) + } + + if (domain & AMDGPU_GEM_DOMAIN_VRAM) { +- unsigned visible_pfn = adev->mc.visible_vram_size >> PAGE_SHIFT; ++ unsigned visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; + + places[c].fpfn = 0; + places[c].lpfn = 0; +@@ -125,7 +125,7 @@ void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain) + if (domain & AMDGPU_GEM_DOMAIN_GTT) { + places[c].fpfn = 0; + if (flags & AMDGPU_GEM_CREATE_SHADOW) +- places[c].lpfn = adev->mc.gart_size >> PAGE_SHIFT; ++ places[c].lpfn = adev->gmc.gart_size >> PAGE_SHIFT; + else + places[c].lpfn = 0; + places[c].flags = TTM_PL_FLAG_TT; +@@ -448,9 +448,9 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev, + if (unlikely(r != 0)) + return r; + +- if (adev->mc.visible_vram_size < adev->mc.real_vram_size && ++ if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size && + bo->tbo.mem.mem_type == TTM_PL_VRAM && +- bo->tbo.mem.start < adev->mc.visible_vram_size >> PAGE_SHIFT) ++ bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT) + amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, + ctx.bytes_moved); + else +@@ -867,25 +867,25 @@ static const char *amdgpu_vram_names[] = { + int amdgpu_bo_init(struct amdgpu_device *adev) + { + /* reserve PAT memory space to WC for VRAM */ +- arch_io_reserve_memtype_wc(adev->mc.aper_base, +- adev->mc.aper_size); ++ arch_io_reserve_memtype_wc(adev->gmc.aper_base, ++ adev->gmc.aper_size); + + /* Add an MTRR for the VRAM */ +- adev->mc.vram_mtrr = arch_phys_wc_add(adev->mc.aper_base, +- adev->mc.aper_size); ++ adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base, ++ adev->gmc.aper_size); + DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", +- adev->mc.mc_vram_size >> 20, +- (unsigned long long)adev->mc.aper_size >> 20); ++ adev->gmc.mc_vram_size >> 20, ++ (unsigned long long)adev->gmc.aper_size >> 20); + DRM_INFO("RAM width %dbits %s\n", +- adev->mc.vram_width, amdgpu_vram_names[adev->mc.vram_type]); ++ adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]); + return amdgpu_ttm_init(adev); + } + + void amdgpu_bo_fini(struct amdgpu_device *adev) + { + amdgpu_ttm_fini(adev); +- arch_phys_wc_del(adev->mc.vram_mtrr); +- arch_io_free_memtype_wc(adev->mc.aper_base, adev->mc.aper_size); ++ arch_phys_wc_del(adev->gmc.vram_mtrr); ++ arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size); + } + + int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo, +@@ -1014,7 +1014,7 @@ int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) + + size = bo->mem.num_pages << PAGE_SHIFT; + offset = bo->mem.start << PAGE_SHIFT; +- if ((offset + size) <= adev->mc.visible_vram_size) ++ if ((offset + size) <= adev->gmc.visible_vram_size) + return 0; + + /* Can't move a pinned BO to visible VRAM */ +@@ -1037,7 +1037,7 @@ int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) + offset = bo->mem.start << PAGE_SHIFT; + /* this should never happen */ + if (bo->mem.mem_type == TTM_PL_VRAM && +- (offset + size) > adev->mc.visible_vram_size) ++ (offset + size) > adev->gmc.visible_vram_size) + return -EINVAL; + + return 0; +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c +index ed8c373..30d84df 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c +@@ -42,7 +42,7 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev) + /* Number of tests = + * (Total GTT - IB pool - writeback page - ring buffers) / test size + */ +- n = adev->mc.gart_size - AMDGPU_IB_POOL_SIZE*64*1024; ++ n = adev->gmc.gart_size - AMDGPU_IB_POOL_SIZE*64*1024; + for (i = 0; i < AMDGPU_MAX_RINGS; ++i) + if (adev->rings[i]) + n -= adev->rings[i]->ring_size; +@@ -142,10 +142,10 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev) + "0x%16llx/0x%16llx)\n", + i, *vram_start, gart_start, + (unsigned long long) +- (gart_addr - adev->mc.gart_start + ++ (gart_addr - adev->gmc.gart_start + + (void*)gart_start - gtt_map), + (unsigned long long) +- (vram_addr - adev->mc.vram_start + ++ (vram_addr - adev->gmc.vram_start + + (void*)gart_start - gtt_map)); + amdgpu_bo_kunmap(vram_obj); + goto out_lclean_unpin; +@@ -187,10 +187,10 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev) + "0x%16llx/0x%16llx)\n", + i, *gart_start, vram_start, + (unsigned long long) +- (vram_addr - adev->mc.vram_start + ++ (vram_addr - adev->gmc.vram_start + + (void*)vram_start - vram_map), + (unsigned long long) +- (gart_addr - adev->mc.gart_start + ++ (gart_addr - adev->gmc.gart_start + + (void*)vram_start - vram_map)); + amdgpu_bo_kunmap(gtt_obj[i]); + goto out_lclean_unpin; +@@ -200,7 +200,7 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev) + amdgpu_bo_kunmap(gtt_obj[i]); + + DRM_INFO("Tested GTT->VRAM and VRAM->GTT copy for GTT offset 0x%llx\n", +- gart_addr - adev->mc.gart_start); ++ gart_addr - adev->gmc.gart_start); + continue; + + out_lclean_unpin: +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +index e5a6623..64d0141 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +@@ -162,7 +162,7 @@ static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, + break; + case TTM_PL_TT: + man->func = &amdgpu_gtt_mgr_func; +- man->gpu_offset = adev->mc.gart_start; ++ man->gpu_offset = adev->gmc.gart_start; + man->available_caching = TTM_PL_MASK_CACHING; + man->default_caching = TTM_PL_FLAG_CACHED; + man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; +@@ -170,7 +170,7 @@ static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, + case TTM_PL_VRAM: + /* "On-card" video ram */ + man->func = &amdgpu_vram_mgr_func; +- man->gpu_offset = adev->mc.vram_start; ++ man->gpu_offset = adev->gmc.vram_start; + man->flags = TTM_MEMTYPE_FLAG_FIXED | + TTM_MEMTYPE_FLAG_MAPPABLE; + man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; +@@ -236,9 +236,9 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo, + adev->mman.buffer_funcs_ring && + adev->mman.buffer_funcs_ring->ready == false) { + amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); +- } else if (adev->mc.visible_vram_size < adev->mc.real_vram_size && ++ } else if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size && + !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) { +- unsigned fpfn = adev->mc.visible_vram_size >> PAGE_SHIFT; ++ unsigned fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; + struct drm_mm_node *node = bo->mem.mm_node; + unsigned long pages_left; + +@@ -697,9 +697,9 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_ + mem->bus.offset = (mem->start << PAGE_SHIFT) + man->gpu_offset - + adev->mc.vram_start; + /* check if it's visible */ +- if ((mem->bus.offset + mem->bus.size) > adev->mc.visible_vram_size) ++ if ((mem->bus.offset + mem->bus.size) > adev->gmc.visible_vram_size) + return -EINVAL; +- mem->bus.base = adev->mc.aper_base; ++ mem->bus.base = adev->gmc.aper_base; + mem->bus.is_iomem = true; + break; + case AMDGPU_PL_DGMA_IMPORT: +@@ -965,7 +965,7 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo) + placement.num_busy_placement = 1; + placement.busy_placement = &placements; + placements.fpfn = 0; +- placements.lpfn = adev->mc.gart_size >> PAGE_SHIFT; ++ placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT; + placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) | + TTM_PL_FLAG_TT; + +@@ -1296,7 +1296,7 @@ static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo, + nodes = amdgpu_find_mm_node(&abo->tbo.mem, &offset); + pos = (nodes->start << PAGE_SHIFT) + offset; + +- while (len && pos < adev->mc.mc_vram_size) { ++ while (len && pos < adev->gmc.mc_vram_size) { + uint64_t aligned_pos = pos & ~(uint64_t)3; + uint32_t bytes = 4 - (pos & 3); + uint32_t shift = (pos & 3) * 8; +@@ -1535,7 +1535,7 @@ static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev) + { + int r = 0; + int i; +- u64 vram_size = adev->mc.visible_vram_size; ++ u64 vram_size = adev->gmc.visible_vram_size; + u64 offset = adev->fw_vram_usage.start_offset; + u64 size = adev->fw_vram_usage.size; + struct amdgpu_bo *bo; +@@ -1625,7 +1625,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) + } + adev->mman.initialized = true; + r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM, +- adev->mc.real_vram_size >> PAGE_SHIFT); ++ adev->gmc.real_vram_size >> PAGE_SHIFT); + if (r) { + DRM_ERROR("Failed initializing VRAM heap.\n"); + return r; +@@ -1634,11 +1634,11 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) + /* Reduce size of CPU-visible VRAM if requested */ + vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024; + if (amdgpu_vis_vram_limit > 0 && +- vis_vram_limit <= adev->mc.visible_vram_size) +- adev->mc.visible_vram_size = vis_vram_limit; ++ vis_vram_limit <= adev->gmc.visible_vram_size) ++ adev->gmc.visible_vram_size = vis_vram_limit; + + /* Change the size here instead of the init above so only lpfn is affected */ +- amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); ++ amdgpu_ttm_set_active_vram_size(adev, adev->gmc.visible_vram_size); + + /* + *The reserved vram for firmware must be pinned to the specified +@@ -1649,7 +1649,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) + return r; + } + +- r = amdgpu_bo_create_kernel(adev, adev->mc.stolen_size, PAGE_SIZE, ++ r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM, + &adev->stolen_vga_memory, + NULL, NULL); +@@ -1657,14 +1657,14 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) + return r; + + DRM_INFO("amdgpu: %uM of VRAM memory ready\n", +- (unsigned) (adev->mc.real_vram_size / (1024 * 1024))); ++ (unsigned) (adev->gmc.real_vram_size / (1024 * 1024))); + + if (amdgpu_gtt_size == -1) { + struct sysinfo si; + + si_meminfo(&si); + gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20), +- adev->mc.mc_vram_size), ++ adev->gmc.mc_vram_size), + ((uint64_t)si.totalram * si.mem_unit * 3/4)); + } + else +@@ -1807,7 +1807,7 @@ static int amdgpu_map_buffer(struct ttm_buffer_object *bo, + BUG_ON(adev->mman.buffer_funcs->copy_max_bytes < + AMDGPU_GTT_MAX_TRANSFER_SIZE * 8); + +- *addr = adev->mc.gart_start; ++ *addr = adev->gmc.gart_start; + *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE * + AMDGPU_GPU_PAGE_SIZE; + +@@ -2066,14 +2066,14 @@ static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf, + if (size & 0x3 || *pos & 0x3) + return -EINVAL; + +- if (*pos >= adev->mc.mc_vram_size) ++ if (*pos >= adev->gmc.mc_vram_size) + return -ENXIO; + + while (size) { + unsigned long flags; + uint32_t value; + +- if (*pos >= adev->mc.mc_vram_size) ++ if (*pos >= adev->gmc.mc_vram_size) + return result; + + spin_lock_irqsave(&adev->mmio_idx_lock, flags); +@@ -2105,14 +2105,14 @@ static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf, + if (size & 0x3 || *pos & 0x3) + return -EINVAL; + +- if (*pos >= adev->mc.mc_vram_size) ++ if (*pos >= adev->gmc.mc_vram_size) + return -ENXIO; + + while (size) { + unsigned long flags; + uint32_t value; + +- if (*pos >= adev->mc.mc_vram_size) ++ if (*pos >= adev->gmc.mc_vram_size) + return result; + + r = get_user(value, (uint32_t *)buf); +@@ -2263,9 +2263,9 @@ static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) + if (IS_ERR(ent)) + return PTR_ERR(ent); + if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM) +- i_size_write(ent->d_inode, adev->mc.mc_vram_size); ++ i_size_write(ent->d_inode, adev->gmc.mc_vram_size); + else if (ttm_debugfs_entries[count].domain == TTM_PL_TT) +- i_size_write(ent->d_inode, adev->mc.gart_size); ++ i_size_write(ent->d_inode, adev->gmc.gart_size); + adev->mman.debugfs_entries[count] = ent; + } + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +index 5c629dd..8a20e53 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +@@ -470,7 +470,7 @@ bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, + + static bool amdgpu_vm_is_large_bar(struct amdgpu_device *adev) + { +- return (adev->mc.real_vram_size == adev->mc.visible_vram_size); ++ return (adev->gmc.real_vram_size == adev->gmc.visible_vram_size); + } + + /** +@@ -684,8 +684,8 @@ static void amdgpu_vm_cpu_set_ptes(struct amdgpu_pte_update_params *params, + value = params->pages_addr ? + amdgpu_vm_map_gart(params->pages_addr, addr) : + addr; +- amdgpu_gart_set_pte_pde(params->adev, (void *)(uintptr_t)pe, +- i, value, flags); ++ amdgpu_gmc_set_pte_pde(params->adev, (void *)(uintptr_t)pe, ++ i, value, flags); + addr += incr; + } + } +@@ -743,7 +743,7 @@ static void amdgpu_vm_update_pde(struct amdgpu_pte_update_params *params, + level += params->adev->vm_manager.root_level; + pt = amdgpu_bo_gpu_offset(bo); + flags = AMDGPU_PTE_VALID; +- amdgpu_gart_get_vm_pde(params->adev, level, &pt, &flags); ++ amdgpu_gmc_get_vm_pde(params->adev, level, &pt, &flags); + if (shadow) { + pde = shadow_addr + (entry - parent->entries) * 8; + params->func(params, pde, pt, 1, 0, flags); +@@ -972,8 +972,7 @@ static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p, + } + + entry->huge = true; +- amdgpu_gart_get_vm_pde(p->adev, AMDGPU_VM_PDB0, +- &dst, &flags); ++ amdgpu_gmc_get_vm_pde(p->adev, AMDGPU_VM_PDB0, &dst, &flags); + + if (parent->base.bo->shadow) { + pd_addr = amdgpu_bo_gpu_offset(parent->base.bo->shadow); +@@ -1512,7 +1511,7 @@ static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev) + + spin_lock_irqsave(&adev->vm_manager.prt_lock, flags); + enable = !!atomic_read(&adev->vm_manager.num_prt_users); +- adev->gart.gart_funcs->set_prt(adev, enable); ++ adev->gmc.gmc_funcs->set_prt(adev, enable); + spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags); + } + +@@ -1521,7 +1520,7 @@ static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev) + */ + static void amdgpu_vm_prt_get(struct amdgpu_device *adev) + { +- if (!adev->gart.gart_funcs->set_prt) ++ if (!adev->gmc.gmc_funcs->set_prt) + return; + + if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1) +@@ -1556,7 +1555,7 @@ static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev, + { + struct amdgpu_prt_cb *cb; + +- if (!adev->gart.gart_funcs->set_prt) ++ if (!adev->gmc.gmc_funcs->set_prt) + return; + + cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL); +@@ -2463,7 +2462,7 @@ static void amdgpu_vm_free_levels(struct amdgpu_device *adev, + void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) + { + struct amdgpu_bo_va_mapping *mapping, *tmp; +- bool prt_fini_needed = !!adev->gart.gart_funcs->set_prt; ++ bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt; + struct amdgpu_bo *root; + u64 fault; + int i, r; +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +index c9f3336..ae0049c 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +@@ -89,11 +89,11 @@ static u64 amdgpu_vram_mgr_vis_size(struct amdgpu_device *adev, + uint64_t start = node->start << PAGE_SHIFT; + uint64_t end = (node->size + node->start) << PAGE_SHIFT; + +- if (start >= adev->mc.visible_vram_size) ++ if (start >= adev->gmc.visible_vram_size) + return 0; + +- return (end > adev->mc.visible_vram_size ? +- adev->mc.visible_vram_size : end) - start; ++ return (end > adev->gmc.visible_vram_size ? ++ adev->gmc.visible_vram_size : end) - start; + } + + /** +diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c +index a0943aa..ab45232 100644 +--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c ++++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c +@@ -905,7 +905,7 @@ static bool ci_dpm_vblank_too_short(void *handle) + { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + u32 vblank_time = amdgpu_dpm_get_vblank_time(adev); +- u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 300; ++ u32 switch_limit = adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 300; + + /* disable mclk switching if the refresh is >120Hz, even if the + * blanking period would allow it +@@ -2954,7 +2954,7 @@ static int ci_calculate_mclk_params(struct amdgpu_device *adev, + mpll_ad_func_cntl &= ~MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK; + mpll_ad_func_cntl |= (mpll_param.post_div << MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT); + +- if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { ++ if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { + mpll_dq_func_cntl &= ~(MPLL_DQ_FUNC_CNTL__YCLK_SEL_MASK | + MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK); + mpll_dq_func_cntl |= (mpll_param.yclk_sel << MPLL_DQ_FUNC_CNTL__YCLK_SEL__SHIFT) | +@@ -3077,7 +3077,7 @@ static int ci_populate_single_memory_level(struct amdgpu_device *adev, + (memory_clock <= pi->mclk_strobe_mode_threshold)) + memory_level->StrobeEnable = 1; + +- if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { ++ if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { + memory_level->StrobeRatio = + ci_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable); + if (pi->mclk_edc_enable_threshold && +@@ -3752,7 +3752,7 @@ static int ci_init_smc_table(struct amdgpu_device *adev) + if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) + table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; + +- if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) ++ if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) + table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5; + + if (ulv->supported) { +@@ -4549,12 +4549,12 @@ static int ci_set_mc_special_registers(struct amdgpu_device *adev, + for (k = 0; k < table->num_entries; k++) { + table->mc_reg_table_entry[k].mc_data[j] = + (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); +- if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) ++ if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) + table->mc_reg_table_entry[k].mc_data[j] |= 0x100; + } + j++; + +- if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) { ++ if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) { + if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) + return -EINVAL; + table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD; +diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +index 0066da3..3ea0be5 100644 +--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c ++++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +@@ -317,7 +317,7 @@ static void cik_sdma_gfx_stop(struct amdgpu_device *adev) + + if ((adev->mman.buffer_funcs_ring == sdma0) || + (adev->mman.buffer_funcs_ring == sdma1)) +- amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); ++ amdgpu_ttm_set_active_vram_size(adev, adev->gmc.visible_vram_size); + + for (i = 0; i < adev->sdma.num_instances; i++) { + rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); +@@ -517,7 +517,7 @@ static int cik_sdma_gfx_resume(struct amdgpu_device *adev) + } + + if (adev->mman.buffer_funcs_ring == ring) +- amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size); ++ amdgpu_ttm_set_active_vram_size(adev, adev->gmc.real_vram_size); + } + + return 0; +diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +index f34bc68..5590bf1 100644 +--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +@@ -2824,7 +2824,7 @@ static int dce_v10_0_sw_init(void *handle) + adev->ddev->mode_config.preferred_depth = 24; + adev->ddev->mode_config.prefer_shadow = 1; + +- adev->ddev->mode_config.fb_base = adev->mc.aper_base; ++ adev->ddev->mode_config.fb_base = adev->gmc.aper_base; + + r = amdgpu_modeset_create_props(adev); + if (r) +diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +index 26378bd..8ee4fc4 100644 +--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +@@ -2939,7 +2939,7 @@ static int dce_v11_0_sw_init(void *handle) + adev->ddev->mode_config.preferred_depth = 24; + adev->ddev->mode_config.prefer_shadow = 1; + +- adev->ddev->mode_config.fb_base = adev->mc.aper_base; ++ adev->ddev->mode_config.fb_base = adev->gmc.aper_base; + + r = amdgpu_modeset_create_props(adev); + if (r) +diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +index bd2c4f7..c943ad1 100644 +--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +@@ -2693,7 +2693,7 @@ static int dce_v6_0_sw_init(void *handle) + adev->ddev->mode_config.max_height = 16384; + adev->ddev->mode_config.preferred_depth = 24; + adev->ddev->mode_config.prefer_shadow = 1; +- adev->ddev->mode_config.fb_base = adev->mc.aper_base; ++ adev->ddev->mode_config.fb_base = adev->gmc.aper_base; + + r = amdgpu_modeset_create_props(adev); + if (r) +diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +index c008dc0..c02308c 100644 +--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +@@ -2724,7 +2724,7 @@ static int dce_v8_0_sw_init(void *handle) + adev->ddev->mode_config.preferred_depth = 24; + adev->ddev->mode_config.prefer_shadow = 1; + +- adev->ddev->mode_config.fb_base = adev->mc.aper_base; ++ adev->ddev->mode_config.fb_base = adev->gmc.aper_base; + + r = amdgpu_modeset_create_props(adev); + if (r) +diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c +index f111bae..24e9cdb 100644 +--- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c ++++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c +@@ -406,7 +406,7 @@ static int dce_virtual_sw_init(void *handle) + adev->ddev->mode_config.preferred_depth = 24; + adev->ddev->mode_config.prefer_shadow = 1; + +- adev->ddev->mode_config.fb_base = adev->mc.aper_base; ++ adev->ddev->mode_config.fb_base = adev->gmc.aper_base; + + r = amdgpu_modeset_create_props(adev); + if (r) +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +index a8a06b3..9b52a68 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +@@ -1946,7 +1946,7 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev) + if (i == 0) + sh_mem_base = 0; + else +- sh_mem_base = adev->mc.shared_aperture_start >> 48; ++ sh_mem_base = adev->gmc.shared_aperture_start >> 48; + cik_srbm_select(adev, 0, 0, 0, i); + /* CP and shaders */ + WREG32(mmSH_MEM_CONFIG, sh_mem_cfg); +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +index 3a2011f..c3207af 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +@@ -3799,7 +3799,7 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) + tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE, + SH_MEM_ALIGNMENT_MODE_UNALIGNED); + WREG32(mmSH_MEM_CONFIG, tmp); +- tmp = adev->mc.shared_aperture_start >> 48; ++ tmp = adev->gmc.shared_aperture_start >> 48; + WREG32(mmSH_MEM_BASES, tmp); + } + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index 3e36448..896ce92 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -1539,7 +1539,7 @@ static void gfx_v9_0_gpu_init(struct amdgpu_device *adev) + tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE, + SH_MEM_ALIGNMENT_MODE_UNALIGNED); + WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp); +- tmp = adev->mc.shared_aperture_start >> 48; ++ tmp = adev->gmc.shared_aperture_start >> 48; + WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); + } + } +@@ -3694,11 +3694,11 @@ static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring, + { + struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; + int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); +- uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid); ++ uint32_t req = ring->adev->gmc.gmc_funcs->get_invalidate_req(vmid); + uint64_t flags = AMDGPU_PTE_VALID; + unsigned eng = ring->vm_inv_eng; + +- amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags); ++ amdgpu_gmc_get_vm_pde(ring->adev, -1, &pd_addr, &flags); + pd_addr |= flags; + + gfx_v9_0_write_data_to_reg(ring, usepfp, true, +diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c +index 56f5fe4..94a07bc 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c +@@ -40,7 +40,7 @@ static void gfxhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev) + uint64_t value; + + BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL)); +- value = adev->gart.table_addr - adev->mc.vram_start ++ value = adev->gart.table_addr - adev->gmc.vram_start + + adev->vm_manager.vram_base_offset; + value &= 0x0000FFFFFFFFF000ULL; + value |= 0x1; /*valid bit*/ +@@ -57,14 +57,14 @@ static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev) + gfxhub_v1_0_init_gart_pt_regs(adev); + + WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, +- (u32)(adev->mc.gart_start >> 12)); ++ (u32)(adev->gmc.gart_start >> 12)); + WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, +- (u32)(adev->mc.gart_start >> 44)); ++ (u32)(adev->gmc.gart_start >> 44)); + + WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, +- (u32)(adev->mc.gart_end >> 12)); ++ (u32)(adev->gmc.gart_end >> 12)); + WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, +- (u32)(adev->mc.gart_end >> 44)); ++ (u32)(adev->gmc.gart_end >> 44)); + } + + static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) +@@ -78,12 +78,12 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) + + /* Program the system aperture low logical page number. */ + WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, +- adev->mc.vram_start >> 18); ++ adev->gmc.vram_start >> 18); + WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, +- adev->mc.vram_end >> 18); ++ adev->gmc.vram_end >> 18); + + /* Set default page address. */ +- value = adev->vram_scratch.gpu_addr - adev->mc.vram_start ++ value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start + + adev->vm_manager.vram_base_offset; + WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, + (u32)(value >> 12)); +@@ -143,7 +143,7 @@ static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev) + WREG32_SOC15(GC, 0, mmVM_L2_CNTL2, tmp); + + tmp = mmVM_L2_CNTL3_DEFAULT; +- if (adev->mc.translate_further) { ++ if (adev->gmc.translate_further) { + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, + L2_CACHE_BIGK_FRAGMENT_SIZE, 9); +@@ -195,7 +195,7 @@ static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev) + + num_level = adev->vm_manager.num_level; + block_size = adev->vm_manager.block_size; +- if (adev->mc.translate_further) ++ if (adev->gmc.translate_further) + num_level -= 1; + else + block_size -= 9; +@@ -257,9 +257,9 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev) + * SRIOV driver need to program them + */ + WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE, +- adev->mc.vram_start >> 24); ++ adev->gmc.vram_start >> 24); + WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP, +- adev->mc.vram_end >> 24); ++ adev->gmc.vram_end >> 24); + } + + /* GART Enable. */ +diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +index ee2e2a8..32fd4e2 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +@@ -36,7 +36,7 @@ + #include "dce/dce_6_0_sh_mask.h" + #include "si_enums.h" + +-static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev); ++static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev); + static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev); + static int gmc_v6_0_wait_for_idle(void *handle); + +@@ -136,19 +136,19 @@ static int gmc_v6_0_init_microcode(struct amdgpu_device *adev) + snprintf(fw_name, sizeof(fw_name), "radeon/si58_mc.bin"); + else + snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name); +- err = request_firmware(&adev->mc.fw, fw_name, adev->dev); ++ err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); + if (err) + goto out; + +- err = amdgpu_ucode_validate(adev->mc.fw); ++ err = amdgpu_ucode_validate(adev->gmc.fw); + + out: + if (err) { + dev_err(adev->dev, + "si_mc: Failed to load firmware \"%s\"\n", + fw_name); +- release_firmware(adev->mc.fw); +- adev->mc.fw = NULL; ++ release_firmware(adev->gmc.fw); ++ adev->gmc.fw = NULL; + } + return err; + } +@@ -161,20 +161,20 @@ static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev) + int i, regs_size, ucode_size; + const struct mc_firmware_header_v1_0 *hdr; + +- if (!adev->mc.fw) ++ if (!adev->gmc.fw) + return -EINVAL; + +- hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data; ++ hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; + + amdgpu_ucode_print_mc_hdr(&hdr->header); + +- adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version); ++ adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); + regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); + new_io_mc_regs = (const __le32 *) +- (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); ++ (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); + ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; + new_fw_data = (const __le32 *) +- (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); ++ (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); + + running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK; + +@@ -217,12 +217,12 @@ static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev) + } + + static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev, +- struct amdgpu_mc *mc) ++ struct amdgpu_gmc *mc) + { + u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; + base <<= 24; + +- amdgpu_device_vram_location(adev, &adev->mc, base); ++ amdgpu_device_vram_location(adev, &adev->gmc, base); + amdgpu_device_gart_location(adev, mc); + } + +@@ -259,9 +259,9 @@ static void gmc_v6_0_mc_program(struct amdgpu_device *adev) + } + /* Update configuration */ + WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, +- adev->mc.vram_start >> 12); ++ adev->gmc.vram_start >> 12); + WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, +- adev->mc.vram_end >> 12); ++ adev->gmc.vram_end >> 12); + WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, + adev->vram_scratch.gpu_addr >> 12); + WREG32(mmMC_VM_AGP_BASE, 0); +@@ -319,10 +319,10 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev) + numchan = 16; + break; + } +- adev->mc.vram_width = numchan * chansize; ++ adev->gmc.vram_width = numchan * chansize; + /* size in MB on si */ +- adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; +- adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; ++ adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; ++ adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; + + #if !defined(BUILD_AS_DKMS) || LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0) + if (!(adev->flags & AMD_IS_APU)) { +@@ -331,44 +331,41 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev) + return r; + } + #endif +- adev->mc.aper_base = pci_resource_start(adev->pdev, 0); +- adev->mc.aper_size = pci_resource_len(adev->pdev, 0); +- adev->mc.visible_vram_size = adev->mc.aper_size; ++ adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); ++ adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); ++ adev->gmc.visible_vram_size = adev->gmc.aper_size; + + /* set the gart size */ + if (amdgpu_gart_size == -1) { + switch (adev->asic_type) { + case CHIP_HAINAN: /* no MM engines */ + default: +- adev->mc.gart_size = 256ULL << 20; ++ adev->gmc.gart_size = 256ULL << 20; + break; + case CHIP_VERDE: /* UVD, VCE do not support GPUVM */ + case CHIP_TAHITI: /* UVD, VCE do not support GPUVM */ + case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */ + case CHIP_OLAND: /* UVD, VCE do not support GPUVM */ +- adev->mc.gart_size = 1024ULL << 20; ++ adev->gmc.gart_size = 1024ULL << 20; + break; + } + } else { +- adev->mc.gart_size = (u64)amdgpu_gart_size << 20; ++ adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; + } + +- gmc_v6_0_vram_gtt_location(adev, &adev->mc); ++ gmc_v6_0_vram_gtt_location(adev, &adev->gmc); + + return 0; + } + +-static void gmc_v6_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, +- uint32_t vmid) ++static void gmc_v6_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid) + { + WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); + } + +-static int gmc_v6_0_gart_set_pte_pde(struct amdgpu_device *adev, +- void *cpu_pt_addr, +- uint32_t gpu_page_idx, +- uint64_t addr, +- uint64_t flags) ++static int gmc_v6_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, ++ uint32_t gpu_page_idx, uint64_t addr, ++ uint64_t flags) + { + void __iomem *ptr = (void *)cpu_pt_addr; + uint64_t value; +@@ -432,9 +429,9 @@ static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable) + { + u32 tmp; + +- if (enable && !adev->mc.prt_warning) { ++ if (enable && !adev->gmc.prt_warning) { + dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); +- adev->mc.prt_warning = true; ++ adev->gmc.prt_warning = true; + } + + tmp = RREG32(mmVM_PRT_CNTL); +@@ -514,8 +511,8 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev) + (field << VM_L2_CNTL3__BANK_SELECT__SHIFT) | + (field << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT)); + /* setup context0 */ +- WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gart_start >> 12); +- WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gart_end >> 12); ++ WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); ++ WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); + WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); + WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, + (u32)(adev->dummy_page.addr >> 12)); +@@ -560,9 +557,9 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev) + else + gmc_v6_0_set_fault_enable_default(adev, true); + +- gmc_v6_0_gart_flush_gpu_tlb(adev, 0); ++ gmc_v6_0_flush_gpu_tlb(adev, 0); + dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n", +- (unsigned)(adev->mc.gart_size >> 20), ++ (unsigned)(adev->gmc.gart_size >> 20), + (unsigned long long)adev->gart.table_addr); + adev->gart.ready = true; + return 0; +@@ -794,7 +791,7 @@ static int gmc_v6_0_early_init(void *handle) + { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + +- gmc_v6_0_set_gart_funcs(adev); ++ gmc_v6_0_set_gmc_funcs(adev); + gmc_v6_0_set_irq_funcs(adev); + + return 0; +@@ -805,7 +802,7 @@ static int gmc_v6_0_late_init(void *handle) + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) +- return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0); ++ return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); + else + return 0; + } +@@ -817,26 +814,26 @@ static int gmc_v6_0_sw_init(void *handle) + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + if (adev->flags & AMD_IS_APU) { +- adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; ++ adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; + } else { + u32 tmp = RREG32(mmMC_SEQ_MISC0); + tmp &= MC_SEQ_MISC0__MT__MASK; +- adev->mc.vram_type = gmc_v6_0_convert_vram_type(tmp); ++ adev->gmc.vram_type = gmc_v6_0_convert_vram_type(tmp); + } + +- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->mc.vm_fault); ++ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault); + if (r) + return r; + +- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->mc.vm_fault); ++ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault); + if (r) + return r; + + amdgpu_vm_adjust_size(adev, 64, 9, 1, 40); + +- adev->mc.mc_mask = 0xffffffffffULL; ++ adev->gmc.mc_mask = 0xffffffffffULL; + +- adev->mc.stolen_size = 256 * 1024; ++ adev->gmc.stolen_size = 256 * 1024; + + adev->need_dma32 = false; + dma_bits = adev->need_dma32 ? 32 : 40; +@@ -900,8 +897,8 @@ static int gmc_v6_0_sw_fini(void *handle) + amdgpu_vm_manager_fini(adev); + gmc_v6_0_gart_fini(adev); + amdgpu_bo_fini(adev); +- release_firmware(adev->mc.fw); +- adev->mc.fw = NULL; ++ release_firmware(adev->gmc.fw); ++ adev->gmc.fw = NULL; + + return 0; + } +@@ -932,7 +929,7 @@ static int gmc_v6_0_hw_fini(void *handle) + { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + +- amdgpu_irq_put(adev, &adev->mc.vm_fault, 0); ++ amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); + gmc_v6_0_gart_disable(adev); + + return 0; +@@ -1127,9 +1124,9 @@ static const struct amd_ip_funcs gmc_v6_0_ip_funcs = { + .set_powergating_state = gmc_v6_0_set_powergating_state, + }; + +-static const struct amdgpu_gart_funcs gmc_v6_0_gart_funcs = { +- .flush_gpu_tlb = gmc_v6_0_gart_flush_gpu_tlb, +- .set_pte_pde = gmc_v6_0_gart_set_pte_pde, ++static const struct amdgpu_gmc_funcs gmc_v6_0_gmc_funcs = { ++ .flush_gpu_tlb = gmc_v6_0_flush_gpu_tlb, ++ .set_pte_pde = gmc_v6_0_set_pte_pde, + .set_prt = gmc_v6_0_set_prt, + .get_vm_pde = gmc_v6_0_get_vm_pde, + .get_vm_pte_flags = gmc_v6_0_get_vm_pte_flags +@@ -1140,16 +1137,16 @@ static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = { + .process = gmc_v6_0_process_interrupt, + }; + +-static void gmc_v6_0_set_gart_funcs(struct amdgpu_device *adev) ++static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev) + { +- if (adev->gart.gart_funcs == NULL) +- adev->gart.gart_funcs = &gmc_v6_0_gart_funcs; ++ if (adev->gmc.gmc_funcs == NULL) ++ adev->gmc.gmc_funcs = &gmc_v6_0_gmc_funcs; + } + + static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev) + { +- adev->mc.vm_fault.num_types = 1; +- adev->mc.vm_fault.funcs = &gmc_v6_0_irq_funcs; ++ adev->gmc.vm_fault.num_types = 1; ++ adev->gmc.vm_fault.funcs = &gmc_v6_0_irq_funcs; + } + + const struct amdgpu_ip_block_version gmc_v6_0_ip_block = +diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +index 754dd0c..7874326 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +@@ -43,7 +43,7 @@ + + #include "amdgpu_atombios.h" + +-static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev); ++static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev); + static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev); + static int gmc_v7_0_wait_for_idle(void *handle); + +@@ -152,16 +152,16 @@ static int gmc_v7_0_init_microcode(struct amdgpu_device *adev) + else + snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name); + +- err = request_firmware(&adev->mc.fw, fw_name, adev->dev); ++ err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); + if (err) + goto out; +- err = amdgpu_ucode_validate(adev->mc.fw); ++ err = amdgpu_ucode_validate(adev->gmc.fw); + + out: + if (err) { + pr_err("cik_mc: Failed to load firmware \"%s\"\n", fw_name); +- release_firmware(adev->mc.fw); +- adev->mc.fw = NULL; ++ release_firmware(adev->gmc.fw); ++ adev->gmc.fw = NULL; + } + return err; + } +@@ -182,19 +182,19 @@ static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev) + u32 running; + int i, ucode_size, regs_size; + +- if (!adev->mc.fw) ++ if (!adev->gmc.fw) + return -EINVAL; + +- hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data; ++ hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; + amdgpu_ucode_print_mc_hdr(&hdr->header); + +- adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version); ++ adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); + regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); + io_mc_regs = (const __le32 *) +- (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); ++ (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); + ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; + fw_data = (const __le32 *) +- (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); ++ (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); + + running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); + +@@ -236,12 +236,12 @@ static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev) + } + + static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev, +- struct amdgpu_mc *mc) ++ struct amdgpu_gmc *mc) + { + u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; + base <<= 24; + +- amdgpu_device_vram_location(adev, &adev->mc, base); ++ amdgpu_device_vram_location(adev, &adev->gmc, base); + amdgpu_device_gart_location(adev, mc); + } + +@@ -284,9 +284,9 @@ static void gmc_v7_0_mc_program(struct amdgpu_device *adev) + } + /* Update configuration */ + WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, +- adev->mc.vram_start >> 12); ++ adev->gmc.vram_start >> 12); + WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, +- adev->mc.vram_end >> 12); ++ adev->gmc.vram_end >> 12); + WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, + adev->vram_scratch.gpu_addr >> 12); + WREG32(mmMC_VM_AGP_BASE, 0); +@@ -319,8 +319,8 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev) + { + int r; + +- adev->mc.vram_width = amdgpu_atombios_get_vram_width(adev); +- if (!adev->mc.vram_width) { ++ adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev); ++ if (!adev->gmc.vram_width) { + u32 tmp; + int chansize, numchan; + +@@ -362,11 +362,11 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev) + numchan = 16; + break; + } +- adev->mc.vram_width = numchan * chansize; ++ adev->gmc.vram_width = numchan * chansize; + } + /* size in MB on si */ +- adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; +- adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; ++ adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; ++ adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; + + #if !defined(BUILD_AS_DKMS) || LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0) + if (!(adev->flags & AMD_IS_APU)) { +@@ -375,27 +375,27 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev) + return r; + } + #endif +- adev->mc.aper_base = pci_resource_start(adev->pdev, 0); +- adev->mc.aper_size = pci_resource_len(adev->pdev, 0); ++ adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); ++ adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); + + #ifdef CONFIG_X86_64 + if (adev->flags & AMD_IS_APU) { +- adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; +- adev->mc.aper_size = adev->mc.real_vram_size; ++ adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; ++ adev->gmc.aper_size = adev->gmc.real_vram_size; + } + #endif + + /* In case the PCI BAR is larger than the actual amount of vram */ +- adev->mc.visible_vram_size = adev->mc.aper_size; +- if (adev->mc.visible_vram_size > adev->mc.real_vram_size) +- adev->mc.visible_vram_size = adev->mc.real_vram_size; ++ adev->gmc.visible_vram_size = adev->gmc.aper_size; ++ if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) ++ adev->gmc.visible_vram_size = adev->gmc.real_vram_size; + + /* set the gart size */ + if (amdgpu_gart_size == -1) { + switch (adev->asic_type) { + case CHIP_TOPAZ: /* no MM engines */ + default: +- adev->mc.gart_size = 256ULL << 20; ++ adev->gmc.gart_size = 256ULL << 20; + break; + #ifdef CONFIG_DRM_AMDGPU_CIK + case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */ +@@ -403,15 +403,15 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev) + case CHIP_KAVERI: /* UVD, VCE do not support GPUVM */ + case CHIP_KABINI: /* UVD, VCE do not support GPUVM */ + case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */ +- adev->mc.gart_size = 1024ULL << 20; ++ adev->gmc.gart_size = 1024ULL << 20; + break; + #endif + } + } else { +- adev->mc.gart_size = (u64)amdgpu_gart_size << 20; ++ adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; + } + +- gmc_v7_0_vram_gtt_location(adev, &adev->mc); ++ gmc_v7_0_vram_gtt_location(adev, &adev->gmc); + + return 0; + } +@@ -424,22 +424,21 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev) + */ + + /** +- * gmc_v7_0_gart_flush_gpu_tlb - gart tlb flush callback ++ * gmc_v7_0_flush_gpu_tlb - gart tlb flush callback + * + * @adev: amdgpu_device pointer + * @vmid: vm instance to flush + * + * Flush the TLB for the requested page table (CIK). + */ +-static void gmc_v7_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, +- uint32_t vmid) ++static void gmc_v7_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid) + { + /* bits 0-15 are the VM contexts0-15 */ + WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); + } + + /** +- * gmc_v7_0_gart_set_pte_pde - update the page tables using MMIO ++ * gmc_v7_0_set_pte_pde - update the page tables using MMIO + * + * @adev: amdgpu_device pointer + * @cpu_pt_addr: cpu address of the page table +@@ -449,11 +448,9 @@ static void gmc_v7_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, + * + * Update the page tables using the CPU. + */ +-static int gmc_v7_0_gart_set_pte_pde(struct amdgpu_device *adev, +- void *cpu_pt_addr, +- uint32_t gpu_page_idx, +- uint64_t addr, +- uint64_t flags) ++static int gmc_v7_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, ++ uint32_t gpu_page_idx, uint64_t addr, ++ uint64_t flags) + { + void __iomem *ptr = (void *)cpu_pt_addr; + uint64_t value; +@@ -523,9 +520,9 @@ static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable) + { + uint32_t tmp; + +- if (enable && !adev->mc.prt_warning) { ++ if (enable && !adev->gmc.prt_warning) { + dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); +- adev->mc.prt_warning = true; ++ adev->gmc.prt_warning = true; + } + + tmp = RREG32(mmVM_PRT_CNTL); +@@ -621,8 +618,8 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev) + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field); + WREG32(mmVM_L2_CNTL3, tmp); + /* setup context0 */ +- WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gart_start >> 12); +- WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gart_end >> 12); ++ WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); ++ WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); + WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); + WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, + (u32)(adev->dummy_page.addr >> 12)); +@@ -674,9 +671,9 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev) + WREG32(mmCHUB_CONTROL, tmp); + } + +- gmc_v7_0_gart_flush_gpu_tlb(adev, 0); ++ gmc_v7_0_flush_gpu_tlb(adev, 0); + DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", +- (unsigned)(adev->mc.gart_size >> 20), ++ (unsigned)(adev->gmc.gart_size >> 20), + (unsigned long long)adev->gart.table_addr); + adev->gart.ready = true; + return 0; +@@ -923,16 +920,16 @@ static int gmc_v7_0_early_init(void *handle) + { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + +- gmc_v7_0_set_gart_funcs(adev); ++ gmc_v7_0_set_gmc_funcs(adev); + gmc_v7_0_set_irq_funcs(adev); + +- adev->mc.shared_aperture_start = 0x2000000000000000ULL; +- adev->mc.shared_aperture_end = +- adev->mc.shared_aperture_start + (4ULL << 30) - 1; +- adev->mc.private_aperture_start = +- adev->mc.shared_aperture_end + 1; +- adev->mc.private_aperture_end = +- adev->mc.private_aperture_start + (4ULL << 30) - 1; ++ adev->gmc.shared_aperture_start = 0x2000000000000000ULL; ++ adev->gmc.shared_aperture_end = ++ adev->gmc.shared_aperture_start + (4ULL << 30) - 1; ++ adev->gmc.private_aperture_start = ++ adev->gmc.shared_aperture_end + 1; ++ adev->gmc.private_aperture_end = ++ adev->gmc.private_aperture_start + (4ULL << 30) - 1; + + return 0; + } +@@ -942,7 +939,7 @@ static int gmc_v7_0_late_init(void *handle) + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) +- return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0); ++ return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); + else + return 0; + } +@@ -954,18 +951,18 @@ static int gmc_v7_0_sw_init(void *handle) + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + if (adev->flags & AMD_IS_APU) { +- adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; ++ adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; + } else { + u32 tmp = RREG32(mmMC_SEQ_MISC0); + tmp &= MC_SEQ_MISC0__MT__MASK; +- adev->mc.vram_type = gmc_v7_0_convert_vram_type(tmp); ++ adev->gmc.vram_type = gmc_v7_0_convert_vram_type(tmp); + } + +- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->mc.vm_fault); ++ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault); + if (r) + return r; + +- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->mc.vm_fault); ++ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault); + if (r) + return r; + +@@ -979,9 +976,9 @@ static int gmc_v7_0_sw_init(void *handle) + * This is the max address of the GPU's + * internal address space. + */ +- adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ ++ adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ + +- adev->mc.stolen_size = 256 * 1024; ++ adev->gmc.stolen_size = 256 * 1024; + + /* set DMA mask + need_dma32 flags. + * PCIE - can handle 40-bits. +@@ -1058,8 +1055,8 @@ static int gmc_v7_0_sw_fini(void *handle) + amdgpu_vm_manager_fini(adev); + gmc_v7_0_gart_fini(adev); + amdgpu_bo_fini(adev); +- release_firmware(adev->mc.fw); +- adev->mc.fw = NULL; ++ release_firmware(adev->gmc.fw); ++ adev->gmc.fw = NULL; + + return 0; + } +@@ -1092,7 +1089,7 @@ static int gmc_v7_0_hw_fini(void *handle) + { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + +- amdgpu_irq_put(adev, &adev->mc.vm_fault, 0); ++ amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); + gmc_v7_0_gart_disable(adev); + + return 0; +@@ -1339,9 +1336,9 @@ static const struct amd_ip_funcs gmc_v7_0_ip_funcs = { + .set_powergating_state = gmc_v7_0_set_powergating_state, + }; + +-static const struct amdgpu_gart_funcs gmc_v7_0_gart_funcs = { +- .flush_gpu_tlb = gmc_v7_0_gart_flush_gpu_tlb, +- .set_pte_pde = gmc_v7_0_gart_set_pte_pde, ++static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = { ++ .flush_gpu_tlb = gmc_v7_0_flush_gpu_tlb, ++ .set_pte_pde = gmc_v7_0_set_pte_pde, + .set_prt = gmc_v7_0_set_prt, + .get_vm_pte_flags = gmc_v7_0_get_vm_pte_flags, + .get_vm_pde = gmc_v7_0_get_vm_pde +@@ -1352,16 +1349,16 @@ static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = { + .process = gmc_v7_0_process_interrupt, + }; + +-static void gmc_v7_0_set_gart_funcs(struct amdgpu_device *adev) ++static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev) + { +- if (adev->gart.gart_funcs == NULL) +- adev->gart.gart_funcs = &gmc_v7_0_gart_funcs; ++ if (adev->gmc.gmc_funcs == NULL) ++ adev->gmc.gmc_funcs = &gmc_v7_0_gmc_funcs; + } + + static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev) + { +- adev->mc.vm_fault.num_types = 1; +- adev->mc.vm_fault.funcs = &gmc_v7_0_irq_funcs; ++ adev->gmc.vm_fault.num_types = 1; ++ adev->gmc.vm_fault.funcs = &gmc_v7_0_irq_funcs; + } + + const struct amdgpu_ip_block_version gmc_v7_0_ip_block = +diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +index 87d127c..623d5f9 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +@@ -45,7 +45,7 @@ + #include "amdgpu_atombios.h" + + +-static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev); ++static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev); + static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev); + static int gmc_v8_0_wait_for_idle(void *handle); + +@@ -236,16 +236,16 @@ static int gmc_v8_0_init_microcode(struct amdgpu_device *adev) + } + + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name); +- err = request_firmware(&adev->mc.fw, fw_name, adev->dev); ++ err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); + if (err) + goto out; +- err = amdgpu_ucode_validate(adev->mc.fw); ++ err = amdgpu_ucode_validate(adev->gmc.fw); + + out: + if (err) { + pr_err("mc: Failed to load firmware \"%s\"\n", fw_name); +- release_firmware(adev->mc.fw); +- adev->mc.fw = NULL; ++ release_firmware(adev->gmc.fw); ++ adev->gmc.fw = NULL; + } + return err; + } +@@ -274,19 +274,19 @@ static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev) + if (amdgpu_sriov_bios(adev)) + return 0; + +- if (!adev->mc.fw) ++ if (!adev->gmc.fw) + return -EINVAL; + +- hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data; ++ hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; + amdgpu_ucode_print_mc_hdr(&hdr->header); + +- adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version); ++ adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); + regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); + io_mc_regs = (const __le32 *) +- (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); ++ (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); + ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; + fw_data = (const __le32 *) +- (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); ++ (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); + + running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN); + +@@ -350,19 +350,19 @@ static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev) + if (vbios_version == 0) + return 0; + +- if (!adev->mc.fw) ++ if (!adev->gmc.fw) + return -EINVAL; + +- hdr = (const struct mc_firmware_header_v1_0 *)adev->mc.fw->data; ++ hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; + amdgpu_ucode_print_mc_hdr(&hdr->header); + +- adev->mc.fw_version = le32_to_cpu(hdr->header.ucode_version); ++ adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); + regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); + io_mc_regs = (const __le32 *) +- (adev->mc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); ++ (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); + ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; + fw_data = (const __le32 *) +- (adev->mc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); ++ (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); + + data = RREG32(mmMC_SEQ_MISC0); + data &= ~(0x40); +@@ -398,7 +398,7 @@ static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev) + } + + static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev, +- struct amdgpu_mc *mc) ++ struct amdgpu_gmc *mc) + { + u64 base = 0; + +@@ -406,7 +406,7 @@ static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev, + base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; + base <<= 24; + +- amdgpu_device_vram_location(adev, &adev->mc, base); ++ amdgpu_device_vram_location(adev, &adev->gmc, base); + amdgpu_device_gart_location(adev, mc); + } + +@@ -449,18 +449,18 @@ static void gmc_v8_0_mc_program(struct amdgpu_device *adev) + } + /* Update configuration */ + WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, +- adev->mc.vram_start >> 12); ++ adev->gmc.vram_start >> 12); + WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, +- adev->mc.vram_end >> 12); ++ adev->gmc.vram_end >> 12); + WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, + adev->vram_scratch.gpu_addr >> 12); + + if (amdgpu_sriov_vf(adev)) { +- tmp = ((adev->mc.vram_end >> 24) & 0xFFFF) << 16; +- tmp |= ((adev->mc.vram_start >> 24) & 0xFFFF); ++ tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16; ++ tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF); + WREG32(mmMC_VM_FB_LOCATION, tmp); + /* XXX double check these! */ +- WREG32(mmHDP_NONSURFACE_BASE, (adev->mc.vram_start >> 8)); ++ WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); + WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); + WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF); + } +@@ -495,8 +495,8 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev) + { + int r; + +- adev->mc.vram_width = amdgpu_atombios_get_vram_width(adev); +- if (!adev->mc.vram_width) { ++ adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev); ++ if (!adev->gmc.vram_width) { + u32 tmp; + int chansize, numchan; + +@@ -538,15 +538,15 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev) + numchan = 16; + break; + } +- adev->mc.vram_width = numchan * chansize; ++ adev->gmc.vram_width = numchan * chansize; + /* FIXME: The above calculation is outdated. + * For HBM provide a temporary fix */ +- if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_HBM) +- adev->mc.vram_width = AMDGPU_VRAM_TYPE_HBM_WIDTH; ++ if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM) ++ adev->gmc.vram_width = AMDGPU_VRAM_TYPE_HBM_WIDTH; + } + /* size in MB on si */ +- adev->mc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; +- adev->mc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; ++ adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; ++ adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; + + #if !defined(BUILD_AS_DKMS) || LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0) + if (!(adev->flags & AMD_IS_APU)) { +@@ -555,20 +555,20 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev) + return r; + } + #endif +- adev->mc.aper_base = pci_resource_start(adev->pdev, 0); +- adev->mc.aper_size = pci_resource_len(adev->pdev, 0); ++ adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); ++ adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); + + #ifdef CONFIG_X86_64 + if (adev->flags & AMD_IS_APU) { +- adev->mc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; +- adev->mc.aper_size = adev->mc.real_vram_size; ++ adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; ++ adev->gmc.aper_size = adev->gmc.real_vram_size; + } + #endif + + /* In case the PCI BAR is larger than the actual amount of vram */ +- adev->mc.visible_vram_size = adev->mc.aper_size; +- if (adev->mc.visible_vram_size > adev->mc.real_vram_size) +- adev->mc.visible_vram_size = adev->mc.real_vram_size; ++ adev->gmc.visible_vram_size = adev->gmc.aper_size; ++ if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) ++ adev->gmc.visible_vram_size = adev->gmc.real_vram_size; + + /* set the gart size */ + if (amdgpu_gart_size == -1) { +@@ -577,20 +577,20 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev) + case CHIP_POLARIS10: /* all engines support GPUVM */ + case CHIP_POLARIS12: /* all engines support GPUVM */ + default: +- adev->mc.gart_size = 256ULL << 20; ++ adev->gmc.gart_size = 256ULL << 20; + break; + case CHIP_TONGA: /* UVD, VCE do not support GPUVM */ + case CHIP_FIJI: /* UVD, VCE do not support GPUVM */ + case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */ + case CHIP_STONEY: /* UVD does not support GPUVM, DCE SG support */ +- adev->mc.gart_size = 1024ULL << 20; ++ adev->gmc.gart_size = 1024ULL << 20; + break; + } + } else { +- adev->mc.gart_size = (u64)amdgpu_gart_size << 20; ++ adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; + } + +- gmc_v8_0_vram_gtt_location(adev, &adev->mc); ++ gmc_v8_0_vram_gtt_location(adev, &adev->gmc); + + return 0; + } +@@ -603,14 +603,14 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev) + */ + + /** +- * gmc_v8_0_gart_flush_gpu_tlb - gart tlb flush callback ++ * gmc_v8_0_flush_gpu_tlb - gart tlb flush callback + * + * @adev: amdgpu_device pointer + * @vmid: vm instance to flush + * + * Flush the TLB for the requested page table (CIK). + */ +-static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, ++static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev, + uint32_t vmid) + { + /* bits 0-15 are the VM contexts0-15 */ +@@ -618,7 +618,7 @@ static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, + } + + /** +- * gmc_v8_0_gart_set_pte_pde - update the page tables using MMIO ++ * gmc_v8_0_set_pte_pde - update the page tables using MMIO + * + * @adev: amdgpu_device pointer + * @cpu_pt_addr: cpu address of the page table +@@ -628,11 +628,9 @@ static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, + * + * Update the page tables using the CPU. + */ +-static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device *adev, +- void *cpu_pt_addr, +- uint32_t gpu_page_idx, +- uint64_t addr, +- uint64_t flags) ++static int gmc_v8_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, ++ uint32_t gpu_page_idx, uint64_t addr, ++ uint64_t flags) + { + void __iomem *ptr = (void *)cpu_pt_addr; + uint64_t value; +@@ -726,9 +724,9 @@ static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable) + { + u32 tmp; + +- if (enable && !adev->mc.prt_warning) { ++ if (enable && !adev->gmc.prt_warning) { + dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n"); +- adev->mc.prt_warning = true; ++ adev->gmc.prt_warning = true; + } + + tmp = RREG32(mmVM_PRT_CNTL); +@@ -840,8 +838,8 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev) + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0); + WREG32(mmVM_L2_CNTL4, tmp); + /* setup context0 */ +- WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gart_start >> 12); +- WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gart_end >> 12); ++ WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); ++ WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); + WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12); + WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, + (u32)(adev->dummy_page.addr >> 12)); +@@ -894,9 +892,9 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev) + else + gmc_v8_0_set_fault_enable_default(adev, true); + +- gmc_v8_0_gart_flush_gpu_tlb(adev, 0); ++ gmc_v8_0_flush_gpu_tlb(adev, 0); + DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", +- (unsigned)(adev->mc.gart_size >> 20), ++ (unsigned)(adev->gmc.gart_size >> 20), + (unsigned long long)adev->gart.table_addr); + adev->gart.ready = true; + return 0; +@@ -1017,16 +1015,16 @@ static int gmc_v8_0_early_init(void *handle) + { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + +- gmc_v8_0_set_gart_funcs(adev); ++ gmc_v8_0_set_gmc_funcs(adev); + gmc_v8_0_set_irq_funcs(adev); + +- adev->mc.shared_aperture_start = 0x2000000000000000ULL; +- adev->mc.shared_aperture_end = +- adev->mc.shared_aperture_start + (4ULL << 30) - 1; +- adev->mc.private_aperture_start = +- adev->mc.shared_aperture_end + 1; +- adev->mc.private_aperture_end = +- adev->mc.private_aperture_start + (4ULL << 30) - 1; ++ adev->gmc.shared_aperture_start = 0x2000000000000000ULL; ++ adev->gmc.shared_aperture_end = ++ adev->gmc.shared_aperture_start + (4ULL << 30) - 1; ++ adev->gmc.private_aperture_start = ++ adev->gmc.shared_aperture_end + 1; ++ adev->gmc.private_aperture_end = ++ adev->gmc.private_aperture_start + (4ULL << 30) - 1; + + return 0; + } +@@ -1036,7 +1034,7 @@ static int gmc_v8_0_late_init(void *handle) + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) +- return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0); ++ return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); + else + return 0; + } +@@ -1050,7 +1048,7 @@ static int gmc_v8_0_sw_init(void *handle) + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + if (adev->flags & AMD_IS_APU) { +- adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; ++ adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; + } else { + u32 tmp; + +@@ -1059,14 +1057,14 @@ static int gmc_v8_0_sw_init(void *handle) + else + tmp = RREG32(mmMC_SEQ_MISC0); + tmp &= MC_SEQ_MISC0__MT__MASK; +- adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp); ++ adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp); + } + +- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->mc.vm_fault); ++ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault); + if (r) + return r; + +- r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->mc.vm_fault); ++ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault); + if (r) + return r; + +@@ -1080,9 +1078,9 @@ static int gmc_v8_0_sw_init(void *handle) + * This is the max address of the GPU's + * internal address space. + */ +- adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ ++ adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ + +- adev->mc.stolen_size = 256 * 1024; ++ adev->gmc.stolen_size = 256 * 1024; + + /* set DMA mask + need_dma32 flags. + * PCIE - can handle 40-bits. +@@ -1159,8 +1157,8 @@ static int gmc_v8_0_sw_fini(void *handle) + amdgpu_vm_manager_fini(adev); + gmc_v8_0_gart_fini(adev); + amdgpu_bo_fini(adev); +- release_firmware(adev->mc.fw); +- adev->mc.fw = NULL; ++ release_firmware(adev->gmc.fw); ++ adev->gmc.fw = NULL; + + return 0; + } +@@ -1201,7 +1199,7 @@ static int gmc_v8_0_hw_fini(void *handle) + { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + +- amdgpu_irq_put(adev, &adev->mc.vm_fault, 0); ++ amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); + gmc_v8_0_gart_disable(adev); + + return 0; +@@ -1281,10 +1279,10 @@ static bool gmc_v8_0_check_soft_reset(void *handle) + SRBM_SOFT_RESET, SOFT_RESET_MC, 1); + } + if (srbm_soft_reset) { +- adev->mc.srbm_soft_reset = srbm_soft_reset; ++ adev->gmc.srbm_soft_reset = srbm_soft_reset; + return true; + } else { +- adev->mc.srbm_soft_reset = 0; ++ adev->gmc.srbm_soft_reset = 0; + return false; + } + } +@@ -1293,7 +1291,7 @@ static int gmc_v8_0_pre_soft_reset(void *handle) + { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + +- if (!adev->mc.srbm_soft_reset) ++ if (!adev->gmc.srbm_soft_reset) + return 0; + + gmc_v8_0_mc_stop(adev); +@@ -1309,9 +1307,9 @@ static int gmc_v8_0_soft_reset(void *handle) + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + u32 srbm_soft_reset; + +- if (!adev->mc.srbm_soft_reset) ++ if (!adev->gmc.srbm_soft_reset) + return 0; +- srbm_soft_reset = adev->mc.srbm_soft_reset; ++ srbm_soft_reset = adev->gmc.srbm_soft_reset; + + if (srbm_soft_reset) { + u32 tmp; +@@ -1339,7 +1337,7 @@ static int gmc_v8_0_post_soft_reset(void *handle) + { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + +- if (!adev->mc.srbm_soft_reset) ++ if (!adev->gmc.srbm_soft_reset) + return 0; + + gmc_v8_0_mc_resume(adev); +@@ -1676,9 +1674,9 @@ static const struct amd_ip_funcs gmc_v8_0_ip_funcs = { + .get_clockgating_state = gmc_v8_0_get_clockgating_state, + }; + +-static const struct amdgpu_gart_funcs gmc_v8_0_gart_funcs = { +- .flush_gpu_tlb = gmc_v8_0_gart_flush_gpu_tlb, +- .set_pte_pde = gmc_v8_0_gart_set_pte_pde, ++static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = { ++ .flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb, ++ .set_pte_pde = gmc_v8_0_set_pte_pde, + .set_prt = gmc_v8_0_set_prt, + .get_vm_pte_flags = gmc_v8_0_get_vm_pte_flags, + .get_vm_pde = gmc_v8_0_get_vm_pde +@@ -1689,16 +1687,16 @@ static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = { + .process = gmc_v8_0_process_interrupt, + }; + +-static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev) ++static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev) + { +- if (adev->gart.gart_funcs == NULL) +- adev->gart.gart_funcs = &gmc_v8_0_gart_funcs; ++ if (adev->gmc.gmc_funcs == NULL) ++ adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs; + } + + static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev) + { +- adev->mc.vm_fault.num_types = 1; +- adev->mc.vm_fault.funcs = &gmc_v8_0_irq_funcs; ++ adev->gmc.vm_fault.num_types = 1; ++ adev->gmc.vm_fault.funcs = &gmc_v8_0_irq_funcs; + } + + const struct amdgpu_ip_block_version gmc_v8_0_ip_block = +diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +index 0bb4ef9..0169aad 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +@@ -284,8 +284,8 @@ static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = { + + static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev) + { +- adev->mc.vm_fault.num_types = 1; +- adev->mc.vm_fault.funcs = &gmc_v9_0_irq_funcs; ++ adev->gmc.vm_fault.num_types = 1; ++ adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; + } + + static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid) +@@ -315,21 +315,21 @@ static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid) + */ + + /** +- * gmc_v9_0_gart_flush_gpu_tlb - gart tlb flush callback ++ * gmc_v9_0_flush_gpu_tlb - gart tlb flush callback + * + * @adev: amdgpu_device pointer + * @vmid: vm instance to flush + * + * Flush the TLB for the requested page table. + */ +-static void gmc_v9_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, ++static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, + uint32_t vmid) + { + /* Use register 17 for GART */ + const unsigned eng = 17; + unsigned i, j; + +- spin_lock(&adev->mc.invalidate_lock); ++ spin_lock(&adev->gmc.invalidate_lock); + + for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { + struct amdgpu_vmhub *hub = &adev->vmhub[i]; +@@ -362,11 +362,11 @@ static void gmc_v9_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, + DRM_ERROR("Timeout waiting for VM flush ACK!\n"); + } + +- spin_unlock(&adev->mc.invalidate_lock); ++ spin_unlock(&adev->gmc.invalidate_lock); + } + + /** +- * gmc_v9_0_gart_set_pte_pde - update the page tables using MMIO ++ * gmc_v9_0_set_pte_pde - update the page tables using MMIO + * + * @adev: amdgpu_device pointer + * @cpu_pt_addr: cpu address of the page table +@@ -376,11 +376,9 @@ static void gmc_v9_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, + * + * Update the page tables using the CPU. + */ +-static int gmc_v9_0_gart_set_pte_pde(struct amdgpu_device *adev, +- void *cpu_pt_addr, +- uint32_t gpu_page_idx, +- uint64_t addr, +- uint64_t flags) ++static int gmc_v9_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, ++ uint32_t gpu_page_idx, uint64_t addr, ++ uint64_t flags) + { + void __iomem *ptr = (void *)cpu_pt_addr; + uint64_t value; +@@ -471,10 +469,10 @@ static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, + { + if (!(*flags & AMDGPU_PDE_PTE)) + *addr = adev->vm_manager.vram_base_offset + *addr - +- adev->mc.vram_start; ++ adev->gmc.vram_start; + BUG_ON(*addr & 0xFFFF00000000003FULL); + +- if (!adev->mc.translate_further) ++ if (!adev->gmc.translate_further) + return; + + if (level == AMDGPU_VM_PDB1) { +@@ -490,34 +488,34 @@ static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level, + } + } + +-static const struct amdgpu_gart_funcs gmc_v9_0_gart_funcs = { +- .flush_gpu_tlb = gmc_v9_0_gart_flush_gpu_tlb, +- .set_pte_pde = gmc_v9_0_gart_set_pte_pde, ++static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { ++ .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, ++ .set_pte_pde = gmc_v9_0_set_pte_pde, + .get_invalidate_req = gmc_v9_0_get_invalidate_req, + .get_vm_pte_flags = gmc_v9_0_get_vm_pte_flags, + .get_vm_pde = gmc_v9_0_get_vm_pde + }; + +-static void gmc_v9_0_set_gart_funcs(struct amdgpu_device *adev) ++static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) + { +- if (adev->gart.gart_funcs == NULL) +- adev->gart.gart_funcs = &gmc_v9_0_gart_funcs; ++ if (adev->gmc.gmc_funcs == NULL) ++ adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; + } + + static int gmc_v9_0_early_init(void *handle) + { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + +- gmc_v9_0_set_gart_funcs(adev); ++ gmc_v9_0_set_gmc_funcs(adev); + gmc_v9_0_set_irq_funcs(adev); + +- adev->mc.shared_aperture_start = 0x2000000000000000ULL; +- adev->mc.shared_aperture_end = +- adev->mc.shared_aperture_start + (4ULL << 30) - 1; +- adev->mc.private_aperture_start = +- adev->mc.shared_aperture_end + 1; +- adev->mc.private_aperture_end = +- adev->mc.private_aperture_start + (4ULL << 30) - 1; ++ adev->gmc.shared_aperture_start = 0x2000000000000000ULL; ++ adev->gmc.shared_aperture_end = ++ adev->gmc.shared_aperture_start + (4ULL << 30) - 1; ++ adev->gmc.private_aperture_start = ++ adev->gmc.shared_aperture_end + 1; ++ adev->gmc.private_aperture_end = ++ adev->gmc.private_aperture_start + (4ULL << 30) - 1; + + return 0; + } +@@ -641,16 +639,16 @@ static int gmc_v9_0_late_init(void *handle) + return r; + } + +- return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0); ++ return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); + } + + static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, +- struct amdgpu_mc *mc) ++ struct amdgpu_gmc *mc) + { + u64 base = 0; + if (!amdgpu_sriov_vf(adev)) + base = mmhub_v1_0_get_fb_location(adev); +- amdgpu_device_vram_location(adev, &adev->mc, base); ++ amdgpu_device_vram_location(adev, &adev->gmc, base); + amdgpu_device_gart_location(adev, mc); + /* base offset of vram pages */ + if (adev->flags & AMD_IS_APU) +@@ -674,8 +672,8 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev) + int chansize, numchan; + int r; + +- adev->mc.vram_width = amdgpu_atomfirmware_get_vram_width(adev); +- if (!adev->mc.vram_width) { ++ adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev); ++ if (!adev->gmc.vram_width) { + /* hbm memory channel size */ + if (adev->flags & AMD_IS_APU) + chansize = 64; +@@ -715,13 +713,13 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev) + numchan = 2; + break; + } +- adev->mc.vram_width = numchan * chansize; ++ adev->gmc.vram_width = numchan * chansize; + } + + /* size in MB on si */ +- adev->mc.mc_vram_size = ++ adev->gmc.mc_vram_size = + adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL; +- adev->mc.real_vram_size = adev->mc.mc_vram_size; ++ adev->gmc.real_vram_size = adev->gmc.mc_vram_size; + + #if !defined(BUILD_AS_DKMS) || LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0) + if (!(adev->flags & AMD_IS_APU)) { +@@ -730,30 +728,30 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev) + return r; + } + #endif +- adev->mc.aper_base = pci_resource_start(adev->pdev, 0); +- adev->mc.aper_size = pci_resource_len(adev->pdev, 0); ++ adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); ++ adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); + + /* In case the PCI BAR is larger than the actual amount of vram */ +- adev->mc.visible_vram_size = adev->mc.aper_size; +- if (adev->mc.visible_vram_size > adev->mc.real_vram_size) +- adev->mc.visible_vram_size = adev->mc.real_vram_size; ++ adev->gmc.visible_vram_size = adev->gmc.aper_size; ++ if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) ++ adev->gmc.visible_vram_size = adev->gmc.real_vram_size; + + /* set the gart size */ + if (amdgpu_gart_size == -1) { + switch (adev->asic_type) { + case CHIP_VEGA10: /* all engines support GPUVM */ + default: +- adev->mc.gart_size = 256ULL << 20; ++ adev->gmc.gart_size = 256ULL << 20; + break; + case CHIP_RAVEN: /* DCE SG support */ +- adev->mc.gart_size = 1024ULL << 20; ++ adev->gmc.gart_size = 1024ULL << 20; + break; + } + } else { +- adev->mc.gart_size = (u64)amdgpu_gart_size << 20; ++ adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; + } + +- gmc_v9_0_vram_gtt_location(adev, &adev->mc); ++ gmc_v9_0_vram_gtt_location(adev, &adev->gmc); + + return 0; + } +@@ -785,23 +783,23 @@ static int gmc_v9_0_sw_init(void *handle) + gfxhub_v1_0_init(adev); + mmhub_v1_0_init(adev); + +- spin_lock_init(&adev->mc.invalidate_lock); ++ spin_lock_init(&adev->gmc.invalidate_lock); + + switch (adev->asic_type) { + case CHIP_RAVEN: +- adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; ++ adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; + if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { + amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48); + } else { + /* vm_size is 128TB + 512GB for legacy 3-level page support */ + amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48); +- adev->mc.translate_further = ++ adev->gmc.translate_further = + adev->vm_manager.num_level > 1; + } + break; + case CHIP_VEGA10: + /* XXX Don't know how to get VRAM type yet. */ +- adev->mc.vram_type = AMDGPU_VRAM_TYPE_HBM; ++ adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM; + /* + * To fulfill 4-level page support, + * vm size is 256TB (48bit), maximum size of Vega10, +@@ -815,9 +813,9 @@ static int gmc_v9_0_sw_init(void *handle) + + /* This interrupt is VMC page fault.*/ + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0, +- &adev->mc.vm_fault); ++ &adev->gmc.vm_fault); + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_UTCL2, 0, +- &adev->mc.vm_fault); ++ &adev->gmc.vm_fault); + + if (r) + return r; +@@ -826,13 +824,13 @@ static int gmc_v9_0_sw_init(void *handle) + * This is the max address of the GPU's + * internal address space. + */ +- adev->mc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ ++ adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ + + /* + * It needs to reserve 8M stolen memory for vega10 + * TODO: Figure out how to avoid that... + */ +- adev->mc.stolen_size = 8 * 1024 * 1024; ++ adev->gmc.stolen_size = 8 * 1024 * 1024; + + /* set DMA mask + need_dma32 flags. + * PCIE - can handle 44-bits. +@@ -982,10 +980,10 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) + + gfxhub_v1_0_set_fault_enable_default(adev, value); + mmhub_v1_0_set_fault_enable_default(adev, value); +- gmc_v9_0_gart_flush_gpu_tlb(adev, 0); ++ gmc_v9_0_flush_gpu_tlb(adev, 0); + + DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", +- (unsigned)(adev->mc.gart_size >> 20), ++ (unsigned)(adev->gmc.gart_size >> 20), + (unsigned long long)adev->gart.table_addr); + adev->gart.ready = true; + return 0; +@@ -1036,7 +1034,7 @@ static int gmc_v9_0_hw_fini(void *handle) + return 0; + } + +- amdgpu_irq_put(adev, &adev->mc.vm_fault, 0); ++ amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); + gmc_v9_0_gart_disable(adev); + + return 0; +diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c +index bdf94c6..82f8bc8 100644 +--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c +@@ -50,7 +50,7 @@ static void mmhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev) + uint64_t value; + + BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL)); +- value = adev->gart.table_addr - adev->mc.vram_start + ++ value = adev->gart.table_addr - adev->gmc.vram_start + + adev->vm_manager.vram_base_offset; + value &= 0x0000FFFFFFFFF000ULL; + value |= 0x1; /* valid bit */ +@@ -67,14 +67,14 @@ static void mmhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev) + mmhub_v1_0_init_gart_pt_regs(adev); + + WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, +- (u32)(adev->mc.gart_start >> 12)); ++ (u32)(adev->gmc.gart_start >> 12)); + WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, +- (u32)(adev->mc.gart_start >> 44)); ++ (u32)(adev->gmc.gart_start >> 44)); + + WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, +- (u32)(adev->mc.gart_end >> 12)); ++ (u32)(adev->gmc.gart_end >> 12)); + WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, +- (u32)(adev->mc.gart_end >> 44)); ++ (u32)(adev->gmc.gart_end >> 44)); + } + + static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) +@@ -89,12 +89,12 @@ static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) + + /* Program the system aperture low logical page number. */ + WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, +- adev->mc.vram_start >> 18); ++ adev->gmc.vram_start >> 18); + WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, +- adev->mc.vram_end >> 18); ++ adev->gmc.vram_end >> 18); + + /* Set default page address. */ +- value = adev->vram_scratch.gpu_addr - adev->mc.vram_start + ++ value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start + + adev->vm_manager.vram_base_offset; + WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, + (u32)(value >> 12)); +@@ -155,7 +155,7 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev) + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); + WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp); + +- if (adev->mc.translate_further) { ++ if (adev->gmc.translate_further) { + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); + tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, + L2_CACHE_BIGK_FRAGMENT_SIZE, 9); +@@ -207,7 +207,7 @@ static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev) + + num_level = adev->vm_manager.num_level; + block_size = adev->vm_manager.block_size; +- if (adev->mc.translate_further) ++ if (adev->gmc.translate_further) + num_level -= 1; + else + block_size -= 9; +@@ -499,9 +499,9 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev) + * SRIOV driver need to program them + */ + WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE, +- adev->mc.vram_start >> 24); ++ adev->gmc.vram_start >> 24); + WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP, +- adev->mc.vram_end >> 24); ++ adev->gmc.vram_end >> 24); + } + + /* GART Enable. */ +diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +index bd844ed..484abb9 100644 +--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c ++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +@@ -346,7 +346,7 @@ static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev) + + if ((adev->mman.buffer_funcs_ring == sdma0) || + (adev->mman.buffer_funcs_ring == sdma1)) +- amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); ++ amdgpu_ttm_set_active_vram_size(adev, adev->gmc.visible_vram_size); + + for (i = 0; i < adev->sdma.num_instances; i++) { + rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); +@@ -491,7 +491,7 @@ static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev) + } + + if (adev->mman.buffer_funcs_ring == ring) +- amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size); ++ amdgpu_ttm_set_active_vram_size(adev, adev->gmc.real_vram_size); + } + + return 0; +diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +index fa63c56..5dd13ea 100644 +--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +@@ -518,7 +518,7 @@ static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev) + + if ((adev->mman.buffer_funcs_ring == sdma0) || + (adev->mman.buffer_funcs_ring == sdma1)) +- amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); ++ amdgpu_ttm_set_active_vram_size(adev, adev->gmc.visible_vram_size); + + for (i = 0; i < adev->sdma.num_instances; i++) { + rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); +@@ -758,7 +758,7 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) + } + + if (adev->mman.buffer_funcs_ring == ring) +- amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size); ++ amdgpu_ttm_set_active_vram_size(adev, adev->gmc.real_vram_size); + } + + return 0; +diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +index 3dc9e59..f9b4578 100644 +--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +@@ -440,7 +440,7 @@ static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev) + + if ((adev->mman.buffer_funcs_ring == sdma0) || + (adev->mman.buffer_funcs_ring == sdma1)) +- amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); ++ amdgpu_ttm_set_active_vram_size(adev, adev->gmc.visible_vram_size); + + for (i = 0; i < adev->sdma.num_instances; i++) { + rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); +@@ -682,7 +682,7 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev) + } + + if (adev->mman.buffer_funcs_ring == ring) +- amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size); ++ amdgpu_ttm_set_active_vram_size(adev, adev->gmc.real_vram_size); + + } + +@@ -1136,11 +1136,11 @@ static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring, + unsigned vmid, uint64_t pd_addr) + { + struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; +- uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid); ++ uint32_t req = ring->adev->gmc.gmc_funcs->get_invalidate_req(vmid); + uint64_t flags = AMDGPU_PTE_VALID; + unsigned eng = ring->vm_inv_eng; + +- amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags); ++ amdgpu_gmc_get_vm_pde(ring->adev, -1, &pd_addr, &flags); + pd_addr |= flags; + + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | +diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c +index 9a29c13..54e7a12 100644 +--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c ++++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c +@@ -134,7 +134,7 @@ static void si_dma_stop(struct amdgpu_device *adev) + WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); + + if (adev->mman.buffer_funcs_ring == ring) +- amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); ++ amdgpu_ttm_set_active_vram_size(adev, adev->gmc.visible_vram_size); + ring->ready = false; + } + } +@@ -197,7 +197,7 @@ static int si_dma_start(struct amdgpu_device *adev) + } + + if (adev->mman.buffer_funcs_ring == ring) +- amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size); ++ amdgpu_ttm_set_active_vram_size(adev, adev->gmc.real_vram_size); + } + + return 0; +diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c +index b1a3ca5..c88447d 100644 +--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c ++++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c +@@ -3065,7 +3065,7 @@ static bool si_dpm_vblank_too_short(void *handle) + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + u32 vblank_time = amdgpu_dpm_get_vblank_time(adev); + /* we never hit the non-gddr5 limit so disable it */ +- u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0; ++ u32 switch_limit = adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0; + + if (vblank_time < switch_limit) + return true; +@@ -4328,7 +4328,7 @@ static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk) + if (mclk <= pi->mclk_strobe_mode_threshold) + strobe_mode = true; + +- if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) ++ if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) + result = si_get_mclk_frequency_ratio(mclk, strobe_mode); + else + result = si_get_ddr3_mclk_frequency_ratio(mclk); +@@ -4915,7 +4915,7 @@ static int si_populate_smc_initial_state(struct amdgpu_device *adev, + table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); + table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen; + +- if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { ++ if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { + table->initialState.levels[0].strobeMode = + si_get_strobe_mode_settings(adev, + initial_state->performance_levels[0].mclk); +@@ -5187,7 +5187,7 @@ static int si_init_smc_table(struct amdgpu_device *adev) + if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) + table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; + +- if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) ++ if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) + table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; + + if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) +@@ -5364,7 +5364,7 @@ static int si_populate_mclk_value(struct amdgpu_device *adev, + mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; + mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); + +- if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { ++ if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { + mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); + mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | + YCLK_POST_DIV(mpll_param.post_div); +@@ -5376,7 +5376,7 @@ static int si_populate_mclk_value(struct amdgpu_device *adev, + u32 tmp; + u32 reference_clock = adev->clock.mpll.reference_freq; + +- if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) ++ if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) + freq_nom = memory_clock * 4; + else + freq_nom = memory_clock * 2; +@@ -5468,7 +5468,7 @@ static int si_convert_power_level_to_smc(struct amdgpu_device *adev, + level->mcFlags |= SISLANDS_SMC_MC_PG_EN; + } + +- if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { ++ if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) { + if (pl->mclk > pi->mclk_edc_enable_threshold) + level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; + +@@ -5839,12 +5839,12 @@ static int si_set_mc_special_registers(struct amdgpu_device *adev, + table->mc_reg_table_entry[k].mc_data[j] = + (temp_reg & 0xffff0000) | + (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); +- if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) ++ if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) + table->mc_reg_table_entry[k].mc_data[j] |= 0x100; + } + j++; + +- if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) { ++ if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) { + if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) + return -EINVAL; + table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD; +diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +index 6b95f4f..4c19c96 100644 +--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +@@ -1294,12 +1294,12 @@ static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, + unsigned vmid, uint64_t pd_addr) + { + struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; +- uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid); ++ uint32_t req = ring->adev->gmc.gmc_funcs->get_invalidate_req(vmid); + uint64_t flags = AMDGPU_PTE_VALID; + unsigned eng = ring->vm_inv_eng; + uint32_t data0, data1, mask; + +- amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags); ++ amdgpu_gmc_get_vm_pde(ring->adev, -1, &pd_addr, &flags); + pd_addr |= flags; + + data0 = (hub->ctx0_ptb_addr_hi32 + vmid * 2) << 2; +@@ -1346,11 +1346,11 @@ static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, + unsigned int vmid, uint64_t pd_addr) + { + struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; +- uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid); ++ uint32_t req = ring->adev->gmc.gmc_funcs->get_invalidate_req(vmid); + uint64_t flags = AMDGPU_PTE_VALID; + unsigned eng = ring->vm_inv_eng; + +- amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags); ++ amdgpu_gmc_get_vm_pde(ring->adev, -1, &pd_addr, &flags); + pd_addr |= flags; + + amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE); +diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +index 7cf2eef..071fb17 100755 +--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +@@ -968,11 +968,11 @@ static void vce_v4_0_emit_vm_flush(struct amdgpu_ring *ring, + unsigned int vmid, uint64_t pd_addr) + { + struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; +- uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid); ++ uint32_t req = ring->adev->gmc.gmc_funcs->get_invalidate_req(vmid); + uint64_t flags = AMDGPU_PTE_VALID; + unsigned eng = ring->vm_inv_eng; + +- amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags); ++ amdgpu_gmc_get_vm_pde(ring->adev, -1, &pd_addr, &flags); + pd_addr |= flags; + + amdgpu_ring_write(ring, VCE_CMD_REG_WRITE); +diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +index 23dbb1e..6e8dad5 100644 +--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +@@ -913,12 +913,12 @@ static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, + unsigned vmid, uint64_t pd_addr) + { + struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; +- uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid); ++ uint32_t req = ring->adev->gmc.gmc_funcs->get_invalidate_req(vmid); + uint64_t flags = AMDGPU_PTE_VALID; + unsigned eng = ring->vm_inv_eng; + uint32_t data0, data1, mask; + +- amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags); ++ amdgpu_gmc_get_vm_pde(ring->adev, -1, &pd_addr, &flags); + pd_addr |= flags; + + data0 = (hub->ctx0_ptb_addr_hi32 + vmid * 2) << 2; +@@ -1046,11 +1046,11 @@ static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, + unsigned int vmid, uint64_t pd_addr) + { + struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; +- uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid); ++ uint32_t req = ring->adev->gmc.gmc_funcs->get_invalidate_req(vmid); + uint64_t flags = AMDGPU_PTE_VALID; + unsigned eng = ring->vm_inv_eng; + +- amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags); ++ amdgpu_gmc_get_vm_pde(ring->adev, -1, &pd_addr, &flags); + pd_addr |= flags; + + amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +index 47a6a02..6f67892 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -438,7 +438,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) + init_data.asic_id.pci_revision_id = adev->rev_id; + init_data.asic_id.hw_internal_rev = adev->external_rev_id; + +- init_data.asic_id.vram_width = adev->mc.vram_width; ++ init_data.asic_id.vram_width = adev->gmc.vram_width; + /* TODO: initialize init_data.asic_id.vram_type here!!!! */ + init_data.asic_id.atombios_base_address = + adev->mode_info.atom_context->bios; +@@ -1356,7 +1356,7 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) + /* indicate support of immediate flip */ + adev->ddev->mode_config.async_page_flip = true; + +- adev->ddev->mode_config.fb_base = adev->mc.aper_base; ++ adev->ddev->mode_config.fb_base = adev->gmc.aper_base; + + r = amdgpu_modeset_create_props(adev); + if (r) +-- +2.7.4 + |