diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3127-drm-amd-display-Update-dcn10_init_hw-for-FPGA.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3127-drm-amd-display-Update-dcn10_init_hw-for-FPGA.patch | 75 |
1 files changed, 75 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3127-drm-amd-display-Update-dcn10_init_hw-for-FPGA.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3127-drm-amd-display-Update-dcn10_init_hw-for-FPGA.patch new file mode 100644 index 00000000..103e3151 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3127-drm-amd-display-Update-dcn10_init_hw-for-FPGA.patch @@ -0,0 +1,75 @@ +From 42ae6312733caf8f889f8eb447c54f4adc2fbc8b Mon Sep 17 00:00:00 2001 +From: Eric Bernstein <eric.bernstein@amd.com> +Date: Tue, 2 Jan 2018 17:04:55 -0500 +Subject: [PATCH 3127/4131] drm/amd/display: Update dcn10_init_hw for FPGA + +Update dcn10_init_hw such that initialization of relevant +HW blocks for Maximus FPGA are also initialized (and not skipped). + +Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Harry Wentland <harry.wentland@amd.com> +--- + .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 35 ++++++++++++---------- + 1 file changed, 19 insertions(+), 16 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index 8b6c249..7e99d78 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -692,26 +692,25 @@ static void dcn10_init_hw(struct dc *dc) + } + + enable_power_gating_plane(dc->hwseq, true); +- return; +- } +- /* end of FPGA. Below if real ASIC */ ++ } else { + +- if (!dcb->funcs->is_accelerated_mode(dcb)) { +- bios_golden_init(dc); +- disable_vga(dc->hwseq); +- } ++ if (!dcb->funcs->is_accelerated_mode(dcb)) { ++ bios_golden_init(dc); ++ disable_vga(dc->hwseq); ++ } + +- for (i = 0; i < dc->link_count; i++) { +- /* Power up AND update implementation according to the +- * required signal (which may be different from the +- * default signal on connector). +- */ +- struct dc_link *link = dc->links[i]; ++ for (i = 0; i < dc->link_count; i++) { ++ /* Power up AND update implementation according to the ++ * required signal (which may be different from the ++ * default signal on connector). ++ */ ++ struct dc_link *link = dc->links[i]; + +- if (link->link_enc->connector.id == CONNECTOR_ID_EDP) +- dc->hwss.edp_power_control(link, true); ++ if (link->link_enc->connector.id == CONNECTOR_ID_EDP) ++ dc->hwss.edp_power_control(link, true); + +- link->link_enc->funcs->hw_init(link->link_enc); ++ link->link_enc->funcs->hw_init(link->link_enc); ++ } + } + + for (i = 0; i < dc->res_pool->pipe_count; i++) { +@@ -779,6 +778,10 @@ static void dcn10_init_hw(struct dc *dc) + tg->funcs->tg_init(tg); + } + ++ /* end of FPGA. Below if real ASIC */ ++ if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) ++ return; ++ + for (i = 0; i < dc->res_pool->audio_count; i++) { + struct audio *audio = dc->res_pool->audios[i]; + +-- +2.7.4 + |