diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3111-drm-amd-display-Move-hubp-reg-access-from-hwss-to-hu.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3111-drm-amd-display-Move-hubp-reg-access-from-hwss-to-hu.patch | 216 |
1 files changed, 216 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3111-drm-amd-display-Move-hubp-reg-access-from-hwss-to-hu.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3111-drm-amd-display-Move-hubp-reg-access-from-hwss-to-hu.patch new file mode 100644 index 00000000..82f4134e --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3111-drm-amd-display-Move-hubp-reg-access-from-hwss-to-hu.patch @@ -0,0 +1,216 @@ +From 13ad72113ee3e2b46d1ea80e3475bf4052855b24 Mon Sep 17 00:00:00 2001 +From: Yongqiang Sun <yongqiang.sun@amd.com> +Date: Mon, 18 Dec 2017 14:09:19 -0500 +Subject: [PATCH 3111/4131] drm/amd/display: Move hubp reg access from hwss to + hubp module. + +Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Harry Wentland <harry.wentland@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 12 ------------ + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 17 +++++++++++++++++ + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 15 ++++++++++++--- + .../gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 10 ++++------ + drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 3 +++ + 5 files changed, 36 insertions(+), 21 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +index b73db9e..af96538 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +@@ -140,14 +140,6 @@ + BL_REG_LIST() + + #define HWSEQ_DCN_REG_LIST()\ +- SRII(DCHUBP_CNTL, HUBP, 0), \ +- SRII(DCHUBP_CNTL, HUBP, 1), \ +- SRII(DCHUBP_CNTL, HUBP, 2), \ +- SRII(DCHUBP_CNTL, HUBP, 3), \ +- SRII(HUBP_CLK_CNTL, HUBP, 0), \ +- SRII(HUBP_CLK_CNTL, HUBP, 1), \ +- SRII(HUBP_CLK_CNTL, HUBP, 2), \ +- SRII(HUBP_CLK_CNTL, HUBP, 3), \ + SRII(DPP_CONTROL, DPP_TOP, 0), \ + SRII(DPP_CONTROL, DPP_TOP, 1), \ + SRII(DPP_CONTROL, DPP_TOP, 2), \ +@@ -260,8 +252,6 @@ struct dce_hwseq_registers { + uint32_t DCHUB_AGP_BOT; + uint32_t DCHUB_AGP_TOP; + +- uint32_t DCHUBP_CNTL[4]; +- uint32_t HUBP_CLK_CNTL[4]; + uint32_t DPP_CONTROL[4]; + uint32_t OPP_PIPE_CONTROL[4]; + uint32_t REFCLK_CNTL; +@@ -433,8 +423,6 @@ struct dce_hwseq_registers { + #define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\ + HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\ + HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \ +- HWS_SF(HUBP0_, DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh), \ +- HWS_SF(HUBP0_, HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh), \ + HWS_SF(DPP_TOP0_, DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \ + HWS_SF(OPP_PIPE0_, OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, mask_sh),\ + HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \ +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c +index 585b333..265092b 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c +@@ -909,6 +909,21 @@ void hubp1_cursor_set_position( + /* TODO Handle surface pixel formats other than 4:4:4 */ + } + ++void hubp1_clk_cntl(struct hubp *hubp, bool enable) ++{ ++ struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); ++ uint32_t clk_enable = enable ? 1 : 0; ++ ++ REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable); ++} ++ ++void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst) ++{ ++ struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); ++ ++ REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst); ++} ++ + static struct hubp_funcs dcn10_hubp_funcs = { + .hubp_program_surface_flip_and_addr = + hubp1_program_surface_flip_and_addr, +@@ -925,6 +940,8 @@ static struct hubp_funcs dcn10_hubp_funcs = { + .set_cursor_attributes = hubp1_cursor_set_attributes, + .set_cursor_position = hubp1_cursor_set_position, + .hubp_disconnect = hubp1_disconnect, ++ .hubp_clk_cntl = hubp1_clk_cntl, ++ .hubp_vtg_sel = hubp1_vtg_sel, + }; + + /*****************************************/ +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h +index 33e91d9..a4bcb59 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h +@@ -96,7 +96,8 @@ + SRI(DCN_SURF0_TTU_CNTL1, HUBPREQ, id),\ + SRI(DCN_SURF1_TTU_CNTL0, HUBPREQ, id),\ + SRI(DCN_SURF1_TTU_CNTL1, HUBPREQ, id),\ +- SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id) ++ SRI(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id),\ ++ SRI(HUBP_CLK_CNTL, HUBP, id) + + #define HUBP_REG_LIST_DCN10(id)\ + HUBP_REG_LIST_DCN(id),\ +@@ -230,7 +231,8 @@ + uint32_t CURSOR_CONTROL; \ + uint32_t CURSOR_POSITION; \ + uint32_t CURSOR_HOT_SPOT; \ +- uint32_t CURSOR_DST_OFFSET ++ uint32_t CURSOR_DST_OFFSET; \ ++ uint32_t HUBP_CLK_CNTL + + #define HUBP_SF(reg_name, field_name, post_fix)\ + .field_name = reg_name ## __ ## field_name ## post_fix +@@ -240,6 +242,7 @@ + HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_TTU_DISABLE, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_UNDERFLOW_STATUS, mask_sh),\ + HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_NO_OUTSTANDING_REQ, mask_sh),\ ++ HUBP_SF(HUBP0_DCHUBP_CNTL, HUBP_VTG_SEL, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_PIPES, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_BANKS, mask_sh),\ + HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, PIPE_INTERLEAVE, mask_sh),\ +@@ -352,7 +355,8 @@ + HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL0, QoS_RAMP_DISABLE, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_SURF0_TTU_CNTL1, REFCYC_PER_REQ_DELIVERY_PRE, mask_sh),\ + HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\ +- HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh) ++ HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, mask_sh),\ ++ HUBP_SF(HUBP0_HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, mask_sh) + + #define HUBP_MASK_SH_LIST_DCN10(mask_sh)\ + HUBP_MASK_SH_LIST_DCN(mask_sh),\ +@@ -398,6 +402,7 @@ + type HUBP_BLANK_EN;\ + type HUBP_TTU_DISABLE;\ + type HUBP_NO_OUTSTANDING_REQ;\ ++ type HUBP_VTG_SEL;\ + type HUBP_UNDERFLOW_STATUS;\ + type NUM_PIPES;\ + type NUM_BANKS;\ +@@ -524,6 +529,7 @@ + type VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB;\ + type ENABLE_L1_TLB;\ + type SYSTEM_ACCESS_MODE;\ ++ type HUBP_CLOCK_ENABLE;\ + type MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM;\ + type MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB;\ + type MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB;\ +@@ -653,6 +659,9 @@ void min_set_viewport(struct hubp *hubp, + const struct rect *viewport, + const struct rect *viewport_c); + ++void hubp1_clk_cntl(struct hubp *hubp, bool enable); ++void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst); ++ + void dcn10_hubp_construct( + struct dcn10_hubp *hubp1, + struct dc_context *ctx, +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index 77c4376..0e58185 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -660,8 +660,8 @@ static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx) + + dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx); + +- REG_UPDATE(HUBP_CLK_CNTL[fe_idx], +- HUBP_CLOCK_ENABLE, 0); ++ hubp->funcs->hubp_clk_cntl(hubp, false); ++ + REG_UPDATE(DPP_CONTROL[fe_idx], + DPP_CLOCK_ENABLE, 0); + +@@ -1326,8 +1326,7 @@ static void dcn10_enable_plane( + pipe_ctx->pipe_idx); + + /* enable DCFCLK current DCHUB */ +- REG_UPDATE(HUBP_CLK_CNTL[pipe_ctx->pipe_idx], +- HUBP_CLOCK_ENABLE, 1); ++ pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true); + + /* make sure OPP_PIPE_CLOCK_EN = 1 */ + REG_UPDATE(OPP_PIPE_CONTROL[pipe_ctx->stream_res.tg->inst], +@@ -1679,7 +1678,6 @@ static void update_dchubp_dpp( + struct pipe_ctx *pipe_ctx, + struct dc_state *context) + { +- struct dce_hwseq *hws = dc->hwseq; + struct hubp *hubp = pipe_ctx->plane_res.hubp; + struct dpp *dpp = pipe_ctx->plane_res.dpp; + struct dc_plane_state *plane_state = pipe_ctx->plane_state; +@@ -1702,7 +1700,7 @@ static void update_dchubp_dpp( + * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG + */ + if (plane_state->update_flags.bits.full_update) { +- REG_UPDATE(DCHUBP_CNTL[pipe_ctx->pipe_idx], HUBP_VTG_SEL, pipe_ctx->stream_res.tg->inst); ++ hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst); + + hubp->funcs->hubp_setup( + hubp, +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +index b7c7e70..9ced254 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +@@ -119,6 +119,9 @@ struct hubp_funcs { + + void (*hubp_disconnect)(struct hubp *hubp); + ++ void (*hubp_clk_cntl)(struct hubp *hubp, bool enable); ++ void (*hubp_vtg_sel)(struct hubp *hubp, uint32_t otg_inst); ++ + }; + + #endif +-- +2.7.4 + |