diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3089-drm-amdgpu-adjust-HDP-write-queue-flushing-for-tlb-i.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3089-drm-amdgpu-adjust-HDP-write-queue-flushing-for-tlb-i.patch | 121 |
1 files changed, 121 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3089-drm-amdgpu-adjust-HDP-write-queue-flushing-for-tlb-i.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3089-drm-amdgpu-adjust-HDP-write-queue-flushing-for-tlb-i.patch new file mode 100644 index 00000000..0ecfe60f --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3089-drm-amdgpu-adjust-HDP-write-queue-flushing-for-tlb-i.patch @@ -0,0 +1,121 @@ +From 56a8c30247482a2c787a6a8b0f1b5dc933092778 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Fri, 5 Jan 2018 10:25:57 -0500 +Subject: [PATCH 3089/4131] drm/amdgpu: adjust HDP write queue flushing for tlb + invalidation +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Separate tlb invalidation and hdp flushing and move the HDP +flush to the caller. + +Reviewed-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 2 ++ + drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 ++ + drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 2 -- + drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 3 --- + drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 3 --- + drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 3 --- + 6 files changed, 4 insertions(+), 11 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c +index 0a4f34a..d0617f1 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c +@@ -247,6 +247,7 @@ int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, + } + } + mb(); ++ amdgpu_asic_flush_hdp(adev); + amdgpu_gart_flush_gpu_tlb(adev, 0); + return 0; + } +@@ -329,6 +330,7 @@ int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, + return r; + + mb(); ++ amdgpu_asic_flush_hdp(adev); + amdgpu_gart_flush_gpu_tlb(adev, 0); + return 0; + } +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +index 1b94caa..ea5f4e8 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +@@ -861,6 +861,7 @@ int amdgpu_vm_update_directories(struct amdgpu_device *adev, + if (vm->use_cpu_for_update) { + /* Flush HDP */ + mb(); ++ amdgpu_asic_flush_hdp(adev); + amdgpu_gart_flush_gpu_tlb(adev, 0); + } else if (params.ib->length_dw == 0) { + amdgpu_job_free(job); +@@ -1484,6 +1485,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, + if (vm->use_cpu_for_update) { + /* Flush HDP */ + mb(); ++ amdgpu_asic_flush_hdp(adev); + amdgpu_gart_flush_gpu_tlb(adev, 0); + } + +diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +index 86ba1e7..ee2e2a8 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +@@ -361,8 +361,6 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev) + static void gmc_v6_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, + uint32_t vmid) + { +- WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0); +- + WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); + } + +diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +index bda5f72..1d5d1c5 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +@@ -434,9 +434,6 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev) + static void gmc_v7_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, + uint32_t vmid) + { +- /* flush hdp cache */ +- WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0); +- + /* bits 0-15 are the VM contexts0-15 */ + WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); + } +diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +index ec7ce94..f663f88 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +@@ -613,9 +613,6 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev) + static void gmc_v8_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, + uint32_t vmid) + { +- /* flush hdp cache */ +- WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0); +- + /* bits 0-15 are the VM contexts0-15 */ + WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); + } +diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +index 5c95680..a669a6e 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +@@ -329,9 +329,6 @@ static void gmc_v9_0_gart_flush_gpu_tlb(struct amdgpu_device *adev, + const unsigned eng = 17; + unsigned i, j; + +- /* flush hdp cache */ +- adev->nbio_funcs->hdp_flush(adev); +- + spin_lock(&adev->mc.invalidate_lock); + + for (i = 0; i < AMDGPU_MAX_VMHUBS; ++i) { +-- +2.7.4 + |