diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3024-drm-amd-display-Update-FMT-and-OPPBUF-functions.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3024-drm-amd-display-Update-FMT-and-OPPBUF-functions.patch | 374 |
1 files changed, 374 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3024-drm-amd-display-Update-FMT-and-OPPBUF-functions.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3024-drm-amd-display-Update-FMT-and-OPPBUF-functions.patch new file mode 100644 index 00000000..6cf44935 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3024-drm-amd-display-Update-FMT-and-OPPBUF-functions.patch @@ -0,0 +1,374 @@ +From bfbb6cc651e164675367cb44918bb1993177bb98 Mon Sep 17 00:00:00 2001 +From: Eric Bernstein <eric.bernstein@amd.com> +Date: Tue, 12 Dec 2017 14:14:10 -0500 +Subject: [PATCH 3024/4131] drm/amd/display: Update FMT and OPPBUF functions + +Updates to FMT and OPPBUF programming from HW team +pseudocode review. + +Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Harry Wentland <harry.wentland@amd.com> +--- + .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 12 +--- + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 72 ++++++++++++++++++++-- + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | 43 +++++++++---- + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 16 ----- + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 8 --- + drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 23 +++++-- + 6 files changed, 120 insertions(+), 54 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index 2ca364f..8257286 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -462,9 +462,6 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg( + struct dc_stream_state *stream = pipe_ctx->stream; + enum dc_color_space color_space; + struct tg_color black_color = {0}; +- bool enableStereo = stream->timing.timing_3d_format == TIMING_3D_FORMAT_NONE ? +- false:true; +- bool rightEyePolarity = stream->timing.flags.RIGHT_EYE_3D_POLARITY; + + /* by upper caller loop, pipe0 is parent pipe and be called first. + * back end is set up by for pipe0. Other children pipe share back end +@@ -499,11 +496,6 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg( + &stream->timing, + true); + +- pipe_ctx->stream_res.opp->funcs->opp_set_stereo_polarity( +- pipe_ctx->stream_res.opp, +- enableStereo, +- rightEyePolarity); +- + #if 0 /* move to after enable_crtc */ + /* TODO: OPP FMT, ABM. etc. should be done here. */ + /* or FPGA now. instance 0 only. TODO: move to opp.c */ +@@ -2251,10 +2243,10 @@ static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc) + + dcn10_config_stereo_parameters(stream, &flags); + +- pipe_ctx->stream_res.opp->funcs->opp_set_stereo_polarity( ++ pipe_ctx->stream_res.opp->funcs->opp_program_stereo( + pipe_ctx->stream_res.opp, + flags.PROGRAM_STEREO == 1 ? true:false, +- stream->timing.flags.RIGHT_EYE_3D_POLARITY == 1 ? true:false); ++ &stream->timing); + + pipe_ctx->stream_res.tg->funcs->program_stereo( + pipe_ctx->stream_res.tg, +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c +index 5f07886..f6ba0ee 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c +@@ -296,13 +296,75 @@ void opp1_program_fmt( + return; + } + +-void opp1_set_stereo_polarity( +- struct output_pixel_processor *opp, +- bool enable, bool rightEyePolarity) ++void opp1_program_stereo( ++ struct output_pixel_processor *opp, ++ bool enable, ++ const struct dc_crtc_timing *timing) + { + struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); + +- REG_UPDATE(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, enable); ++ uint32_t active_width = timing->h_addressable - timing->h_border_right - timing->h_border_right; ++ uint32_t space1_size = timing->v_total - timing->v_addressable; ++ /* TODO: confirm computation of space2_size */ ++ uint32_t space2_size = timing->v_total - timing->v_addressable; ++ ++ if (!enable) { ++ active_width = 0; ++ space1_size = 0; ++ space2_size = 0; ++ } ++ ++ /* TODO: for which cases should FMT_STEREOSYNC_OVERRIDE be set? */ ++ REG_UPDATE(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, 0); ++ ++ REG_UPDATE(OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, active_width); ++ ++ /* Program OPPBUF_3D_VACT_SPACE1_SIZE and OPPBUF_VACT_SPACE2_SIZE registers ++ * In 3D progressive frames, Vactive space happens only in between the 2 frames, ++ * so only need to program OPPBUF_3D_VACT_SPACE1_SIZE ++ * In 3D alternative frames, left and right frames, top and bottom field. ++ */ ++ if (timing->timing_3d_format == TIMING_3D_FORMAT_FRAME_ALTERNATE) ++ REG_UPDATE(OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE2_SIZE, space2_size); ++ else ++ REG_UPDATE(OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, space1_size); ++ ++ /* TODO: Is programming of OPPBUF_DUMMY_DATA_R/G/B needed? */ ++ /* ++ REG_UPDATE(OPPBUF_3D_PARAMETERS_0, ++ OPPBUF_DUMMY_DATA_R, data_r); ++ REG_UPDATE(OPPBUF_3D_PARAMETERS_1, ++ OPPBUF_DUMMY_DATA_G, data_g); ++ REG_UPDATE(OPPBUF_3D_PARAMETERS_1, ++ OPPBUF_DUMMY_DATA_B, _data_b); ++ */ ++} ++ ++void opp1_program_oppbuf( ++ struct output_pixel_processor *opp, ++ struct oppbuf_params *oppbuf) ++{ ++ struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp); ++ ++ /* Program the oppbuf active width to be the frame width from mpc */ ++ REG_UPDATE(OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, oppbuf->active_width); ++ ++ /* Specifies the number of segments in multi-segment mode (DP-MSO operation) ++ * description "In 1/2/4 segment mode, specifies the horizontal active width in pixels of the display panel. ++ * In 4 segment split left/right mode, specifies the horizontal 1/2 active width in pixels of the display panel. ++ * Used to determine segment boundaries in multi-segment mode. Used to determine the width of the vertical active space in 3D frame packed modes. ++ * OPPBUF_ACTIVE_WIDTH must be integer divisible by the total number of segments." ++ */ ++ REG_UPDATE(OPPBUF_CONTROL, OPPBUF_DISPLAY_SEGMENTATION, oppbuf->mso_segmentation); ++ ++ /* description "Specifies the number of overlap pixels (1-8 overlapping pixels supported), used in multi-segment mode (DP-MSO operation)" */ ++ REG_UPDATE(OPPBUF_CONTROL, OPPBUF_OVERLAP_PIXEL_NUM, oppbuf->mso_overlap_pixel_num); ++ ++ /* description "Specifies the number of times a pixel is replicated (0-15 pixel replications supported). ++ * A value of 0 disables replication. The total number of times a pixel is output is OPPBUF_PIXEL_REPETITION + 1." ++ */ ++ REG_UPDATE(OPPBUF_CONTROL, OPPBUF_PIXEL_REPETITION, oppbuf->pixel_repetition); ++ + } + + /*****************************************/ +@@ -319,7 +381,7 @@ static struct opp_funcs dcn10_opp_funcs = { + .opp_set_dyn_expansion = opp1_set_dyn_expansion, + .opp_program_fmt = opp1_program_fmt, + .opp_program_bit_depth_reduction = opp1_program_bit_depth_reduction, +- .opp_set_stereo_polarity = opp1_set_stereo_polarity, ++ .opp_program_stereo = opp1_program_stereo, + .opp_destroy = opp1_destroy + }; + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h +index f3c298e..bc5058a 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h +@@ -41,7 +41,10 @@ + SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \ + SRI(FMT_CLAMP_CNTL, FMT, id), \ + SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \ +- SRI(FMT_MAP420_MEMORY_CONTROL, FMT, id) ++ SRI(FMT_MAP420_MEMORY_CONTROL, FMT, id), \ ++ SRI(OPPBUF_CONTROL, OPPBUF, id),\ ++ SRI(OPPBUF_3D_PARAMETERS_0, OPPBUF, id), \ ++ SRI(OPPBUF_3D_PARAMETERS_1, OPPBUF, id) + + #define OPP_REG_LIST_DCN10(id) \ + OPP_REG_LIST_DCN(id) +@@ -54,7 +57,11 @@ + uint32_t FMT_DITHER_RAND_B_SEED; \ + uint32_t FMT_CLAMP_CNTL; \ + uint32_t FMT_DYNAMIC_EXP_CNTL; \ +- uint32_t FMT_MAP420_MEMORY_CONTROL; ++ uint32_t FMT_MAP420_MEMORY_CONTROL; \ ++ uint32_t OPPBUF_CONTROL; \ ++ uint32_t OPPBUF_CONTROL1; \ ++ uint32_t OPPBUF_3D_PARAMETERS_0; \ ++ uint32_t OPPBUF_3D_PARAMETERS_1 + + #define OPP_MASK_SH_LIST_DCN(mask_sh) \ + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh), \ +@@ -78,10 +85,16 @@ + OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh), \ + OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh), \ + OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh), \ +- OPP_SF(FMT0_FMT_MAP420_MEMORY_CONTROL, FMT_MAP420MEM_PWR_FORCE, mask_sh) ++ OPP_SF(FMT0_FMT_MAP420_MEMORY_CONTROL, FMT_MAP420MEM_PWR_FORCE, mask_sh), \ ++ OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, mask_sh),\ ++ OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_PIXEL_REPETITION, mask_sh),\ ++ OPP_SF(OPPBUF0_OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, mask_sh), \ ++ OPP_SF(OPPBUF0_OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE2_SIZE, mask_sh) + + #define OPP_MASK_SH_LIST_DCN10(mask_sh) \ +- OPP_MASK_SH_LIST_DCN(mask_sh) ++ OPP_MASK_SH_LIST_DCN(mask_sh), \ ++ OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_DISPLAY_SEGMENTATION, mask_sh),\ ++ OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_OVERLAP_PIXEL_NUM, mask_sh) + + #define OPP_DCN10_REG_FIELD_LIST(type) \ + type FMT_TRUNCATE_EN; \ +@@ -105,18 +118,25 @@ + type FMT_DYNAMIC_EXP_EN; \ + type FMT_DYNAMIC_EXP_MODE; \ + type FMT_MAP420MEM_PWR_FORCE; \ +- type FMT_STEREOSYNC_OVERRIDE; ++ type FMT_STEREOSYNC_OVERRIDE; \ ++ type OPPBUF_ACTIVE_WIDTH;\ ++ type OPPBUF_PIXEL_REPETITION;\ ++ type OPPBUF_DISPLAY_SEGMENTATION;\ ++ type OPPBUF_OVERLAP_PIXEL_NUM;\ ++ type OPPBUF_NUM_SEGMENT_PADDED_PIXELS; \ ++ type OPPBUF_3D_VACT_SPACE1_SIZE; \ ++ type OPPBUF_3D_VACT_SPACE2_SIZE + + struct dcn10_opp_registers { +- OPP_COMMON_REG_VARIABLE_LIST ++ OPP_COMMON_REG_VARIABLE_LIST; + }; + + struct dcn10_opp_shift { +- OPP_DCN10_REG_FIELD_LIST(uint8_t) ++ OPP_DCN10_REG_FIELD_LIST(uint8_t); + }; + + struct dcn10_opp_mask { +- OPP_DCN10_REG_FIELD_LIST(uint32_t) ++ OPP_DCN10_REG_FIELD_LIST(uint32_t); + }; + + struct dcn10_opp { +@@ -151,9 +171,10 @@ void opp1_program_bit_depth_reduction( + struct output_pixel_processor *opp, + const struct bit_depth_reduction_params *params); + +-void opp1_set_stereo_polarity( +- struct output_pixel_processor *opp, +- bool enable, bool rightEyePolarity); ++void opp1_program_stereo( ++ struct output_pixel_processor *opp, ++ bool enable, ++ const struct dc_crtc_timing *timing); + + void opp1_destroy(struct output_pixel_processor **opp); + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c +index 827dd14..4bf64d1 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c +@@ -91,11 +91,6 @@ static void optc1_disable_stereo(struct timing_generator *optc) + OTG_3D_STRUCTURE_EN, 0, + OTG_3D_STRUCTURE_V_UPDATE_MODE, 0, + OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0); +- +- REG_UPDATE(OPPBUF_CONTROL, +- OPPBUF_ACTIVE_WIDTH, 0); +- REG_UPDATE(OPPBUF_3D_PARAMETERS_0, +- OPPBUF_3D_VACT_SPACE1_SIZE, 0); + } + + /** +@@ -1078,16 +1073,11 @@ void optc1_get_crtc_scanoutpos( + *v_position = position.vertical_count; + } + +- +- + static void optc1_enable_stereo(struct timing_generator *optc, + const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags) + { + struct optc *optc1 = DCN10TG_FROM_TG(optc); + +- uint32_t active_width = timing->h_addressable; +- uint32_t space1_size = timing->v_total - timing->v_addressable; +- + if (flags) { + uint32_t stereo_en; + stereo_en = flags->FRAME_PACKED == 0 ? 1 : 0; +@@ -1114,12 +1104,6 @@ static void optc1_enable_stereo(struct timing_generator *optc, + OTG_3D_STRUCTURE_STEREO_SEL_OVR, flags->FRAME_PACKED); + + } +- +- REG_UPDATE(OPPBUF_CONTROL, +- OPPBUF_ACTIVE_WIDTH, active_width); +- +- REG_UPDATE(OPPBUF_3D_PARAMETERS_0, +- OPPBUF_3D_VACT_SPACE1_SIZE, space1_size); + } + + void optc1_program_stereo(struct timing_generator *optc, +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h +index eec860fa..a3c7c20 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h +@@ -70,8 +70,6 @@ + SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\ + SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\ + SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\ +- SRI(OPPBUF_CONTROL, OPPBUF, inst),\ +- SRI(OPPBUF_3D_PARAMETERS_0, OPPBUF, inst),\ + SRI(CONTROL, VTG, inst),\ + SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\ + SRI(OTG_MASTER_UPDATE_MODE, OTG, inst),\ +@@ -129,8 +127,6 @@ struct dcn_optc_registers { + uint32_t OPTC_INPUT_CLOCK_CONTROL; + uint32_t OPTC_DATA_SOURCE_SELECT; + uint32_t OPTC_INPUT_GLOBAL_CONTROL; +- uint32_t OPPBUF_CONTROL; +- uint32_t OPPBUF_3D_PARAMETERS_0; + uint32_t CONTROL; + uint32_t OTG_GSL_WINDOW_X; + uint32_t OTG_GSL_WINDOW_Y; +@@ -215,8 +211,6 @@ struct dcn_optc_registers { + SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\ + SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\ + SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\ +- SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, mask_sh),\ +- SF(OPPBUF0_OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, mask_sh),\ + SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\ + SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\ + SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\ +@@ -336,8 +330,6 @@ struct dcn_optc_registers { + type OPTC_SEG0_SRC_SEL;\ + type OPTC_UNDERFLOW_OCCURRED_STATUS;\ + type OPTC_UNDERFLOW_CLEAR;\ +- type OPPBUF_ACTIVE_WIDTH;\ +- type OPPBUF_3D_VACT_SPACE1_SIZE;\ + type VTG0_ENABLE;\ + type VTG0_FP2;\ + type VTG0_VCOUNT_INIT;\ +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h +index 17e143e..ab8fb77 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h +@@ -249,6 +249,21 @@ enum ovl_csc_adjust_item { + OVERLAY_COLOR_TEMPERATURE + }; + ++enum oppbuf_display_segmentation { ++ OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT = 0, ++ OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT = 1, ++ OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT = 2, ++ OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT = 3, ++ OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT = 4 ++}; ++ ++struct oppbuf_params { ++ uint32_t active_width; ++ enum oppbuf_display_segmentation mso_segmentation; ++ uint32_t mso_overlap_pixel_num; ++ uint32_t pixel_repetition; ++}; ++ + struct opp_funcs { + + +@@ -277,10 +292,10 @@ struct opp_funcs { + + void (*opp_destroy)(struct output_pixel_processor **opp); + +- void (*opp_set_stereo_polarity)( +- struct output_pixel_processor *opp, +- bool enable, +- bool rightEyePolarity); ++ void (*opp_program_stereo)( ++ struct output_pixel_processor *opp, ++ bool enable, ++ const struct dc_crtc_timing *timing); + + }; + +-- +2.7.4 + |