diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3009-drm-amd-display-fix-global-sync-param-retrieval-when.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3009-drm-amd-display-fix-global-sync-param-retrieval-when.patch | 86 |
1 files changed, 86 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3009-drm-amd-display-fix-global-sync-param-retrieval-when.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3009-drm-amd-display-fix-global-sync-param-retrieval-when.patch new file mode 100644 index 00000000..d3c98ec0 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/3009-drm-amd-display-fix-global-sync-param-retrieval-when.patch @@ -0,0 +1,86 @@ +From a783270edebb69a1c756a56b6c02cbf096206048 Mon Sep 17 00:00:00 2001 +From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Date: Mon, 4 Dec 2017 15:48:13 -0500 +Subject: [PATCH 3009/4131] drm/amd/display: fix global sync param retrieval + when not pipe splitting + +Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Harry Wentland <harry.wentland@amd.com> +--- + drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c | 8 ++++---- + drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 12 ++++++------ + drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h | 6 +++--- + 3 files changed, 13 insertions(+), 13 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c +index 366aace..5e2ea12 100644 +--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c ++++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c +@@ -782,11 +782,11 @@ void mode_support_and_system_configuration(struct dcn_bw_internal_vars *v) + v->dst_y_after_scaler = 0.0; + } + v->time_calc = 24.0 / v->projected_dcfclk_deep_sleep; +- v->v_update_offset[k] =dcn_bw_ceil2(v->htotal[k] / 4.0, 1.0); ++ v->v_update_offset[k][j] = dcn_bw_ceil2(v->htotal[k] / 4.0, 1.0); + v->total_repeater_delay = v->max_inter_dcn_tile_repeaters * (2.0 / (v->required_dispclk[i][j] / (j + 1)) + 3.0 / v->required_dispclk[i][j]); +- v->v_update_width[k] = (14.0 / v->projected_dcfclk_deep_sleep + 12.0 / (v->required_dispclk[i][j] / (j + 1)) + v->total_repeater_delay) * v->pixel_clock[k]; +- v->v_ready_offset[k] =dcn_bw_max2(150.0 / (v->required_dispclk[i][j] / (j + 1)), v->total_repeater_delay + 20.0 / v->projected_dcfclk_deep_sleep + 10.0 / (v->required_dispclk[i][j] / (j + 1))) * v->pixel_clock[k]; +- v->time_setup = (v->v_update_offset[k] + v->v_update_width[k] + v->v_ready_offset[k]) / v->pixel_clock[k]; ++ v->v_update_width[k][j] = (14.0 / v->projected_dcfclk_deep_sleep + 12.0 / (v->required_dispclk[i][j] / (j + 1)) + v->total_repeater_delay) * v->pixel_clock[k]; ++ v->v_ready_offset[k][j] = dcn_bw_max2(150.0 / (v->required_dispclk[i][j] / (j + 1)), v->total_repeater_delay + 20.0 / v->projected_dcfclk_deep_sleep + 10.0 / (v->required_dispclk[i][j] / (j + 1))) * v->pixel_clock[k]; ++ v->time_setup = (v->v_update_offset[k][j] + v->v_update_width[k][j] + v->v_ready_offset[k][j]) / v->pixel_clock[k]; + v->extra_latency = v->urgent_round_trip_and_out_of_order_latency_per_state[i] + (v->total_number_of_active_dpp[i][j] * v->pixel_chunk_size_in_kbyte + v->total_number_of_dcc_active_dpp[i][j] * v->meta_chunk_size) * 1024.0 / v->return_bw_per_state[i]; + if (v->pte_enable == dcn_bw_yes) { + v->extra_latency = v->extra_latency + v->total_number_of_active_dpp[i][j] * v->pte_chunk_size * 1024.0 / v->return_bw_per_state[i]; +diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +index c3cfd48..331891c 100644 +--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c ++++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +@@ -1014,9 +1014,9 @@ bool dcn_validate_bandwidth( + if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) + continue; + +- pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx]; +- pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset[input_idx]; +- pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx]; ++ pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0]; ++ pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0]; ++ pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0]; + pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx]; + + pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total; +@@ -1055,9 +1055,9 @@ bool dcn_validate_bandwidth( + TIMING_3D_FORMAT_SIDE_BY_SIDE))) { + if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) { + /* update previously split pipe */ +- hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx]; +- hsplit_pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset[input_idx]; +- hsplit_pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx]; ++ hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0]; ++ hsplit_pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0]; ++ hsplit_pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx][v->dpp_per_plane[input_idx] == 2 ? 1 : 0]; + hsplit_pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx]; + + hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total; +diff --git a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h +index 1e231f6..132d18d 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h +@@ -349,10 +349,10 @@ struct dcn_bw_internal_vars { + float dst_x_after_scaler; + float dst_y_after_scaler; + float time_calc; +- float v_update_offset[number_of_planes_minus_one + 1]; ++ float v_update_offset[number_of_planes_minus_one + 1][2]; + float total_repeater_delay; +- float v_update_width[number_of_planes_minus_one + 1]; +- float v_ready_offset[number_of_planes_minus_one + 1]; ++ float v_update_width[number_of_planes_minus_one + 1][2]; ++ float v_ready_offset[number_of_planes_minus_one + 1][2]; + float time_setup; + float extra_latency; + float maximum_vstartup; +-- +2.7.4 + |