diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2987-drm-amd-pp-delete-dead-code-of-arbiter-overdriver-cl.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2987-drm-amd-pp-delete-dead-code-of-arbiter-overdriver-cl.patch | 397 |
1 files changed, 397 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2987-drm-amd-pp-delete-dead-code-of-arbiter-overdriver-cl.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2987-drm-amd-pp-delete-dead-code-of-arbiter-overdriver-cl.patch new file mode 100644 index 00000000..15af1bda --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2987-drm-amd-pp-delete-dead-code-of-arbiter-overdriver-cl.patch @@ -0,0 +1,397 @@ +From 48cdb4218c64eacb4460883bf875653e28b52542 Mon Sep 17 00:00:00 2001 +From: Rex Zhu <Rex.Zhu@amd.com> +Date: Mon, 18 Dec 2017 15:03:23 +0800 +Subject: [PATCH 2987/4131] drm/amd/pp: delete dead code of arbiter overdriver + clk + +for sclk/mclk, can be adjusted through sysfs. +for uvd/vce clk, will be adjusted case by case when +requested. + +Change-Id: I30d6b18ddf8512bf1478079f60fc01163d64314b +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> +--- + drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 29 +++------------- + drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 34 ------------------ + drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 35 ------------------- + drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 40 +--------------------- + drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 34 ------------------ + drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c | 5 +-- + drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c | 5 +-- + .../gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c | 5 +-- + .../drm/amd/powerplay/smumgr/polaris10_smumgr.c | 5 +-- + .../gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c | 5 +-- + 10 files changed, 10 insertions(+), 187 deletions(-) + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c +index ad1f6b5..b314d09 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c +@@ -728,9 +728,6 @@ static int cz_update_sclk_limit(struct pp_hwmgr *hwmgr) + + if (clock < stable_pstate_sclk) + clock = stable_pstate_sclk; +- } else { +- if (clock < hwmgr->gfx_arbiter.sclk) +- clock = hwmgr->gfx_arbiter.sclk; + } + + if (cz_hwmgr->sclk_dpm.soft_min_clk != clock) { +@@ -1085,14 +1082,8 @@ static int cz_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, + uint32_t num_of_active_displays = 0; + struct cgs_display_info info = {0}; + +- cz_ps->evclk = hwmgr->vce_arbiter.evclk; +- cz_ps->ecclk = hwmgr->vce_arbiter.ecclk; +- + cz_ps->need_dfs_bypass = true; + +- cz_hwmgr->video_start = (hwmgr->uvd_arbiter.vclk != 0 || hwmgr->uvd_arbiter.dclk != 0 || +- hwmgr->vce_arbiter.evclk != 0 || hwmgr->vce_arbiter.ecclk != 0); +- + cz_hwmgr->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label); + + clocks.memoryClock = hwmgr->display_config.min_mem_set_clock != 0 ? +@@ -1105,9 +1096,6 @@ static int cz_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) + clocks.memoryClock = hwmgr->dyn_state.max_clock_voltage_on_ac.mclk; + +- if (clocks.memoryClock < hwmgr->gfx_arbiter.mclk) +- clocks.memoryClock = hwmgr->gfx_arbiter.mclk; +- + force_high = (clocks.memoryClock > cz_hwmgr->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORYCLOCK - 1]) + || (num_of_active_displays >= 3); + +@@ -1339,22 +1327,13 @@ int cz_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr) + cz_hwmgr->vce_dpm.hard_min_clk, + PPSMC_MSG_SetEclkHardMin)); + } else { +- /*Program HardMin based on the vce_arbiter.ecclk */ +- if (hwmgr->vce_arbiter.ecclk == 0) { +- smum_send_msg_to_smc_with_parameter(hwmgr, +- PPSMC_MSG_SetEclkHardMin, 0); ++ ++ smum_send_msg_to_smc_with_parameter(hwmgr, ++ PPSMC_MSG_SetEclkHardMin, 0); + /* disable ECLK DPM 0. Otherwise VCE could hang if + * switching SCLK from DPM 0 to 6/7 */ +- smum_send_msg_to_smc_with_parameter(hwmgr, ++ smum_send_msg_to_smc_with_parameter(hwmgr, + PPSMC_MSG_SetEclkSoftMin, 1); +- } else { +- cz_hwmgr->vce_dpm.hard_min_clk = hwmgr->vce_arbiter.ecclk; +- smum_send_msg_to_smc_with_parameter(hwmgr, +- PPSMC_MSG_SetEclkHardMin, +- cz_get_eclk_level(hwmgr, +- cz_hwmgr->vce_dpm.hard_min_clk, +- PPSMC_MSG_SetEclkHardMin)); +- } + } + return 0; + } +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c +index 527576e..f7e9d9d 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c +@@ -159,7 +159,6 @@ static int rv_construct_boot_state(struct pp_hwmgr *hwmgr) + + static int rv_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input) + { +- struct rv_hwmgr *rv_data = (struct rv_hwmgr *)(hwmgr->backend); + struct PP_Clocks clocks = {0}; + struct pp_display_clock_request clock_req; + +@@ -170,39 +169,6 @@ static int rv_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input) + PP_ASSERT_WITH_CODE(!rv_display_clock_voltage_request(hwmgr, &clock_req), + "Attempt to set DCF Clock Failed!", return -EINVAL); + +- if (((hwmgr->uvd_arbiter.vclk_soft_min / 100) != rv_data->vclk_soft_min) || +- ((hwmgr->uvd_arbiter.dclk_soft_min / 100) != rv_data->dclk_soft_min)) { +- rv_data->vclk_soft_min = hwmgr->uvd_arbiter.vclk_soft_min / 100; +- rv_data->dclk_soft_min = hwmgr->uvd_arbiter.dclk_soft_min / 100; +- smum_send_msg_to_smc_with_parameter(hwmgr, +- PPSMC_MSG_SetSoftMinVcn, +- (rv_data->vclk_soft_min << 16) | rv_data->vclk_soft_min); +- } +- +- if((hwmgr->gfx_arbiter.sclk_hard_min != 0) && +- ((hwmgr->gfx_arbiter.sclk_hard_min / 100) != rv_data->soc_actual_hard_min_freq)) { +- smum_send_msg_to_smc_with_parameter(hwmgr, +- PPSMC_MSG_SetHardMinSocclkByFreq, +- hwmgr->gfx_arbiter.sclk_hard_min / 100); +- rv_read_arg_from_smc(hwmgr, &rv_data->soc_actual_hard_min_freq); +- } +- +- if ((hwmgr->gfx_arbiter.gfxclk != 0) && +- (rv_data->gfx_actual_soft_min_freq != (hwmgr->gfx_arbiter.gfxclk))) { +- smum_send_msg_to_smc_with_parameter(hwmgr, +- PPSMC_MSG_SetMinVideoGfxclkFreq, +- hwmgr->gfx_arbiter.gfxclk / 100); +- rv_read_arg_from_smc(hwmgr, &rv_data->gfx_actual_soft_min_freq); +- } +- +- if ((hwmgr->gfx_arbiter.fclk != 0) && +- (rv_data->fabric_actual_soft_min_freq != (hwmgr->gfx_arbiter.fclk / 100))) { +- smum_send_msg_to_smc_with_parameter(hwmgr, +- PPSMC_MSG_SetMinVideoFclkFreq, +- hwmgr->gfx_arbiter.fclk / 100); +- rv_read_arg_from_smc(hwmgr, &rv_data->fabric_actual_soft_min_freq); +- } +- + return 0; + } + +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +index cce3939..00a7447 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +@@ -2722,9 +2722,6 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, + } + } + +- smu7_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk; +- smu7_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk; +- + cgs_get_active_displays_info(hwmgr->device, &info); + + minimum_clocks.engineClock = hwmgr->display_config.min_core_set_clock; +@@ -2754,38 +2751,6 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, + minimum_clocks.memoryClock = stable_pstate_mclk; + } + +- if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk) +- minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk; +- +- if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk) +- minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk; +- +- smu7_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold; +- +- if (0 != hwmgr->gfx_arbiter.sclk_over_drive) { +- PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <= +- hwmgr->platform_descriptor.overdriveLimit.engineClock), +- "Overdrive sclk exceeds limit", +- hwmgr->gfx_arbiter.sclk_over_drive = +- hwmgr->platform_descriptor.overdriveLimit.engineClock); +- +- if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk) +- smu7_ps->performance_levels[1].engine_clock = +- hwmgr->gfx_arbiter.sclk_over_drive; +- } +- +- if (0 != hwmgr->gfx_arbiter.mclk_over_drive) { +- PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <= +- hwmgr->platform_descriptor.overdriveLimit.memoryClock), +- "Overdrive mclk exceeds limit", +- hwmgr->gfx_arbiter.mclk_over_drive = +- hwmgr->platform_descriptor.overdriveLimit.memoryClock); +- +- if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk) +- smu7_ps->performance_levels[1].memory_clock = +- hwmgr->gfx_arbiter.mclk_over_drive; +- } +- + disable_mclk_switching_for_frame_lock = phm_cap_enabled( + hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_DisableMclkSwitchingForFrameLock); +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +index 98398f0..00e05ac 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +@@ -3124,9 +3124,6 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, + } + } + +- vega10_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk; +- vega10_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk; +- + cgs_get_active_displays_info(hwmgr->device, &info); + + /* result = PHM_CheckVBlankTime(hwmgr, &vblankTooShort);*/ +@@ -3165,38 +3162,6 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, + minimum_clocks.memoryClock = stable_pstate_mclk; + } + +- if (minimum_clocks.engineClock < hwmgr->gfx_arbiter.sclk) +- minimum_clocks.engineClock = hwmgr->gfx_arbiter.sclk; +- +- if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk) +- minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk; +- +- vega10_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold; +- +- if (hwmgr->gfx_arbiter.sclk_over_drive) { +- PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <= +- hwmgr->platform_descriptor.overdriveLimit.engineClock), +- "Overdrive sclk exceeds limit", +- hwmgr->gfx_arbiter.sclk_over_drive = +- hwmgr->platform_descriptor.overdriveLimit.engineClock); +- +- if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk) +- vega10_ps->performance_levels[1].gfx_clock = +- hwmgr->gfx_arbiter.sclk_over_drive; +- } +- +- if (hwmgr->gfx_arbiter.mclk_over_drive) { +- PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.mclk_over_drive <= +- hwmgr->platform_descriptor.overdriveLimit.memoryClock), +- "Overdrive mclk exceeds limit", +- hwmgr->gfx_arbiter.mclk_over_drive = +- hwmgr->platform_descriptor.overdriveLimit.memoryClock); +- +- if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk) +- vega10_ps->performance_levels[1].mem_clock = +- hwmgr->gfx_arbiter.mclk_over_drive; +- } +- + disable_mclk_switching_for_frame_lock = phm_cap_enabled( + hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_DisableMclkSwitchingForFrameLock); +@@ -3822,10 +3787,7 @@ static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr) + uint32_t low_sclk_interrupt_threshold = 0; + + if (PP_CAP(PHM_PlatformCaps_SclkThrottleLowNotification) && +- (hwmgr->gfx_arbiter.sclk_threshold != +- data->low_sclk_interrupt_threshold)) { +- data->low_sclk_interrupt_threshold = +- hwmgr->gfx_arbiter.sclk_threshold; ++ (data->low_sclk_interrupt_threshold != 0)) { + low_sclk_interrupt_threshold = + data->low_sclk_interrupt_threshold; + +diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +index 004a40e..39eedbc 100644 +--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h ++++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h +@@ -105,36 +105,6 @@ struct phm_set_power_state_input { + const struct pp_hw_power_state *pnew_state; + }; + +-struct phm_acp_arbiter { +- uint32_t acpclk; +-}; +- +-struct phm_uvd_arbiter { +- uint32_t vclk; +- uint32_t dclk; +- uint32_t vclk_ceiling; +- uint32_t dclk_ceiling; +- uint32_t vclk_soft_min; +- uint32_t dclk_soft_min; +-}; +- +-struct phm_vce_arbiter { +- uint32_t evclk; +- uint32_t ecclk; +-}; +- +-struct phm_gfx_arbiter { +- uint32_t sclk; +- uint32_t sclk_hard_min; +- uint32_t mclk; +- uint32_t sclk_over_drive; +- uint32_t mclk_over_drive; +- uint32_t sclk_threshold; +- uint32_t num_cus; +- uint32_t gfxclk; +- uint32_t fclk; +-}; +- + struct phm_clock_array { + uint32_t count; + uint32_t values[1]; +@@ -737,10 +707,6 @@ struct pp_hwmgr { + enum amd_dpm_forced_level dpm_level; + enum amd_dpm_forced_level saved_dpm_level; + enum amd_dpm_forced_level request_dpm_level; +- struct phm_gfx_arbiter gfx_arbiter; +- struct phm_acp_arbiter acp_arbiter; +- struct phm_uvd_arbiter uvd_arbiter; +- struct phm_vce_arbiter vce_arbiter; + uint32_t usec_timeout; + void *pptable; + struct phm_platform_descriptor platform_descriptor; +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c +index c36f00e..c6c741a 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c +@@ -2218,10 +2218,7 @@ static int ci_update_sclk_threshold(struct pp_hwmgr *hwmgr) + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_SclkThrottleLowNotification) +- && (hwmgr->gfx_arbiter.sclk_threshold != +- data->low_sclk_interrupt_threshold)) { +- data->low_sclk_interrupt_threshold = +- hwmgr->gfx_arbiter.sclk_threshold; ++ && (data->low_sclk_interrupt_threshold != 0)) { + low_sclk_interrupt_threshold = + data->low_sclk_interrupt_threshold; + +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c +index f572bef..085d81c 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c +@@ -2385,10 +2385,7 @@ static int fiji_update_sclk_threshold(struct pp_hwmgr *hwmgr) + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_SclkThrottleLowNotification) +- && (hwmgr->gfx_arbiter.sclk_threshold != +- data->low_sclk_interrupt_threshold)) { +- data->low_sclk_interrupt_threshold = +- hwmgr->gfx_arbiter.sclk_threshold; ++ && (data->low_sclk_interrupt_threshold != 0)) { + low_sclk_interrupt_threshold = + data->low_sclk_interrupt_threshold; + +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c +index d620786..d75bb99 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c +@@ -2202,10 +2202,7 @@ static int iceland_update_sclk_threshold(struct pp_hwmgr *hwmgr) + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_SclkThrottleLowNotification) +- && (hwmgr->gfx_arbiter.sclk_threshold != +- data->low_sclk_interrupt_threshold)) { +- data->low_sclk_interrupt_threshold = +- hwmgr->gfx_arbiter.sclk_threshold; ++ && (data->low_sclk_interrupt_threshold != 0)) { + low_sclk_interrupt_threshold = + data->low_sclk_interrupt_threshold; + +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c +index bd6be77..cdb4765 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c +@@ -2369,10 +2369,7 @@ static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr) + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_SclkThrottleLowNotification) +- && (hwmgr->gfx_arbiter.sclk_threshold != +- data->low_sclk_interrupt_threshold)) { +- data->low_sclk_interrupt_threshold = +- hwmgr->gfx_arbiter.sclk_threshold; ++ && (data->low_sclk_interrupt_threshold != 0)) { + low_sclk_interrupt_threshold = + data->low_sclk_interrupt_threshold; + +diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c +index 81b8790..79e5c05 100644 +--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c ++++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c +@@ -2654,10 +2654,7 @@ static int tonga_update_sclk_threshold(struct pp_hwmgr *hwmgr) + + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, + PHM_PlatformCaps_SclkThrottleLowNotification) +- && (hwmgr->gfx_arbiter.sclk_threshold != +- data->low_sclk_interrupt_threshold)) { +- data->low_sclk_interrupt_threshold = +- hwmgr->gfx_arbiter.sclk_threshold; ++ && (data->low_sclk_interrupt_threshold != 0)) { + low_sclk_interrupt_threshold = + data->low_sclk_interrupt_threshold; + +-- +2.7.4 + |