diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2981-drm-amdgpu-rename-ip-block-helper-functions.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2981-drm-amdgpu-rename-ip-block-helper-functions.patch | 929 |
1 files changed, 929 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2981-drm-amdgpu-rename-ip-block-helper-functions.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2981-drm-amdgpu-rename-ip-block-helper-functions.patch new file mode 100644 index 00000000..6539102d --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2981-drm-amdgpu-rename-ip-block-helper-functions.patch @@ -0,0 +1,929 @@ +From ead39913182b6c9879483dccc62b5ce7b2866df4 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Fri, 15 Dec 2017 16:18:00 -0500 +Subject: [PATCH 2981/4131] drm/amdgpu: rename ip block helper functions +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +add device to the name for consistency. + +Acked-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu.h | 38 +++++---- + drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 2 +- + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 50 +++++------ + drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 18 ++-- + drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 18 ++-- + drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 16 ++-- + drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- + drivers/gpu/drm/amd/amdgpu/ci_dpm.c | 8 +- + drivers/gpu/drm/amd/amdgpu/cik.c | 88 +++++++++---------- + drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 18 ++-- + drivers/gpu/drm/amd/amdgpu/kv_dpm.c | 8 +- + drivers/gpu/drm/amd/amdgpu/si.c | 54 ++++++------ + drivers/gpu/drm/amd/amdgpu/soc15.c | 46 +++++----- + drivers/gpu/drm/amd/amdgpu/vi.c | 132 ++++++++++++++--------------- + 14 files changed, 252 insertions(+), 246 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +index e28c685..62d6e0e 100755 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +@@ -227,17 +227,18 @@ enum amdgpu_kiq_irq { + AMDGPU_CP_KIQ_IRQ_LAST + }; + +-int amdgpu_set_clockgating_state(struct amdgpu_device *adev, +- enum amd_ip_block_type block_type, +- enum amd_clockgating_state state); +-int amdgpu_set_powergating_state(struct amdgpu_device *adev, +- enum amd_ip_block_type block_type, +- enum amd_powergating_state state); +-void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags); +-int amdgpu_wait_for_idle(struct amdgpu_device *adev, +- enum amd_ip_block_type block_type); +-bool amdgpu_is_idle(struct amdgpu_device *adev, +- enum amd_ip_block_type block_type); ++int amdgpu_device_ip_set_clockgating_state(struct amdgpu_device *adev, ++ enum amd_ip_block_type block_type, ++ enum amd_clockgating_state state); ++int amdgpu_device_ip_set_powergating_state(struct amdgpu_device *adev, ++ enum amd_ip_block_type block_type, ++ enum amd_powergating_state state); ++void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, ++ u32 *flags); ++int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, ++ enum amd_ip_block_type block_type); ++bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, ++ enum amd_ip_block_type block_type); + + #define AMDGPU_MAX_IP_NUM 16 + +@@ -262,15 +263,16 @@ struct amdgpu_ip_block { + const struct amdgpu_ip_block_version *version; + }; + +-int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, +- enum amd_ip_block_type type, +- u32 major, u32 minor); ++int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, ++ enum amd_ip_block_type type, ++ u32 major, u32 minor); + +-struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, +- enum amd_ip_block_type type); ++struct amdgpu_ip_block * ++amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, ++ enum amd_ip_block_type type); + +-int amdgpu_ip_block_add(struct amdgpu_device *adev, +- const struct amdgpu_ip_block_version *ip_block_version); ++int amdgpu_device_ip_block_add(struct amdgpu_device *adev, ++ const struct amdgpu_ip_block_version *ip_block_version); + + /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ + struct amdgpu_buffer_funcs { +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c +index 08eb67d..bdec5c7 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c +@@ -277,7 +277,7 @@ static int acp_hw_init(void *handle) + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + const struct amdgpu_ip_block *ip_block = +- amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ACP); ++ amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ACP); + + if (!ip_block) + return -EINVAL; +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +index a640aef..16ce2ed 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +@@ -964,9 +964,9 @@ static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { + .can_switch = amdgpu_switcheroo_can_switch, + }; + +-int amdgpu_set_clockgating_state(struct amdgpu_device *adev, +- enum amd_ip_block_type block_type, +- enum amd_clockgating_state state) ++int amdgpu_device_ip_set_clockgating_state(struct amdgpu_device *adev, ++ enum amd_ip_block_type block_type, ++ enum amd_clockgating_state state) + { + int i, r = 0; + +@@ -986,9 +986,9 @@ int amdgpu_set_clockgating_state(struct amdgpu_device *adev, + return r; + } + +-int amdgpu_set_powergating_state(struct amdgpu_device *adev, +- enum amd_ip_block_type block_type, +- enum amd_powergating_state state) ++int amdgpu_device_ip_set_powergating_state(struct amdgpu_device *adev, ++ enum amd_ip_block_type block_type, ++ enum amd_powergating_state state) + { + int i, r = 0; + +@@ -1008,7 +1008,8 @@ int amdgpu_set_powergating_state(struct amdgpu_device *adev, + return r; + } + +-void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags) ++void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, ++ u32 *flags) + { + int i; + +@@ -1020,8 +1021,8 @@ void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags) + } + } + +-int amdgpu_wait_for_idle(struct amdgpu_device *adev, +- enum amd_ip_block_type block_type) ++int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, ++ enum amd_ip_block_type block_type) + { + int i, r; + +@@ -1039,8 +1040,8 @@ int amdgpu_wait_for_idle(struct amdgpu_device *adev, + + } + +-bool amdgpu_is_idle(struct amdgpu_device *adev, +- enum amd_ip_block_type block_type) ++bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, ++ enum amd_ip_block_type block_type) + { + int i; + +@@ -1054,8 +1055,9 @@ bool amdgpu_is_idle(struct amdgpu_device *adev, + + } + +-struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, +- enum amd_ip_block_type type) ++struct amdgpu_ip_block * ++amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, ++ enum amd_ip_block_type type) + { + int i; + +@@ -1067,7 +1069,7 @@ struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, + } + + /** +- * amdgpu_ip_block_version_cmp ++ * amdgpu_device_ip_block_version_cmp + * + * @adev: amdgpu_device pointer + * @type: enum amd_ip_block_type +@@ -1077,11 +1079,11 @@ struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, + * return 0 if equal or greater + * return 1 if smaller or the ip_block doesn't exist + */ +-int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, +- enum amd_ip_block_type type, +- u32 major, u32 minor) ++int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, ++ enum amd_ip_block_type type, ++ u32 major, u32 minor) + { +- struct amdgpu_ip_block *ip_block = amdgpu_get_ip_block(adev, type); ++ struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type); + + if (ip_block && ((ip_block->version->major > major) || + ((ip_block->version->major == major) && +@@ -1092,7 +1094,7 @@ int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, + } + + /** +- * amdgpu_ip_block_add ++ * amdgpu_device_ip_block_add + * + * @adev: amdgpu_device pointer + * @ip_block_version: pointer to the IP to add +@@ -1100,8 +1102,8 @@ int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, + * Adds the IP block driver information to the collection of IPs + * on the asic. + */ +-int amdgpu_ip_block_add(struct amdgpu_device *adev, +- const struct amdgpu_ip_block_version *ip_block_version) ++int amdgpu_device_ip_block_add(struct amdgpu_device *adev, ++ const struct amdgpu_ip_block_version *ip_block_version) + { + if (!ip_block_version) + return -EINVAL; +@@ -1599,10 +1601,10 @@ int amdgpu_device_ip_suspend(struct amdgpu_device *adev) + amdgpu_virt_request_full_gpu(adev, false); + + /* ungate SMC block first */ +- r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC, +- AMD_CG_STATE_UNGATE); ++ r = amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC, ++ AMD_CG_STATE_UNGATE); + if (r) { +- DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r); ++ DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n", r); + } + + for (i = adev->num_ip_blocks - 1; i >= 0; i--) { +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +index f2090d1..d460000 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +@@ -1275,16 +1275,16 @@ void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) + /* XXX select vce level based on ring/task */ + adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; + mutex_unlock(&adev->pm.mutex); +- amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, +- AMD_CG_STATE_UNGATE); +- amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, +- AMD_PG_STATE_UNGATE); ++ amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, ++ AMD_CG_STATE_UNGATE); ++ amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, ++ AMD_PG_STATE_UNGATE); + amdgpu_pm_compute_clocks(adev); + } else { +- amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, +- AMD_PG_STATE_GATE); +- amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, +- AMD_CG_STATE_GATE); ++ amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, ++ AMD_PG_STATE_GATE); ++ amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, ++ AMD_CG_STATE_GATE); + mutex_lock(&adev->pm.mutex); + adev->pm.dpm.vce_active = false; + mutex_unlock(&adev->pm.mutex); +@@ -1581,7 +1581,7 @@ static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data) + struct drm_device *ddev = adev->ddev; + u32 flags = 0; + +- amdgpu_get_clockgating_state(adev, &flags); ++ amdgpu_device_ip_get_clockgating_state(adev, &flags); + seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags); + amdgpu_parse_cg_state(m, flags); + seq_printf(m, "\n"); +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +index 154a8e0..b0a4a0c 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +@@ -244,7 +244,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev) + } + + /* from uvd v5.0 HW addressing capacity increased to 64 bits */ +- if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0)) ++ if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0)) + adev->uvd.address_64_bit = true; + + switch (adev->asic_type) { +@@ -1155,10 +1155,10 @@ static void amdgpu_uvd_idle_work_handler(struct work_struct *work) + } else { + amdgpu_asic_set_uvd_clocks(adev, 0, 0); + /* shutdown the UVD block */ +- amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, +- AMD_PG_STATE_GATE); +- amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, +- AMD_CG_STATE_GATE); ++ amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, ++ AMD_PG_STATE_GATE); ++ amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, ++ AMD_CG_STATE_GATE); + } + } else { + schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT); +@@ -1178,10 +1178,10 @@ void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring) + amdgpu_dpm_enable_uvd(adev, true); + } else { + amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); +- amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, +- AMD_CG_STATE_UNGATE); +- amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, +- AMD_PG_STATE_UNGATE); ++ amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, ++ AMD_CG_STATE_UNGATE); ++ amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, ++ AMD_PG_STATE_UNGATE); + } + } + } +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +index 5b70088..ffa66a2 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +@@ -311,10 +311,10 @@ static void amdgpu_vce_idle_work_handler(struct work_struct *work) + amdgpu_dpm_enable_vce(adev, false); + } else { + amdgpu_asic_set_vce_clocks(adev, 0, 0); +- amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, +- AMD_PG_STATE_GATE); +- amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, +- AMD_CG_STATE_GATE); ++ amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, ++ AMD_PG_STATE_GATE); ++ amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, ++ AMD_CG_STATE_GATE); + } + } else { + schedule_delayed_work(&adev->vce.idle_work, VCE_IDLE_TIMEOUT); +@@ -343,10 +343,10 @@ void amdgpu_vce_ring_begin_use(struct amdgpu_ring *ring) + amdgpu_dpm_enable_vce(adev, true); + } else { + amdgpu_asic_set_vce_clocks(adev, 53300, 40000); +- amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, +- AMD_CG_STATE_UNGATE); +- amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, +- AMD_PG_STATE_UNGATE); ++ amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, ++ AMD_CG_STATE_UNGATE); ++ amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, ++ AMD_PG_STATE_UNGATE); + + } + } +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +index 2a35362..578efae 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +@@ -750,7 +750,7 @@ void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev) + + has_compute_vm_bug = false; + +- ip_block = amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); ++ ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); + if (ip_block) { + /* Compute has a VM bug for GFX version < 7. + Compute has a VM bug for GFX 8 MEC firmware version < 673.*/ +diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c +index f11c0aac..a0943aa 100644 +--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c ++++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c +@@ -891,12 +891,12 @@ static void ci_dpm_powergate_uvd(void *handle, bool gate) + + if (gate) { + /* stop the UVD block */ +- amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, +- AMD_PG_STATE_GATE); ++ amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, ++ AMD_PG_STATE_GATE); + ci_update_uvd_dpm(adev, gate); + } else { +- amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, +- AMD_PG_STATE_UNGATE); ++ amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, ++ AMD_PG_STATE_UNGATE); + ci_update_uvd_dpm(adev, gate); + } + } +diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c +index 132ba22..6a92abc 100644 +--- a/drivers/gpu/drm/amd/amdgpu/cik.c ++++ b/drivers/gpu/drm/amd/amdgpu/cik.c +@@ -1974,77 +1974,77 @@ int cik_set_ip_blocks(struct amdgpu_device *adev) + + switch (adev->asic_type) { + case CHIP_BONAIRE: +- amdgpu_ip_block_add(adev, &cik_common_ip_block); +- amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block); +- amdgpu_ip_block_add(adev, &cik_ih_ip_block); +- amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); ++ amdgpu_device_ip_block_add(adev, &cik_common_ip_block); ++ amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &cik_ih_ip_block); ++ amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block); + if (adev->enable_virtual_display) +- amdgpu_ip_block_add(adev, &dce_virtual_ip_block); ++ amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); + #if defined(CONFIG_DRM_AMD_DC) + else if (amdgpu_device_has_dc_support(adev)) +- amdgpu_ip_block_add(adev, &dm_ip_block); ++ amdgpu_device_ip_block_add(adev, &dm_ip_block); + #endif + else +- amdgpu_ip_block_add(adev, &dce_v8_2_ip_block); +- amdgpu_ip_block_add(adev, &gfx_v7_2_ip_block); +- amdgpu_ip_block_add(adev, &cik_sdma_ip_block); +- amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block); +- amdgpu_ip_block_add(adev, &vce_v2_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &dce_v8_2_ip_block); ++ amdgpu_device_ip_block_add(adev, &gfx_v7_2_ip_block); ++ amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block); ++ amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block); ++ amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block); + break; + case CHIP_HAWAII: +- amdgpu_ip_block_add(adev, &cik_common_ip_block); +- amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block); +- amdgpu_ip_block_add(adev, &cik_ih_ip_block); +- amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); ++ amdgpu_device_ip_block_add(adev, &cik_common_ip_block); ++ amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &cik_ih_ip_block); ++ amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block); + if (adev->enable_virtual_display) +- amdgpu_ip_block_add(adev, &dce_virtual_ip_block); ++ amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); + #if defined(CONFIG_DRM_AMD_DC) + else if (amdgpu_device_has_dc_support(adev)) +- amdgpu_ip_block_add(adev, &dm_ip_block); ++ amdgpu_device_ip_block_add(adev, &dm_ip_block); + #endif + else +- amdgpu_ip_block_add(adev, &dce_v8_5_ip_block); +- amdgpu_ip_block_add(adev, &gfx_v7_3_ip_block); +- amdgpu_ip_block_add(adev, &cik_sdma_ip_block); +- amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block); +- amdgpu_ip_block_add(adev, &vce_v2_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &dce_v8_5_ip_block); ++ amdgpu_device_ip_block_add(adev, &gfx_v7_3_ip_block); ++ amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block); ++ amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block); ++ amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block); + break; + case CHIP_KAVERI: +- amdgpu_ip_block_add(adev, &cik_common_ip_block); +- amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block); +- amdgpu_ip_block_add(adev, &cik_ih_ip_block); +- amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); ++ amdgpu_device_ip_block_add(adev, &cik_common_ip_block); ++ amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &cik_ih_ip_block); ++ amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block); + if (adev->enable_virtual_display) +- amdgpu_ip_block_add(adev, &dce_virtual_ip_block); ++ amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); + #if defined(CONFIG_DRM_AMD_DC) + else if (amdgpu_device_has_dc_support(adev)) +- amdgpu_ip_block_add(adev, &dm_ip_block); ++ amdgpu_device_ip_block_add(adev, &dm_ip_block); + #endif + else +- amdgpu_ip_block_add(adev, &dce_v8_1_ip_block); +- amdgpu_ip_block_add(adev, &gfx_v7_1_ip_block); +- amdgpu_ip_block_add(adev, &cik_sdma_ip_block); +- amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block); +- amdgpu_ip_block_add(adev, &vce_v2_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &dce_v8_1_ip_block); ++ amdgpu_device_ip_block_add(adev, &gfx_v7_1_ip_block); ++ amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block); ++ amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block); ++ amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block); + break; + case CHIP_KABINI: + case CHIP_MULLINS: +- amdgpu_ip_block_add(adev, &cik_common_ip_block); +- amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block); +- amdgpu_ip_block_add(adev, &cik_ih_ip_block); +- amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); ++ amdgpu_device_ip_block_add(adev, &cik_common_ip_block); ++ amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &cik_ih_ip_block); ++ amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block); + if (adev->enable_virtual_display) +- amdgpu_ip_block_add(adev, &dce_virtual_ip_block); ++ amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); + #if defined(CONFIG_DRM_AMD_DC) + else if (amdgpu_device_has_dc_support(adev)) +- amdgpu_ip_block_add(adev, &dm_ip_block); ++ amdgpu_device_ip_block_add(adev, &dm_ip_block); + #endif + else +- amdgpu_ip_block_add(adev, &dce_v8_3_ip_block); +- amdgpu_ip_block_add(adev, &gfx_v7_2_ip_block); +- amdgpu_ip_block_add(adev, &cik_sdma_ip_block); +- amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block); +- amdgpu_ip_block_add(adev, &vce_v2_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &dce_v8_3_ip_block); ++ amdgpu_device_ip_block_add(adev, &gfx_v7_2_ip_block); ++ amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block); ++ amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block); ++ amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block); + break; + default: + /* FIXME: not supported yet */ +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +index 3ab7cb9..c0877e8 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +@@ -5065,8 +5065,9 @@ static int gfx_v8_0_hw_fini(void *handle) + gfx_v8_0_cp_enable(adev, false); + gfx_v8_0_rlc_stop(adev); + +- amdgpu_set_powergating_state(adev, +- AMD_IP_BLOCK_TYPE_GFX, AMD_PG_STATE_UNGATE); ++ amdgpu_device_ip_set_powergating_state(adev, ++ AMD_IP_BLOCK_TYPE_GFX, ++ AMD_PG_STATE_UNGATE); + + return 0; + } +@@ -5483,8 +5484,9 @@ static int gfx_v8_0_late_init(void *handle) + if (r) + return r; + +- amdgpu_set_powergating_state(adev, +- AMD_IP_BLOCK_TYPE_GFX, AMD_PG_STATE_GATE); ++ amdgpu_device_ip_set_powergating_state(adev, ++ AMD_IP_BLOCK_TYPE_GFX, ++ AMD_PG_STATE_GATE); + + return 0; + } +@@ -5495,10 +5497,10 @@ static void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *ade + if ((adev->asic_type == CHIP_POLARIS11) || + (adev->asic_type == CHIP_POLARIS12)) + /* Send msg to SMU via Powerplay */ +- amdgpu_set_powergating_state(adev, +- AMD_IP_BLOCK_TYPE_SMC, +- enable ? +- AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE); ++ amdgpu_device_ip_set_powergating_state(adev, ++ AMD_IP_BLOCK_TYPE_SMC, ++ enable ? ++ AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE); + + WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0); + } +diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c +index f33d1ff..d9e9e52 100644 +--- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c ++++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c +@@ -1682,8 +1682,8 @@ static void kv_dpm_powergate_uvd(void *handle, bool gate) + + if (gate) { + /* stop the UVD block */ +- ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, +- AMD_PG_STATE_GATE); ++ ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, ++ AMD_PG_STATE_GATE); + kv_update_uvd_dpm(adev, gate); + if (pi->caps_uvd_pg) + /* power off the UVD block */ +@@ -1695,8 +1695,8 @@ static void kv_dpm_powergate_uvd(void *handle, bool gate) + /* re-init the UVD block */ + kv_update_uvd_dpm(adev, gate); + +- ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, +- AMD_PG_STATE_UNGATE); ++ ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, ++ AMD_PG_STATE_UNGATE); + } + } + +diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c +index b90aed2..3598151 100644 +--- a/drivers/gpu/drm/amd/amdgpu/si.c ++++ b/drivers/gpu/drm/amd/amdgpu/si.c +@@ -2024,42 +2024,42 @@ int si_set_ip_blocks(struct amdgpu_device *adev) + case CHIP_VERDE: + case CHIP_TAHITI: + case CHIP_PITCAIRN: +- amdgpu_ip_block_add(adev, &si_common_ip_block); +- amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block); +- amdgpu_ip_block_add(adev, &si_ih_ip_block); +- amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); ++ amdgpu_device_ip_block_add(adev, &si_common_ip_block); ++ amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &si_ih_ip_block); ++ amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block); + if (adev->enable_virtual_display) +- amdgpu_ip_block_add(adev, &dce_virtual_ip_block); ++ amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); + else +- amdgpu_ip_block_add(adev, &dce_v6_0_ip_block); +- amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block); +- amdgpu_ip_block_add(adev, &si_dma_ip_block); +- /* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */ +- /* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */ ++ amdgpu_device_ip_block_add(adev, &dce_v6_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &si_dma_ip_block); ++ /* amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block); */ ++ /* amdgpu_device_ip_block_add(adev, &vce_v1_0_ip_block); */ + break; + case CHIP_OLAND: +- amdgpu_ip_block_add(adev, &si_common_ip_block); +- amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block); +- amdgpu_ip_block_add(adev, &si_ih_ip_block); +- amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); ++ amdgpu_device_ip_block_add(adev, &si_common_ip_block); ++ amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &si_ih_ip_block); ++ amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block); + if (adev->enable_virtual_display) +- amdgpu_ip_block_add(adev, &dce_virtual_ip_block); ++ amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); + else +- amdgpu_ip_block_add(adev, &dce_v6_4_ip_block); +- amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block); +- amdgpu_ip_block_add(adev, &si_dma_ip_block); +- /* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */ +- /* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */ ++ amdgpu_device_ip_block_add(adev, &dce_v6_4_ip_block); ++ amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &si_dma_ip_block); ++ /* amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block); */ ++ /* amdgpu_device_ip_block_add(adev, &vce_v1_0_ip_block); */ + break; + case CHIP_HAINAN: +- amdgpu_ip_block_add(adev, &si_common_ip_block); +- amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block); +- amdgpu_ip_block_add(adev, &si_ih_ip_block); +- amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); ++ amdgpu_device_ip_block_add(adev, &si_common_ip_block); ++ amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &si_ih_ip_block); ++ amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block); + if (adev->enable_virtual_display) +- amdgpu_ip_block_add(adev, &dce_virtual_ip_block); +- amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block); +- amdgpu_ip_block_add(adev, &si_dma_ip_block); ++ amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); ++ amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &si_dma_ip_block); + break; + default: + BUG(); +diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c +index 56dec06..400594a 100644 +--- a/drivers/gpu/drm/amd/amdgpu/soc15.c ++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c +@@ -533,43 +533,43 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) + + switch (adev->asic_type) { + case CHIP_VEGA10: +- amdgpu_ip_block_add(adev, &vega10_common_ip_block); +- amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block); +- amdgpu_ip_block_add(adev, &vega10_ih_ip_block); ++ amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); ++ amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); + if (amdgpu_fw_load_type == 2 || amdgpu_fw_load_type == -1) +- amdgpu_ip_block_add(adev, &psp_v3_1_ip_block); ++ amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); + if (!amdgpu_sriov_vf(adev)) +- amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); ++ amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block); + if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) +- amdgpu_ip_block_add(adev, &dce_virtual_ip_block); ++ amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); + #if defined(CONFIG_DRM_AMD_DC) + else if (amdgpu_device_has_dc_support(adev)) +- amdgpu_ip_block_add(adev, &dm_ip_block); ++ amdgpu_device_ip_block_add(adev, &dm_ip_block); + #else + # warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15." + #endif +- amdgpu_ip_block_add(adev, &gfx_v9_0_ip_block); +- amdgpu_ip_block_add(adev, &sdma_v4_0_ip_block); +- amdgpu_ip_block_add(adev, &uvd_v7_0_ip_block); +- amdgpu_ip_block_add(adev, &vce_v4_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); + break; + case CHIP_RAVEN: +- amdgpu_ip_block_add(adev, &vega10_common_ip_block); +- amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block); +- amdgpu_ip_block_add(adev, &vega10_ih_ip_block); +- amdgpu_ip_block_add(adev, &psp_v10_0_ip_block); +- amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); ++ amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); ++ amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); ++ amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block); + if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) +- amdgpu_ip_block_add(adev, &dce_virtual_ip_block); ++ amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); + #if defined(CONFIG_DRM_AMD_DC) + else if (amdgpu_device_has_dc_support(adev)) +- amdgpu_ip_block_add(adev, &dm_ip_block); ++ amdgpu_device_ip_block_add(adev, &dm_ip_block); + #else + # warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15." + #endif +- amdgpu_ip_block_add(adev, &gfx_v9_0_ip_block); +- amdgpu_ip_block_add(adev, &sdma_v4_0_ip_block); +- amdgpu_ip_block_add(adev, &vcn_v1_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); + break; + default: + return -EINVAL; +@@ -616,8 +616,8 @@ static int soc15_common_early_init(void *handle) + + adev->asic_funcs = &soc15_asic_funcs; + +- if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP) && +- (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_PSP))) ++ if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP) && ++ (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_PSP))) + psp_enabled = true; + + adev->rev_id = soc15_get_rev_id(adev); +diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c +index cc7cf05..70dab1d 100644 +--- a/drivers/gpu/drm/amd/amdgpu/vi.c ++++ b/drivers/gpu/drm/amd/amdgpu/vi.c +@@ -939,8 +939,8 @@ static int vi_common_early_init(void *handle) + + adev->asic_funcs = &vi_asic_funcs; + +- if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC) && +- (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_SMC))) ++ if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC) && ++ (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_SMC))) + smc_enabled = true; + + adev->rev_id = vi_get_rev_id(adev); +@@ -1535,115 +1535,115 @@ int vi_set_ip_blocks(struct amdgpu_device *adev) + switch (adev->asic_type) { + case CHIP_TOPAZ: + /* topaz has no DCE, UVD, VCE */ +- amdgpu_ip_block_add(adev, &vi_common_ip_block); +- amdgpu_ip_block_add(adev, &gmc_v7_4_ip_block); +- amdgpu_ip_block_add(adev, &iceland_ih_ip_block); +- amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); ++ amdgpu_device_ip_block_add(adev, &vi_common_ip_block); ++ amdgpu_device_ip_block_add(adev, &gmc_v7_4_ip_block); ++ amdgpu_device_ip_block_add(adev, &iceland_ih_ip_block); ++ amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block); + if (adev->enable_virtual_display) +- amdgpu_ip_block_add(adev, &dce_virtual_ip_block); +- amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block); +- amdgpu_ip_block_add(adev, &sdma_v2_4_ip_block); ++ amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); ++ amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &sdma_v2_4_ip_block); + break; + case CHIP_FIJI: +- amdgpu_ip_block_add(adev, &vi_common_ip_block); +- amdgpu_ip_block_add(adev, &gmc_v8_5_ip_block); +- amdgpu_ip_block_add(adev, &tonga_ih_ip_block); +- amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); ++ amdgpu_device_ip_block_add(adev, &vi_common_ip_block); ++ amdgpu_device_ip_block_add(adev, &gmc_v8_5_ip_block); ++ amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block); ++ amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block); + if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) +- amdgpu_ip_block_add(adev, &dce_virtual_ip_block); ++ amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); + #if defined(CONFIG_DRM_AMD_DC) + else if (amdgpu_device_has_dc_support(adev)) +- amdgpu_ip_block_add(adev, &dm_ip_block); ++ amdgpu_device_ip_block_add(adev, &dm_ip_block); + #endif + else +- amdgpu_ip_block_add(adev, &dce_v10_1_ip_block); +- amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block); +- amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &dce_v10_1_ip_block); ++ amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block); + if (!amdgpu_sriov_vf(adev)) { +- amdgpu_ip_block_add(adev, &uvd_v6_0_ip_block); +- amdgpu_ip_block_add(adev, &vce_v3_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block); + } + break; + case CHIP_TONGA: +- amdgpu_ip_block_add(adev, &vi_common_ip_block); +- amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block); +- amdgpu_ip_block_add(adev, &tonga_ih_ip_block); +- amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); ++ amdgpu_device_ip_block_add(adev, &vi_common_ip_block); ++ amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block); ++ amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block); + if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) +- amdgpu_ip_block_add(adev, &dce_virtual_ip_block); ++ amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); + #if defined(CONFIG_DRM_AMD_DC) + else if (amdgpu_device_has_dc_support(adev)) +- amdgpu_ip_block_add(adev, &dm_ip_block); ++ amdgpu_device_ip_block_add(adev, &dm_ip_block); + #endif + else +- amdgpu_ip_block_add(adev, &dce_v10_0_ip_block); +- amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block); +- amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &dce_v10_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block); + if (!amdgpu_sriov_vf(adev)) { +- amdgpu_ip_block_add(adev, &uvd_v5_0_ip_block); +- amdgpu_ip_block_add(adev, &vce_v3_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &uvd_v5_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block); + } + break; + case CHIP_POLARIS11: + case CHIP_POLARIS10: + case CHIP_POLARIS12: +- amdgpu_ip_block_add(adev, &vi_common_ip_block); +- amdgpu_ip_block_add(adev, &gmc_v8_1_ip_block); +- amdgpu_ip_block_add(adev, &tonga_ih_ip_block); +- amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); ++ amdgpu_device_ip_block_add(adev, &vi_common_ip_block); ++ amdgpu_device_ip_block_add(adev, &gmc_v8_1_ip_block); ++ amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block); ++ amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block); + if (adev->enable_virtual_display) +- amdgpu_ip_block_add(adev, &dce_virtual_ip_block); ++ amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); + #if defined(CONFIG_DRM_AMD_DC) + else if (amdgpu_device_has_dc_support(adev)) +- amdgpu_ip_block_add(adev, &dm_ip_block); ++ amdgpu_device_ip_block_add(adev, &dm_ip_block); + #endif + else +- amdgpu_ip_block_add(adev, &dce_v11_2_ip_block); +- amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block); +- amdgpu_ip_block_add(adev, &sdma_v3_1_ip_block); +- amdgpu_ip_block_add(adev, &uvd_v6_3_ip_block); +- amdgpu_ip_block_add(adev, &vce_v3_4_ip_block); ++ amdgpu_device_ip_block_add(adev, &dce_v11_2_ip_block); ++ amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &sdma_v3_1_ip_block); ++ amdgpu_device_ip_block_add(adev, &uvd_v6_3_ip_block); ++ amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block); + break; + case CHIP_CARRIZO: +- amdgpu_ip_block_add(adev, &vi_common_ip_block); +- amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block); +- amdgpu_ip_block_add(adev, &cz_ih_ip_block); +- amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); ++ amdgpu_device_ip_block_add(adev, &vi_common_ip_block); ++ amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &cz_ih_ip_block); ++ amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block); + if (adev->enable_virtual_display) +- amdgpu_ip_block_add(adev, &dce_virtual_ip_block); ++ amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); + #if defined(CONFIG_DRM_AMD_DC) + else if (amdgpu_device_has_dc_support(adev)) +- amdgpu_ip_block_add(adev, &dm_ip_block); ++ amdgpu_device_ip_block_add(adev, &dm_ip_block); + #endif + else +- amdgpu_ip_block_add(adev, &dce_v11_0_ip_block); +- amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block); +- amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block); +- amdgpu_ip_block_add(adev, &uvd_v6_0_ip_block); +- amdgpu_ip_block_add(adev, &vce_v3_1_ip_block); ++ amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &vce_v3_1_ip_block); + #if defined(CONFIG_DRM_AMD_ACP) +- amdgpu_ip_block_add(adev, &acp_ip_block); ++ amdgpu_device_ip_block_add(adev, &acp_ip_block); + #endif + break; + case CHIP_STONEY: +- amdgpu_ip_block_add(adev, &vi_common_ip_block); +- amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block); +- amdgpu_ip_block_add(adev, &cz_ih_ip_block); +- amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); ++ amdgpu_device_ip_block_add(adev, &vi_common_ip_block); ++ amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &cz_ih_ip_block); ++ amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block); + if (adev->enable_virtual_display) +- amdgpu_ip_block_add(adev, &dce_virtual_ip_block); ++ amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); + #if defined(CONFIG_DRM_AMD_DC) + else if (amdgpu_device_has_dc_support(adev)) +- amdgpu_ip_block_add(adev, &dm_ip_block); ++ amdgpu_device_ip_block_add(adev, &dm_ip_block); + #endif + else +- amdgpu_ip_block_add(adev, &dce_v11_0_ip_block); +- amdgpu_ip_block_add(adev, &gfx_v8_1_ip_block); +- amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block); +- amdgpu_ip_block_add(adev, &uvd_v6_2_ip_block); +- amdgpu_ip_block_add(adev, &vce_v3_4_ip_block); ++ amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &gfx_v8_1_ip_block); ++ amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block); ++ amdgpu_device_ip_block_add(adev, &uvd_v6_2_ip_block); ++ amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block); + #if defined(CONFIG_DRM_AMD_ACP) +- amdgpu_ip_block_add(adev, &acp_ip_block); ++ amdgpu_device_ip_block_add(adev, &acp_ip_block); + #endif + break; + default: +-- +2.7.4 + |