diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2975-drm-amdgpu-rename-amdgpu_program_register_sequence.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2975-drm-amdgpu-rename-amdgpu_program_register_sequence.patch | 891 |
1 files changed, 891 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2975-drm-amdgpu-rename-amdgpu_program_register_sequence.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2975-drm-amdgpu-rename-amdgpu_program_register_sequence.patch new file mode 100644 index 00000000..01a8cd1a --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2975-drm-amdgpu-rename-amdgpu_program_register_sequence.patch @@ -0,0 +1,891 @@ +From b019ad03ee3464644a1cbe2a790c81aab8755835 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Thu, 14 Dec 2017 16:20:19 -0500 +Subject: [PATCH 2975/4131] drm/amdgpu: rename amdgpu_program_register_sequence +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +add device for consistency with other functions in this file. + +Acked-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +- + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 +- + drivers/gpu/drm/amd/amdgpu/cik.c | 120 ++++++++++++++--------------- + drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 24 +++--- + drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 30 ++++---- + drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 114 +++++++++++++-------------- + drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 12 +-- + drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 54 ++++++------- + drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 6 +- + drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c | 48 ++++++------ + drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 12 +-- + drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 60 +++++++-------- + drivers/gpu/drm/amd/amdgpu/si.c | 102 ++++++++++++------------ + drivers/gpu/drm/amd/amdgpu/vi.c | 30 ++++---- + 14 files changed, 311 insertions(+), 311 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +index a49bbd4..fb313c2 100755 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +@@ -1986,7 +1986,7 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); + void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); + int amdgpu_ttm_init(struct amdgpu_device *adev); + void amdgpu_ttm_fini(struct amdgpu_device *adev); +-void amdgpu_program_register_sequence(struct amdgpu_device *adev, ++void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, + const u32 *registers, + const u32 array_size); + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +index 1ddc200..2eeed96 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +@@ -341,7 +341,7 @@ static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev) + } + + /** +- * amdgpu_program_register_sequence - program an array of registers. ++ * amdgpu_device_program_register_sequence - program an array of registers. + * + * @adev: amdgpu_device pointer + * @registers: pointer to the register array +@@ -350,9 +350,9 @@ static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev) + * Programs an array or registers with and and or masks. + * This is a helper for setting golden registers. + */ +-void amdgpu_program_register_sequence(struct amdgpu_device *adev, +- const u32 *registers, +- const u32 array_size) ++void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, ++ const u32 *registers, ++ const u32 array_size) + { + u32 tmp, reg, and_mask, or_mask; + int i; +diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c +index 8ba056a..39d4971 100644 +--- a/drivers/gpu/drm/amd/amdgpu/cik.c ++++ b/drivers/gpu/drm/amd/amdgpu/cik.c +@@ -755,74 +755,74 @@ static void cik_init_golden_registers(struct amdgpu_device *adev) + + switch (adev->asic_type) { + case CHIP_BONAIRE: +- amdgpu_program_register_sequence(adev, +- bonaire_mgcg_cgcg_init, +- ARRAY_SIZE(bonaire_mgcg_cgcg_init)); +- amdgpu_program_register_sequence(adev, +- bonaire_golden_registers, +- ARRAY_SIZE(bonaire_golden_registers)); +- amdgpu_program_register_sequence(adev, +- bonaire_golden_common_registers, +- ARRAY_SIZE(bonaire_golden_common_registers)); +- amdgpu_program_register_sequence(adev, +- bonaire_golden_spm_registers, +- ARRAY_SIZE(bonaire_golden_spm_registers)); ++ amdgpu_device_program_register_sequence(adev, ++ bonaire_mgcg_cgcg_init, ++ ARRAY_SIZE(bonaire_mgcg_cgcg_init)); ++ amdgpu_device_program_register_sequence(adev, ++ bonaire_golden_registers, ++ ARRAY_SIZE(bonaire_golden_registers)); ++ amdgpu_device_program_register_sequence(adev, ++ bonaire_golden_common_registers, ++ ARRAY_SIZE(bonaire_golden_common_registers)); ++ amdgpu_device_program_register_sequence(adev, ++ bonaire_golden_spm_registers, ++ ARRAY_SIZE(bonaire_golden_spm_registers)); + break; + case CHIP_KABINI: +- amdgpu_program_register_sequence(adev, +- kalindi_mgcg_cgcg_init, +- ARRAY_SIZE(kalindi_mgcg_cgcg_init)); +- amdgpu_program_register_sequence(adev, +- kalindi_golden_registers, +- ARRAY_SIZE(kalindi_golden_registers)); +- amdgpu_program_register_sequence(adev, +- kalindi_golden_common_registers, +- ARRAY_SIZE(kalindi_golden_common_registers)); +- amdgpu_program_register_sequence(adev, +- kalindi_golden_spm_registers, +- ARRAY_SIZE(kalindi_golden_spm_registers)); ++ amdgpu_device_program_register_sequence(adev, ++ kalindi_mgcg_cgcg_init, ++ ARRAY_SIZE(kalindi_mgcg_cgcg_init)); ++ amdgpu_device_program_register_sequence(adev, ++ kalindi_golden_registers, ++ ARRAY_SIZE(kalindi_golden_registers)); ++ amdgpu_device_program_register_sequence(adev, ++ kalindi_golden_common_registers, ++ ARRAY_SIZE(kalindi_golden_common_registers)); ++ amdgpu_device_program_register_sequence(adev, ++ kalindi_golden_spm_registers, ++ ARRAY_SIZE(kalindi_golden_spm_registers)); + break; + case CHIP_MULLINS: +- amdgpu_program_register_sequence(adev, +- kalindi_mgcg_cgcg_init, +- ARRAY_SIZE(kalindi_mgcg_cgcg_init)); +- amdgpu_program_register_sequence(adev, +- godavari_golden_registers, +- ARRAY_SIZE(godavari_golden_registers)); +- amdgpu_program_register_sequence(adev, +- kalindi_golden_common_registers, +- ARRAY_SIZE(kalindi_golden_common_registers)); +- amdgpu_program_register_sequence(adev, +- kalindi_golden_spm_registers, +- ARRAY_SIZE(kalindi_golden_spm_registers)); ++ amdgpu_device_program_register_sequence(adev, ++ kalindi_mgcg_cgcg_init, ++ ARRAY_SIZE(kalindi_mgcg_cgcg_init)); ++ amdgpu_device_program_register_sequence(adev, ++ godavari_golden_registers, ++ ARRAY_SIZE(godavari_golden_registers)); ++ amdgpu_device_program_register_sequence(adev, ++ kalindi_golden_common_registers, ++ ARRAY_SIZE(kalindi_golden_common_registers)); ++ amdgpu_device_program_register_sequence(adev, ++ kalindi_golden_spm_registers, ++ ARRAY_SIZE(kalindi_golden_spm_registers)); + break; + case CHIP_KAVERI: +- amdgpu_program_register_sequence(adev, +- spectre_mgcg_cgcg_init, +- ARRAY_SIZE(spectre_mgcg_cgcg_init)); +- amdgpu_program_register_sequence(adev, +- spectre_golden_registers, +- ARRAY_SIZE(spectre_golden_registers)); +- amdgpu_program_register_sequence(adev, +- spectre_golden_common_registers, +- ARRAY_SIZE(spectre_golden_common_registers)); +- amdgpu_program_register_sequence(adev, +- spectre_golden_spm_registers, +- ARRAY_SIZE(spectre_golden_spm_registers)); ++ amdgpu_device_program_register_sequence(adev, ++ spectre_mgcg_cgcg_init, ++ ARRAY_SIZE(spectre_mgcg_cgcg_init)); ++ amdgpu_device_program_register_sequence(adev, ++ spectre_golden_registers, ++ ARRAY_SIZE(spectre_golden_registers)); ++ amdgpu_device_program_register_sequence(adev, ++ spectre_golden_common_registers, ++ ARRAY_SIZE(spectre_golden_common_registers)); ++ amdgpu_device_program_register_sequence(adev, ++ spectre_golden_spm_registers, ++ ARRAY_SIZE(spectre_golden_spm_registers)); + break; + case CHIP_HAWAII: +- amdgpu_program_register_sequence(adev, +- hawaii_mgcg_cgcg_init, +- ARRAY_SIZE(hawaii_mgcg_cgcg_init)); +- amdgpu_program_register_sequence(adev, +- hawaii_golden_registers, +- ARRAY_SIZE(hawaii_golden_registers)); +- amdgpu_program_register_sequence(adev, +- hawaii_golden_common_registers, +- ARRAY_SIZE(hawaii_golden_common_registers)); +- amdgpu_program_register_sequence(adev, +- hawaii_golden_spm_registers, +- ARRAY_SIZE(hawaii_golden_spm_registers)); ++ amdgpu_device_program_register_sequence(adev, ++ hawaii_mgcg_cgcg_init, ++ ARRAY_SIZE(hawaii_mgcg_cgcg_init)); ++ amdgpu_device_program_register_sequence(adev, ++ hawaii_golden_registers, ++ ARRAY_SIZE(hawaii_golden_registers)); ++ amdgpu_device_program_register_sequence(adev, ++ hawaii_golden_common_registers, ++ ARRAY_SIZE(hawaii_golden_common_registers)); ++ amdgpu_device_program_register_sequence(adev, ++ hawaii_golden_spm_registers, ++ ARRAY_SIZE(hawaii_golden_spm_registers)); + break; + default: + break; +diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +index a397111..f34bc68 100644 +--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +@@ -145,20 +145,20 @@ static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev) + { + switch (adev->asic_type) { + case CHIP_FIJI: +- amdgpu_program_register_sequence(adev, +- fiji_mgcg_cgcg_init, +- ARRAY_SIZE(fiji_mgcg_cgcg_init)); +- amdgpu_program_register_sequence(adev, +- golden_settings_fiji_a10, +- ARRAY_SIZE(golden_settings_fiji_a10)); ++ amdgpu_device_program_register_sequence(adev, ++ fiji_mgcg_cgcg_init, ++ ARRAY_SIZE(fiji_mgcg_cgcg_init)); ++ amdgpu_device_program_register_sequence(adev, ++ golden_settings_fiji_a10, ++ ARRAY_SIZE(golden_settings_fiji_a10)); + break; + case CHIP_TONGA: +- amdgpu_program_register_sequence(adev, +- tonga_mgcg_cgcg_init, +- ARRAY_SIZE(tonga_mgcg_cgcg_init)); +- amdgpu_program_register_sequence(adev, +- golden_settings_tonga_a11, +- ARRAY_SIZE(golden_settings_tonga_a11)); ++ amdgpu_device_program_register_sequence(adev, ++ tonga_mgcg_cgcg_init, ++ ARRAY_SIZE(tonga_mgcg_cgcg_init)); ++ amdgpu_device_program_register_sequence(adev, ++ golden_settings_tonga_a11, ++ ARRAY_SIZE(golden_settings_tonga_a11)); + break; + default: + break; +diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +index 67e6709..26378bd 100644 +--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +@@ -154,28 +154,28 @@ static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) + { + switch (adev->asic_type) { + case CHIP_CARRIZO: +- amdgpu_program_register_sequence(adev, +- cz_mgcg_cgcg_init, +- ARRAY_SIZE(cz_mgcg_cgcg_init)); +- amdgpu_program_register_sequence(adev, +- cz_golden_settings_a11, +- ARRAY_SIZE(cz_golden_settings_a11)); ++ amdgpu_device_program_register_sequence(adev, ++ cz_mgcg_cgcg_init, ++ ARRAY_SIZE(cz_mgcg_cgcg_init)); ++ amdgpu_device_program_register_sequence(adev, ++ cz_golden_settings_a11, ++ ARRAY_SIZE(cz_golden_settings_a11)); + break; + case CHIP_STONEY: +- amdgpu_program_register_sequence(adev, +- stoney_golden_settings_a11, +- ARRAY_SIZE(stoney_golden_settings_a11)); ++ amdgpu_device_program_register_sequence(adev, ++ stoney_golden_settings_a11, ++ ARRAY_SIZE(stoney_golden_settings_a11)); + break; + case CHIP_POLARIS11: + case CHIP_POLARIS12: +- amdgpu_program_register_sequence(adev, +- polaris11_golden_settings_a11, +- ARRAY_SIZE(polaris11_golden_settings_a11)); ++ amdgpu_device_program_register_sequence(adev, ++ polaris11_golden_settings_a11, ++ ARRAY_SIZE(polaris11_golden_settings_a11)); + break; + case CHIP_POLARIS10: +- amdgpu_program_register_sequence(adev, +- polaris10_golden_settings_a11, +- ARRAY_SIZE(polaris10_golden_settings_a11)); ++ amdgpu_device_program_register_sequence(adev, ++ polaris10_golden_settings_a11, ++ ARRAY_SIZE(polaris10_golden_settings_a11)); + break; + default: + break; +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +index cfabb4e..3ab7cb9 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +@@ -679,55 +679,55 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev) + { + switch (adev->asic_type) { + case CHIP_TOPAZ: +- amdgpu_program_register_sequence(adev, +- iceland_mgcg_cgcg_init, +- ARRAY_SIZE(iceland_mgcg_cgcg_init)); +- amdgpu_program_register_sequence(adev, +- golden_settings_iceland_a11, +- ARRAY_SIZE(golden_settings_iceland_a11)); +- amdgpu_program_register_sequence(adev, +- iceland_golden_common_all, +- ARRAY_SIZE(iceland_golden_common_all)); ++ amdgpu_device_program_register_sequence(adev, ++ iceland_mgcg_cgcg_init, ++ ARRAY_SIZE(iceland_mgcg_cgcg_init)); ++ amdgpu_device_program_register_sequence(adev, ++ golden_settings_iceland_a11, ++ ARRAY_SIZE(golden_settings_iceland_a11)); ++ amdgpu_device_program_register_sequence(adev, ++ iceland_golden_common_all, ++ ARRAY_SIZE(iceland_golden_common_all)); + break; + case CHIP_FIJI: +- amdgpu_program_register_sequence(adev, +- fiji_mgcg_cgcg_init, +- ARRAY_SIZE(fiji_mgcg_cgcg_init)); +- amdgpu_program_register_sequence(adev, +- golden_settings_fiji_a10, +- ARRAY_SIZE(golden_settings_fiji_a10)); +- amdgpu_program_register_sequence(adev, +- fiji_golden_common_all, +- ARRAY_SIZE(fiji_golden_common_all)); ++ amdgpu_device_program_register_sequence(adev, ++ fiji_mgcg_cgcg_init, ++ ARRAY_SIZE(fiji_mgcg_cgcg_init)); ++ amdgpu_device_program_register_sequence(adev, ++ golden_settings_fiji_a10, ++ ARRAY_SIZE(golden_settings_fiji_a10)); ++ amdgpu_device_program_register_sequence(adev, ++ fiji_golden_common_all, ++ ARRAY_SIZE(fiji_golden_common_all)); + break; + + case CHIP_TONGA: +- amdgpu_program_register_sequence(adev, +- tonga_mgcg_cgcg_init, +- ARRAY_SIZE(tonga_mgcg_cgcg_init)); +- amdgpu_program_register_sequence(adev, +- golden_settings_tonga_a11, +- ARRAY_SIZE(golden_settings_tonga_a11)); +- amdgpu_program_register_sequence(adev, +- tonga_golden_common_all, +- ARRAY_SIZE(tonga_golden_common_all)); ++ amdgpu_device_program_register_sequence(adev, ++ tonga_mgcg_cgcg_init, ++ ARRAY_SIZE(tonga_mgcg_cgcg_init)); ++ amdgpu_device_program_register_sequence(adev, ++ golden_settings_tonga_a11, ++ ARRAY_SIZE(golden_settings_tonga_a11)); ++ amdgpu_device_program_register_sequence(adev, ++ tonga_golden_common_all, ++ ARRAY_SIZE(tonga_golden_common_all)); + break; + case CHIP_POLARIS11: + case CHIP_POLARIS12: +- amdgpu_program_register_sequence(adev, +- golden_settings_polaris11_a11, +- ARRAY_SIZE(golden_settings_polaris11_a11)); +- amdgpu_program_register_sequence(adev, +- polaris11_golden_common_all, +- ARRAY_SIZE(polaris11_golden_common_all)); ++ amdgpu_device_program_register_sequence(adev, ++ golden_settings_polaris11_a11, ++ ARRAY_SIZE(golden_settings_polaris11_a11)); ++ amdgpu_device_program_register_sequence(adev, ++ polaris11_golden_common_all, ++ ARRAY_SIZE(polaris11_golden_common_all)); + break; + case CHIP_POLARIS10: +- amdgpu_program_register_sequence(adev, +- golden_settings_polaris10_a11, +- ARRAY_SIZE(golden_settings_polaris10_a11)); +- amdgpu_program_register_sequence(adev, +- polaris10_golden_common_all, +- ARRAY_SIZE(polaris10_golden_common_all)); ++ amdgpu_device_program_register_sequence(adev, ++ golden_settings_polaris10_a11, ++ ARRAY_SIZE(golden_settings_polaris10_a11)); ++ amdgpu_device_program_register_sequence(adev, ++ polaris10_golden_common_all, ++ ARRAY_SIZE(polaris10_golden_common_all)); + WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C); + if (adev->pdev->revision == 0xc7 && + ((adev->pdev->subsystem_device == 0xb37 && adev->pdev->subsystem_vendor == 0x1002) || +@@ -738,26 +738,26 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev) + } + break; + case CHIP_CARRIZO: +- amdgpu_program_register_sequence(adev, +- cz_mgcg_cgcg_init, +- ARRAY_SIZE(cz_mgcg_cgcg_init)); +- amdgpu_program_register_sequence(adev, +- cz_golden_settings_a11, +- ARRAY_SIZE(cz_golden_settings_a11)); +- amdgpu_program_register_sequence(adev, +- cz_golden_common_all, +- ARRAY_SIZE(cz_golden_common_all)); ++ amdgpu_device_program_register_sequence(adev, ++ cz_mgcg_cgcg_init, ++ ARRAY_SIZE(cz_mgcg_cgcg_init)); ++ amdgpu_device_program_register_sequence(adev, ++ cz_golden_settings_a11, ++ ARRAY_SIZE(cz_golden_settings_a11)); ++ amdgpu_device_program_register_sequence(adev, ++ cz_golden_common_all, ++ ARRAY_SIZE(cz_golden_common_all)); + break; + case CHIP_STONEY: +- amdgpu_program_register_sequence(adev, +- stoney_mgcg_cgcg_init, +- ARRAY_SIZE(stoney_mgcg_cgcg_init)); +- amdgpu_program_register_sequence(adev, +- stoney_golden_settings_a11, +- ARRAY_SIZE(stoney_golden_settings_a11)); +- amdgpu_program_register_sequence(adev, +- stoney_golden_common_all, +- ARRAY_SIZE(stoney_golden_common_all)); ++ amdgpu_device_program_register_sequence(adev, ++ stoney_mgcg_cgcg_init, ++ ARRAY_SIZE(stoney_mgcg_cgcg_init)); ++ amdgpu_device_program_register_sequence(adev, ++ stoney_golden_settings_a11, ++ ARRAY_SIZE(stoney_golden_settings_a11)); ++ amdgpu_device_program_register_sequence(adev, ++ stoney_golden_common_all, ++ ARRAY_SIZE(stoney_golden_common_all)); + break; + default: + break; +diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +index 05cf66b..dc4c683 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +@@ -68,12 +68,12 @@ static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev) + { + switch (adev->asic_type) { + case CHIP_TOPAZ: +- amdgpu_program_register_sequence(adev, +- iceland_mgcg_cgcg_init, +- ARRAY_SIZE(iceland_mgcg_cgcg_init)); +- amdgpu_program_register_sequence(adev, +- golden_settings_iceland_a11, +- ARRAY_SIZE(golden_settings_iceland_a11)); ++ amdgpu_device_program_register_sequence(adev, ++ iceland_mgcg_cgcg_init, ++ ARRAY_SIZE(iceland_mgcg_cgcg_init)); ++ amdgpu_device_program_register_sequence(adev, ++ golden_settings_iceland_a11, ++ ARRAY_SIZE(golden_settings_iceland_a11)); + break; + default: + break; +diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +index c09721b..59dbefe 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +@@ -121,44 +121,44 @@ static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) + { + switch (adev->asic_type) { + case CHIP_FIJI: +- amdgpu_program_register_sequence(adev, +- fiji_mgcg_cgcg_init, +- ARRAY_SIZE(fiji_mgcg_cgcg_init)); +- amdgpu_program_register_sequence(adev, +- golden_settings_fiji_a10, +- ARRAY_SIZE(golden_settings_fiji_a10)); ++ amdgpu_device_program_register_sequence(adev, ++ fiji_mgcg_cgcg_init, ++ ARRAY_SIZE(fiji_mgcg_cgcg_init)); ++ amdgpu_device_program_register_sequence(adev, ++ golden_settings_fiji_a10, ++ ARRAY_SIZE(golden_settings_fiji_a10)); + break; + case CHIP_TONGA: +- amdgpu_program_register_sequence(adev, +- tonga_mgcg_cgcg_init, +- ARRAY_SIZE(tonga_mgcg_cgcg_init)); +- amdgpu_program_register_sequence(adev, +- golden_settings_tonga_a11, +- ARRAY_SIZE(golden_settings_tonga_a11)); ++ amdgpu_device_program_register_sequence(adev, ++ tonga_mgcg_cgcg_init, ++ ARRAY_SIZE(tonga_mgcg_cgcg_init)); ++ amdgpu_device_program_register_sequence(adev, ++ golden_settings_tonga_a11, ++ ARRAY_SIZE(golden_settings_tonga_a11)); + break; + case CHIP_POLARIS11: + case CHIP_POLARIS12: +- amdgpu_program_register_sequence(adev, +- golden_settings_polaris11_a11, +- ARRAY_SIZE(golden_settings_polaris11_a11)); ++ amdgpu_device_program_register_sequence(adev, ++ golden_settings_polaris11_a11, ++ ARRAY_SIZE(golden_settings_polaris11_a11)); + break; + case CHIP_POLARIS10: +- amdgpu_program_register_sequence(adev, +- golden_settings_polaris10_a11, +- ARRAY_SIZE(golden_settings_polaris10_a11)); ++ amdgpu_device_program_register_sequence(adev, ++ golden_settings_polaris10_a11, ++ ARRAY_SIZE(golden_settings_polaris10_a11)); + break; + case CHIP_CARRIZO: +- amdgpu_program_register_sequence(adev, +- cz_mgcg_cgcg_init, +- ARRAY_SIZE(cz_mgcg_cgcg_init)); ++ amdgpu_device_program_register_sequence(adev, ++ cz_mgcg_cgcg_init, ++ ARRAY_SIZE(cz_mgcg_cgcg_init)); + break; + case CHIP_STONEY: +- amdgpu_program_register_sequence(adev, +- stoney_mgcg_cgcg_init, +- ARRAY_SIZE(stoney_mgcg_cgcg_init)); +- amdgpu_program_register_sequence(adev, +- golden_settings_stoney_common, +- ARRAY_SIZE(golden_settings_stoney_common)); ++ amdgpu_device_program_register_sequence(adev, ++ stoney_mgcg_cgcg_init, ++ ARRAY_SIZE(stoney_mgcg_cgcg_init)); ++ amdgpu_device_program_register_sequence(adev, ++ golden_settings_stoney_common, ++ ARRAY_SIZE(golden_settings_stoney_common)); + break; + default: + break; +diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +index d45aaef..5383c3d 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +@@ -941,9 +941,9 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) + bool value; + u32 tmp; + +- amdgpu_program_register_sequence(adev, +- golden_settings_vega10_hdp, +- ARRAY_SIZE(golden_settings_vega10_hdp)); ++ amdgpu_device_program_register_sequence(adev, ++ golden_settings_vega10_hdp, ++ ARRAY_SIZE(golden_settings_vega10_hdp)); + + if (adev->gart.robj == NULL) { + dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); +diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c +index da7c261..af2d47e9 100644 +--- a/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c ++++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c +@@ -279,32 +279,32 @@ void xgpu_vi_init_golden_registers(struct amdgpu_device *adev) + { + switch (adev->asic_type) { + case CHIP_FIJI: +- amdgpu_program_register_sequence(adev, +- xgpu_fiji_mgcg_cgcg_init, +- ARRAY_SIZE( +- xgpu_fiji_mgcg_cgcg_init)); +- amdgpu_program_register_sequence(adev, +- xgpu_fiji_golden_settings_a10, +- ARRAY_SIZE( +- xgpu_fiji_golden_settings_a10)); +- amdgpu_program_register_sequence(adev, +- xgpu_fiji_golden_common_all, +- ARRAY_SIZE( +- xgpu_fiji_golden_common_all)); ++ amdgpu_device_program_register_sequence(adev, ++ xgpu_fiji_mgcg_cgcg_init, ++ ARRAY_SIZE( ++ xgpu_fiji_mgcg_cgcg_init)); ++ amdgpu_device_program_register_sequence(adev, ++ xgpu_fiji_golden_settings_a10, ++ ARRAY_SIZE( ++ xgpu_fiji_golden_settings_a10)); ++ amdgpu_device_program_register_sequence(adev, ++ xgpu_fiji_golden_common_all, ++ ARRAY_SIZE( ++ xgpu_fiji_golden_common_all)); + break; + case CHIP_TONGA: +- amdgpu_program_register_sequence(adev, +- xgpu_tonga_mgcg_cgcg_init, +- ARRAY_SIZE( +- xgpu_tonga_mgcg_cgcg_init)); +- amdgpu_program_register_sequence(adev, +- xgpu_tonga_golden_settings_a11, +- ARRAY_SIZE( +- xgpu_tonga_golden_settings_a11)); +- amdgpu_program_register_sequence(adev, +- xgpu_tonga_golden_common_all, +- ARRAY_SIZE( +- xgpu_tonga_golden_common_all)); ++ amdgpu_device_program_register_sequence(adev, ++ xgpu_tonga_mgcg_cgcg_init, ++ ARRAY_SIZE( ++ xgpu_tonga_mgcg_cgcg_init)); ++ amdgpu_device_program_register_sequence(adev, ++ xgpu_tonga_golden_settings_a11, ++ ARRAY_SIZE( ++ xgpu_tonga_golden_settings_a11)); ++ amdgpu_device_program_register_sequence(adev, ++ xgpu_tonga_golden_common_all, ++ ARRAY_SIZE( ++ xgpu_tonga_golden_common_all)); + break; + default: + BUG_ON("Doesn't support chip type.\n"); +diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +index f38f5a3..b069b90 100644 +--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c ++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +@@ -93,12 +93,12 @@ static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev) + { + switch (adev->asic_type) { + case CHIP_TOPAZ: +- amdgpu_program_register_sequence(adev, +- iceland_mgcg_cgcg_init, +- ARRAY_SIZE(iceland_mgcg_cgcg_init)); +- amdgpu_program_register_sequence(adev, +- golden_settings_iceland_a11, +- ARRAY_SIZE(golden_settings_iceland_a11)); ++ amdgpu_device_program_register_sequence(adev, ++ iceland_mgcg_cgcg_init, ++ ARRAY_SIZE(iceland_mgcg_cgcg_init)); ++ amdgpu_device_program_register_sequence(adev, ++ golden_settings_iceland_a11, ++ ARRAY_SIZE(golden_settings_iceland_a11)); + break; + default: + break; +diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +index 8514465..c3e0e61 100644 +--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +@@ -192,47 +192,47 @@ static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) + { + switch (adev->asic_type) { + case CHIP_FIJI: +- amdgpu_program_register_sequence(adev, +- fiji_mgcg_cgcg_init, +- ARRAY_SIZE(fiji_mgcg_cgcg_init)); +- amdgpu_program_register_sequence(adev, +- golden_settings_fiji_a10, +- ARRAY_SIZE(golden_settings_fiji_a10)); ++ amdgpu_device_program_register_sequence(adev, ++ fiji_mgcg_cgcg_init, ++ ARRAY_SIZE(fiji_mgcg_cgcg_init)); ++ amdgpu_device_program_register_sequence(adev, ++ golden_settings_fiji_a10, ++ ARRAY_SIZE(golden_settings_fiji_a10)); + break; + case CHIP_TONGA: +- amdgpu_program_register_sequence(adev, +- tonga_mgcg_cgcg_init, +- ARRAY_SIZE(tonga_mgcg_cgcg_init)); +- amdgpu_program_register_sequence(adev, +- golden_settings_tonga_a11, +- ARRAY_SIZE(golden_settings_tonga_a11)); ++ amdgpu_device_program_register_sequence(adev, ++ tonga_mgcg_cgcg_init, ++ ARRAY_SIZE(tonga_mgcg_cgcg_init)); ++ amdgpu_device_program_register_sequence(adev, ++ golden_settings_tonga_a11, ++ ARRAY_SIZE(golden_settings_tonga_a11)); + break; + case CHIP_POLARIS11: + case CHIP_POLARIS12: +- amdgpu_program_register_sequence(adev, +- golden_settings_polaris11_a11, +- ARRAY_SIZE(golden_settings_polaris11_a11)); ++ amdgpu_device_program_register_sequence(adev, ++ golden_settings_polaris11_a11, ++ ARRAY_SIZE(golden_settings_polaris11_a11)); + break; + case CHIP_POLARIS10: +- amdgpu_program_register_sequence(adev, +- golden_settings_polaris10_a11, +- ARRAY_SIZE(golden_settings_polaris10_a11)); ++ amdgpu_device_program_register_sequence(adev, ++ golden_settings_polaris10_a11, ++ ARRAY_SIZE(golden_settings_polaris10_a11)); + break; + case CHIP_CARRIZO: +- amdgpu_program_register_sequence(adev, +- cz_mgcg_cgcg_init, +- ARRAY_SIZE(cz_mgcg_cgcg_init)); +- amdgpu_program_register_sequence(adev, +- cz_golden_settings_a11, +- ARRAY_SIZE(cz_golden_settings_a11)); ++ amdgpu_device_program_register_sequence(adev, ++ cz_mgcg_cgcg_init, ++ ARRAY_SIZE(cz_mgcg_cgcg_init)); ++ amdgpu_device_program_register_sequence(adev, ++ cz_golden_settings_a11, ++ ARRAY_SIZE(cz_golden_settings_a11)); + break; + case CHIP_STONEY: +- amdgpu_program_register_sequence(adev, +- stoney_mgcg_cgcg_init, +- ARRAY_SIZE(stoney_mgcg_cgcg_init)); +- amdgpu_program_register_sequence(adev, +- stoney_golden_settings_a11, +- ARRAY_SIZE(stoney_golden_settings_a11)); ++ amdgpu_device_program_register_sequence(adev, ++ stoney_mgcg_cgcg_init, ++ ARRAY_SIZE(stoney_mgcg_cgcg_init)); ++ amdgpu_device_program_register_sequence(adev, ++ stoney_golden_settings_a11, ++ ARRAY_SIZE(stoney_golden_settings_a11)); + break; + default: + break; +diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c +index f6298d0..b90aed2 100644 +--- a/drivers/gpu/drm/amd/amdgpu/si.c ++++ b/drivers/gpu/drm/amd/amdgpu/si.c +@@ -1458,65 +1458,65 @@ static void si_init_golden_registers(struct amdgpu_device *adev) + { + switch (adev->asic_type) { + case CHIP_TAHITI: +- amdgpu_program_register_sequence(adev, +- tahiti_golden_registers, +- ARRAY_SIZE(tahiti_golden_registers)); +- amdgpu_program_register_sequence(adev, +- tahiti_golden_rlc_registers, +- ARRAY_SIZE(tahiti_golden_rlc_registers)); +- amdgpu_program_register_sequence(adev, +- tahiti_mgcg_cgcg_init, +- ARRAY_SIZE(tahiti_mgcg_cgcg_init)); +- amdgpu_program_register_sequence(adev, +- tahiti_golden_registers2, +- ARRAY_SIZE(tahiti_golden_registers2)); ++ amdgpu_device_program_register_sequence(adev, ++ tahiti_golden_registers, ++ ARRAY_SIZE(tahiti_golden_registers)); ++ amdgpu_device_program_register_sequence(adev, ++ tahiti_golden_rlc_registers, ++ ARRAY_SIZE(tahiti_golden_rlc_registers)); ++ amdgpu_device_program_register_sequence(adev, ++ tahiti_mgcg_cgcg_init, ++ ARRAY_SIZE(tahiti_mgcg_cgcg_init)); ++ amdgpu_device_program_register_sequence(adev, ++ tahiti_golden_registers2, ++ ARRAY_SIZE(tahiti_golden_registers2)); + break; + case CHIP_PITCAIRN: +- amdgpu_program_register_sequence(adev, +- pitcairn_golden_registers, +- ARRAY_SIZE(pitcairn_golden_registers)); +- amdgpu_program_register_sequence(adev, +- pitcairn_golden_rlc_registers, +- ARRAY_SIZE(pitcairn_golden_rlc_registers)); +- amdgpu_program_register_sequence(adev, +- pitcairn_mgcg_cgcg_init, +- ARRAY_SIZE(pitcairn_mgcg_cgcg_init)); ++ amdgpu_device_program_register_sequence(adev, ++ pitcairn_golden_registers, ++ ARRAY_SIZE(pitcairn_golden_registers)); ++ amdgpu_device_program_register_sequence(adev, ++ pitcairn_golden_rlc_registers, ++ ARRAY_SIZE(pitcairn_golden_rlc_registers)); ++ amdgpu_device_program_register_sequence(adev, ++ pitcairn_mgcg_cgcg_init, ++ ARRAY_SIZE(pitcairn_mgcg_cgcg_init)); + break; + case CHIP_VERDE: +- amdgpu_program_register_sequence(adev, +- verde_golden_registers, +- ARRAY_SIZE(verde_golden_registers)); +- amdgpu_program_register_sequence(adev, +- verde_golden_rlc_registers, +- ARRAY_SIZE(verde_golden_rlc_registers)); +- amdgpu_program_register_sequence(adev, +- verde_mgcg_cgcg_init, +- ARRAY_SIZE(verde_mgcg_cgcg_init)); +- amdgpu_program_register_sequence(adev, +- verde_pg_init, +- ARRAY_SIZE(verde_pg_init)); ++ amdgpu_device_program_register_sequence(adev, ++ verde_golden_registers, ++ ARRAY_SIZE(verde_golden_registers)); ++ amdgpu_device_program_register_sequence(adev, ++ verde_golden_rlc_registers, ++ ARRAY_SIZE(verde_golden_rlc_registers)); ++ amdgpu_device_program_register_sequence(adev, ++ verde_mgcg_cgcg_init, ++ ARRAY_SIZE(verde_mgcg_cgcg_init)); ++ amdgpu_device_program_register_sequence(adev, ++ verde_pg_init, ++ ARRAY_SIZE(verde_pg_init)); + break; + case CHIP_OLAND: +- amdgpu_program_register_sequence(adev, +- oland_golden_registers, +- ARRAY_SIZE(oland_golden_registers)); +- amdgpu_program_register_sequence(adev, +- oland_golden_rlc_registers, +- ARRAY_SIZE(oland_golden_rlc_registers)); +- amdgpu_program_register_sequence(adev, +- oland_mgcg_cgcg_init, +- ARRAY_SIZE(oland_mgcg_cgcg_init)); ++ amdgpu_device_program_register_sequence(adev, ++ oland_golden_registers, ++ ARRAY_SIZE(oland_golden_registers)); ++ amdgpu_device_program_register_sequence(adev, ++ oland_golden_rlc_registers, ++ ARRAY_SIZE(oland_golden_rlc_registers)); ++ amdgpu_device_program_register_sequence(adev, ++ oland_mgcg_cgcg_init, ++ ARRAY_SIZE(oland_mgcg_cgcg_init)); + break; + case CHIP_HAINAN: +- amdgpu_program_register_sequence(adev, +- hainan_golden_registers, +- ARRAY_SIZE(hainan_golden_registers)); +- amdgpu_program_register_sequence(adev, +- hainan_golden_registers2, +- ARRAY_SIZE(hainan_golden_registers2)); +- amdgpu_program_register_sequence(adev, +- hainan_mgcg_cgcg_init, +- ARRAY_SIZE(hainan_mgcg_cgcg_init)); ++ amdgpu_device_program_register_sequence(adev, ++ hainan_golden_registers, ++ ARRAY_SIZE(hainan_golden_registers)); ++ amdgpu_device_program_register_sequence(adev, ++ hainan_golden_registers2, ++ ARRAY_SIZE(hainan_golden_registers2)); ++ amdgpu_device_program_register_sequence(adev, ++ hainan_mgcg_cgcg_init, ++ ARRAY_SIZE(hainan_mgcg_cgcg_init)); + break; + + +diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c +index 3b06706..42a3b27 100644 +--- a/drivers/gpu/drm/amd/amdgpu/vi.c ++++ b/drivers/gpu/drm/amd/amdgpu/vi.c +@@ -282,29 +282,29 @@ static void vi_init_golden_registers(struct amdgpu_device *adev) + + switch (adev->asic_type) { + case CHIP_TOPAZ: +- amdgpu_program_register_sequence(adev, +- iceland_mgcg_cgcg_init, +- ARRAY_SIZE(iceland_mgcg_cgcg_init)); ++ amdgpu_device_program_register_sequence(adev, ++ iceland_mgcg_cgcg_init, ++ ARRAY_SIZE(iceland_mgcg_cgcg_init)); + break; + case CHIP_FIJI: +- amdgpu_program_register_sequence(adev, +- fiji_mgcg_cgcg_init, +- ARRAY_SIZE(fiji_mgcg_cgcg_init)); ++ amdgpu_device_program_register_sequence(adev, ++ fiji_mgcg_cgcg_init, ++ ARRAY_SIZE(fiji_mgcg_cgcg_init)); + break; + case CHIP_TONGA: +- amdgpu_program_register_sequence(adev, +- tonga_mgcg_cgcg_init, +- ARRAY_SIZE(tonga_mgcg_cgcg_init)); ++ amdgpu_device_program_register_sequence(adev, ++ tonga_mgcg_cgcg_init, ++ ARRAY_SIZE(tonga_mgcg_cgcg_init)); + break; + case CHIP_CARRIZO: +- amdgpu_program_register_sequence(adev, +- cz_mgcg_cgcg_init, +- ARRAY_SIZE(cz_mgcg_cgcg_init)); ++ amdgpu_device_program_register_sequence(adev, ++ cz_mgcg_cgcg_init, ++ ARRAY_SIZE(cz_mgcg_cgcg_init)); + break; + case CHIP_STONEY: +- amdgpu_program_register_sequence(adev, +- stoney_mgcg_cgcg_init, +- ARRAY_SIZE(stoney_mgcg_cgcg_init)); ++ amdgpu_device_program_register_sequence(adev, ++ stoney_mgcg_cgcg_init, ++ ARRAY_SIZE(stoney_mgcg_cgcg_init)); + break; + case CHIP_POLARIS11: + case CHIP_POLARIS10: +-- +2.7.4 + |