diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2951-drm-amdgpu-drop-soc15_init_golden_registers.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2951-drm-amdgpu-drop-soc15_init_golden_registers.patch | 69 |
1 files changed, 69 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2951-drm-amdgpu-drop-soc15_init_golden_registers.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2951-drm-amdgpu-drop-soc15_init_golden_registers.patch new file mode 100644 index 00000000..0ba4e45c --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2951-drm-amdgpu-drop-soc15_init_golden_registers.patch @@ -0,0 +1,69 @@ +From 3c580479f98346013193704efa26ddb01053cf6f Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Fri, 8 Dec 2017 13:18:23 -0500 +Subject: [PATCH 2951/4131] drm/amdgpu: drop soc15_init_golden_registers +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The golden register arrays were empty so the function was +effectively useless. + +Acked-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/soc15.c | 31 ------------------------------- + 1 file changed, 31 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c +index 418e186..388e754 100644 +--- a/drivers/gpu/drm/amd/amdgpu/soc15.c ++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c +@@ -231,35 +231,6 @@ static u32 soc15_get_config_memsize(struct amdgpu_device *adev) + return adev->nbio_funcs->get_memsize(adev); + } + +-static const u32 vega10_golden_init[] = +-{ +-}; +- +-static const u32 raven_golden_init[] = +-{ +-}; +- +-static void soc15_init_golden_registers(struct amdgpu_device *adev) +-{ +- /* Some of the registers might be dependent on GRBM_GFX_INDEX */ +- mutex_lock(&adev->grbm_idx_mutex); +- +- switch (adev->asic_type) { +- case CHIP_VEGA10: +- amdgpu_program_register_sequence(adev, +- vega10_golden_init, +- ARRAY_SIZE(vega10_golden_init)); +- break; +- case CHIP_RAVEN: +- amdgpu_program_register_sequence(adev, +- raven_golden_init, +- ARRAY_SIZE(raven_golden_init)); +- break; +- default: +- break; +- } +- mutex_unlock(&adev->grbm_idx_mutex); +-} + static u32 soc15_get_xclk(struct amdgpu_device *adev) + { + return adev->clock.spll.reference_freq; +@@ -745,8 +716,6 @@ static int soc15_common_hw_init(void *handle) + { + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + +- /* move the golden regs per IP block */ +- soc15_init_golden_registers(adev); + /* enable pcie gen2/3 link */ + soc15_pcie_gen3_enable(adev); + /* enable aspm */ +-- +2.7.4 + |