diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2918-drm-amd-display-Add-dppclk-to-dcn_bw_clocks.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2918-drm-amd-display-Add-dppclk-to-dcn_bw_clocks.patch | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2918-drm-amd-display-Add-dppclk-to-dcn_bw_clocks.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2918-drm-amd-display-Add-dppclk-to-dcn_bw_clocks.patch new file mode 100644 index 00000000..158b794f --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2918-drm-amd-display-Add-dppclk-to-dcn_bw_clocks.patch @@ -0,0 +1,55 @@ +From 018b39edbbbd34ede3e68f4acf9f7112423dc912 Mon Sep 17 00:00:00 2001 +From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Date: Tue, 14 Nov 2017 11:52:11 -0500 +Subject: [PATCH 2918/4131] drm/amd/display: Add dppclk to dcn_bw_clocks + +Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Harry Wentland <harry.wentland@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 3 ++- + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 1 - + drivers/gpu/drm/amd/display/dc/inc/core_types.h | 1 + + 3 files changed, 3 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +index 3b0db25..b73db9e 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +@@ -582,7 +582,8 @@ struct dce_hwseq_registers { + type DOMAIN7_PGFSM_PWR_STATUS; \ + type DCFCLK_GATE_DIS; \ + type DCHUBBUB_GLOBAL_TIMER_REFDIV; \ +- type DENTIST_DPPCLK_WDIVIDER; ++ type DENTIST_DPPCLK_WDIVIDER; \ ++ type DENTIST_DISPCLK_WDIVIDER; + + struct dce_hwseq_shift { + HWSEQ_REG_FIELD_LIST(uint8_t) +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index a4d756c..39a4d1a 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -1335,7 +1335,6 @@ static void dcn10_enable_plane( + /* make sure OPP_PIPE_CLOCK_EN = 1 */ + REG_UPDATE(OPP_PIPE_CONTROL[pipe_ctx->stream_res.tg->inst], + OPP_PIPE_CLOCK_EN, 1); +- /*TODO: REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, 0x1f);*/ + + /* TODO: enable/disable in dm as per update type. + if (plane_state) { +diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h +index d680b56..9cc6bbb 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h +@@ -241,6 +241,7 @@ struct dce_bw_output { + + struct dcn_bw_clocks { + int dispclk_khz; ++ int dppclk_khz; + bool dppclk_div; + int dcfclk_khz; + int dcfclk_deep_sleep_khz; +-- +2.7.4 + |