diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2910-drm-amd-display-Set-mpcc_disconnect_pending-during-M.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2910-drm-amd-display-Set-mpcc_disconnect_pending-during-M.patch | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2910-drm-amd-display-Set-mpcc_disconnect_pending-during-M.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2910-drm-amd-display-Set-mpcc_disconnect_pending-during-M.patch new file mode 100644 index 00000000..386e0dd3 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2910-drm-amd-display-Set-mpcc_disconnect_pending-during-M.patch @@ -0,0 +1,70 @@ +From fa8962f41e4fd7a3a0f4bb99f6babdb717f3ba3a Mon Sep 17 00:00:00 2001 +From: Tony Cheng <tony.cheng@amd.com> +Date: Tue, 21 Nov 2017 17:51:50 -0500 +Subject: [PATCH 2910/4131] drm/amd/display: Set mpcc_disconnect_pending during + MPC reset + +This prevents an issue where the MPCC will not go to idle due to us not +waiting for it to become idle during disable plane. + +Signed-off-by: Andrew Jiang <Andrew.Jiang@amd.com> +Signed-off-by: Tony Cheng <tony.cheng@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Harry Wentland <harry.wentland@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 18 ++++++++++++++---- + .../gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 ++-- + 2 files changed, 16 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c +index 584e82c..1984ac2 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c +@@ -42,15 +42,25 @@ void hubp1_set_blank(struct hubp *hubp, bool blank) + { + struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp); + uint32_t blank_en = blank ? 1 : 0; ++ uint32_t reg_val = 0; + +- REG_UPDATE_2(DCHUBP_CNTL, ++ reg_val = REG_UPDATE_2(DCHUBP_CNTL, + HUBP_BLANK_EN, blank_en, + HUBP_TTU_DISABLE, blank_en); + + if (blank) { +- REG_WAIT(DCHUBP_CNTL, +- HUBP_NO_OUTSTANDING_REQ, 1, +- 1, 200); ++ if (reg_val) { ++ /* init sequence workaround: in case HUBP is ++ * power gated, this wait would timeout. ++ * ++ * we just wrote reg_val to non-0, if it stay 0 ++ * it means HUBP is gated ++ */ ++ REG_WAIT(DCHUBP_CNTL, ++ HUBP_NO_OUTSTANDING_REQ, 1, ++ 1, 200); ++ } ++ + hubp->mpcc_id = 0xf; + hubp->opp_id = 0xf; + } +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index 7846534..a4d756c 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -782,8 +782,8 @@ static void dcn10_init_hw(struct dc *dc) + hubp->opp_id = 0xf; + hubp->power_gated = false; + +- if (hubp->opp_id != 0xf) +- pipe_ctx->stream_res.opp = dc->res_pool->opps[hubp->opp_id]; ++ dc->res_pool->opps[i]->mpcc_disconnect_pending[i] = true; ++ pipe_ctx->stream_res.opp = dc->res_pool->opps[i]; + + plane_atomic_disconnect(dc, pipe_ctx); + } +-- +2.7.4 + |