diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2856-drm-amdkfd-Use-order_base_2-to-get-log2-of-buffes-si.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2856-drm-amdkfd-Use-order_base_2-to-get-log2-of-buffes-si.patch | 113 |
1 files changed, 113 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2856-drm-amdkfd-Use-order_base_2-to-get-log2-of-buffes-si.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2856-drm-amdkfd-Use-order_base_2-to-get-log2-of-buffes-si.patch new file mode 100644 index 00000000..f66fb047 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2856-drm-amdkfd-Use-order_base_2-to-get-log2-of-buffes-si.patch @@ -0,0 +1,113 @@ +From 427bc862e9e7fdd7aba7eb49eaa137b76af77c81 Mon Sep 17 00:00:00 2001 +From: Felix Kuehling <Felix.Kuehling@amd.com> +Date: Thu, 2 Nov 2017 18:10:19 -0400 +Subject: [PATCH 2856/4131] drm/amdkfd: Use order_base_2 to get log2 of buffes + sizes + +Replace (ffs(size) - 1) with order_base_2(size) as a more straight +forward way to get log2 of buffer sizes. + +Change-Id: Ibb9d0fa63eaafa93c7fb1a9008ae182e752410ee +Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> +--- + drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 6 +++--- + drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 6 +++--- + drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 6 +++--- + 3 files changed, 9 insertions(+), 9 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c +index a628e28..bac692d 100644 +--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c ++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c +@@ -251,7 +251,7 @@ static int __update_mqd(struct mqd_manager *mm, void *mqd, + * Calculating queue size which is log base 2 of actual queue size -1 + * dwords and another -1 for ffs + */ +- m->cp_hqd_pq_control |= ffs(q->queue_size / 4) - 1 - 1; ++ m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; + m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); + m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); + m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); +@@ -292,7 +292,7 @@ static int update_mqd_sdma(struct mqd_manager *mm, void *mqd, + struct cik_sdma_rlc_registers *m; + + m = get_sdma_mqd(mqd); +- m->sdma_rlc_rb_cntl = (ffs(q->queue_size / 4) - 1) ++ m->sdma_rlc_rb_cntl = order_base_2(q->queue_size / 4) + << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | + q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT | + 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | +@@ -433,7 +433,7 @@ static int update_mqd_hiq(struct mqd_manager *mm, void *mqd, + * Calculating queue size which is log base 2 of actual queue + * size -1 dwords + */ +- m->cp_hqd_pq_control |= ffs(q->queue_size / 4) - 1 - 1; ++ m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; + m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); + m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); + m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); +diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c +index e65725b..9a219c0 100644 +--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c ++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c +@@ -203,7 +203,7 @@ static int update_mqd(struct mqd_manager *mm, void *mqd, + m = get_mqd(mqd); + + m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; +- m->cp_hqd_pq_control |= ffs(q->queue_size / 4) - 1 - 1; ++ m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; + pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); + + m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); +@@ -230,7 +230,7 @@ static int update_mqd(struct mqd_manager *mm, void *mqd, + * is safe, giving a maximum field value of 0xA. + */ + m->cp_hqd_eop_control = min(0xA, +- ffs(q->eop_ring_buffer_size / 4) - 1 - 1); ++ order_base_2(q->eop_ring_buffer_size / 4) - 1); + m->cp_hqd_eop_base_addr_lo = + lower_32_bits(q->eop_ring_buffer_address >> 8); + m->cp_hqd_eop_base_addr_hi = +@@ -401,7 +401,7 @@ static int update_mqd_sdma(struct mqd_manager *mm, void *mqd, + struct v9_sdma_mqd *m; + + m = get_sdma_mqd(mqd); +- m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / 4) - 1) ++ m->sdmax_rlcx_rb_cntl = order_base_2(q->queue_size / 4) + << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | + q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT | + 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | +diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c +index 2e6fc62..f4b08ee 100644 +--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c ++++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c +@@ -209,7 +209,7 @@ static int __update_mqd(struct mqd_manager *mm, void *mqd, + m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT | + atc_bit << CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT | + mtype << CP_HQD_PQ_CONTROL__MTYPE__SHIFT; +- m->cp_hqd_pq_control |= ffs(q->queue_size / 4) - 1 - 1; ++ m->cp_hqd_pq_control |= order_base_2(q->queue_size / 4) - 1; + pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); + + m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); +@@ -241,7 +241,7 @@ static int __update_mqd(struct mqd_manager *mm, void *mqd, + * is safe, giving a maximum field value of 0xA. + */ + m->cp_hqd_eop_control |= min(0xA, +- ffs(q->eop_ring_buffer_size / 4) - 1 - 1); ++ order_base_2(q->eop_ring_buffer_size / 4) - 1); + m->cp_hqd_eop_base_addr_lo = + lower_32_bits(q->eop_ring_buffer_address >> 8); + m->cp_hqd_eop_base_addr_hi = +@@ -413,7 +413,7 @@ static int update_mqd_sdma(struct mqd_manager *mm, void *mqd, + struct vi_sdma_mqd *m; + + m = get_sdma_mqd(mqd); +- m->sdmax_rlcx_rb_cntl = (ffs(q->queue_size / 4) - 1) ++ m->sdmax_rlcx_rb_cntl = order_base_2(q->queue_size / 4) + << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT | + q->vmid << SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT | + 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | +-- +2.7.4 + |