diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2843-drm-amdgpu-Change-SOC15_REG_OFFSET-to-use-dynamic-re.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2843-drm-amdgpu-Change-SOC15_REG_OFFSET-to-use-dynamic-re.patch | 281 |
1 files changed, 281 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2843-drm-amdgpu-Change-SOC15_REG_OFFSET-to-use-dynamic-re.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2843-drm-amdgpu-Change-SOC15_REG_OFFSET-to-use-dynamic-re.patch new file mode 100644 index 00000000..9b2a99ce --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2843-drm-amdgpu-Change-SOC15_REG_OFFSET-to-use-dynamic-re.patch @@ -0,0 +1,281 @@ +From 0a6d410bd77e6e20bfce7c420f188c8a28d6cf70 Mon Sep 17 00:00:00 2001 +From: Shaoyun Liu <Shaoyun.Liu@amd.com> +Date: Wed, 29 Nov 2017 13:51:32 -0500 +Subject: [PATCH 2843/4131] drm/amdgpu: Change SOC15_REG_OFFSET to use dynamic + register offset + +Change-Id: Ibfeb782a67e07c4b0d24b1e1903f860735a307e6 +Acked-by: Christian Konig <christian.koenig@amd.com> +Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++++ + drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 9 +++++---- + drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 9 +++++---- + drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 2 ++ + drivers/gpu/drm/amd/amdgpu/soc15.c | 7 ++----- + drivers/gpu/drm/amd/amdgpu/soc15_common.h | 6 +----- + drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 13 +++++++++++++ + drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 14 ++++++++++++++ + 8 files changed, 46 insertions(+), 18 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +index 6bd5eb1..efe6d12 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -3591,6 +3591,8 @@ static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) + + static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) + { ++ struct amdgpu_device *adev = ring->adev; ++ + gfx_v9_0_write_data_to_reg(ring, 0, true, + SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); + } +@@ -3752,6 +3754,8 @@ static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring) + static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, + u64 seq, unsigned int flags) + { ++ struct amdgpu_device *adev = ring->adev; ++ + /* we only allocate 32bit for each seq wb address */ + BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); + +diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c +index fa0cf67..3ccd148 100644 +--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c +@@ -301,9 +301,10 @@ int psp_v10_0_cmd_submit(struct psp_context *psp, + } + + static int +-psp_v10_0_sram_map(unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, +- unsigned int *sram_data_reg_offset, +- enum AMDGPU_UCODE_ID ucode_id) ++psp_v10_0_sram_map(struct amdgpu_device *adev, ++ unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, ++ unsigned int *sram_data_reg_offset, ++ enum AMDGPU_UCODE_ID ucode_id) + { + int ret = 0; + +@@ -398,7 +399,7 @@ bool psp_v10_0_compare_sram_data(struct psp_context *psp, + uint32_t *ucode_mem = NULL; + struct amdgpu_device *adev = psp->adev; + +- err = psp_v10_0_sram_map(&fw_sram_reg_val, &fw_sram_addr_reg_offset, ++ err = psp_v10_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset, + &fw_sram_data_reg_offset, ucode_type); + if (err) + return false; +diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c +index e75a23d..0b22e58 100644 +--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c ++++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c +@@ -410,9 +410,10 @@ int psp_v3_1_cmd_submit(struct psp_context *psp, + } + + static int +-psp_v3_1_sram_map(unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, +- unsigned int *sram_data_reg_offset, +- enum AMDGPU_UCODE_ID ucode_id) ++psp_v3_1_sram_map(struct amdgpu_device *adev, ++ unsigned int *sram_offset, unsigned int *sram_addr_reg_offset, ++ unsigned int *sram_data_reg_offset, ++ enum AMDGPU_UCODE_ID ucode_id) + { + int ret = 0; + +@@ -507,7 +508,7 @@ bool psp_v3_1_compare_sram_data(struct psp_context *psp, + uint32_t *ucode_mem = NULL; + struct amdgpu_device *adev = psp->adev; + +- err = psp_v3_1_sram_map(&fw_sram_reg_val, &fw_sram_addr_reg_offset, ++ err = psp_v3_1_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset, + &fw_sram_data_reg_offset, ucode_type); + if (err) + return false; +diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +index 01007bb..a73e567 100644 +--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +@@ -385,6 +385,8 @@ static void sdma_v4_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) + + static void sdma_v4_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) + { ++ struct amdgpu_device *adev = ring->adev; ++ + amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) | + SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)); + amdgpu_ring_write(ring, SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE)); +diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c +index 5ce4308..e13a5c6 100644 +--- a/drivers/gpu/drm/amd/amdgpu/soc15.c ++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c +@@ -373,12 +373,9 @@ static uint32_t soc15_get_register_value(struct amdgpu_device *adev, + if (indexed) { + return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); + } else { +- switch (reg_offset) { +- case SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG): ++ if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG)) + return adev->gfx.config.gb_addr_config; +- default: +- return RREG32(reg_offset); +- } ++ return RREG32(reg_offset); + } + } + +diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h +index e2207c5..413951c 100644 +--- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h ++++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h +@@ -41,11 +41,7 @@ struct nbio_hdp_flush_reg { + + + /* Register Access Macros */ +-#define SOC15_REG_OFFSET(ip, inst, reg) (0 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG0 + reg : \ +- (1 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG1 + reg : \ +- (2 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG2 + reg : \ +- (3 == reg##_BASE_IDX ? ip##_BASE__INST##inst##_SEG3 + reg : \ +- (ip##_BASE__INST##inst##_SEG4 + reg))))) ++#define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + + #define WREG32_FIELD15(ip, idx, reg, field, val) \ + WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \ +diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +index dfaf9cb..b22adeb 100644 +--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +@@ -1086,6 +1086,8 @@ static void uvd_v7_0_stop(struct amdgpu_device *adev) + static void uvd_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, + unsigned flags) + { ++ struct amdgpu_device *adev = ring->adev; ++ + WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); + + amdgpu_ring_write(ring, +@@ -1123,6 +1125,7 @@ static void uvd_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq + static void uvd_v7_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, + u64 seq, unsigned flags) + { ++ + WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); + + amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE); +@@ -1141,6 +1144,8 @@ static void uvd_v7_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, + */ + static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) + { ++ struct amdgpu_device *adev = ring->adev; ++ + amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(NBIF, 0, + mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0)); + amdgpu_ring_write(ring, 0); +@@ -1155,6 +1160,8 @@ static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) + */ + static void uvd_v7_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) + { ++ struct amdgpu_device *adev = ring->adev; ++ + amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 0)); + amdgpu_ring_write(ring, 1); + } +@@ -1214,6 +1221,8 @@ static void uvd_v7_0_ring_emit_ib(struct amdgpu_ring *ring, + struct amdgpu_ib *ib, + unsigned vm_id, bool ctx_switch) + { ++ struct amdgpu_device *adev = ring->adev; ++ + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0)); + amdgpu_ring_write(ring, vm_id); +@@ -1250,6 +1259,8 @@ static void uvd_v7_0_enc_ring_emit_ib(struct amdgpu_ring *ring, + static void uvd_v7_0_vm_reg_write(struct amdgpu_ring *ring, + uint32_t data0, uint32_t data1) + { ++ struct amdgpu_device *adev = ring->adev; ++ + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); + amdgpu_ring_write(ring, data0); +@@ -1264,6 +1275,8 @@ static void uvd_v7_0_vm_reg_write(struct amdgpu_ring *ring, + static void uvd_v7_0_vm_reg_wait(struct amdgpu_ring *ring, + uint32_t data0, uint32_t data1, uint32_t mask) + { ++ struct amdgpu_device *adev = ring->adev; ++ + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); + amdgpu_ring_write(ring, data0); +diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +index f2ce3e6..29e3f78 100644 +--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +@@ -766,6 +766,8 @@ static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring) + */ + static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring) + { ++ struct amdgpu_device *adev = ring->adev; ++ + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); + amdgpu_ring_write(ring, 0); +@@ -783,6 +785,8 @@ static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring) + */ + static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring) + { ++ struct amdgpu_device *adev = ring->adev; ++ + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); + amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1); +@@ -799,6 +803,8 @@ static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring) + static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, + unsigned flags) + { ++ struct amdgpu_device *adev = ring->adev; ++ + WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); + + amdgpu_ring_write(ring, +@@ -834,6 +840,8 @@ static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 + */ + static void vcn_v1_0_dec_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) + { ++ struct amdgpu_device *adev = ring->adev; ++ + amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 0)); + amdgpu_ring_write(ring, 1); + } +@@ -850,6 +858,8 @@ static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring, + struct amdgpu_ib *ib, + unsigned vm_id, bool ctx_switch) + { ++ struct amdgpu_device *adev = ring->adev; ++ + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0)); + amdgpu_ring_write(ring, vm_id); +@@ -868,6 +878,8 @@ static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring, + static void vcn_v1_0_dec_vm_reg_write(struct amdgpu_ring *ring, + uint32_t data0, uint32_t data1) + { ++ struct amdgpu_device *adev = ring->adev; ++ + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); + amdgpu_ring_write(ring, data0); +@@ -882,6 +894,8 @@ static void vcn_v1_0_dec_vm_reg_write(struct amdgpu_ring *ring, + static void vcn_v1_0_dec_vm_reg_wait(struct amdgpu_ring *ring, + uint32_t data0, uint32_t data1, uint32_t mask) + { ++ struct amdgpu_device *adev = ring->adev; ++ + amdgpu_ring_write(ring, + PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); + amdgpu_ring_write(ring, data0); +-- +2.7.4 + |