diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2840-drm-amdgpu-Dynamic-initialize-IP-base-offset.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2840-drm-amdgpu-Dynamic-initialize-IP-base-offset.patch | 172 |
1 files changed, 172 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2840-drm-amdgpu-Dynamic-initialize-IP-base-offset.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2840-drm-amdgpu-Dynamic-initialize-IP-base-offset.patch new file mode 100644 index 00000000..b441bdf4 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2840-drm-amdgpu-Dynamic-initialize-IP-base-offset.patch @@ -0,0 +1,172 @@ +From 6793c26a24bafa70066fafafb8cefda340e2f731 Mon Sep 17 00:00:00 2001 +From: Shaoyun Liu <Shaoyun.Liu@amd.com> +Date: Mon, 27 Nov 2017 13:16:35 -0500 +Subject: [PATCH 2840/4131] drm/amdgpu: Dynamic initialize IP base offset + +Change-Id: I84217de7c188f8886383500da3c91e488086586b +Acked-by: Christian Konig <christian.koenig@amd.com> +Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- + drivers/gpu/drm/amd/amdgpu/amdgpu.h | 27 ++++++++++++++ + drivers/gpu/drm/amd/amdgpu/soc15.c | 10 +++++ + drivers/gpu/drm/amd/amdgpu/soc15.h | 2 + + drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c | 56 ++++++++++++++++++++++++++++ + 5 files changed, 96 insertions(+), 1 deletion(-) + create mode 100644 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c + +diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile +index dd784de..cc5aef2 100755 +--- a/drivers/gpu/drm/amd/amdgpu/Makefile ++++ b/drivers/gpu/drm/amd/amdgpu/Makefile +@@ -41,7 +41,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \ + amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce_v6_0.o si_dpm.o si_smc.o + + amdgpu-y += \ +- vi.o mxgpu_vi.o nbio_v6_1.o soc15.o mxgpu_ai.o nbio_v7_0.o ++ vi.o mxgpu_vi.o nbio_v6_1.o soc15.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o + + # add GMC block + amdgpu-y += \ +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +index 092d637..09fa95e 100755 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +@@ -1493,6 +1493,30 @@ struct amdgpu_ssg { + #endif + }; + ++/* Define the HW IP blocks will be used in driver , add more if necessary */ ++enum amd_hw_ip_block_type { ++ GC_HWIP = 1, ++ HDP_HWIP, ++ SDMA0_HWIP, ++ SDMA1_HWIP, ++ MMHUB_HWIP, ++ ATHUB_HWIP, ++ NBIO_HWIP, ++ MP0_HWIP, ++ UVD_HWIP, ++ VCN_HWIP = UVD_HWIP, ++ VCE_HWIP, ++ DF_HWIP, ++ DCE_HWIP, ++ OSSSYS_HWIP, ++ SMUIO_HWIP, ++ PWR_HWIP, ++ NBIF_HWIP, ++ MAX_HWIP ++}; ++ ++#define HWIP_MAX_INSTANCE 6 ++ + struct amd_powerplay { + struct cgs_device *cgs_device; + void *pp_handle; +@@ -1689,6 +1713,9 @@ struct amdgpu_device { + /* amdkfd interface */ + struct kfd_dev *kfd; + ++ /* soc15 register offset based on ip, instance and segment */ ++ uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; ++ + /* delayed work_func for deferring clockgating during resume */ + struct delayed_work late_init_work; + +diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c +index 5ccac91..af2eaf6 100644 +--- a/drivers/gpu/drm/amd/amdgpu/soc15.c ++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c +@@ -516,6 +516,16 @@ static const struct amdgpu_ip_block_version vega10_common_ip_block = + + int soc15_set_ip_blocks(struct amdgpu_device *adev) + { ++ /* Set IP register base before any HW register access */ ++ switch (adev->asic_type) { ++ case CHIP_VEGA10: ++ case CHIP_RAVEN: ++ vega10_reg_base_init(adev); ++ break; ++ default: ++ return -EINVAL; ++ } ++ + nbio_v6_1_detect_hw_virt(adev); + + if (amdgpu_sriov_vf(adev)) +diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h +index acb3cdb..c34496f 100644 +--- a/drivers/gpu/drm/amd/amdgpu/soc15.h ++++ b/drivers/gpu/drm/amd/amdgpu/soc15.h +@@ -33,4 +33,6 @@ void soc15_grbm_select(struct amdgpu_device *adev, + u32 me, u32 pipe, u32 queue, u32 vmid); + int soc15_set_ip_blocks(struct amdgpu_device *adev); + ++int vega10_reg_base_init(struct amdgpu_device *adev); ++ + #endif +diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c +new file mode 100644 +index 0000000..b7bdd04 +--- /dev/null ++++ b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c +@@ -0,0 +1,56 @@ ++/* ++ * Copyright 2017 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR ++ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ * ++ */ ++#include "amdgpu.h" ++#include "soc15.h" ++ ++#include "soc15_common.h" ++#include "soc15ip.h" ++ ++int vega10_reg_base_init(struct amdgpu_device *adev) ++{ ++ /* HW has more IP blocks, only initialized the blocke beend by our driver */ ++ uint32_t i; ++ for (i = 0 ; i < MAX_INSTANCE ; ++i) { ++ adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); ++ adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); ++ adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); ++ adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i])); ++ adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); ++ adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); ++ adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); ++ adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i])); ++ adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i])); ++ adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); ++ adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCE_BASE.instance[i])); ++ adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); ++ adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i])); ++ adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i])); ++ adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i])); ++ adev->reg_offset[PWR_HWIP][i] = (uint32_t *)(&(PWR_BASE.instance[i])); ++ adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIF_BASE.instance[i])); ++ ++ } ++ return 0; ++} ++ ++ +-- +2.7.4 + |