diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2806-drm-amd-display-fix-AZ-clock-not-enabled-before-prog.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2806-drm-amd-display-fix-AZ-clock-not-enabled-before-prog.patch | 101 |
1 files changed, 101 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2806-drm-amd-display-fix-AZ-clock-not-enabled-before-prog.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2806-drm-amd-display-fix-AZ-clock-not-enabled-before-prog.patch new file mode 100644 index 00000000..a2c00130 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2806-drm-amd-display-fix-AZ-clock-not-enabled-before-prog.patch @@ -0,0 +1,101 @@ +From a787efcd7c6878c0ce87c2dbaa29bcf5220f3f6b Mon Sep 17 00:00:00 2001 +From: Charlene Liu <charlene.liu@amd.com> +Date: Wed, 25 Oct 2017 14:12:51 -0400 +Subject: [PATCH 2806/4131] drm/amd/display: fix AZ clock not enabled before + program AZ endpoint + +Signed-off-by: Charlene Liu <charlene.liu@amd.com> +Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> +Acked-by: Harry Wentland <harry.wentland@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dce/dce_audio.c | 31 ++++++++++++++++++++++++-- + 1 file changed, 29 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c +index d882adf..81c40f8 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c +@@ -348,29 +348,44 @@ static void set_audio_latency( + + void dce_aud_az_enable(struct audio *audio) + { ++ struct dce_audio *aud = DCE_AUD(audio); + uint32_t value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); + +- if (get_reg_field_value(value, ++ set_reg_field_value(value, 1, + AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, +- AUDIO_ENABLED) != 1) ++ CLOCK_GATING_DISABLE); + set_reg_field_value(value, 1, + AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, + AUDIO_ENABLED); + + AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); ++ value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); ++ ++ dm_logger_write(CTX->logger, LOG_HW_AUDIO, ++ "\n\t========= AUDIO:dce_aud_az_enable: index: %u data: 0x%x\n", ++ audio->inst, value); + } + + void dce_aud_az_disable(struct audio *audio) + { + uint32_t value; ++ struct dce_audio *aud = DCE_AUD(audio); + + value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); + + set_reg_field_value(value, 0, + AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, + AUDIO_ENABLED); ++ AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); + ++ set_reg_field_value(value, 0, ++ AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, ++ CLOCK_GATING_DISABLE); + AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); ++ value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); ++ dm_logger_write(CTX->logger, LOG_HW_AUDIO, ++ "\n\t========= AUDIO:dce_aud_az_disable: index: %u data: 0x%x\n", ++ audio->inst, value); + } + + void dce_aud_az_configure( +@@ -390,6 +405,11 @@ void dce_aud_az_configure( + bool is_ac3_supported = false; + union audio_sample_rates sample_rate; + uint32_t strlen = 0; ++ value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); ++ set_reg_field_value(value, 1, ++ AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, ++ CLOCK_GATING_DISABLE); ++ AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); + + /* Speaker Allocation */ + /* +@@ -852,6 +872,7 @@ static bool dce_aud_endpoint_valid(struct audio *audio) + void dce_aud_hw_init( + struct audio *audio) + { ++ uint32_t value; + struct dce_audio *aud = DCE_AUD(audio); + + /* we only need to program the following registers once, so we only do +@@ -863,6 +884,12 @@ void dce_aud_hw_init( + * Suport R6 - 44.1khz + * Suport R7 - 48khz + */ ++ /*disable clock gating before write to endpoint register*/ ++ value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); ++ set_reg_field_value(value, 1, ++ AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, ++ CLOCK_GATING_DISABLE); ++ AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); + REG_UPDATE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, + AUDIO_RATE_CAPABILITIES, 0x70); + +-- +2.7.4 + |