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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2794-drm-amdgpu-unify-VM-size-handling-of-Vega10-with-old.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2794-drm-amdgpu-unify-VM-size-handling-of-Vega10-with-old.patch212
1 files changed, 212 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2794-drm-amdgpu-unify-VM-size-handling-of-Vega10-with-old.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2794-drm-amdgpu-unify-VM-size-handling-of-Vega10-with-old.patch
new file mode 100644
index 00000000..2fdba1f3
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2794-drm-amdgpu-unify-VM-size-handling-of-Vega10-with-old.patch
@@ -0,0 +1,212 @@
+From e873e0a83c710169c651cbccdb43585f455b534b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Christian=20K=C3=B6nig?= <christian.koenig@amd.com>
+Date: Wed, 22 Nov 2017 17:00:35 +0100
+Subject: [PATCH 2794/4131] drm/amdgpu: unify VM size handling of Vega10 with
+ older generation
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+One function to rule them all.
+
+Signed-off-by: Christian König <christian.koenig@amd.com>
+Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 34 +++++++++++++---------------------
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 4 +---
+ drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 3 +--
+ drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 3 +--
+ drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 3 +--
+ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 22 +++++-----------------
+ 6 files changed, 22 insertions(+), 47 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+index 1386998..a58937b 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+@@ -2611,43 +2611,35 @@ static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
+ }
+
+ /**
+- * amdgpu_vm_set_fragment_size - adjust fragment size in PTE
+- *
+- * @adev: amdgpu_device pointer
+- * @fragment_size_default: the default fragment size if it's set auto
+- */
+-void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev,
+- uint32_t fragment_size_default)
+-{
+- if (amdgpu_vm_fragment_size == -1)
+- adev->vm_manager.fragment_size = fragment_size_default;
+- else
+- adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
+-}
+-
+-/**
+ * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
+ *
+ * @adev: amdgpu_device pointer
+ * @vm_size: the default vm size if it's set auto
+ */
+ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
+- uint32_t fragment_size_default)
++ uint32_t fragment_size_default, unsigned max_level)
+ {
+- /* adjust vm size firstly */
+- if (amdgpu_vm_size != -1)
++ /* adjust vm size first, but only for two level setups for now */
++ if (amdgpu_vm_size != -1 && max_level == 1)
+ vm_size = amdgpu_vm_size;
+
+ adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
++ adev->vm_manager.num_level = max_level;
+
+- /* block size depends on vm size */
+- if (amdgpu_vm_block_size == -1)
++ /* block size depends on vm size and hw setup*/
++ if (adev->vm_manager.num_level > 1)
++ /* Use fixed block_size for multi level page tables */
++ adev->vm_manager.block_size = 9;
++ else if (amdgpu_vm_block_size == -1)
+ adev->vm_manager.block_size =
+ amdgpu_vm_get_block_size(vm_size);
+ else
+ adev->vm_manager.block_size = amdgpu_vm_block_size;
+
+- amdgpu_vm_set_fragment_size(adev, fragment_size_default);
++ if (amdgpu_vm_fragment_size == -1)
++ adev->vm_manager.fragment_size = fragment_size_default;
++ else
++ adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
+
+ DRM_INFO("vm size is %u GB, block size is %u-bit, fragment size is %u-bit\n",
+ vm_size, adev->vm_manager.block_size,
+diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+index 2f9eb95..7ad0b30 100644
+--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+@@ -329,10 +329,8 @@ struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
+ uint64_t addr);
+ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
+ struct amdgpu_bo_va *bo_va);
+-void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev,
+- uint32_t fragment_size_default);
+ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
+- uint32_t fragment_size_default);
++ uint32_t fragment_size_default, unsigned max_level);
+ int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
+ bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
+ struct amdgpu_job *job);
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+index 3d4adc4..5f5a593 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+@@ -826,7 +826,7 @@ static int gmc_v6_0_sw_init(void *handle)
+ if (r)
+ return r;
+
+- amdgpu_vm_adjust_size(adev, 64, 9);
++ amdgpu_vm_adjust_size(adev, 64, 9, 1);
+
+ adev->mc.mc_mask = 0xffffffffffULL;
+
+@@ -871,7 +871,6 @@ static int gmc_v6_0_sw_init(void *handle)
+ * amdkfd will use VMIDs 8-15
+ */
+ adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
+- adev->vm_manager.num_level = 1;
+ amdgpu_vm_manager_init(adev);
+
+ /* base offset of vram pages */
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+index 0b6f387..810f484 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+@@ -967,7 +967,7 @@ static int gmc_v7_0_sw_init(void *handle)
+ * Currently set to 4GB ((1 << 20) 4k pages).
+ * Max GPUVM size for cayman and SI is 40 bits.
+ */
+- amdgpu_vm_adjust_size(adev, 64, 9);
++ amdgpu_vm_adjust_size(adev, 64, 9, 1);
+
+ /* Set the internal MC address mask
+ * This is the max address of the GPU's
+@@ -1022,7 +1022,6 @@ static int gmc_v7_0_sw_init(void *handle)
+ * amdkfd will use VMIDs 8-15
+ */
+ adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
+- adev->vm_manager.num_level = 1;
+ amdgpu_vm_manager_init(adev);
+
+ /* base offset of vram pages */
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+index 21e81aa..4c7e517 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+@@ -1068,7 +1068,7 @@ static int gmc_v8_0_sw_init(void *handle)
+ * Currently set to 4GB ((1 << 20) 4k pages).
+ * Max GPUVM size for cayman and SI is 40 bits.
+ */
+- amdgpu_vm_adjust_size(adev, 64, 9);
++ amdgpu_vm_adjust_size(adev, 64, 9, 1);
+
+ /* Set the internal MC address mask
+ * This is the max address of the GPU's
+@@ -1123,7 +1123,6 @@ static int gmc_v8_0_sw_init(void *handle)
+ * amdkfd will use VMIDs 8-15
+ */
+ adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
+- adev->vm_manager.num_level = 1;
+ amdgpu_vm_manager_init(adev);
+
+ /* base offset of vram pages */
+diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+index 09e3c22..57e71c6 100644
+--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+@@ -766,16 +766,11 @@ static int gmc_v9_0_sw_init(void *handle)
+ switch (adev->asic_type) {
+ case CHIP_RAVEN:
+ adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
+- if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
+- adev->vm_manager.max_pfn = 1ULL << 36;
+- adev->vm_manager.block_size = 9;
+- adev->vm_manager.num_level = 3;
+- amdgpu_vm_set_fragment_size(adev, 9);
+- } else {
++ if (adev->rev_id == 0x0 || adev->rev_id == 0x1)
++ amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3);
++ else
+ /* vm_size is 64GB for legacy 2-level page support */
+- amdgpu_vm_adjust_size(adev, 64, 9);
+- adev->vm_manager.num_level = 1;
+- }
++ amdgpu_vm_adjust_size(adev, 64, 9, 1);
+ break;
+ case CHIP_VEGA10:
+ /* XXX Don't know how to get VRAM type yet. */
+@@ -785,19 +780,12 @@ static int gmc_v9_0_sw_init(void *handle)
+ * vm size is 256TB (48bit), maximum size of Vega10,
+ * block size 512 (9bit)
+ */
+- adev->vm_manager.max_pfn = 1ULL << 36;
+- adev->vm_manager.block_size = 9;
+- adev->vm_manager.num_level = 3;
+- amdgpu_vm_set_fragment_size(adev, 9);
++ amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3);
+ break;
+ default:
+ break;
+ }
+
+- DRM_INFO("vm size is %llu GB, block size is %u-bit, fragment size is %u-bit\n",
+- adev->vm_manager.max_pfn >> 18, adev->vm_manager.block_size,
+- adev->vm_manager.fragment_size);
+-
+ /* This interrupt is VMC page fault.*/
+ r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0,
+ &adev->mc.vm_fault);
+--
+2.7.4
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-05-01 03:48:59 +0000