diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2791-drm-amdgpu-correct-vce4.0-fw-config-for-SRIOV-V2.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2791-drm-amdgpu-correct-vce4.0-fw-config-for-SRIOV-V2.patch | 91 |
1 files changed, 91 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2791-drm-amdgpu-correct-vce4.0-fw-config-for-SRIOV-V2.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2791-drm-amdgpu-correct-vce4.0-fw-config-for-SRIOV-V2.patch new file mode 100644 index 00000000..19f08da0 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2791-drm-amdgpu-correct-vce4.0-fw-config-for-SRIOV-V2.patch @@ -0,0 +1,91 @@ +From 4bf2f95b03d7199870158a38445d68fc490199a3 Mon Sep 17 00:00:00 2001 +From: Frank Min <Frank.Min@amd.com> +Date: Mon, 6 Nov 2017 15:34:55 +0800 +Subject: [PATCH 2791/4131] drm/amdgpu: correct vce4.0 fw config for SRIOV (V2) +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +1. program vce 4.0 fw with 48 bit address +2. correct vce 4.0 fw stack and date offset + +Acked-by: Christian König <christian.koenig@amd.com> +Signed-off-by: Frank Min <Frank.Min@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 38 +++++++++++++++++++++++------------ + 1 file changed, 25 insertions(+), 13 deletions(-) + mode change 100644 => 100755 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c + +diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +old mode 100644 +new mode 100755 +index d06bafe..f2f7136 +--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +@@ -243,37 +243,49 @@ static int vce_v4_0_sriov_start(struct amdgpu_device *adev) + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VM_CTRL), 0); + + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { +- MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0), +- adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8); +- MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR1), +- adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8); +- MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR2), ++ MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, ++ mmVCE_LMI_VCPU_CACHE_40BIT_BAR0), + adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 8); ++ MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, ++ mmVCE_LMI_VCPU_CACHE_64BIT_BAR0), ++ (adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].mc_addr >> 40) & 0xff); + } else { +- MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR0), ++ MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, ++ mmVCE_LMI_VCPU_CACHE_40BIT_BAR0), + adev->vce.gpu_addr >> 8); +- MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR1), ++ MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, ++ mmVCE_LMI_VCPU_CACHE_64BIT_BAR0), ++ (adev->vce.gpu_addr >> 40) & 0xff); ++ } ++ MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, ++ mmVCE_LMI_VCPU_CACHE_40BIT_BAR1), + adev->vce.gpu_addr >> 8); +- MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR2), ++ MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, ++ mmVCE_LMI_VCPU_CACHE_64BIT_BAR1), ++ (adev->vce.gpu_addr >> 40) & 0xff); ++ MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, ++ mmVCE_LMI_VCPU_CACHE_40BIT_BAR2), + adev->vce.gpu_addr >> 8); +- } ++ MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, ++ mmVCE_LMI_VCPU_CACHE_64BIT_BAR2), ++ (adev->vce.gpu_addr >> 40) & 0xff); + + offset = AMDGPU_VCE_FIRMWARE_OFFSET; + size = VCE_V4_0_FW_SIZE; + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET0), +- offset & 0x7FFFFFFF); ++ offset & ~0x0f000000); + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE0), size); + +- offset += size; ++ offset = (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) ? offset + size : 0; + size = VCE_V4_0_STACK_SIZE; + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET1), +- offset & 0x7FFFFFFF); ++ (offset & ~0x0f000000) | (1 << 24)); + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE1), size); + + offset += size; + size = VCE_V4_0_DATA_SIZE; + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET2), +- offset & 0x7FFFFFFF); ++ (offset & ~0x0f000000) | (2 << 24)); + MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE2), size); + + MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL2), ~0x100, 0); +-- +2.7.4 + |