diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2786-drm-amd-display-DMCU-and-ABM-maintenance-and-refacto.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2786-drm-amd-display-DMCU-and-ABM-maintenance-and-refacto.patch | 215 |
1 files changed, 215 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2786-drm-amd-display-DMCU-and-ABM-maintenance-and-refacto.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2786-drm-amd-display-DMCU-and-ABM-maintenance-and-refacto.patch new file mode 100644 index 00000000..671d05b2 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2786-drm-amd-display-DMCU-and-ABM-maintenance-and-refacto.patch @@ -0,0 +1,215 @@ +From 1ee2e6e6856000e003c523bbc6fe5dea27fba9bd Mon Sep 17 00:00:00 2001 +From: Anthony Koo <Anthony.Koo@amd.com> +Date: Mon, 13 Nov 2017 10:54:59 -0500 +Subject: [PATCH 2786/4131] drm/amd/display: DMCU and ABM maintenance and + refactor + +Remove some globals that should really be per block state. + +Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Harry Wentland <harry.wentland@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dce/dce_abm.c | 32 +++++++++++---------------- + drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 18 ++++++++------- + drivers/gpu/drm/amd/display/dc/inc/hw/abm.h | 10 +++++++++ + drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h | 4 +++- + 4 files changed, 36 insertions(+), 28 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c +index 0e0336c..3fe8e69 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c +@@ -51,16 +51,6 @@ + + #define MCP_DISABLE_ABM_IMMEDIATELY 255 + +-struct abm_backlight_registers { +- unsigned int BL_PWM_CNTL; +- unsigned int BL_PWM_CNTL2; +- unsigned int BL_PWM_PERIOD_CNTL; +- unsigned int LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV; +-}; +- +-/* registers setting needs to be save and restored used at InitBacklight */ +-static struct abm_backlight_registers stored_backlight_registers = {0}; +- + + static unsigned int get_current_backlight_16_bit(struct dce_abm *abm_dce) + { +@@ -347,16 +337,16 @@ static bool dce_abm_init_backlight(struct abm *abm) + */ + REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value); + if (value == 0 || value == 1) { +- if (stored_backlight_registers.BL_PWM_CNTL != 0) { ++ if (abm->stored_backlight_registers.BL_PWM_CNTL != 0) { + REG_WRITE(BL_PWM_CNTL, +- stored_backlight_registers.BL_PWM_CNTL); ++ abm->stored_backlight_registers.BL_PWM_CNTL); + REG_WRITE(BL_PWM_CNTL2, +- stored_backlight_registers.BL_PWM_CNTL2); ++ abm->stored_backlight_registers.BL_PWM_CNTL2); + REG_WRITE(BL_PWM_PERIOD_CNTL, +- stored_backlight_registers.BL_PWM_PERIOD_CNTL); ++ abm->stored_backlight_registers.BL_PWM_PERIOD_CNTL); + REG_UPDATE(LVTMA_PWRSEQ_REF_DIV, + BL_PWM_REF_DIV, +- stored_backlight_registers. ++ abm->stored_backlight_registers. + LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV); + } else { + /* TODO: Note: This should not really happen since VBIOS +@@ -366,15 +356,15 @@ static bool dce_abm_init_backlight(struct abm *abm) + REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0); + } + } else { +- stored_backlight_registers.BL_PWM_CNTL = ++ abm->stored_backlight_registers.BL_PWM_CNTL = + REG_READ(BL_PWM_CNTL); +- stored_backlight_registers.BL_PWM_CNTL2 = ++ abm->stored_backlight_registers.BL_PWM_CNTL2 = + REG_READ(BL_PWM_CNTL2); +- stored_backlight_registers.BL_PWM_PERIOD_CNTL = ++ abm->stored_backlight_registers.BL_PWM_PERIOD_CNTL = + REG_READ(BL_PWM_PERIOD_CNTL); + + REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, +- &stored_backlight_registers. ++ &abm->stored_backlight_registers. + LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV); + } + +@@ -450,6 +440,10 @@ static void dce_abm_construct( + + base->ctx = ctx; + base->funcs = &dce_funcs; ++ base->stored_backlight_registers.BL_PWM_CNTL = 0; ++ base->stored_backlight_registers.BL_PWM_CNTL2 = 0; ++ base->stored_backlight_registers.BL_PWM_PERIOD_CNTL = 0; ++ base->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV = 0; + + abm_dce->regs = regs; + abm_dce->abm_shift = abm_shift; +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c +index 508c1aa..a6de99d 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c +@@ -53,7 +53,6 @@ + #define MCP_INIT_IRAM 0x89 + #define MCP_DMCU_VERSION 0x90 + #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L +-unsigned int cached_wait_loop_number = 0; + + static bool dce_dmcu_init(struct dmcu *dmcu) + { +@@ -270,7 +269,7 @@ static void dce_psr_wait_loop( + { + struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); + union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1; +- if (cached_wait_loop_number == wait_loop_number) ++ if (dmcu->cached_wait_loop_number == wait_loop_number) + return; + + /* waitDMCUReadyForCmd */ +@@ -278,7 +277,7 @@ static void dce_psr_wait_loop( + + masterCmdData1.u32 = 0; + masterCmdData1.bits.wait_loop = wait_loop_number; +- cached_wait_loop_number = wait_loop_number; ++ dmcu->cached_wait_loop_number = wait_loop_number; + dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); + + /* setDMCUParam_Cmd */ +@@ -288,9 +287,10 @@ static void dce_psr_wait_loop( + REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); + } + +-static void dce_get_psr_wait_loop(unsigned int *psr_wait_loop_number) ++static void dce_get_psr_wait_loop( ++ struct dmcu *dmcu, unsigned int *psr_wait_loop_number) + { +- *psr_wait_loop_number = cached_wait_loop_number; ++ *psr_wait_loop_number = dmcu->cached_wait_loop_number; + return; + } + +@@ -673,7 +673,7 @@ static void dcn10_psr_wait_loop( + + masterCmdData1.u32 = 0; + masterCmdData1.bits.wait_loop = wait_loop_number; +- cached_wait_loop_number = wait_loop_number; ++ dmcu->cached_wait_loop_number = wait_loop_number; + dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); + + /* setDMCUParam_Cmd */ +@@ -684,9 +684,10 @@ static void dcn10_psr_wait_loop( + } + } + +-static void dcn10_get_psr_wait_loop(unsigned int *psr_wait_loop_number) ++static void dcn10_get_psr_wait_loop( ++ struct dmcu *dmcu, unsigned int *psr_wait_loop_number) + { +- *psr_wait_loop_number = cached_wait_loop_number; ++ *psr_wait_loop_number = dmcu->cached_wait_loop_number; + return; + } + +@@ -725,6 +726,7 @@ static void dce_dmcu_construct( + + base->ctx = ctx; + base->funcs = &dce_funcs; ++ base->cached_wait_loop_number = 0; + + dmcu_dce->regs = regs; + dmcu_dce->dmcu_shift = dmcu_shift; +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h b/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h +index c93b9b9..48217ec 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/abm.h +@@ -27,9 +27,19 @@ + + #include "dm_services_types.h" + ++struct abm_backlight_registers { ++ unsigned int BL_PWM_CNTL; ++ unsigned int BL_PWM_CNTL2; ++ unsigned int BL_PWM_PERIOD_CNTL; ++ unsigned int LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV; ++}; ++ + struct abm { + struct dc_context *ctx; + const struct abm_funcs *funcs; ++ ++ /* registers setting needs to be saved and restored at InitBacklight */ ++ struct abm_backlight_registers stored_backlight_registers; + }; + + struct abm_funcs { +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h +index 67996c6..b59712b 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h +@@ -45,6 +45,7 @@ struct dmcu { + + enum dmcu_state dmcu_state; + struct dmcu_version dmcu_version; ++ unsigned int cached_wait_loop_number; + }; + + struct dmcu_funcs { +@@ -60,7 +61,8 @@ struct dmcu_funcs { + void (*get_psr_state)(struct dmcu *dmcu, uint32_t *psr_state); + void (*set_psr_wait_loop)(struct dmcu *dmcu, + unsigned int wait_loop_number); +- void (*get_psr_wait_loop)(unsigned int *psr_wait_loop_number); ++ void (*get_psr_wait_loop)(struct dmcu *dmcu, ++ unsigned int *psr_wait_loop_number); + }; + + #endif +-- +2.7.4 + |