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-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2746-drm-amd-display-Change-frontend-backend-programming-.patch95
1 files changed, 95 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2746-drm-amd-display-Change-frontend-backend-programming-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2746-drm-amd-display-Change-frontend-backend-programming-.patch
new file mode 100644
index 00000000..6e5f1ddd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2746-drm-amd-display-Change-frontend-backend-programming-.patch
@@ -0,0 +1,95 @@
+From e41ce37f330c2404937c811360d325c0fb3fb640 Mon Sep 17 00:00:00 2001
+From: "Leo (Sunpeng) Li" <sunpeng.li@amd.com>
+Date: Tue, 7 Nov 2017 13:51:02 -0500
+Subject: [PATCH 2746/4131] drm/amd/display: Change frontend/backend
+ programming sequence
+
+This is a follow-up to the following change:
+
+Yongqiang Sun: Program front end first when set mode.
+
+Due to pipe-splitting features, how we handle stream enabling and
+disabling needs to change.
+
+In the case of pipe split disable, two planes need to be combined back
+into the same stream. This needs to be done before any stream
+programming happens.
+
+The previous patch addresses this, but breaks cross-platform
+compatibility. It's not guaranteed that a dc commit will be called
+separately to program planes and streams.
+
+Therefore, we handle the combined commit case by doing plane programming
+both before and after stream programming, to handle pipe split disable
+and plane enable respectively.
+
+Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
+Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
+Acked-by: Harry Wentland <harry.wentland@amd.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/display/dc/core/dc.c | 41 ++++++++++++++++++++++----------
+ 1 file changed, 28 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
+index 0b4c288..9a30dc0 100644
+--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
+@@ -839,6 +839,33 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
+ if (!dcb->funcs->is_accelerated_mode(dcb))
+ dc->hwss.enable_accelerated_mode(dc);
+
++ /* Combine planes if required, in case of pipe split disable */
++ for (i = 0; i < dc->current_state->stream_count; i++) {
++ dc->hwss.apply_ctx_for_surface(
++ dc, dc->current_state->streams[i],
++ dc->current_state->stream_status[i].plane_count,
++ dc->current_state);
++ }
++
++ /* Program hardware */
++ dc->hwss.ready_shared_resources(dc, context);
++
++ for (i = 0; i < dc->res_pool->pipe_count; i++) {
++ pipe = &context->res_ctx.pipe_ctx[i];
++ dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
++ }
++
++ result = dc->hwss.apply_ctx_to_hw(dc, context);
++
++ if (result != DC_OK)
++ goto fail;
++
++ if (context->stream_count > 1) {
++ enable_timing_multisync(dc, context);
++ program_timing_sync(dc, context);
++ }
++
++ /* Program all planes within new context*/
+ for (i = 0; i < context->stream_count; i++) {
+ const struct dc_sink *sink = context->streams[i]->sink;
+
+@@ -872,19 +899,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
+ context->streams[i]->timing.pix_clk_khz);
+ }
+
+- dc->hwss.ready_shared_resources(dc, context);
+-
+- for (i = 0; i < dc->res_pool->pipe_count; i++) {
+- pipe = &context->res_ctx.pipe_ctx[i];
+- dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe);
+- }
+- result = dc->hwss.apply_ctx_to_hw(dc, context);
+-
+- if (context->stream_count > 1) {
+- enable_timing_multisync(dc, context);
+- program_timing_sync(dc, context);
+- }
+-
++fail:
+ dc_enable_stereo(dc, context, dc_streams, context->stream_count);
+
+ dc_release_state(dc->current_state);
+--
+2.7.4
+