diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2699-drm-amd-display-function-renaming-for-hubbub.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2699-drm-amd-display-function-renaming-for-hubbub.patch | 315 |
1 files changed, 315 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2699-drm-amd-display-function-renaming-for-hubbub.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2699-drm-amd-display-function-renaming-for-hubbub.patch new file mode 100644 index 00000000..cdf92fa7 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2699-drm-amd-display-function-renaming-for-hubbub.patch @@ -0,0 +1,315 @@ +From 379e3f9fb241881cbceabea45dca79379f74cca4 Mon Sep 17 00:00:00 2001 +From: Yue Hin Lau <Yuehin.Lau@amd.com> +Date: Tue, 24 Oct 2017 15:16:38 -0400 +Subject: [PATCH 2699/4131] drm/amd/display: function renaming for hubbub + +following the naming convention with correct prefix + +Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Harry Wentland <harry.wentland@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + .../gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c | 16 +++---- + .../gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h | 9 ++-- + .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 55 +++++++++++++--------- + 3 files changed, 43 insertions(+), 37 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c +index f60e90c..b1c9ba2 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c +@@ -75,7 +75,7 @@ void hubbub1_wm_read_state(struct hubbub *hubbub, + s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D); + } + +-void verify_allow_pstate_change_high( ++bool hubbub1_verify_allow_pstate_change_high( + struct hubbub *hubbub) + { + /* pstate latency is ~20us so if we wait over 40us and pstate allow +@@ -89,7 +89,6 @@ void verify_allow_pstate_change_high( + static unsigned int pstate_wait_expected_timeout_us = 40; + static unsigned int max_sampled_pstate_wait_us; /* data collection */ + static bool forced_pstate_allow; /* help with revert wa */ +- static bool should_log_hw_state; /* prevent hw state log by default */ + + unsigned int debug_index = 0x7; + unsigned int debug_data; +@@ -140,7 +139,7 @@ void verify_allow_pstate_change_high( + "pstate took longer than expected ~%dus\n", + i); + +- return; ++ return false; + } + if (max_sampled_pstate_wait_us < i) + max_sampled_pstate_wait_us = i; +@@ -156,14 +155,11 @@ void verify_allow_pstate_change_high( + DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, 1); + forced_pstate_allow = true; + +- if (should_log_hw_state) { +- dcn10_log_hw_state(hubbub->ctx->dc); +- } +- + dm_logger_write(hubbub->ctx->logger, LOG_WARNING, + "pstate TEST_DEBUG_DATA: 0x%X\n", + debug_data); +- BREAK_TO_DEBUGGER(); ++ ++ return true; + } + + static uint32_t convert_and_clamp( +@@ -182,7 +178,7 @@ static uint32_t convert_and_clamp( + } + + +-void program_watermarks( ++void hubbub1_program_watermarks( + struct hubbub *hubbub, + struct dcn_watermark_set *watermarks, + unsigned int refclk_mhz) +@@ -472,7 +468,7 @@ void hubbub1_update_dchub( + dh_data->dchub_info_valid = false; + } + +-void toggle_watermark_change_req(struct hubbub *hubbub) ++void hubbub1_toggle_watermark_change_req(struct hubbub *hubbub) + { + uint32_t watermark_change_req; + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h +index e9abb88..d5c9784 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h +@@ -191,18 +191,15 @@ void hubbub1_update_dchub( + struct hubbub *hubbub, + struct dchub_init_data *dh_data); + +-void dcn10_log_hw_state( +- struct dc *dc); +- +-void verify_allow_pstate_change_high( ++bool hubbub1_verify_allow_pstate_change_high( + struct hubbub *hubbub); + +-void program_watermarks( ++void hubbub1_program_watermarks( + struct hubbub *hubbub, + struct dcn_watermark_set *watermarks, + unsigned int refclk_mhz); + +-void toggle_watermark_change_req( ++void hubbub1_toggle_watermark_change_req( + struct hubbub *hubbub); + + void hubbub1_wm_read_state(struct hubbub *hubbub, +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index ced6c41..e2dc834 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -544,6 +544,19 @@ static void reset_back_end_for_pipe( + pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); + } + ++void dcn10_verify_allow_pstate_change_high(struct dc *dc) ++{ ++ static bool should_log_hw_state; /* prevent hw state log by default */ ++ ++ if (hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) { ++ if (should_log_hw_state) { ++ dcn10_log_hw_state(dc); ++ } ++ ++ BREAK_TO_DEBUGGER(); ++ } ++} ++ + /* trigger HW to start disconnect plane from stream on the next vsync */ + static void plane_atomic_disconnect(struct dc *dc, + int fe_idx) +@@ -571,10 +584,10 @@ static void plane_atomic_disconnect(struct dc *dc, + return; + + if (dc->debug.sanity_checks) +- verify_allow_pstate_change_high(dc->res_pool->hubbub); ++ dcn10_verify_allow_pstate_change_high(dc); + hubp->funcs->dcc_control(hubp, false, false); + if (dc->debug.sanity_checks) +- verify_allow_pstate_change_high(dc->res_pool->hubbub); ++ dcn10_verify_allow_pstate_change_high(dc); + + mpc->funcs->remove(mpc, &(dc->res_pool->opps[opp_id]->mpc_tree), + dc->res_pool->opps[opp_id]->inst, fe_idx); +@@ -602,7 +615,7 @@ static void plane_atomic_disable(struct dc *dc, + hubp->funcs->set_blank(hubp, true); + + if (dc->debug.sanity_checks) +- verify_allow_pstate_change_high(dc->res_pool->hubbub); ++ dcn10_verify_allow_pstate_change_high(dc); + + REG_UPDATE(HUBP_CLK_CNTL[fe_idx], + HUBP_CLOCK_ENABLE, 0); +@@ -614,7 +627,7 @@ static void plane_atomic_disable(struct dc *dc, + OPP_PIPE_CLOCK_EN, 0); + + if (dc->debug.sanity_checks) +- verify_allow_pstate_change_high(dc->res_pool->hubbub); ++ dcn10_verify_allow_pstate_change_high(dc); + } + + static void reset_front_end( +@@ -638,7 +651,7 @@ static void reset_front_end( + tg->funcs->unlock(tg); + + if (dc->debug.sanity_checks) +- verify_allow_pstate_change_high(dc->res_pool->hubbub); ++ dcn10_verify_allow_pstate_change_high(dc); + + if (tg->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) + REG_WAIT(OTG_GLOBAL_SYNC_STATUS[tg->inst], +@@ -670,7 +683,7 @@ static void dcn10_power_down_fe(struct dc *dc, int fe_idx) + "Power gated front end %d\n", fe_idx); + + if (dc->debug.sanity_checks) +- verify_allow_pstate_change_high(dc->res_pool->hubbub); ++ dcn10_verify_allow_pstate_change_high(dc); + } + + static void dcn10_init_hw(struct dc *dc) +@@ -1243,7 +1256,7 @@ static void dcn10_pipe_control_lock( + return; + + if (dc->debug.sanity_checks) +- verify_allow_pstate_change_high(dc->res_pool->hubbub); ++ dcn10_verify_allow_pstate_change_high(dc); + + if (lock) + pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg); +@@ -1251,7 +1264,7 @@ static void dcn10_pipe_control_lock( + pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg); + + if (dc->debug.sanity_checks) +- verify_allow_pstate_change_high(dc->res_pool->hubbub); ++ dcn10_verify_allow_pstate_change_high(dc); + } + + static bool wait_for_reset_trigger_to_occur( +@@ -1475,7 +1488,7 @@ static void dcn10_power_on_fe( + struct dce_hwseq *hws = dc->hwseq; + + if (dc->debug.sanity_checks) { +- verify_allow_pstate_change_high(dc->res_pool->hubbub); ++ dcn10_verify_allow_pstate_change_high(dc); + } + + power_on_plane(dc->hwseq, +@@ -1527,7 +1540,7 @@ static void dcn10_power_on_fe( + } + + if (dc->debug.sanity_checks) { +- verify_allow_pstate_change_high(dc->res_pool->hubbub); ++ dcn10_verify_allow_pstate_change_high(dc); + } + } + +@@ -1960,11 +1973,11 @@ static void program_all_pipe_in_tree( + * this OTG. this is done only one time. + */ + /* watermark is for all pipes */ +- program_watermarks(dc->res_pool->hubbub, &context->bw.dcn.watermarks, ref_clk_mhz); ++ hubbub1_program_watermarks(dc->res_pool->hubbub, &context->bw.dcn.watermarks, ref_clk_mhz); + + if (dc->debug.sanity_checks) { + /* pstate stuck check after watermark update */ +- verify_allow_pstate_change_high(dc->res_pool->hubbub); ++ dcn10_verify_allow_pstate_change_high(dc); + } + + pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg); +@@ -1995,7 +2008,7 @@ static void program_all_pipe_in_tree( + * DCHUBBUB_ARB_WATERMARK_CHANGE_REQUEST is owned by SMU we should have + * both driver and fw accessing same register + */ +- toggle_watermark_change_req(dc->res_pool->hubbub); ++ hubbub1_toggle_watermark_change_req(dc->res_pool->hubbub); + + update_dchubp_dpp(dc, pipe_ctx, context); + +@@ -2018,7 +2031,7 @@ static void program_all_pipe_in_tree( + + if (dc->debug.sanity_checks) { + /* pstate stuck check after each pipe is programmed */ +- verify_allow_pstate_change_high(dc->res_pool->hubbub); ++ dcn10_verify_allow_pstate_change_high(dc); + } + + if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx) +@@ -2085,7 +2098,7 @@ static void dcn10_apply_ctx_for_surface( + int i, be_idx; + + if (dc->debug.sanity_checks) +- verify_allow_pstate_change_high(dc->res_pool->hubbub); ++ dcn10_verify_allow_pstate_change_high(dc); + + be_idx = -1; + for (i = 0; i < dc->res_pool->pipe_count; i++) { +@@ -2168,7 +2181,7 @@ static void dcn10_apply_ctx_for_surface( + hubp->funcs->hubp_disconnect(hubp); + + if (dc->debug.sanity_checks) +- verify_allow_pstate_change_high(dc->res_pool->hubbub); ++ dcn10_verify_allow_pstate_change_high(dc); + + old_pipe_ctx->top_pipe = NULL; + old_pipe_ctx->bottom_pipe = NULL; +@@ -2246,7 +2259,7 @@ static void dcn10_apply_ctx_for_surface( + ); + + if (dc->debug.sanity_checks) +- verify_allow_pstate_change_high(dc->res_pool->hubbub); ++ dcn10_verify_allow_pstate_change_high(dc); + } + + static void dcn10_set_bandwidth( +@@ -2260,7 +2273,7 @@ static void dcn10_set_bandwidth( + struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu; + + if (dc->debug.sanity_checks) { +- verify_allow_pstate_change_high(dc->res_pool->hubbub); ++ dcn10_verify_allow_pstate_change_high(dc); + } + + if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) +@@ -2316,7 +2329,7 @@ static void dcn10_set_bandwidth( + dcn10_pplib_apply_display_requirements(dc, context); + + if (dc->debug.sanity_checks) { +- verify_allow_pstate_change_high(dc->res_pool->hubbub); ++ dcn10_verify_allow_pstate_change_high(dc); + } + + /* need to fix this function. not doing the right thing here */ +@@ -2441,7 +2454,7 @@ static void dcn10_wait_for_mpcc_disconnect( + int i; + + if (dc->debug.sanity_checks) { +- verify_allow_pstate_change_high(dc->res_pool->hubbub); ++ dcn10_verify_allow_pstate_change_high(dc); + } + + if (!pipe_ctx->stream_res.opp) +@@ -2459,7 +2472,7 @@ static void dcn10_wait_for_mpcc_disconnect( + } + + if (dc->debug.sanity_checks) { +- verify_allow_pstate_change_high(dc->res_pool->hubbub); ++ dcn10_verify_allow_pstate_change_high(dc); + } + + } +-- +2.7.4 + |