diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2650-drm-amd-display-Reject-PPLib-clock-values-if-they-ar.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2650-drm-amd-display-Reject-PPLib-clock-values-if-they-ar.patch | 110 |
1 files changed, 110 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2650-drm-amd-display-Reject-PPLib-clock-values-if-they-ar.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2650-drm-amd-display-Reject-PPLib-clock-values-if-they-ar.patch new file mode 100644 index 00000000..35ac4bd1 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2650-drm-amd-display-Reject-PPLib-clock-values-if-they-ar.patch @@ -0,0 +1,110 @@ +From 1a659444a2451966c1149999ade7ed50d27fe02f Mon Sep 17 00:00:00 2001 +From: Andrew Jiang <Andrew.Jiang@amd.com> +Date: Thu, 19 Oct 2017 14:43:36 -0400 +Subject: [PATCH 2650/4131] drm/amd/display: Reject PPLib clock values if they + are invalid + +We should be sticking with the default clock values if the values +obtained from PPLib are bogus. + +Signed-off-by: Andrew Jiang <Andrew.Jiang@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Harry Wentland <harry.wentland@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 68 ++++++++++++++++-------- + 1 file changed, 45 insertions(+), 23 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +index e151523..01f92f8 100644 +--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c ++++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +@@ -1231,40 +1231,62 @@ unsigned int dcn_find_dcfclk_suits_all( + return dcf_clk; + } + ++static bool verify_clock_values(struct dm_pp_clock_levels_with_voltage *clks) ++{ ++ int i; ++ ++ if (clks->num_levels == 0) ++ return false; ++ ++ for (i = 0; i < clks->num_levels; i++) ++ /* Ensure that the result is sane */ ++ if (clks->data[i].clocks_in_khz == 0) ++ return false; ++ ++ return true; ++} ++ + void dcn_bw_update_from_pplib(struct dc *dc) + { + struct dc_context *ctx = dc->ctx; +- struct dm_pp_clock_levels_with_voltage clks = {0}; ++ struct dm_pp_clock_levels_with_voltage fclks = {0}, dcfclks = {0}; ++ bool res; + + kernel_fpu_begin(); + + /* TODO: This is not the proper way to obtain fabric_and_dram_bandwidth, should be min(fclk, memclk) */ +- +- if (dm_pp_get_clock_levels_by_type_with_voltage( +- ctx, DM_PP_CLOCK_TYPE_FCLK, &clks) && +- clks.num_levels != 0) { +- ASSERT(clks.num_levels >= 3); +- dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 32 * (clks.data[0].clocks_in_khz / 1000.0) / 1000.0; +- if (clks.num_levels > 2) { +- dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->number_of_channels * +- (clks.data[clks.num_levels - 3].clocks_in_khz / 1000.0) * ddr4_dram_factor_single_Channel / 1000.0; +- } else { +- dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->number_of_channels * +- (clks.data[clks.num_levels - 2].clocks_in_khz / 1000.0) * ddr4_dram_factor_single_Channel / 1000.0; +- } ++ res = dm_pp_get_clock_levels_by_type_with_voltage( ++ ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks); ++ ++ if (res) ++ res = verify_clock_values(&fclks); ++ ++ if (res) { ++ ASSERT(fclks.num_levels >= 3); ++ dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 = 32 * (fclks.data[0].clocks_in_khz / 1000.0) / 1000.0; ++ dc->dcn_soc->fabric_and_dram_bandwidth_vmid0p72 = dc->dcn_soc->number_of_channels * ++ (fclks.data[fclks.num_levels - (fclks.num_levels > 2 ? 3 : 2)].clocks_in_khz / 1000.0) ++ * ddr4_dram_factor_single_Channel / 1000.0; + dc->dcn_soc->fabric_and_dram_bandwidth_vnom0p8 = dc->dcn_soc->number_of_channels * +- (clks.data[clks.num_levels - 2].clocks_in_khz / 1000.0) * ddr4_dram_factor_single_Channel / 1000.0; ++ (fclks.data[fclks.num_levels - 2].clocks_in_khz / 1000.0) ++ * ddr4_dram_factor_single_Channel / 1000.0; + dc->dcn_soc->fabric_and_dram_bandwidth_vmax0p9 = dc->dcn_soc->number_of_channels * +- (clks.data[clks.num_levels - 1].clocks_in_khz / 1000.0) * ddr4_dram_factor_single_Channel / 1000.0; ++ (fclks.data[fclks.num_levels - 1].clocks_in_khz / 1000.0) ++ * ddr4_dram_factor_single_Channel / 1000.0; + } else + BREAK_TO_DEBUGGER(); +- if (dm_pp_get_clock_levels_by_type_with_voltage( +- ctx, DM_PP_CLOCK_TYPE_DCFCLK, &clks) && +- clks.num_levels >= 3) { +- dc->dcn_soc->dcfclkv_min0p65 = clks.data[0].clocks_in_khz / 1000.0; +- dc->dcn_soc->dcfclkv_mid0p72 = clks.data[clks.num_levels - 3].clocks_in_khz / 1000.0; +- dc->dcn_soc->dcfclkv_nom0p8 = clks.data[clks.num_levels - 2].clocks_in_khz / 1000.0; +- dc->dcn_soc->dcfclkv_max0p9 = clks.data[clks.num_levels - 1].clocks_in_khz / 1000.0; ++ ++ res = dm_pp_get_clock_levels_by_type_with_voltage( ++ ctx, DM_PP_CLOCK_TYPE_DCFCLK, &dcfclks); ++ ++ if (res) ++ res = verify_clock_values(&dcfclks); ++ ++ if (res && dcfclks.num_levels >= 3) { ++ dc->dcn_soc->dcfclkv_min0p65 = dcfclks.data[0].clocks_in_khz / 1000.0; ++ dc->dcn_soc->dcfclkv_mid0p72 = dcfclks.data[dcfclks.num_levels - 3].clocks_in_khz / 1000.0; ++ dc->dcn_soc->dcfclkv_nom0p8 = dcfclks.data[dcfclks.num_levels - 2].clocks_in_khz / 1000.0; ++ dc->dcn_soc->dcfclkv_max0p9 = dcfclks.data[dcfclks.num_levels - 1].clocks_in_khz / 1000.0; + } else + BREAK_TO_DEBUGGER(); + +-- +2.7.4 + |