diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2619-drm-amd-display-Adding-DCN1-registers.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2619-drm-amd-display-Adding-DCN1-registers.patch | 83 |
1 files changed, 83 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2619-drm-amd-display-Adding-DCN1-registers.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2619-drm-amd-display-Adding-DCN1-registers.patch new file mode 100644 index 00000000..7e8a9fc8 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2619-drm-amd-display-Adding-DCN1-registers.patch @@ -0,0 +1,83 @@ +From f5212156acdd8815a99b77ec7e72099380320b3d Mon Sep 17 00:00:00 2001 +From: Mikita Lipski <mikita.lipski@amd.com> +Date: Tue, 17 Oct 2017 10:53:43 -0400 +Subject: [PATCH 2619/4131] drm/amd/display: Adding DCN1 registers + +Registers added to definition list that are required +for multi display synchronization + +Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Harry Wentland <Harry.Wentland@amd.com> +--- + .../amd/display/dc/dcn10/dcn10_timing_generator.h | 33 ++++++++++++++++++++-- + 1 file changed, 30 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h +index 7d4818d..3958206 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.h +@@ -72,7 +72,10 @@ + SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\ + SRI(OPPBUF_CONTROL, OPPBUF, inst),\ + SRI(OPPBUF_3D_PARAMETERS_0, OPPBUF, inst),\ +- SRI(CONTROL, VTG, inst) ++ SRI(CONTROL, VTG, inst),\ ++ SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\ ++ SRI(OTG_MASTER_UPDATE_MODE, OTG, inst),\ ++ SRI(OTG_GSL_CONTROL, OTG, inst) + + #define TG_COMMON_REG_LIST_DCN1_0(inst) \ + TG_COMMON_REG_LIST_DCN(inst),\ +@@ -82,6 +85,9 @@ + + + struct dcn_tg_registers { ++ uint32_t OTG_VERT_SYNC_CONTROL; ++ uint32_t OTG_MASTER_UPDATE_MODE; ++ uint32_t OTG_GSL_CONTROL; + uint32_t OTG_VSTARTUP_PARAM; + uint32_t OTG_VUPDATE_PARAM; + uint32_t OTG_VREADY_PARAM; +@@ -208,7 +214,18 @@ struct dcn_tg_registers { + SF(OPPBUF0_OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, mask_sh),\ + SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\ + SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\ +- SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh) ++ SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\ ++ SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\ ++ SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\ ++ SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\ ++ SF(OTG0_OTG_MASTER_UPDATE_MODE, MASTER_UPDATE_INTERLACED_MODE, mask_sh),\ ++ SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\ ++ SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\ ++ SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\ ++ SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\ ++ SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\ ++ SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh) ++ + + #define TG_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\ + TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\ +@@ -317,7 +334,17 @@ struct dcn_tg_registers { + type OPPBUF_3D_VACT_SPACE1_SIZE;\ + type VTG0_ENABLE;\ + type VTG0_FP2;\ +- type VTG0_VCOUNT_INIT; ++ type VTG0_VCOUNT_INIT;\ ++ type OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED;\ ++ type OTG_FORCE_VSYNC_NEXT_LINE_CLEAR;\ ++ type OTG_AUTO_FORCE_VSYNC_MODE;\ ++ type MASTER_UPDATE_INTERLACED_MODE;\ ++ type OTG_GSL0_EN;\ ++ type OTG_GSL1_EN;\ ++ type OTG_GSL2_EN;\ ++ type OTG_GSL_MASTER_EN;\ ++ type OTG_GSL_FORCE_DELAY;\ ++ type OTG_GSL_CHECK_ALL_FIELDS; + + struct dcn_tg_shift { + TG_REG_FIELD_LIST(uint8_t) +-- +2.7.4 + |