diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2617-drm-amd-display-Move-lock-to-front-end-program.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2617-drm-amd-display-Move-lock-to-front-end-program.patch | 177 |
1 files changed, 177 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2617-drm-amd-display-Move-lock-to-front-end-program.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2617-drm-amd-display-Move-lock-to-front-end-program.patch new file mode 100644 index 00000000..6ae38395 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2617-drm-amd-display-Move-lock-to-front-end-program.patch @@ -0,0 +1,177 @@ +From 069b1b0f1c98b94f3a293d8c2032ae7819e66015 Mon Sep 17 00:00:00 2001 +From: Yongqiang Sun <yongqiang.sun@amd.com> +Date: Tue, 17 Oct 2017 14:48:11 -0400 +Subject: [PATCH 2617/4131] drm/amd/display: Move lock to front end program. + +Moved lock and unlock to apply_ctx_to_surface, since all +the front end programming is within apply_ctx_to_surface. + +Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Harry Wentland <Harry.Wentland@amd.com> +--- + drivers/gpu/drm/amd/display/dc/core/dc.c | 52 +--------------------- + .../amd/display/dc/dce110/dce110_hw_sequencer.c | 16 +++++++ + .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 13 +++++- + 3 files changed, 29 insertions(+), 52 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c +index 08ea89e..a178838 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -799,7 +799,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c + struct dc_bios *dcb = dc->ctx->dc_bios; + enum dc_status result = DC_ERROR_UNEXPECTED; + struct pipe_ctx *pipe; +- int i, j, k, l; ++ int i, k, l; + struct dc_stream_state *dc_streams[MAX_STREAMS] = {0}; + + for (i = 0; i < context->stream_count; i++) +@@ -853,15 +853,6 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c + + dc_enable_stereo(dc, context, dc_streams, context->stream_count); + +- for (i = 0; i < context->stream_count; i++) { +- for (j = 0; j < MAX_PIPES; j++) { +- pipe = &context->res_ctx.pipe_ctx[j]; +- +- if (!pipe->top_pipe && pipe->stream == context->streams[i]) +- dc->hwss.pipe_control_lock(dc, pipe, false); +- } +- } +- + dc_release_state(dc->current_state); + + dc->current_state = context; +@@ -1265,27 +1256,6 @@ static void commit_planes_for_stream(struct dc *dc, + return; + } + +- /* Lock pipes for provided surfaces, or all active if full update*/ +- for (i = 0; i < surface_count; i++) { +- struct dc_plane_state *plane_state = srf_updates[i].surface; +- +- for (j = 0; j < dc->res_pool->pipe_count; j++) { +- struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; +- +- if (update_type != UPDATE_TYPE_FULL && pipe_ctx->plane_state != plane_state) +- continue; +- if (!pipe_ctx->plane_state || pipe_ctx->top_pipe) +- continue; +- +- dc->hwss.pipe_control_lock( +- dc, +- pipe_ctx, +- true); +- } +- if (update_type == UPDATE_TYPE_FULL) +- break; +- } +- + /* Full fe update*/ + for (j = 0; j < dc->res_pool->pipe_count; j++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; +@@ -1342,26 +1312,6 @@ static void commit_planes_for_stream(struct dc *dc, + } + } + } +- +- /* Unlock pipes */ +- for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { +- struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; +- +- for (j = 0; j < surface_count; j++) { +- if (update_type != UPDATE_TYPE_FULL && +- srf_updates[j].surface != pipe_ctx->plane_state) +- continue; +- if (!pipe_ctx->plane_state || pipe_ctx->top_pipe) +- continue; +- +- dc->hwss.pipe_control_lock( +- dc, +- pipe_ctx, +- false); +- +- break; +- } +- } + } + + void dc_commit_updates_for_stream(struct dc *dc, +diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +index 6b4053c..76b48e7 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +@@ -2881,8 +2881,14 @@ static void dce110_apply_ctx_for_surface( + + be_idx = -1; + for (i = 0; i < dc->res_pool->pipe_count; i++) { ++ struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; ++ struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; ++ + if (stream == context->res_ctx.pipe_ctx[i].stream) { + be_idx = context->res_ctx.pipe_ctx[i].stream_res.tg->inst; ++ if (!pipe_ctx->top_pipe && ++ (pipe_ctx->plane_state || old_pipe_ctx->plane_state)) ++ dc->hwss.pipe_control_lock(dc, pipe_ctx, true); + break; + } + } +@@ -2897,6 +2903,16 @@ static void dce110_apply_ctx_for_surface( + program_surface_visibility(dc, pipe_ctx); + + } ++ ++ for (i = 0; i < dc->res_pool->pipe_count; i++) { ++ struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; ++ struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; ++ ++ if ((stream == pipe_ctx->stream) && ++ (!pipe_ctx->top_pipe) && ++ (pipe_ctx->plane_state || old_pipe_ctx->plane_state)) ++ dc->hwss.pipe_control_lock(dc, pipe_ctx, false); ++ } + } + + static void dce110_power_down_fe(struct dc *dc, int fe_idx) +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index 63c2f52..0d1f0e2 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -2550,6 +2550,11 @@ static void dcn10_apply_ctx_for_surface( + if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state) + continue; + ++ if (pipe_ctx->stream_res.tg && ++ pipe_ctx->stream_res.tg->inst == be_idx && ++ !pipe_ctx->top_pipe) ++ pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg); ++ + /* + * Powergate reused pipes that are not powergated + * fairly hacky right now, using opp_id as indicator +@@ -2605,13 +2610,19 @@ static void dcn10_apply_ctx_for_surface( + + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; ++ struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + + if (pipe_ctx->stream != stream) + continue; + + /* looking for top pipe to program */ +- if (!pipe_ctx->top_pipe) ++ if (!pipe_ctx->top_pipe) { + program_all_pipe_in_tree(dc, pipe_ctx, context); ++ if (pipe_ctx->stream_res.tg && ++ pipe_ctx->stream_res.tg->inst == be_idx && ++ (pipe_ctx->plane_state || old_pipe_ctx->plane_state)) ++ pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg); ++ } + } + + dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS, +-- +2.7.4 + |