diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2512-drm-amd-display-Expose-some-mem_input-functions-for-.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2512-drm-amd-display-Expose-some-mem_input-functions-for-.patch | 229 |
1 files changed, 229 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2512-drm-amd-display-Expose-some-mem_input-functions-for-.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2512-drm-amd-display-Expose-some-mem_input-functions-for-.patch new file mode 100644 index 00000000..adf8270f --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2512-drm-amd-display-Expose-some-mem_input-functions-for-.patch @@ -0,0 +1,229 @@ +From e9337e36e7094ba4144128f724da2e4e9961b19b Mon Sep 17 00:00:00 2001 +From: Yue Hin Lau <Yuehin.Lau@amd.com> +Date: Wed, 27 Sep 2017 15:34:35 -0400 +Subject: [PATCH 2512/4131] drm/amd/display: Expose some mem_input functions + for reuse + +Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Harry Wentland <Harry.Wentland@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 1 - + .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 26 +++++----- + .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h | 60 ++++++++++++++++++++++ + 3 files changed, 73 insertions(+), 14 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h +index 7fecdb1..889f91c 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h +@@ -113,7 +113,6 @@ + SRI(FORMAT_CONTROL, CNVC_CFG, id), \ + SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \ + SRI(CURSOR0_CONTROL, CNVC_CUR, id), \ +- SRI(CURSOR0_CONTROL, CNVC_CUR, id), \ + SRI(CURSOR0_COLOR0, CNVC_CUR, id), \ + SRI(CURSOR0_COLOR1, CNVC_CUR, id) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c +index efa1aca..b61f41c 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c +@@ -38,7 +38,7 @@ + #define FN(reg_name, field_name) \ + mi->mi_shift->field_name, mi->mi_mask->field_name + +-static void min10_set_blank(struct mem_input *mem_input, bool blank) ++void min10_set_blank(struct mem_input *mem_input, bool blank) + { + struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input); + uint32_t blank_en = blank ? 1 : 0; +@@ -87,7 +87,7 @@ static void min10_vready_workaround(struct mem_input *mem_input, + REG_WRITE(HUBPREQ_DEBUG_DB, value); + } + +-static void min10_program_tiling( ++void min10_program_tiling( + struct dcn10_mem_input *mi, + const union dc_tiling_info *info, + const enum surface_pixel_format pixel_format) +@@ -107,7 +107,7 @@ static void min10_program_tiling( + PIPE_ALIGNED, info->gfx9.pipe_aligned); + } + +-static void min10_program_size_and_rotation( ++void min10_program_size_and_rotation( + struct dcn10_mem_input *mi, + enum dc_rotation_angle rotation, + enum surface_pixel_format format, +@@ -169,7 +169,7 @@ static void min10_program_size_and_rotation( + H_MIRROR_EN, mirror); + } + +-static void min10_program_pixel_format( ++void min10_program_pixel_format( + struct dcn10_mem_input *mi, + enum surface_pixel_format format) + { +@@ -245,7 +245,7 @@ static void min10_program_pixel_format( + /* don't see the need of program the xbar in DCN 1.0 */ + } + +-static bool min10_program_surface_flip_and_addr( ++bool min10_program_surface_flip_and_addr( + struct mem_input *mem_input, + const struct dc_plane_address *address, + bool flip_immediate) +@@ -395,7 +395,7 @@ static bool min10_program_surface_flip_and_addr( + return true; + } + +-static void min10_dcc_control(struct mem_input *mem_input, bool enable, ++void min10_dcc_control(struct mem_input *mem_input, bool enable, + bool independent_64b_blks) + { + uint32_t dcc_en = enable ? 1 : 0; +@@ -425,7 +425,7 @@ static void min10_program_surface_config( + min10_program_pixel_format(mi, format); + } + +-static void min10_program_requestor( ++void min10_program_requestor( + struct mem_input *mem_input, + struct _vcs_dpi_display_rq_regs_st *rq_regs) + { +@@ -459,7 +459,7 @@ static void min10_program_requestor( + } + + +-static void min10_program_deadline( ++void min10_program_deadline( + struct mem_input *mem_input, + struct _vcs_dpi_display_dlg_regs_st *dlg_attr, + struct _vcs_dpi_display_ttu_regs_st *ttu_attr) +@@ -595,7 +595,7 @@ static void min10_setup( + min10_vready_workaround(mem_input, pipe_dest); + } + +-static void min10_program_display_marks( ++void min10_program_display_marks( + struct mem_input *mem_input, + struct dce_watermarks nbp, + struct dce_watermarks stutter, +@@ -607,7 +607,7 @@ static void min10_program_display_marks( + */ + } + +-static bool min10_is_flip_pending(struct mem_input *mem_input) ++bool min10_is_flip_pending(struct mem_input *mem_input) + { + uint32_t flip_pending = 0; + struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input); +@@ -696,7 +696,7 @@ static void min10_set_vm_context0_settings(struct mem_input *mem_input, + SYSTEM_ACCESS_MODE, 3); + } + +-static void min_set_viewport( ++void min_set_viewport( + struct mem_input *mem_input, + const struct rect *viewport, + const struct rect *viewport_c) +@@ -845,7 +845,7 @@ static enum cursor_lines_per_chunk ippn10_get_lines_per_chunk( + return line_per_chunk; + } + +-static void ippn10_cursor_set_attributes( ++void ippn10_cursor_set_attributes( + struct mem_input *mem_input, + const struct dc_cursor_attributes *attr) + { +@@ -873,7 +873,7 @@ static void ippn10_cursor_set_attributes( + attr->color_format); + } + +-static void ippn10_cursor_set_position( ++void ippn10_cursor_set_position( + struct mem_input *mem_input, + const struct dc_cursor_position *pos, + const struct dc_cursor_mi_param *param) +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h +index 2c79d7a..fdeb0e8 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h +@@ -589,6 +589,65 @@ struct dcn10_mem_input { + const struct dcn_mi_mask *mi_mask; + }; + ++void min10_program_deadline( ++ struct mem_input *mem_input, ++ struct _vcs_dpi_display_dlg_regs_st *dlg_attr, ++ struct _vcs_dpi_display_ttu_regs_st *ttu_attr); ++ ++void min10_program_requestor( ++ struct mem_input *mem_input, ++ struct _vcs_dpi_display_rq_regs_st *rq_regs); ++ ++void min10_program_pixel_format( ++ struct dcn10_mem_input *mi, ++ enum surface_pixel_format format); ++ ++void min10_program_size_and_rotation( ++ struct dcn10_mem_input *mi, ++ enum dc_rotation_angle rotation, ++ enum surface_pixel_format format, ++ const union plane_size *plane_size, ++ struct dc_plane_dcc_param *dcc, ++ bool horizontal_mirror); ++ ++void min10_program_tiling( ++ struct dcn10_mem_input *mi, ++ const union dc_tiling_info *info, ++ const enum surface_pixel_format pixel_format); ++ ++void min10_dcc_control(struct mem_input *mem_input, ++ bool enable, ++ bool independent_64b_blks); ++ ++void min10_program_display_marks( ++ struct mem_input *mem_input, ++ struct dce_watermarks nbp, ++ struct dce_watermarks stutter, ++ struct dce_watermarks urgent, ++ uint32_t total_dest_line_time_ns); ++ ++bool min10_program_surface_flip_and_addr( ++ struct mem_input *mem_input, ++ const struct dc_plane_address *address, ++ bool flip_immediate); ++ ++bool min10_is_flip_pending(struct mem_input *mem_input); ++ ++void ippn10_cursor_set_attributes( ++ struct mem_input *mem_input, ++ const struct dc_cursor_attributes *attr); ++ ++void ippn10_cursor_set_position( ++ struct mem_input *mem_input, ++ const struct dc_cursor_position *pos, ++ const struct dc_cursor_mi_param *param); ++ ++void min10_set_blank(struct mem_input *mem_input, bool blank); ++ ++void min_set_viewport(struct mem_input *mem_input, ++ const struct rect *viewport, ++ const struct rect *viewport_c); ++ + void dcn10_mem_input_construct( + struct dcn10_mem_input *mi, + struct dc_context *ctx, +@@ -597,6 +656,7 @@ void dcn10_mem_input_construct( + const struct dcn_mi_shift *mi_shift, + const struct dcn_mi_mask *mi_mask); + ++ + struct dcn_hubp_state { + uint32_t pixel_format; + uint32_t inuse_addr_hi; +-- +2.7.4 + |