diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2510-drm-amd-display-Add-override-for-reporting-wm-ranges.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2510-drm-amd-display-Add-override-for-reporting-wm-ranges.patch | 130 |
1 files changed, 130 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2510-drm-amd-display-Add-override-for-reporting-wm-ranges.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2510-drm-amd-display-Add-override-for-reporting-wm-ranges.patch new file mode 100644 index 00000000..5990212b --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2510-drm-amd-display-Add-override-for-reporting-wm-ranges.patch @@ -0,0 +1,130 @@ +From 1954802890bc1277bcfbe83a83b858285caab06c Mon Sep 17 00:00:00 2001 +From: Eric Yang <Eric.Yang2@amd.com> +Date: Wed, 27 Sep 2017 11:44:43 -0400 +Subject: [PATCH 2510/4131] drm/amd/display: Add override for reporting wm + ranges + +For verification of watermark select with SMU team, proper +implementation will follow + +Signed-off-by: Eric Yang <Eric.Yang2@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Harry Wentland <Harry.Wentland@amd.com> +--- + drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 47 ++++++++++++++++++++++ + drivers/gpu/drm/amd/display/dc/dc.h | 6 +++ + .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 ++ + .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 1 + + 4 files changed, 57 insertions(+) + +diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +index 9337cca..6318f9f 100644 +--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c ++++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +@@ -1441,6 +1441,53 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc) + ranges.writer_wm_sets[3].min_drain_clk_khz = max_fclk_khz; + ranges.writer_wm_sets[3].max_drain_clk_khz = max_fclk_khz; + ++ if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE) { ++ ranges.reader_wm_sets[0].wm_inst = WM_A; ++ ranges.reader_wm_sets[0].min_drain_clk_khz = 300000; ++ ranges.reader_wm_sets[0].max_drain_clk_khz = 654000; ++ ranges.reader_wm_sets[0].min_fill_clk_khz = 800000; ++ ranges.reader_wm_sets[0].max_fill_clk_khz = 800000; ++ ranges.writer_wm_sets[0].wm_inst = WM_A; ++ ranges.writer_wm_sets[0].min_fill_clk_khz = 200000; ++ ranges.writer_wm_sets[0].max_fill_clk_khz = 757000; ++ ranges.writer_wm_sets[0].min_drain_clk_khz = 800000; ++ ranges.writer_wm_sets[0].max_drain_clk_khz = 800000; ++ ++ ranges.reader_wm_sets[1].wm_inst = WM_B; ++ ranges.reader_wm_sets[1].min_drain_clk_khz = 300000; ++ ranges.reader_wm_sets[1].max_drain_clk_khz = 654000; ++ ranges.reader_wm_sets[1].min_fill_clk_khz = 933000; ++ ranges.reader_wm_sets[1].max_fill_clk_khz = 933000; ++ ranges.writer_wm_sets[1].wm_inst = WM_B; ++ ranges.writer_wm_sets[1].min_fill_clk_khz = 200000; ++ ranges.writer_wm_sets[1].max_fill_clk_khz = 757000; ++ ranges.writer_wm_sets[1].min_drain_clk_khz = 933000; ++ ranges.writer_wm_sets[1].max_drain_clk_khz = 933000; ++ ++ ++ ranges.reader_wm_sets[2].wm_inst = WM_C; ++ ranges.reader_wm_sets[2].min_drain_clk_khz = 300000; ++ ranges.reader_wm_sets[2].max_drain_clk_khz = 654000; ++ ranges.reader_wm_sets[2].min_fill_clk_khz = 1067000; ++ ranges.reader_wm_sets[2].max_fill_clk_khz = 1067000; ++ ranges.writer_wm_sets[2].wm_inst = WM_C; ++ ranges.writer_wm_sets[2].min_fill_clk_khz = 200000; ++ ranges.writer_wm_sets[2].max_fill_clk_khz = 757000; ++ ranges.writer_wm_sets[2].min_drain_clk_khz = 1067000; ++ ranges.writer_wm_sets[2].max_drain_clk_khz = 1067000; ++ ++ ranges.reader_wm_sets[3].wm_inst = WM_D; ++ ranges.reader_wm_sets[3].min_drain_clk_khz = 300000; ++ ranges.reader_wm_sets[3].max_drain_clk_khz = 654000; ++ ranges.reader_wm_sets[3].min_fill_clk_khz = 1200000; ++ ranges.reader_wm_sets[3].max_fill_clk_khz = 1200000; ++ ranges.writer_wm_sets[3].wm_inst = WM_D; ++ ranges.writer_wm_sets[3].min_fill_clk_khz = 200000; ++ ranges.writer_wm_sets[3].max_fill_clk_khz = 757000; ++ ranges.writer_wm_sets[3].min_drain_clk_khz = 1200000; ++ ranges.writer_wm_sets[3].max_drain_clk_khz = 1200000; ++ } ++ + /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ + pp->set_wm_ranges(&pp->pp_smu, &ranges); + } +diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h +index 349d3da..bfa468d 100644 +--- a/drivers/gpu/drm/amd/display/dc/dc.h ++++ b/drivers/gpu/drm/amd/display/dc/dc.h +@@ -173,6 +173,11 @@ enum pipe_split_policy { + MPC_SPLIT_AVOID_MULT_DISP = 2, + }; + ++enum wm_report_mode { ++ WM_REPORT_DEFAULT = 0, ++ WM_REPORT_OVERRIDE = 1, ++}; ++ + struct dc_debug { + bool surface_visual_confirm; + bool sanity_checks; +@@ -194,6 +199,7 @@ struct dc_debug { + bool disable_dpp_power_gate; + bool disable_hubp_power_gate; + bool disable_pplib_wm_range; ++ enum wm_report_mode pplib_wm_report_mode; + bool use_dml_wm; + unsigned int min_disp_clk_khz; + int sr_exit_time_dpm0_ns; +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index efa3f6f..86cfab3 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -2451,6 +2451,9 @@ static void optimize_shared_resources(struct dc *dc) + /* S0i2 message */ + dcn10_pplib_apply_display_requirements(dc, dc->current_state); + } ++ ++ if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE) ++ dcn_bw_notify_pplib_of_wm_ranges(dc); + } + + static void ready_shared_resources(struct dc *dc, struct dc_state *context) +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +index 7a766be..a9bb927 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +@@ -424,6 +424,7 @@ static const struct dc_debug debug_defaults_drv = { + + .disable_pplib_clock_request = true, + .disable_pplib_wm_range = false, ++ .pplib_wm_report_mode = WM_REPORT_DEFAULT, + .use_dml_wm = false, + + .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, +-- +2.7.4 + |