diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2478-drm-amd-display-make-tile-changing-run-at-ISR.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2478-drm-amd-display-make-tile-changing-run-at-ISR.patch | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2478-drm-amd-display-make-tile-changing-run-at-ISR.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2478-drm-amd-display-make-tile-changing-run-at-ISR.patch new file mode 100644 index 00000000..3cd1dc8c --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2478-drm-amd-display-make-tile-changing-run-at-ISR.patch @@ -0,0 +1,56 @@ +From ec2ed9301005e3b06748955d4da66c4fc4139a42 Mon Sep 17 00:00:00 2001 +From: ShihChen Chen <ShihChen.Chen@amd.com> +Date: Tue, 12 Sep 2017 11:10:12 +0800 +Subject: [PATCH 2478/4131] drm/amd/display: make tile changing run at ISR + +Signed-off-by: ShihChen Chen <ShihChen.Chen@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Harry Wentland <Harry.Wentland@amd.com> +--- + drivers/gpu/drm/amd/display/dc/core/dc.c | 21 ++++++++++++++++++--- + 1 file changed, 18 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c +index 9433f9b..17abfdd 100644 +--- a/drivers/gpu/drm/amd/display/dc/core/dc.c ++++ b/drivers/gpu/drm/amd/display/dc/core/dc.c +@@ -1031,7 +1031,6 @@ static enum surface_update_type get_plane_info_update_type( + temp_plane_info.plane_size = u->surface->plane_size; + temp_plane_info.rotation = u->surface->rotation; + temp_plane_info.stereo_format = u->surface->stereo_format; +- temp_plane_info.tiling_info = u->surface->tiling_info; + + if (surface_index == 0) + temp_plane_info.visible = u->plane_info->visible; +@@ -1044,10 +1043,26 @@ static enum surface_update_type get_plane_info_update_type( + + if (pixel_format_to_bpp(u->plane_info->format) != + pixel_format_to_bpp(u->surface->format)) { ++ /* different bytes per element will require full bandwidth ++ * and DML calculation ++ */ + return UPDATE_TYPE_FULL; +- } else { +- return UPDATE_TYPE_MED; + } ++ ++ if (memcmp(&u->plane_info->tiling_info, &u->surface->tiling_info, ++ sizeof(union dc_tiling_info)) != 0) { ++ /* todo: below are HW dependent, we should add a hook to ++ * DCE/N resource and validated there. ++ */ ++ if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) { ++ /* swizzled mode requires RQ to be setup properly, ++ * thus need to run DML to calculate RQ settings ++ */ ++ return UPDATE_TYPE_FULL; ++ } ++ } ++ ++ return UPDATE_TYPE_MED; + } + + static enum surface_update_type get_scaling_info_update_type( +-- +2.7.4 + |