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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2432-amdgpu-dc-another-round-of-dce-dcn-construct-cleanup.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2432-amdgpu-dc-another-round-of-dce-dcn-construct-cleanup.patch679
1 files changed, 679 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2432-amdgpu-dc-another-round-of-dce-dcn-construct-cleanup.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2432-amdgpu-dc-another-round-of-dce-dcn-construct-cleanup.patch
new file mode 100644
index 00000000..00887ca2
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2432-amdgpu-dc-another-round-of-dce-dcn-construct-cleanup.patch
@@ -0,0 +1,679 @@
+From 78174c211920abf4a191318e97df989d6bd78027 Mon Sep 17 00:00:00 2001
+From: Dave Airlie <airlied@redhat.com>
+Date: Fri, 29 Sep 2017 14:34:39 +1000
+Subject: [PATCH 2432/4131] amdgpu/dc: another round of dce/dcn construct
+ cleanups.
+
+This removes any remaining pointless return codepaths from the
+DCE code.
+
+Signed-off-by: Dave Airlie <airlied@redhat.com>
+Reviewed-by: Harry Wentland <harry.wentland@amd.com>
+---
+ .../drm/amd/display/dc/dce100/dce100_hw_sequencer.c | 4 +---
+ .../drm/amd/display/dc/dce100/dce100_hw_sequencer.h | 2 +-
+ .../gpu/drm/amd/display/dc/dce100/dce100_resource.c | 4 +---
+ .../drm/amd/display/dc/dce110/dce110_compressor.c | 11 +++--------
+ .../drm/amd/display/dc/dce110/dce110_compressor.h | 2 +-
+ .../drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 4 +---
+ .../drm/amd/display/dc/dce110/dce110_hw_sequencer.h | 2 +-
+ drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c | 4 +---
+ drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h | 2 +-
+ .../gpu/drm/amd/display/dc/dce110/dce110_resource.c | 6 ++----
+ .../display/dc/dce110/dce110_timing_generator_v.c | 7 +------
+ .../display/dc/dce110/dce110_timing_generator_v.h | 2 +-
+ .../drm/amd/display/dc/dce112/dce112_compressor.c | 11 +++--------
+ .../drm/amd/display/dc/dce112/dce112_compressor.h | 2 +-
+ .../drm/amd/display/dc/dce112/dce112_hw_sequencer.c | 4 +---
+ .../drm/amd/display/dc/dce112/dce112_hw_sequencer.h | 2 +-
+ .../gpu/drm/amd/display/dc/dce112/dce112_resource.c | 3 +--
+ .../drm/amd/display/dc/dce120/dce120_hw_sequencer.c | 4 +---
+ .../drm/amd/display/dc/dce120/dce120_hw_sequencer.h | 2 +-
+ .../gpu/drm/amd/display/dc/dce120/dce120_resource.c | 8 ++------
+ .../amd/display/dc/dce120/dce120_timing_generator.c | 7 +------
+ .../amd/display/dc/dce120/dce120_timing_generator.h | 2 +-
+ .../gpu/drm/amd/display/dc/dce80/dce80_compressor.c | 11 +++--------
+ .../gpu/drm/amd/display/dc/dce80/dce80_compressor.h | 2 +-
+ .../drm/amd/display/dc/dce80/dce80_hw_sequencer.c | 4 +---
+ .../drm/amd/display/dc/dce80/dce80_hw_sequencer.h | 2 +-
+ .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 9 +++------
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 4 +---
+ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 2 +-
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 4 +---
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h | 2 +-
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 20 ++++++--------------
+ 32 files changed, 47 insertions(+), 108 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
+index 492ea60..e7a6948 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
+@@ -142,13 +142,11 @@ void dce100_set_bandwidth(
+
+ /**************************************************************************/
+
+-bool dce100_hw_sequencer_construct(struct dc *dc)
++void dce100_hw_sequencer_construct(struct dc *dc)
+ {
+ dce110_hw_sequencer_construct(dc);
+
+ dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;
+ dc->hwss.set_bandwidth = dce100_set_bandwidth;
+-
+- return true;
+ }
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h
+index 770b5bb..cb5384e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h
+@@ -31,7 +31,7 @@
+ struct dc;
+ struct dc_state;
+
+-bool dce100_hw_sequencer_construct(struct dc *dc);
++void dce100_hw_sequencer_construct(struct dc *dc);
+
+ void dce100_set_bandwidth(
+ struct dc *dc,
+diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+index 1caf298..0db987d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+@@ -909,9 +909,7 @@ static bool construct(
+ goto res_create_fail;
+
+ /* Create hardware sequencer */
+- if (!dce100_hw_sequencer_construct(dc))
+- goto res_create_fail;
+-
++ dce100_hw_sequencer_construct(dc);
+ return true;
+
+ res_create_fail:
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
+index 90770cb..3872feb 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c
+@@ -393,12 +393,8 @@ struct compressor *dce110_compressor_create(struct dc_context *ctx)
+ if (!cp110)
+ return NULL;
+
+- if (dce110_compressor_construct(cp110, ctx))
+- return &cp110->base;
+-
+- BREAK_TO_DEBUGGER();
+- kfree(cp110);
+- return NULL;
++ dce110_compressor_construct(cp110, ctx);
++ return &cp110->base;
+ }
+
+ void dce110_compressor_destroy(struct compressor **compressor)
+@@ -485,7 +481,7 @@ static const struct compressor_funcs dce110_compressor_funcs = {
+ };
+
+
+-bool dce110_compressor_construct(struct dce110_compressor *compressor,
++void dce110_compressor_construct(struct dce110_compressor *compressor,
+ struct dc_context *ctx)
+ {
+
+@@ -522,6 +518,5 @@ bool dce110_compressor_construct(struct dce110_compressor *compressor,
+ compressor->base.funcs = &dce110_compressor_funcs;
+
+ #endif
+- return true;
+ }
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h
+index 460cb77..26c7335 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h
+@@ -42,7 +42,7 @@ struct dce110_compressor {
+
+ struct compressor *dce110_compressor_create(struct dc_context *ctx);
+
+-bool dce110_compressor_construct(struct dce110_compressor *cp110,
++void dce110_compressor_construct(struct dce110_compressor *cp110,
+ struct dc_context *ctx);
+
+ void dce110_compressor_destroy(struct compressor **cp);
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+index 92810db..1e512ba 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+@@ -2718,10 +2718,8 @@ static const struct hw_sequencer_funcs dce110_funcs = {
+
+ };
+
+-bool dce110_hw_sequencer_construct(struct dc *dc)
++void dce110_hw_sequencer_construct(struct dc *dc)
+ {
+ dc->hwss = dce110_funcs;
+-
+- return true;
+ }
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
+index baa20c1..db6c19c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h
+@@ -33,7 +33,7 @@ struct dc;
+ struct dc_state;
+ struct dm_pp_display_configuration;
+
+-bool dce110_hw_sequencer_construct(struct dc *dc);
++void dce110_hw_sequencer_construct(struct dc *dc);
+
+ enum dc_status dce110_apply_ctx_to_hw(
+ struct dc *dc,
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c
+index 69d6a11..3545e43 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c
+@@ -44,13 +44,11 @@ static const struct opp_funcs funcs = {
+ dce110_opp_program_bit_depth_reduction
+ };
+
+-bool dce110_opp_v_construct(struct dce110_opp *opp110,
++void dce110_opp_v_construct(struct dce110_opp *opp110,
+ struct dc_context *ctx)
+ {
+ opp110->base.funcs = &funcs;
+
+ opp110->base.ctx = ctx;
+-
+- return true;
+ }
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h
+index 269c1a8..152af4c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h
+@@ -29,7 +29,7 @@
+ #include "opp.h"
+ #include "core_types.h"
+
+-bool dce110_opp_v_construct(struct dce110_opp *opp110,
++void dce110_opp_v_construct(struct dce110_opp *opp110,
+ struct dc_context *ctx);
+
+ /* underlay callbacks */
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+index 45c5fac..017a1fd 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
+@@ -1041,8 +1041,7 @@ static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool)
+ (dce110_oppv == NULL))
+ return false;
+
+- if (!dce110_opp_v_construct(dce110_oppv, ctx))
+- return false;
++ dce110_opp_v_construct(dce110_oppv, ctx);
+
+ dce110_timing_generator_v_construct(dce110_tgv, ctx);
+ dce110_mem_input_v_construct(dce110_miv, ctx);
+@@ -1292,8 +1291,7 @@ static bool construct(
+ goto res_create_fail;
+
+ /* Create hardware sequencer */
+- if (!dce110_hw_sequencer_construct(dc))
+- goto res_create_fail;
++ dce110_hw_sequencer_construct(dc);
+
+ dc->caps.max_planes = pool->base.pipe_count;
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
+index 93ca6ae..07d9303 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c
+@@ -668,13 +668,10 @@ static const struct timing_generator_funcs dce110_tg_v_funcs = {
+ dce110_timing_generator_v_enable_advanced_request
+ };
+
+-bool dce110_timing_generator_v_construct(
++void dce110_timing_generator_v_construct(
+ struct dce110_timing_generator *tg110,
+ struct dc_context *ctx)
+ {
+- if (!tg110)
+- return false;
+-
+ tg110->controller_id = CONTROLLER_ID_UNDERLAY0;
+
+ tg110->base.funcs = &dce110_tg_v_funcs;
+@@ -688,6 +685,4 @@ bool dce110_timing_generator_v_construct(
+ tg110->min_h_blank = 56;
+ tg110->min_h_front_porch = 4;
+ tg110->min_h_back_porch = 4;
+-
+- return true;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.h
+index 7e49ca8..d2623a5 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.h
++++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.h
+@@ -26,7 +26,7 @@
+ #ifndef __DC_TIMING_GENERATOR_V_DCE110_H__
+ #define __DC_TIMING_GENERATOR_V_DCE110_H__
+
+-bool dce110_timing_generator_v_construct(
++void dce110_timing_generator_v_construct(
+ struct dce110_timing_generator *tg110,
+ struct dc_context *ctx);
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c
+index e75895b..6964992 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c
++++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c
+@@ -791,7 +791,7 @@ void dce112_compressor_set_fbc_invalidation_triggers(
+ dm_write_reg(compressor->ctx, addr, value);
+ }
+
+-bool dce112_compressor_construct(struct dce112_compressor *compressor,
++void dce112_compressor_construct(struct dce112_compressor *compressor,
+ struct dc_context *ctx)
+ {
+ struct dc_bios *bp = ctx->dc_bios;
+@@ -833,7 +833,6 @@ bool dce112_compressor_construct(struct dce112_compressor *compressor,
+ compressor->base.embedded_panel_v_size =
+ panel_info.lcd_timing.vertical_addressable;
+ }
+- return true;
+ }
+
+ struct compressor *dce112_compressor_create(struct dc_context *ctx)
+@@ -844,12 +843,8 @@ struct compressor *dce112_compressor_create(struct dc_context *ctx)
+ if (!cp110)
+ return NULL;
+
+- if (dce112_compressor_construct(cp110, ctx))
+- return &cp110->base;
+-
+- BREAK_TO_DEBUGGER();
+- kfree(cp110);
+- return NULL;
++ dce112_compressor_construct(cp110, ctx);
++ return &cp110->base;
+ }
+
+ void dce112_compressor_destroy(struct compressor **compressor)
+diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h
+index 1065063..f122713 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h
++++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h
+@@ -42,7 +42,7 @@ struct dce112_compressor {
+
+ struct compressor *dce112_compressor_create(struct dc_context *ctx);
+
+-bool dce112_compressor_construct(struct dce112_compressor *cp110,
++void dce112_compressor_construct(struct dce112_compressor *cp110,
+ struct dc_context *ctx);
+
+ void dce112_compressor_destroy(struct compressor **cp);
+diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c
+index 8816e09..1e4a7c1 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c
+@@ -152,14 +152,12 @@ static bool dce112_enable_display_power_gating(
+ return false;
+ }
+
+-bool dce112_hw_sequencer_construct(struct dc *dc)
++void dce112_hw_sequencer_construct(struct dc *dc)
+ {
+ /* All registers used by dce11.2 match those in dce11 in offset and
+ * structure
+ */
+ dce110_hw_sequencer_construct(dc);
+ dc->hwss.enable_display_power_gating = dce112_enable_display_power_gating;
+-
+- return true;
+ }
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h
+index 37bd60c..e646f4a 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h
+@@ -30,7 +30,7 @@
+
+ struct dc;
+
+-bool dce112_hw_sequencer_construct(struct dc *dc);
++void dce112_hw_sequencer_construct(struct dc *dc);
+
+ #endif /* __DC_HWSS_DCE112_H__ */
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+index 251e4a2..11902a2 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
+@@ -1256,8 +1256,7 @@ static bool construct(
+ dc->caps.max_planes = pool->base.pipe_count;
+
+ /* Create hardware sequencer */
+- if (!dce112_hw_sequencer_construct(dc))
+- goto res_create_fail;
++ dce112_hw_sequencer_construct(dc);
+
+ bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
+index 30f4ac0..75d0297 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
+@@ -245,7 +245,7 @@ static void dce120_update_dchub(
+
+
+
+-bool dce120_hw_sequencer_construct(struct dc *dc)
++void dce120_hw_sequencer_construct(struct dc *dc)
+ {
+ /* All registers used by dce11.2 match those in dce11 in offset and
+ * structure
+@@ -253,7 +253,5 @@ bool dce120_hw_sequencer_construct(struct dc *dc)
+ dce110_hw_sequencer_construct(dc);
+ dc->hwss.enable_display_power_gating = dce120_enable_display_power_gating;
+ dc->hwss.update_dchub = dce120_update_dchub;
+-
+- return true;
+ }
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h
+index 6448a17..77a6b86 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h
+@@ -30,7 +30,7 @@
+
+ struct dc;
+
+-bool dce120_hw_sequencer_construct(struct dc *dc);
++void dce120_hw_sequencer_construct(struct dc *dc);
+
+ #endif /* __DC_HWSS_DCE112_H__ */
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+index 46ba6ae..e93ad74 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+@@ -429,12 +429,8 @@ static struct timing_generator *dce120_timing_generator_create(
+ if (!tg110)
+ return NULL;
+
+- if (dce120_timing_generator_construct(tg110, ctx, instance, offsets))
+- return &tg110->base;
+-
+- BREAK_TO_DEBUGGER();
+- kfree(tg110);
+- return NULL;
++ dce120_timing_generator_construct(tg110, ctx, instance, offsets);
++ return &tg110->base;
+ }
+
+ static void dce120_transform_destroy(struct transform **xfm)
+diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+index 323ff2c..1d4efb0 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
+@@ -1143,15 +1143,12 @@ static const struct timing_generator_funcs dce120_tg_funcs = {
+ };
+
+
+-bool dce120_timing_generator_construct(
++void dce120_timing_generator_construct(
+ struct dce110_timing_generator *tg110,
+ struct dc_context *ctx,
+ uint32_t instance,
+ const struct dce110_timing_generator_offsets *offsets)
+ {
+- if (!tg110)
+- return false;
+-
+ tg110->controller_id = CONTROLLER_ID_D0 + instance;
+ tg110->base.inst = instance;
+
+@@ -1175,6 +1172,4 @@ bool dce120_timing_generator_construct(
+ tg110->min_h_sync_width = 8;
+ tg110->min_v_sync_width = 1;
+ tg110->min_v_blank = 3;
+-
+- return true;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.h
+index 243c0a3..d69871e 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.h
++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.h
+@@ -32,7 +32,7 @@
+ #include "dce110/dce110_timing_generator.h"
+
+
+-bool dce120_timing_generator_construct(
++void dce120_timing_generator_construct(
+ struct dce110_timing_generator *tg110,
+ struct dc_context *ctx,
+ uint32_t instance,
+diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c
+index cc1c0d3..951f2ca 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c
++++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c
+@@ -771,7 +771,7 @@ void dce80_compressor_set_fbc_invalidation_triggers(
+ dm_write_reg(compressor->ctx, addr, value);
+ }
+
+-bool dce80_compressor_construct(struct dce80_compressor *compressor,
++void dce80_compressor_construct(struct dce80_compressor *compressor,
+ struct dc_context *ctx)
+ {
+ struct dc_bios *bp = ctx->dc_bios;
+@@ -813,7 +813,6 @@ bool dce80_compressor_construct(struct dce80_compressor *compressor,
+ compressor->base.embedded_panel_v_size =
+ panel_info.lcd_timing.vertical_addressable;
+ }
+- return true;
+ }
+
+ struct compressor *dce80_compressor_create(struct dc_context *ctx)
+@@ -824,12 +823,8 @@ struct compressor *dce80_compressor_create(struct dc_context *ctx)
+ if (!cp80)
+ return NULL;
+
+- if (dce80_compressor_construct(cp80, ctx))
+- return &cp80->base;
+-
+- BREAK_TO_DEBUGGER();
+- kfree(cp80);
+- return NULL;
++ dce80_compressor_construct(cp80, ctx);
++ return &cp80->base;
+ }
+
+ void dce80_compressor_destroy(struct compressor **compressor)
+diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.h b/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.h
+index 0129096..cca58b0 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.h
++++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.h
+@@ -42,7 +42,7 @@ struct dce80_compressor {
+
+ struct compressor *dce80_compressor_create(struct dc_context *ctx);
+
+-bool dce80_compressor_construct(struct dce80_compressor *cp80,
++void dce80_compressor_construct(struct dce80_compressor *cp80,
+ struct dc_context *ctx);
+
+ void dce80_compressor_destroy(struct compressor **cp);
+diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c
+index 28fe382..ccfcf1c 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c
+@@ -106,14 +106,12 @@ static bool dce80_enable_display_power_gating(
+ return false;
+ }
+
+-bool dce80_hw_sequencer_construct(struct dc *dc)
++void dce80_hw_sequencer_construct(struct dc *dc)
+ {
+ dce110_hw_sequencer_construct(dc);
+
+ dc->hwss.enable_display_power_gating = dce80_enable_display_power_gating;
+ dc->hwss.pipe_control_lock = dce_pipe_control_lock;
+ dc->hwss.set_bandwidth = dce100_set_bandwidth;
+-
+- return true;
+ }
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h
+index 9d6dd05..7a1b31d 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h
++++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h
+@@ -30,7 +30,7 @@
+
+ struct dc;
+
+-bool dce80_hw_sequencer_construct(struct dc *dc);
++void dce80_hw_sequencer_construct(struct dc *dc);
+
+ #endif /* __DC_HWSS_DCE80_H__ */
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+index 5e00ca6..c6571a9 100644
+--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+@@ -910,8 +910,7 @@ static bool dce80_construct(
+ goto res_create_fail;
+
+ /* Create hardware sequencer */
+- if (!dce80_hw_sequencer_construct(dc))
+- goto res_create_fail;
++ dce80_hw_sequencer_construct(dc);
+
+ return true;
+
+@@ -1075,8 +1074,7 @@ static bool dce81_construct(
+ goto res_create_fail;
+
+ /* Create hardware sequencer */
+- if (!dce80_hw_sequencer_construct(dc))
+- goto res_create_fail;
++ dce80_hw_sequencer_construct(dc);
+
+ return true;
+
+@@ -1236,8 +1234,7 @@ static bool dce83_construct(
+ goto res_create_fail;
+
+ /* Create hardware sequencer */
+- if (!dce80_hw_sequencer_construct(dc))
+- goto res_create_fail;
++ dce80_hw_sequencer_construct(dc);
+
+ return true;
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+index 8607ab2..9d9604f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+@@ -397,7 +397,7 @@ static const struct transform_funcs dcn10_dpp_funcs = {
+ /* Constructor, Destructor */
+ /*****************************************/
+
+-bool dcn10_dpp_construct(
++void dcn10_dpp_construct(
+ struct dcn10_dpp *xfm,
+ struct dc_context *ctx,
+ uint32_t inst,
+@@ -421,6 +421,4 @@ bool dcn10_dpp_construct(
+
+ xfm->lb_bits_per_entry = LB_BITS_PER_ENTRY;
+ xfm->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/
+-
+- return true;
+ }
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+index afe9d8f..a1f6b01 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+@@ -1356,7 +1356,7 @@ void ippn10_cnv_setup (
+
+ void ippn10_full_bypass(struct transform *xfm_base);
+
+-bool dcn10_dpp_construct(struct dcn10_dpp *xfm110,
++void dcn10_dpp_construct(struct dcn10_dpp *xfm110,
+ struct dc_context *ctx,
+ uint32_t inst,
+ const struct dcn_dpp_registers *tf_regs,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
+index 9008cd0..c808848 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
+@@ -786,7 +786,7 @@ static struct mem_input_funcs dcn10_mem_input_funcs = {
+ /* Constructor, Destructor */
+ /*****************************************/
+
+-bool dcn10_mem_input_construct(
++void dcn10_mem_input_construct(
+ struct dcn10_mem_input *mi,
+ struct dc_context *ctx,
+ uint32_t inst,
+@@ -802,7 +802,5 @@ bool dcn10_mem_input_construct(
+ mi->base.inst = inst;
+ mi->base.opp_id = 0xf;
+ mi->base.mpcc_id = 0xf;
+-
+- return true;
+ }
+
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
+index acee051..aefd3e7 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
+@@ -538,7 +538,7 @@ struct dcn10_mem_input {
+ const struct dcn_mi_mask *mi_mask;
+ };
+
+-bool dcn10_mem_input_construct(
++void dcn10_mem_input_construct(
+ struct dcn10_mem_input *mi,
+ struct dc_context *ctx,
+ uint32_t inst,
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+index c941a22..4fa883f 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+@@ -462,13 +462,9 @@ static struct transform *dcn10_dpp_create(
+ if (!dpp)
+ return NULL;
+
+- if (dcn10_dpp_construct(dpp, ctx, inst,
+- &tf_regs[inst], &tf_shift, &tf_mask))
+- return &dpp->base;
+-
+- BREAK_TO_DEBUGGER();
+- kfree(dpp);
+- return NULL;
++ dcn10_dpp_construct(dpp, ctx, inst,
++ &tf_regs[inst], &tf_shift, &tf_mask);
++ return &dpp->base;
+ }
+
+ static struct input_pixel_processor *dcn10_ipp_create(
+@@ -771,13 +767,9 @@ static struct mem_input *dcn10_mem_input_create(
+ if (!mem_inputn10)
+ return NULL;
+
+- if (dcn10_mem_input_construct(mem_inputn10, ctx, inst,
+- &mi_regs[inst], &mi_shift, &mi_mask))
+- return &mem_inputn10->base;
+-
+- BREAK_TO_DEBUGGER();
+- kfree(mem_inputn10);
+- return NULL;
++ dcn10_mem_input_construct(mem_inputn10, ctx, inst,
++ &mi_regs[inst], &mi_shift, &mi_mask);
++ return &mem_inputn10->base;
+ }
+
+ static void get_pixel_clock_parameters(
+--
+2.7.4
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-05-01 02:34:24 +0000