diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2420-amdgpu-dc-constify-a-bunch-of-dc-structs.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2420-amdgpu-dc-constify-a-bunch-of-dc-structs.patch | 110 |
1 files changed, 110 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2420-amdgpu-dc-constify-a-bunch-of-dc-structs.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2420-amdgpu-dc-constify-a-bunch-of-dc-structs.patch new file mode 100644 index 00000000..8e8633e2 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2420-amdgpu-dc-constify-a-bunch-of-dc-structs.patch @@ -0,0 +1,110 @@ +From 489ed5c63cd51d68a2052f81f25b31c14723ca19 Mon Sep 17 00:00:00 2001 +From: Dave Airlie <airlied@redhat.com> +Date: Fri, 29 Sep 2017 10:39:29 +1000 +Subject: [PATCH 2420/4131] amdgpu/dc: constify a bunch of dc structs. + +Signed-off-by: Dave Airlie <airlied@redhat.com> +Reviewed-by: Harry Wentland <harry.wentland@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 8 ++++---- + drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | 2 +- + drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c | 2 +- + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 2 +- + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c | 2 +- + 5 files changed, 8 insertions(+), 8 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c +index 3e9ff2f5..9031d22 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c +@@ -51,7 +51,7 @@ + clk_dce->base.ctx + + /* Max clock values for each state indexed by "enum clocks_state": */ +-static struct state_dependent_clocks dce80_max_clks_by_state[] = { ++static const struct state_dependent_clocks dce80_max_clks_by_state[] = { + /* ClocksStateInvalid - should not be used */ + { .display_clk_khz = 0, .pixel_clk_khz = 0 }, + /* ClocksStateUltraLow - not expected to be used for DCE 8.0 */ +@@ -63,7 +63,7 @@ static struct state_dependent_clocks dce80_max_clks_by_state[] = { + /* ClocksStatePerformance */ + { .display_clk_khz = 600000, .pixel_clk_khz = 400000 } }; + +-static struct state_dependent_clocks dce110_max_clks_by_state[] = { ++static const struct state_dependent_clocks dce110_max_clks_by_state[] = { + /*ClocksStateInvalid - should not be used*/ + { .display_clk_khz = 0, .pixel_clk_khz = 0 }, + /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/ +@@ -75,7 +75,7 @@ static struct state_dependent_clocks dce110_max_clks_by_state[] = { + /*ClocksStatePerformance*/ + { .display_clk_khz = 643000, .pixel_clk_khz = 400000 } }; + +-static struct state_dependent_clocks dce112_max_clks_by_state[] = { ++static const struct state_dependent_clocks dce112_max_clks_by_state[] = { + /*ClocksStateInvalid - should not be used*/ + { .display_clk_khz = 0, .pixel_clk_khz = 0 }, + /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/ +@@ -87,7 +87,7 @@ static struct state_dependent_clocks dce112_max_clks_by_state[] = { + /*ClocksStatePerformance*/ + { .display_clk_khz = 1132000, .pixel_clk_khz = 600000 } }; + +-static struct state_dependent_clocks dce120_max_clks_by_state[] = { ++static const struct state_dependent_clocks dce120_max_clks_by_state[] = { + /*ClocksStateInvalid - should not be used*/ + { .display_clk_khz = 0, .pixel_clk_khz = 0 }, + /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/ +diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +index 73e091a..e51d8ba 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +@@ -302,7 +302,7 @@ static const struct dce_opp_mask opp_mask = { + AUD_COMMON_REG_LIST(id)\ + } + +-static struct dce_audio_registers audio_regs[] = { ++static const struct dce_audio_registers audio_regs[] = { + audio_regs(0), + audio_regs(1), + audio_regs(2), +diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c +index 42d492b..323ff2c 100644 +--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c ++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c +@@ -1109,7 +1109,7 @@ static bool dce120_arm_vert_intr( + return true; + } + +-static struct timing_generator_funcs dce120_tg_funcs = { ++static const struct timing_generator_funcs dce120_tg_funcs = { + .validate_timing = dce120_tg_validate_timing, + .program_timing = dce120_tg_program_timing, + .enable_crtc = dce120_timing_generator_enable_crtc, +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c +index 4876941..ac03b04 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c +@@ -373,7 +373,7 @@ void ippn10_cnv_setup ( + } + } + +-static struct transform_funcs dcn10_dpp_funcs = { ++static const struct transform_funcs dcn10_dpp_funcs = { + .transform_reset = dpp_reset, + .transform_set_scaler = dcn10_dpp_dscl_set_scaler_manual_scale, + .transform_get_optimal_number_of_taps = dpp_get_optimal_number_of_taps, +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c +index 2d3dd9a..7cd10cbc 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c +@@ -1146,7 +1146,7 @@ void tgn10_read_otg_state(struct dcn10_timing_generator *tgn10, + } + + +-static struct timing_generator_funcs dcn10_tg_funcs = { ++static const struct timing_generator_funcs dcn10_tg_funcs = { + .validate_timing = tgn10_validate_timing, + .program_timing = tgn10_program_timing, + .program_global_sync = tgn10_program_global_sync, +-- +2.7.4 + |