diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2371-drm-amd-display-remove-output_format-from-ipp_setup.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2371-drm-amd-display-remove-output_format-from-ipp_setup.patch | 110 |
1 files changed, 110 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2371-drm-amd-display-remove-output_format-from-ipp_setup.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2371-drm-amd-display-remove-output_format-from-ipp_setup.patch new file mode 100644 index 00000000..2883cbab --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2371-drm-amd-display-remove-output_format-from-ipp_setup.patch @@ -0,0 +1,110 @@ +From 81086a3a0e8b2749743ad6e59b01a8b3a6fd8aca Mon Sep 17 00:00:00 2001 +From: Eric Bernstein <eric.bernstein@amd.com> +Date: Thu, 31 Aug 2017 16:04:24 -0400 +Subject: [PATCH 2371/4131] drm/amd/display: remove output_format from + ipp_setup + +Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> +Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> +Acked-by: Harry Wentland <Harry.Wentland@amd.com> +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +--- + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 3 +-- + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 3 +-- + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | 4 ++-- + drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 +-- + drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h | 3 +-- + drivers/gpu/drm/amd/display/dc/inc/hw/transform.h | 3 +-- + 6 files changed, 7 insertions(+), 12 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c +index 99caafb..4876941 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c +@@ -266,8 +266,7 @@ static void ippn10_set_degamma_format_float( + void ippn10_cnv_setup ( + struct transform *xfm_base, + enum surface_pixel_format input_format, +- enum expansion_mode mode, +- enum ipp_output_format cnv_out_format) ++ enum expansion_mode mode) + { + uint32_t pixel_format; + uint32_t alpha_en; +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h +index 70d6ba0..34e5019 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h +@@ -1358,8 +1358,7 @@ void dcn10_dpp_dscl_set_scaler_manual_scale( + void ippn10_cnv_setup ( + struct transform *xfm_base, + enum surface_pixel_format input_format, +- enum expansion_mode mode, +- enum ipp_output_format cnv_out_format); ++ enum expansion_mode mode); + + void ippn10_full_bypass(struct transform *xfm_base); + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c +index 840dd03..d0e72ac 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c +@@ -727,11 +727,11 @@ void ippn10_full_bypass(struct transform *xfm_base) + FORMAT_EXPANSION_MODE, 0); + + /* COLOR_KEYER_CONTROL.COLOR_KEYER_EN = 0 this should be default */ +- REG_SET(CM_CONTROL, 0, CM_BYPASS_EN, 1); ++ if (xfm->tf_mask->CM_BYPASS_EN) ++ REG_SET(CM_CONTROL, 0, CM_BYPASS_EN, 1); + + /* Setting degamma bypass for now */ + REG_SET(CM_DGAM_CONTROL, 0, CM_DGAM_LUT_MODE, 0); +- REG_SET(CM_IGAM_CONTROL, 0, CM_IGAM_LUT_MODE, 0); + } + + static bool ippn10_ingamma_ram_inuse(struct transform *xfm_base, +diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +index a1f4a00..6fee695 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +@@ -2316,8 +2316,7 @@ static void update_dchubp_dpp( + + xfm->funcs->ipp_setup(xfm, + plane_state->format, +- 1, +- IPP_OUTPUT_FORMAT_12_BIT_FIX); ++ EXPANSION_MODE_ZERO); + + mpcc_cfg.mi = mi; + mpcc_cfg.opp = pipe_ctx->stream_res.opp; +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h +index 7ebfdc1..f11aa48 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h +@@ -86,8 +86,7 @@ struct ipp_funcs { + void (*ipp_setup)( + struct input_pixel_processor *ipp, + enum surface_pixel_format input_format, +- enum expansion_mode mode, +- enum ipp_output_format output_format); ++ enum expansion_mode mode); + + /* DCE function to setup IPP. TODO: see if we can consolidate to setup */ + void (*ipp_program_prescale)( +diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h +index 623042d..3294745 100644 +--- a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h +@@ -234,8 +234,7 @@ struct transform_funcs { + void (*ipp_setup)( + struct transform *xfm_base, + enum surface_pixel_format input_format, +- enum expansion_mode mode, +- enum ipp_output_format cnv_out_format); ++ enum expansion_mode mode); + + void (*ipp_full_bypass)(struct transform *xfm_base); + +-- +2.7.4 + |