diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2258-drm-amd-include-cleanup-vega10-nbif-header-files.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2258-drm-amd-include-cleanup-vega10-nbif-header-files.patch | 25278 |
1 files changed, 25278 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2258-drm-amd-include-cleanup-vega10-nbif-header-files.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2258-drm-amd-include-cleanup-vega10-nbif-header-files.patch new file mode 100644 index 00000000..2d1a5e18 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2258-drm-amd-include-cleanup-vega10-nbif-header-files.patch @@ -0,0 +1,25278 @@ +From d40f09a6751bab235a7b6666469c327e55662e1b Mon Sep 17 00:00:00 2001 +From: Feifei Xu <Feifei.Xu@amd.com> +Date: Thu, 23 Nov 2017 15:02:23 +0800 +Subject: [PATCH 2258/4131] drm/amd/include:cleanup vega10 nbif header files. + +Cleanup asic_reg/vega10/NBIF folder. + +Change-Id: Iafd95103840eed8bcf0f2a7312fcbe85f4f99cd5 +Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 2 +- + .../amd/include/asic_reg/nbif/nbif_6_1_offset.h | 1688 +++ + .../amd/include/asic_reg/nbif/nbif_6_1_sh_mask.h | 10281 +++++++++++++++++++ + .../asic_reg/vega10/NBIF/nbif_6_1_default.h | 1271 --- + .../include/asic_reg/vega10/NBIF/nbif_6_1_offset.h | 1688 --- + .../asic_reg/vega10/NBIF/nbif_6_1_sh_mask.h | 10281 ------------------- + 6 files changed, 11970 insertions(+), 13241 deletions(-) + create mode 100644 drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_offset.h + create mode 100644 drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_sh_mask.h + delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_default.h + delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_offset.h + delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_sh_mask.h + +diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +index 19beff3..c271c6b 100644 +--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +@@ -35,7 +35,7 @@ + #include "vce/vce_4_0_offset.h" + #include "vce/vce_4_0_default.h" + #include "vce/vce_4_0_sh_mask.h" +-#include "vega10/NBIF/nbif_6_1_offset.h" ++#include "nbif/nbif_6_1_offset.h" + #include "hdp/hdp_4_0_offset.h" + #include "mmhub/mmhub_1_0_offset.h" + #include "mmhub/mmhub_1_0_sh_mask.h" +diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_offset.h +new file mode 100644 +index 0000000..68d0ffa +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_offset.h +@@ -0,0 +1,1688 @@ ++/* ++ * Copyright (C) 2017 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#ifndef _nbif_6_1_OFFSET_HEADER ++#define _nbif_6_1_OFFSET_HEADER ++ ++ ++// addressBlock: bif_cfg_dev0_epf0_bifcfgdecp ++// base address: 0x0 ++#define cfgVENDOR_ID 0x0000 // duplicate ++#define cfgDEVICE_ID 0x0002 // duplicate ++#define cfgCOMMAND 0x0004 // duplicate ++#define cfgSTATUS 0x0006 // duplicate ++#define cfgREVISION_ID 0x0008 // duplicate ++#define cfgPROG_INTERFACE 0x0009 // duplicate ++#define cfgSUB_CLASS 0x000a // duplicate ++#define cfgBASE_CLASS 0x000b // duplicate ++#define cfgCACHE_LINE 0x000c // duplicate ++#define cfgLATENCY 0x000d // duplicate ++#define cfgHEADER 0x000e // duplicate ++#define cfgBIST 0x000f // duplicate ++#define cfgBASE_ADDR_1 0x0010 // duplicate ++#define cfgBASE_ADDR_2 0x0014 // duplicate ++#define cfgBASE_ADDR_3 0x0018 // duplicate ++#define cfgBASE_ADDR_4 0x001c // duplicate ++#define cfgBASE_ADDR_5 0x0020 // duplicate ++#define cfgBASE_ADDR_6 0x0024 // duplicate ++#define cfgADAPTER_ID 0x002c // duplicate ++#define cfgROM_BASE_ADDR 0x0030 // duplicate ++#define cfgCAP_PTR 0x0034 // duplicate ++#define cfgINTERRUPT_LINE 0x003c // duplicate ++#define cfgINTERRUPT_PIN 0x003d // duplicate ++#define cfgMIN_GRANT 0x003e // duplicate ++#define cfgMAX_LATENCY 0x003f // duplicate ++#define cfgVENDOR_CAP_LIST 0x0048 // duplicate ++#define cfgADAPTER_ID_W 0x004c // duplicate ++#define cfgPMI_CAP_LIST 0x0050 // duplicate ++#define cfgPMI_CAP 0x0052 // duplicate ++#define cfgPMI_STATUS_CNTL 0x0054 // duplicate ++#define cfgPCIE_CAP_LIST 0x0064 // duplicate ++#define cfgPCIE_CAP 0x0066 // duplicate ++#define cfgDEVICE_CAP 0x0068 // duplicate ++#define cfgDEVICE_CNTL 0x006c // duplicate ++#define cfgDEVICE_STATUS 0x006e // duplicate ++#define cfgLINK_CAP 0x0070 // duplicate ++#define cfgLINK_CNTL 0x0074 // duplicate ++#define cfgLINK_STATUS 0x0076 // duplicate ++#define cfgDEVICE_CAP2 0x0088 // duplicate ++#define cfgDEVICE_CNTL2 0x008c // duplicate ++#define cfgDEVICE_STATUS2 0x008e // duplicate ++#define cfgLINK_CAP2 0x0090 // duplicate ++#define cfgLINK_CNTL2 0x0094 // duplicate ++#define cfgLINK_STATUS2 0x0096 // duplicate ++#define cfgSLOT_CAP2 0x0098 // duplicate ++#define cfgSLOT_CNTL2 0x009c // duplicate ++#define cfgSLOT_STATUS2 0x009e // duplicate ++#define cfgMSI_CAP_LIST 0x00a0 // duplicate ++#define cfgMSI_MSG_CNTL 0x00a2 // duplicate ++#define cfgMSI_MSG_ADDR_LO 0x00a4 // duplicate ++#define cfgMSI_MSG_ADDR_HI 0x00a8 // duplicate ++#define cfgMSI_MSG_DATA 0x00a8 // duplicate ++#define cfgMSI_MSG_DATA_64 0x00ac // duplicate ++#define cfgMSI_MASK 0x00ac // duplicate ++#define cfgMSI_PENDING 0x00b0 // duplicate ++#define cfgMSI_MASK_64 0x00b0 // duplicate ++#define cfgMSI_PENDING_64 0x00b4 // duplicate ++#define cfgMSIX_CAP_LIST 0x00c0 // duplicate ++#define cfgMSIX_MSG_CNTL 0x00c2 // duplicate ++#define cfgMSIX_TABLE 0x00c4 // duplicate ++#define cfgMSIX_PBA 0x00c8 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR 0x0104 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC1 0x0108 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC2 0x010c // duplicate ++#define cfgPCIE_VC_ENH_CAP_LIST 0x0110 // duplicate ++#define cfgPCIE_PORT_VC_CAP_REG1 0x0114 // duplicate ++#define cfgPCIE_PORT_VC_CAP_REG2 0x0118 // duplicate ++#define cfgPCIE_PORT_VC_CNTL 0x011c // duplicate ++#define cfgPCIE_PORT_VC_STATUS 0x011e // duplicate ++#define cfgPCIE_VC0_RESOURCE_CAP 0x0120 // duplicate ++#define cfgPCIE_VC0_RESOURCE_CNTL 0x0124 // duplicate ++#define cfgPCIE_VC0_RESOURCE_STATUS 0x012a // duplicate ++#define cfgPCIE_VC1_RESOURCE_CAP 0x012c // duplicate ++#define cfgPCIE_VC1_RESOURCE_CNTL 0x0130 // duplicate ++#define cfgPCIE_VC1_RESOURCE_STATUS 0x0136 // duplicate ++#define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 // duplicate ++#define cfgPCIE_DEV_SERIAL_NUM_DW1 0x0144 // duplicate ++#define cfgPCIE_DEV_SERIAL_NUM_DW2 0x0148 // duplicate ++#define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 // duplicate ++#define cfgPCIE_UNCORR_ERR_STATUS 0x0154 // duplicate ++#define cfgPCIE_UNCORR_ERR_MASK 0x0158 // duplicate ++#define cfgPCIE_UNCORR_ERR_SEVERITY 0x015c // duplicate ++#define cfgPCIE_CORR_ERR_STATUS 0x0160 // duplicate ++#define cfgPCIE_CORR_ERR_MASK 0x0164 // duplicate ++#define cfgPCIE_ADV_ERR_CAP_CNTL 0x0168 // duplicate ++#define cfgPCIE_HDR_LOG0 0x016c // duplicate ++#define cfgPCIE_HDR_LOG1 0x0170 // duplicate ++#define cfgPCIE_HDR_LOG2 0x0174 // duplicate ++#define cfgPCIE_HDR_LOG3 0x0178 // duplicate ++#define cfgPCIE_ROOT_ERR_CMD 0x017c // duplicate ++#define cfgPCIE_ROOT_ERR_STATUS 0x0180 // duplicate ++#define cfgPCIE_ERR_SRC_ID 0x0184 // duplicate ++#define cfgPCIE_TLP_PREFIX_LOG0 0x0188 // duplicate ++#define cfgPCIE_TLP_PREFIX_LOG1 0x018c // duplicate ++#define cfgPCIE_TLP_PREFIX_LOG2 0x0190 // duplicate ++#define cfgPCIE_TLP_PREFIX_LOG3 0x0194 // duplicate ++#define cfgPCIE_BAR_ENH_CAP_LIST 0x0200 // duplicate ++#define cfgPCIE_BAR1_CAP 0x0204 // duplicate ++#define cfgPCIE_BAR1_CNTL 0x0208 // duplicate ++#define cfgPCIE_BAR2_CAP 0x020c // duplicate ++#define cfgPCIE_BAR2_CNTL 0x0210 // duplicate ++#define cfgPCIE_BAR3_CAP 0x0214 // duplicate ++#define cfgPCIE_BAR3_CNTL 0x0218 // duplicate ++#define cfgPCIE_BAR4_CAP 0x021c // duplicate ++#define cfgPCIE_BAR4_CNTL 0x0220 // duplicate ++#define cfgPCIE_BAR5_CAP 0x0224 // duplicate ++#define cfgPCIE_BAR5_CNTL 0x0228 // duplicate ++#define cfgPCIE_BAR6_CAP 0x022c // duplicate ++#define cfgPCIE_BAR6_CNTL 0x0230 // duplicate ++#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 // duplicate ++#define cfgPCIE_PWR_BUDGET_DATA_SELECT 0x0244 // duplicate ++#define cfgPCIE_PWR_BUDGET_DATA 0x0248 // duplicate ++#define cfgPCIE_PWR_BUDGET_CAP 0x024c // duplicate ++#define cfgPCIE_DPA_ENH_CAP_LIST 0x0250 // duplicate ++#define cfgPCIE_DPA_CAP 0x0254 // duplicate ++#define cfgPCIE_DPA_LATENCY_INDICATOR 0x0258 // duplicate ++#define cfgPCIE_DPA_STATUS 0x025c // duplicate ++#define cfgPCIE_DPA_CNTL 0x025e // duplicate ++#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 // duplicate ++#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 // duplicate ++#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 // duplicate ++#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 // duplicate ++#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 // duplicate ++#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 // duplicate ++#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 // duplicate ++#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 // duplicate ++#define cfgPCIE_SECONDARY_ENH_CAP_LIST 0x0270 // duplicate ++#define cfgPCIE_LINK_CNTL3 0x0274 // duplicate ++#define cfgPCIE_LANE_ERROR_STATUS 0x0278 // duplicate ++#define cfgPCIE_LANE_0_EQUALIZATION_CNTL 0x027c // duplicate ++#define cfgPCIE_LANE_1_EQUALIZATION_CNTL 0x027e // duplicate ++#define cfgPCIE_LANE_2_EQUALIZATION_CNTL 0x0280 // duplicate ++#define cfgPCIE_LANE_3_EQUALIZATION_CNTL 0x0282 // duplicate ++#define cfgPCIE_LANE_4_EQUALIZATION_CNTL 0x0284 // duplicate ++#define cfgPCIE_LANE_5_EQUALIZATION_CNTL 0x0286 // duplicate ++#define cfgPCIE_LANE_6_EQUALIZATION_CNTL 0x0288 // duplicate ++#define cfgPCIE_LANE_7_EQUALIZATION_CNTL 0x028a // duplicate ++#define cfgPCIE_LANE_8_EQUALIZATION_CNTL 0x028c // duplicate ++#define cfgPCIE_LANE_9_EQUALIZATION_CNTL 0x028e // duplicate ++#define cfgPCIE_LANE_10_EQUALIZATION_CNTL 0x0290 // duplicate ++#define cfgPCIE_LANE_11_EQUALIZATION_CNTL 0x0292 // duplicate ++#define cfgPCIE_LANE_12_EQUALIZATION_CNTL 0x0294 // duplicate ++#define cfgPCIE_LANE_13_EQUALIZATION_CNTL 0x0296 // duplicate ++#define cfgPCIE_LANE_14_EQUALIZATION_CNTL 0x0298 // duplicate ++#define cfgPCIE_LANE_15_EQUALIZATION_CNTL 0x029a // duplicate ++#define cfgPCIE_ACS_ENH_CAP_LIST 0x02a0 // duplicate ++#define cfgPCIE_ACS_CAP 0x02a4 // duplicate ++#define cfgPCIE_ACS_CNTL 0x02a6 // duplicate ++#define cfgPCIE_ATS_ENH_CAP_LIST 0x02b0 // duplicate ++#define cfgPCIE_ATS_CAP 0x02b4 // duplicate ++#define cfgPCIE_ATS_CNTL 0x02b6 // duplicate ++#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0 // duplicate ++#define cfgPCIE_PAGE_REQ_CNTL 0x02c4 // duplicate ++#define cfgPCIE_PAGE_REQ_STATUS 0x02c6 // duplicate ++#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8 // duplicate ++#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc // duplicate ++#define cfgPCIE_PASID_ENH_CAP_LIST 0x02d0 // duplicate ++#define cfgPCIE_PASID_CAP 0x02d4 // duplicate ++#define cfgPCIE_PASID_CNTL 0x02d6 // duplicate ++#define cfgPCIE_TPH_REQR_ENH_CAP_LIST 0x02e0 // duplicate ++#define cfgPCIE_TPH_REQR_CAP 0x02e4 // duplicate ++#define cfgPCIE_TPH_REQR_CNTL 0x02e8 // duplicate ++#define cfgPCIE_MC_ENH_CAP_LIST 0x02f0 // duplicate ++#define cfgPCIE_MC_CAP 0x02f4 // duplicate ++#define cfgPCIE_MC_CNTL 0x02f6 // duplicate ++#define cfgPCIE_MC_ADDR0 0x02f8 // duplicate ++#define cfgPCIE_MC_ADDR1 0x02fc // duplicate ++#define cfgPCIE_MC_RCV0 0x0300 // duplicate ++#define cfgPCIE_MC_RCV1 0x0304 // duplicate ++#define cfgPCIE_MC_BLOCK_ALL0 0x0308 // duplicate ++#define cfgPCIE_MC_BLOCK_ALL1 0x030c // duplicate ++#define cfgPCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 // duplicate ++#define cfgPCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 // duplicate ++#define cfgPCIE_LTR_ENH_CAP_LIST 0x0320 // duplicate ++#define cfgPCIE_LTR_CAP 0x0324 // duplicate ++#define cfgPCIE_ARI_ENH_CAP_LIST 0x0328 // duplicate ++#define cfgPCIE_ARI_CAP 0x032c // duplicate ++#define cfgPCIE_ARI_CNTL 0x032e // duplicate ++#define cfgPCIE_SRIOV_ENH_CAP_LIST 0x0330 // duplicate ++#define cfgPCIE_SRIOV_CAP 0x0334 // duplicate ++#define cfgPCIE_SRIOV_CONTROL 0x0338 // duplicate ++#define cfgPCIE_SRIOV_STATUS 0x033a // duplicate ++#define cfgPCIE_SRIOV_INITIAL_VFS 0x033c // duplicate ++#define cfgPCIE_SRIOV_TOTAL_VFS 0x033e // duplicate ++#define cfgPCIE_SRIOV_NUM_VFS 0x0340 // duplicate ++#define cfgPCIE_SRIOV_FUNC_DEP_LINK 0x0342 // duplicate ++#define cfgPCIE_SRIOV_FIRST_VF_OFFSET 0x0344 // duplicate ++#define cfgPCIE_SRIOV_VF_STRIDE 0x0346 // duplicate ++#define cfgPCIE_SRIOV_VF_DEVICE_ID 0x034a // duplicate ++#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c // duplicate ++#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 // duplicate ++#define cfgPCIE_SRIOV_VF_BASE_ADDR_0 0x0354 // duplicate ++#define cfgPCIE_SRIOV_VF_BASE_ADDR_1 0x0358 // duplicate ++#define cfgPCIE_SRIOV_VF_BASE_ADDR_2 0x035c // duplicate ++#define cfgPCIE_SRIOV_VF_BASE_ADDR_3 0x0360 // duplicate ++#define cfgPCIE_SRIOV_VF_BASE_ADDR_4 0x0364 // duplicate ++#define cfgPCIE_SRIOV_VF_BASE_ADDR_5 0x0368 // duplicate ++#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0400 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0404 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0408 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x040c // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0410 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0414 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0418 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x041c // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x0420 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0424 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0428 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x042c // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0430 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x0434 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x0438 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x043c // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0440 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x0444 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x0448 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x044c // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0450 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x0454 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x0458 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x045c // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0460 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x0464 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x0468 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x046c // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0x0470 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0x0474 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0x0478 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0x047c // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0x0480 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0x0484 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0x0488 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0x048c // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0x0490 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0x0494 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0x0498 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0x049c // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0x04a0 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0x04a4 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0x04a8 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0x04ac // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0x04b0 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0x04b4 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0x04b8 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0x04bc // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0x04c0 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0x04c4 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0x04c8 // duplicate ++#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0x04cc // duplicate ++ ++ ++// addressBlock: bif_cfg_dev0_swds_bifcfgdecp ++// base address: 0x0 ++#define mmSUB_BUS_NUMBER_LATENCY 0x0006 // duplicate ++#define mmSUB_BUS_NUMBER_LATENCY_BASE_IDX 0 ++#define mmIO_BASE_LIMIT 0x0007 // duplicate ++#define mmIO_BASE_LIMIT_BASE_IDX 0 ++#define mmSECONDARY_STATUS 0x0007 // duplicate ++#define mmSECONDARY_STATUS_BASE_IDX 0 ++#define mmMEM_BASE_LIMIT 0x0008 // duplicate ++#define mmMEM_BASE_LIMIT_BASE_IDX 0 ++#define mmPREF_BASE_LIMIT 0x0009 // duplicate ++#define mmPREF_BASE_LIMIT_BASE_IDX 0 ++#define mmPREF_BASE_UPPER 0x000a // duplicate ++#define mmPREF_BASE_UPPER_BASE_IDX 0 ++#define mmPREF_LIMIT_UPPER 0x000b // duplicate ++#define mmPREF_LIMIT_UPPER_BASE_IDX 0 ++#define mmIO_BASE_LIMIT_HI 0x000c // duplicate ++#define mmIO_BASE_LIMIT_HI_BASE_IDX 0 ++#define mmIRQ_BRIDGE_CNTL 0x000f // duplicate ++#define mmIRQ_BRIDGE_CNTL_BASE_IDX 0 ++#define mmSLOT_CAP 0x001b // duplicate ++#define mmSLOT_CAP_BASE_IDX 0 ++#define mmSLOT_CNTL 0x001c // duplicate ++#define mmSLOT_CNTL_BASE_IDX 0 ++#define mmSLOT_STATUS 0x001c // duplicate ++#define mmSLOT_STATUS_BASE_IDX 0 ++#define mmSSID_CAP_LIST 0x0030 // duplicate ++#define mmSSID_CAP_LIST_BASE_IDX 0 ++#define mmSSID_CAP 0x0031 // duplicate ++#define mmSSID_CAP_BASE_IDX 0 ++ ++ ++// addressBlock: rcc_shadow_reg_shadowdec ++// base address: 0x0 ++#define ixSHADOW_COMMAND 0x0004 // duplicate ++#define ixSHADOW_BASE_ADDR_1 0x0010 // duplicate ++#define ixSHADOW_BASE_ADDR_2 0x0014 // duplicate ++#define ixSHADOW_SUB_BUS_NUMBER_LATENCY 0x0018 // duplicate ++#define ixSHADOW_IO_BASE_LIMIT 0x001c // duplicate ++#define ixSHADOW_MEM_BASE_LIMIT 0x0020 // duplicate ++#define ixSHADOW_PREF_BASE_LIMIT 0x0024 // duplicate ++#define ixSHADOW_PREF_BASE_UPPER 0x0028 // duplicate ++#define ixSHADOW_PREF_LIMIT_UPPER 0x002c // duplicate ++#define ixSHADOW_IO_BASE_LIMIT_HI 0x0030 // duplicate ++#define ixSHADOW_IRQ_BRIDGE_CNTL 0x003e // duplicate ++#define ixSUC_INDEX 0x00e0 // duplicate ++#define ixSUC_DATA 0x00e4 // duplicate ++ ++ ++// addressBlock: bif_bx_pf_SUMDEC ++// base address: 0x0 ++#define ixSUM_INDEX 0x00e0 // duplicate ++#define ixSUM_DATA 0x00e4 // duplicate ++ ++ ++// addressBlock: gdc_GDCDEC ++// base address: 0x1400000 ++#define mmA2S_CNTL_CL0 0x4f0ab0 // duplicate ++#define mmA2S_CNTL_CL0_BASE_IDX 3 ++#define mmA2S_CNTL_CL1 0x4f0ab1 // duplicate ++#define mmA2S_CNTL_CL1_BASE_IDX 3 ++#define mmA2S_CNTL_CL2 0x4f0ab2 // duplicate ++#define mmA2S_CNTL_CL2_BASE_IDX 3 ++#define mmA2S_CNTL_CL3 0x4f0ab3 // duplicate ++#define mmA2S_CNTL_CL3_BASE_IDX 3 ++#define mmA2S_CNTL_CL4 0x4f0ab4 // duplicate ++#define mmA2S_CNTL_CL4_BASE_IDX 3 ++#define mmA2S_CNTL_SW0 0x4f0ad0 // duplicate ++#define mmA2S_CNTL_SW0_BASE_IDX 3 ++#define mmA2S_CNTL_SW1 0x4f0ad1 // duplicate ++#define mmA2S_CNTL_SW1_BASE_IDX 3 ++#define mmA2S_CNTL_SW2 0x4f0ad2 // duplicate ++#define mmA2S_CNTL_SW2_BASE_IDX 3 ++#define mmNGDC_MGCG_CTRL 0x4f0ae0 // duplicate ++#define mmNGDC_MGCG_CTRL_BASE_IDX 3 ++#define mmA2S_MISC_CNTL 0x4f0ae1 // duplicate ++#define mmA2S_MISC_CNTL_BASE_IDX 3 ++#define mmNGDC_SDP_PORT_CTRL 0x4f0ae2 // duplicate ++#define mmNGDC_SDP_PORT_CTRL_BASE_IDX 3 ++#define mmNGDC_RESERVED_0 0x4f0aeb // duplicate ++#define mmNGDC_RESERVED_0_BASE_IDX 3 ++#define mmNGDC_RESERVED_1 0x4f0aec // duplicate ++#define mmNGDC_RESERVED_1_BASE_IDX 3 ++#define mmBIF_SDMA0_DOORBELL_RANGE 0x4f0af0 // duplicate ++#define mmBIF_SDMA0_DOORBELL_RANGE_BASE_IDX 3 ++#define mmBIF_SDMA1_DOORBELL_RANGE 0x4f0af1 // duplicate ++#define mmBIF_SDMA1_DOORBELL_RANGE_BASE_IDX 3 ++#define mmBIF_IH_DOORBELL_RANGE 0x4f0af2 // duplicate ++#define mmBIF_IH_DOORBELL_RANGE_BASE_IDX 3 ++#define mmBIF_MMSCH0_DOORBELL_RANGE 0x4f0af3 // duplicate ++#define mmBIF_MMSCH0_DOORBELL_RANGE_BASE_IDX 3 ++#define mmBIF_DOORBELL_FENCE_CNTL 0x4f0afe // duplicate ++#define mmBIF_DOORBELL_FENCE_CNTL_BASE_IDX 3 ++#define mmS2A_MISC_CNTL 0x4f0aff // duplicate ++#define mmS2A_MISC_CNTL_BASE_IDX 3 ++#define mmA2S_CNTL2_SEC_CL0 0x4f0b00 // duplicate ++#define mmA2S_CNTL2_SEC_CL0_BASE_IDX 3 ++#define mmA2S_CNTL2_SEC_CL1 0x4f0b01 // duplicate ++#define mmA2S_CNTL2_SEC_CL1_BASE_IDX 3 ++#define mmA2S_CNTL2_SEC_CL2 0x4f0b02 // duplicate ++#define mmA2S_CNTL2_SEC_CL2_BASE_IDX 3 ++#define mmA2S_CNTL2_SEC_CL3 0x4f0b03 // duplicate ++#define mmA2S_CNTL2_SEC_CL3_BASE_IDX 3 ++#define mmA2S_CNTL2_SEC_CL4 0x4f0b04 // duplicate ++#define mmA2S_CNTL2_SEC_CL4_BASE_IDX 3 ++ ++ ++// addressBlock: nbif_sion_SIONDEC ++// base address: 0x1400000 ++#define ixSION_CL0_RdRsp_BurstTarget_REG0 0x1e000 ++#define ixSION_CL0_RdRsp_BurstTarget_REG1 0x1e004 ++#define ixSION_CL0_RdRsp_TimeSlot_REG0 0x1e008 ++#define ixSION_CL0_RdRsp_TimeSlot_REG1 0x1e00c ++#define ixSION_CL0_WrRsp_BurstTarget_REG0 0x1e010 ++#define ixSION_CL0_WrRsp_BurstTarget_REG1 0x1e014 ++#define ixSION_CL0_WrRsp_TimeSlot_REG0 0x1e018 ++#define ixSION_CL0_WrRsp_TimeSlot_REG1 0x1e01c ++#define ixSION_CL0_Req_BurstTarget_REG0 0x1e020 ++#define ixSION_CL0_Req_BurstTarget_REG1 0x1e024 ++#define ixSION_CL0_Req_TimeSlot_REG0 0x1e028 ++#define ixSION_CL0_Req_TimeSlot_REG1 0x1e02c ++#define ixSION_CL0_ReqPoolCredit_Alloc_REG0 0x1e030 ++#define ixSION_CL0_ReqPoolCredit_Alloc_REG1 0x1e034 ++#define ixSION_CL0_DataPoolCredit_Alloc_REG0 0x1e038 ++#define ixSION_CL0_DataPoolCredit_Alloc_REG1 0x1e03c ++#define ixSION_CL0_RdRspPoolCredit_Alloc_REG0 0x1e040 ++#define ixSION_CL0_RdRspPoolCredit_Alloc_REG1 0x1e044 ++#define ixSION_CL0_WrRspPoolCredit_Alloc_REG0 0x1e048 ++#define ixSION_CL0_WrRspPoolCredit_Alloc_REG1 0x1e04c ++#define ixSION_CL1_RdRsp_BurstTarget_REG0 0x1e050 ++#define ixSION_CL1_RdRsp_BurstTarget_REG1 0x1e054 ++#define ixSION_CL1_RdRsp_TimeSlot_REG0 0x1e058 ++#define ixSION_CL1_RdRsp_TimeSlot_REG1 0x1e05c ++#define ixSION_CL1_WrRsp_BurstTarget_REG0 0x1e060 ++#define ixSION_CL1_WrRsp_BurstTarget_REG1 0x1e064 ++#define ixSION_CL1_WrRsp_TimeSlot_REG0 0x1e068 ++#define ixSION_CL1_WrRsp_TimeSlot_REG1 0x1e06c ++#define ixSION_CL1_Req_BurstTarget_REG0 0x1e070 ++#define ixSION_CL1_Req_BurstTarget_REG1 0x1e074 ++#define ixSION_CL1_Req_TimeSlot_REG0 0x1e078 ++#define ixSION_CL1_Req_TimeSlot_REG1 0x1e07c ++#define ixSION_CL1_ReqPoolCredit_Alloc_REG0 0x1e080 ++#define ixSION_CL1_ReqPoolCredit_Alloc_REG1 0x1e084 ++#define ixSION_CL1_DataPoolCredit_Alloc_REG0 0x1e088 ++#define ixSION_CL1_DataPoolCredit_Alloc_REG1 0x1e08c ++#define ixSION_CL1_RdRspPoolCredit_Alloc_REG0 0x1e090 ++#define ixSION_CL1_RdRspPoolCredit_Alloc_REG1 0x1e094 ++#define ixSION_CL1_WrRspPoolCredit_Alloc_REG0 0x1e098 ++#define ixSION_CL1_WrRspPoolCredit_Alloc_REG1 0x1e09c ++#define ixSION_CL2_RdRsp_BurstTarget_REG0 0x1e0a0 ++#define ixSION_CL2_RdRsp_BurstTarget_REG1 0x1e0a4 ++#define ixSION_CL2_RdRsp_TimeSlot_REG0 0x1e0a8 ++#define ixSION_CL2_RdRsp_TimeSlot_REG1 0x1e0ac ++#define ixSION_CL2_WrRsp_BurstTarget_REG0 0x1e0b0 ++#define ixSION_CL2_WrRsp_BurstTarget_REG1 0x1e0b4 ++#define ixSION_CL2_WrRsp_TimeSlot_REG0 0x1e0b8 ++#define ixSION_CL2_WrRsp_TimeSlot_REG1 0x1e0bc ++#define ixSION_CL2_Req_BurstTarget_REG0 0x1e0c0 ++#define ixSION_CL2_Req_BurstTarget_REG1 0x1e0c4 ++#define ixSION_CL2_Req_TimeSlot_REG0 0x1e0c8 ++#define ixSION_CL2_Req_TimeSlot_REG1 0x1e0cc ++#define ixSION_CL2_ReqPoolCredit_Alloc_REG0 0x1e0d0 ++#define ixSION_CL2_ReqPoolCredit_Alloc_REG1 0x1e0d4 ++#define ixSION_CL2_DataPoolCredit_Alloc_REG0 0x1e0d8 ++#define ixSION_CL2_DataPoolCredit_Alloc_REG1 0x1e0dc ++#define ixSION_CL2_RdRspPoolCredit_Alloc_REG0 0x1e0e0 ++#define ixSION_CL2_RdRspPoolCredit_Alloc_REG1 0x1e0e4 ++#define ixSION_CL2_WrRspPoolCredit_Alloc_REG0 0x1e0e8 ++#define ixSION_CL2_WrRspPoolCredit_Alloc_REG1 0x1e0ec ++#define ixSION_CL3_RdRsp_BurstTarget_REG0 0x1e0f0 ++#define ixSION_CL3_RdRsp_BurstTarget_REG1 0x1e0f4 ++#define ixSION_CL3_RdRsp_TimeSlot_REG0 0x1e0f8 ++#define ixSION_CL3_RdRsp_TimeSlot_REG1 0x1e0fc ++#define ixSION_CL3_WrRsp_BurstTarget_REG0 0x1e100 ++#define ixSION_CL3_WrRsp_BurstTarget_REG1 0x1e104 ++#define ixSION_CL3_WrRsp_TimeSlot_REG0 0x1e108 ++#define ixSION_CL3_WrRsp_TimeSlot_REG1 0x1e10c ++#define ixSION_CL3_Req_BurstTarget_REG0 0x1e110 ++#define ixSION_CL3_Req_BurstTarget_REG1 0x1e114 ++#define ixSION_CL3_Req_TimeSlot_REG0 0x1e118 ++#define ixSION_CL3_Req_TimeSlot_REG1 0x1e11c ++#define ixSION_CL3_ReqPoolCredit_Alloc_REG0 0x1e120 ++#define ixSION_CL3_ReqPoolCredit_Alloc_REG1 0x1e124 ++#define ixSION_CL3_DataPoolCredit_Alloc_REG0 0x1e128 ++#define ixSION_CL3_DataPoolCredit_Alloc_REG1 0x1e12c ++#define ixSION_CL3_RdRspPoolCredit_Alloc_REG0 0x1e130 ++#define ixSION_CL3_RdRspPoolCredit_Alloc_REG1 0x1e134 ++#define ixSION_CL3_WrRspPoolCredit_Alloc_REG0 0x1e138 ++#define ixSION_CL3_WrRspPoolCredit_Alloc_REG1 0x1e13c ++#define ixSION_CL4_RdRsp_BurstTarget_REG0 0x1e140 ++#define ixSION_CL4_RdRsp_BurstTarget_REG1 0x1e144 ++#define ixSION_CL4_RdRsp_TimeSlot_REG0 0x1e148 ++#define ixSION_CL4_RdRsp_TimeSlot_REG1 0x1e14c ++#define ixSION_CL4_WrRsp_BurstTarget_REG0 0x1e150 ++#define ixSION_CL4_WrRsp_BurstTarget_REG1 0x1e154 ++#define ixSION_CL4_WrRsp_TimeSlot_REG0 0x1e158 ++#define ixSION_CL4_WrRsp_TimeSlot_REG1 0x1e15c ++#define ixSION_CL4_Req_BurstTarget_REG0 0x1e160 ++#define ixSION_CL4_Req_BurstTarget_REG1 0x1e164 ++#define ixSION_CL4_Req_TimeSlot_REG0 0x1e168 ++#define ixSION_CL4_Req_TimeSlot_REG1 0x1e16c ++#define ixSION_CL4_ReqPoolCredit_Alloc_REG0 0x1e170 ++#define ixSION_CL4_ReqPoolCredit_Alloc_REG1 0x1e174 ++#define ixSION_CL4_DataPoolCredit_Alloc_REG0 0x1e178 ++#define ixSION_CL4_DataPoolCredit_Alloc_REG1 0x1e17c ++#define ixSION_CL4_RdRspPoolCredit_Alloc_REG0 0x1e180 ++#define ixSION_CL4_RdRspPoolCredit_Alloc_REG1 0x1e184 ++#define ixSION_CL4_WrRspPoolCredit_Alloc_REG0 0x1e188 ++#define ixSION_CL4_WrRspPoolCredit_Alloc_REG1 0x1e18c ++#define ixSION_CL5_RdRsp_BurstTarget_REG0 0x1e190 ++#define ixSION_CL5_RdRsp_BurstTarget_REG1 0x1e194 ++#define ixSION_CL5_RdRsp_TimeSlot_REG0 0x1e198 ++#define ixSION_CL5_RdRsp_TimeSlot_REG1 0x1e19c ++#define ixSION_CL5_WrRsp_BurstTarget_REG0 0x1e1a0 ++#define ixSION_CL5_WrRsp_BurstTarget_REG1 0x1e1a4 ++#define ixSION_CL5_WrRsp_TimeSlot_REG0 0x1e1a8 ++#define ixSION_CL5_WrRsp_TimeSlot_REG1 0x1e1ac ++#define ixSION_CL5_Req_BurstTarget_REG0 0x1e1b0 ++#define ixSION_CL5_Req_BurstTarget_REG1 0x1e1b4 ++#define ixSION_CL5_Req_TimeSlot_REG0 0x1e1b8 ++#define ixSION_CL5_Req_TimeSlot_REG1 0x1e1bc ++#define ixSION_CL5_ReqPoolCredit_Alloc_REG0 0x1e1c0 ++#define ixSION_CL5_ReqPoolCredit_Alloc_REG1 0x1e1c4 ++#define ixSION_CL5_DataPoolCredit_Alloc_REG0 0x1e1c8 ++#define ixSION_CL5_DataPoolCredit_Alloc_REG1 0x1e1cc ++#define ixSION_CL5_RdRspPoolCredit_Alloc_REG0 0x1e1d0 ++#define ixSION_CL5_RdRspPoolCredit_Alloc_REG1 0x1e1d4 ++#define ixSION_CL5_WrRspPoolCredit_Alloc_REG0 0x1e1d8 ++#define ixSION_CL5_WrRspPoolCredit_Alloc_REG1 0x1e1dc ++#define ixSION_CNTL_REG0 0x1e1e0 ++#define ixSION_CNTL_REG1 0x1e1e4 ++ ++ ++// addressBlock: syshub_mmreg_direct_syshubdirect ++// base address: 0x1400000 ++#define ixSYSHUB_DS_CTRL_SOCCLK 0x10000 // duplicate ++#define ixSYSHUB_DS_CTRL2_SOCCLK 0x10004 // duplicate ++#define ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK 0x10008 // duplicate ++#define ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK 0x1000c // duplicate ++#define ixDMA_CLK0_SW0_SYSHUB_QOS_CNTL 0x10010 // duplicate ++#define ixDMA_CLK0_SW1_SYSHUB_QOS_CNTL 0x10014 // duplicate ++#define ixDMA_CLK0_SW0_CL0_CNTL 0x10018 // duplicate ++#define ixDMA_CLK0_SW0_CL1_CNTL 0x1001c // duplicate ++#define ixDMA_CLK0_SW0_CL2_CNTL 0x10020 // duplicate ++#define ixDMA_CLK0_SW0_CL3_CNTL 0x10024 // duplicate ++#define ixDMA_CLK0_SW0_CL4_CNTL 0x10028 // duplicate ++#define ixDMA_CLK0_SW0_CL5_CNTL 0x1002c // duplicate ++#define ixDMA_CLK0_SW1_CL0_CNTL 0x10030 // duplicate ++#define ixDMA_CLK0_SW2_CL0_CNTL 0x10034 // duplicate ++#define ixSYSHUB_CG_CNTL 0x10300 // duplicate ++#define ixSYSHUB_TRANS_IDLE 0x10308 // duplicate ++#define ixSYSHUB_HP_TIMER 0x1030c // duplicate ++#define ixSYSHUB_SCRATCH 0x10f00 // duplicate ++#define ixSYSHUB_DS_CTRL_SHUBCLK 0x11000 // duplicate ++#define ixSYSHUB_DS_CTRL2_SHUBCLK 0x11004 // duplicate ++#define ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK 0x11008 // duplicate ++#define ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK 0x1100c // duplicate ++#define ixDMA_CLK1_SW0_SYSHUB_QOS_CNTL 0x11010 // duplicate ++#define ixDMA_CLK1_SW1_SYSHUB_QOS_CNTL 0x11014 // duplicate ++#define ixDMA_CLK1_SW0_CL0_CNTL 0x11018 // duplicate ++#define ixDMA_CLK1_SW0_CL1_CNTL 0x1101c // duplicate ++#define ixDMA_CLK1_SW0_CL2_CNTL 0x11020 // duplicate ++#define ixDMA_CLK1_SW0_CL3_CNTL 0x11024 // duplicate ++#define ixDMA_CLK1_SW0_CL4_CNTL 0x11028 // duplicate ++#define ixDMA_CLK1_SW1_CL0_CNTL 0x1102c // duplicate ++#define ixDMA_CLK1_SW1_CL1_CNTL 0x11030 // duplicate ++#define ixDMA_CLK1_SW1_CL2_CNTL 0x11034 // duplicate ++#define ixDMA_CLK1_SW1_CL3_CNTL 0x11038 // duplicate ++#define ixDMA_CLK1_SW1_CL4_CNTL 0x1103c // duplicate ++ ++ ++// addressBlock: gdc_ras_gdc_ras_regblk ++// base address: 0x1400000 ++#define ixGDC_RAS_LEAF0_CTRL 0x1f800 ++#define ixGDC_RAS_LEAF1_CTRL 0x1f804 ++#define ixGDC_RAS_LEAF2_CTRL 0x1f808 ++#define ixGDC_RAS_LEAF3_CTRL 0x1f80c ++#define ixGDC_RAS_LEAF4_CTRL 0x1f810 ++#define ixGDC_RAS_LEAF5_CTRL 0x1f814 ++ ++ ++// addressBlock: gdc_rst_GDCRST_DEC ++// base address: 0x1400000 ++#define ixSHUB_PF_FLR_RST 0x1f000 ++#define ixSHUB_GFX_DRV_MODE1_RST 0x1f004 ++#define ixSHUB_LINK_RESET 0x1f008 ++#define ixSHUB_PF0_VF_FLR_RST 0x1f020 ++#define ixSHUB_HARD_RST_CTRL 0x1f040 ++#define ixSHUB_SOFT_RST_CTRL 0x1f044 ++#define ixSHUB_SDP_PORT_RST 0x1f048 ++ ++ ++// memoryMap:EP0F0Reg ++ ++ ++// addressBlock: bif_bx_pf_SYSDEC ++// base address: 0x0 ++#define mmSBIOS_SCRATCH_0 0x0048 // duplicate ++#define mmSBIOS_SCRATCH_0_BASE_IDX 0 ++#define mmSBIOS_SCRATCH_1 0x0049 // duplicate ++#define mmSBIOS_SCRATCH_1_BASE_IDX 0 ++#define mmSBIOS_SCRATCH_2 0x004a // duplicate ++#define mmSBIOS_SCRATCH_2_BASE_IDX 0 ++#define mmSBIOS_SCRATCH_3 0x004b // duplicate ++#define mmSBIOS_SCRATCH_3_BASE_IDX 0 ++#define mmBIOS_SCRATCH_0 0x004c // duplicate ++#define mmBIOS_SCRATCH_0_BASE_IDX 0 ++#define mmBIOS_SCRATCH_1 0x004d // duplicate ++#define mmBIOS_SCRATCH_1_BASE_IDX 0 ++#define mmBIOS_SCRATCH_2 0x004e // duplicate ++#define mmBIOS_SCRATCH_2_BASE_IDX 0 ++#define mmBIOS_SCRATCH_3 0x004f // duplicate ++#define mmBIOS_SCRATCH_3_BASE_IDX 0 ++#define mmBIOS_SCRATCH_4 0x0050 // duplicate ++#define mmBIOS_SCRATCH_4_BASE_IDX 0 ++#define mmBIOS_SCRATCH_5 0x0051 // duplicate ++#define mmBIOS_SCRATCH_5_BASE_IDX 0 ++#define mmBIOS_SCRATCH_6 0x0052 // duplicate ++#define mmBIOS_SCRATCH_6_BASE_IDX 0 ++#define mmBIOS_SCRATCH_7 0x0053 // duplicate ++#define mmBIOS_SCRATCH_7_BASE_IDX 0 ++#define mmBIOS_SCRATCH_8 0x0054 // duplicate ++#define mmBIOS_SCRATCH_8_BASE_IDX 0 ++#define mmBIOS_SCRATCH_9 0x0055 // duplicate ++#define mmBIOS_SCRATCH_9_BASE_IDX 0 ++#define mmBIOS_SCRATCH_10 0x0056 // duplicate ++#define mmBIOS_SCRATCH_10_BASE_IDX 0 ++#define mmBIOS_SCRATCH_11 0x0057 // duplicate ++#define mmBIOS_SCRATCH_11_BASE_IDX 0 ++#define mmBIOS_SCRATCH_12 0x0058 // duplicate ++#define mmBIOS_SCRATCH_12_BASE_IDX 0 ++#define mmBIOS_SCRATCH_13 0x0059 // duplicate ++#define mmBIOS_SCRATCH_13_BASE_IDX 0 ++#define mmBIOS_SCRATCH_14 0x005a // duplicate ++#define mmBIOS_SCRATCH_14_BASE_IDX 0 ++#define mmBIOS_SCRATCH_15 0x005b // duplicate ++#define mmBIOS_SCRATCH_15_BASE_IDX 0 ++#define mmBIF_RLC_INTR_CNTL 0x0060 // duplicate ++#define mmBIF_RLC_INTR_CNTL_BASE_IDX 0 ++#define mmBIF_VCE_INTR_CNTL 0x0061 // duplicate ++#define mmBIF_VCE_INTR_CNTL_BASE_IDX 0 ++#define mmBIF_UVD_INTR_CNTL 0x0062 // duplicate ++#define mmBIF_UVD_INTR_CNTL_BASE_IDX 0 ++#define mmGFX_MMIOREG_CAM_ADDR0 0x0080 // duplicate ++#define mmGFX_MMIOREG_CAM_ADDR0_BASE_IDX 0 ++#define mmGFX_MMIOREG_CAM_REMAP_ADDR0 0x0081 // duplicate ++#define mmGFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 0 ++#define mmGFX_MMIOREG_CAM_ADDR1 0x0082 // duplicate ++#define mmGFX_MMIOREG_CAM_ADDR1_BASE_IDX 0 ++#define mmGFX_MMIOREG_CAM_REMAP_ADDR1 0x0083 // duplicate ++#define mmGFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 0 ++#define mmGFX_MMIOREG_CAM_ADDR2 0x0084 // duplicate ++#define mmGFX_MMIOREG_CAM_ADDR2_BASE_IDX 0 ++#define mmGFX_MMIOREG_CAM_REMAP_ADDR2 0x0085 // duplicate ++#define mmGFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 0 ++#define mmGFX_MMIOREG_CAM_ADDR3 0x0086 // duplicate ++#define mmGFX_MMIOREG_CAM_ADDR3_BASE_IDX 0 ++#define mmGFX_MMIOREG_CAM_REMAP_ADDR3 0x0087 // duplicate ++#define mmGFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 0 ++#define mmGFX_MMIOREG_CAM_ADDR4 0x0088 // duplicate ++#define mmGFX_MMIOREG_CAM_ADDR4_BASE_IDX 0 ++#define mmGFX_MMIOREG_CAM_REMAP_ADDR4 0x0089 // duplicate ++#define mmGFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 0 ++#define mmGFX_MMIOREG_CAM_ADDR5 0x008a // duplicate ++#define mmGFX_MMIOREG_CAM_ADDR5_BASE_IDX 0 ++#define mmGFX_MMIOREG_CAM_REMAP_ADDR5 0x008b // duplicate ++#define mmGFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 0 ++#define mmGFX_MMIOREG_CAM_ADDR6 0x008c // duplicate ++#define mmGFX_MMIOREG_CAM_ADDR6_BASE_IDX 0 ++#define mmGFX_MMIOREG_CAM_REMAP_ADDR6 0x008d // duplicate ++#define mmGFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 0 ++#define mmGFX_MMIOREG_CAM_ADDR7 0x008e // duplicate ++#define mmGFX_MMIOREG_CAM_ADDR7_BASE_IDX 0 ++#define mmGFX_MMIOREG_CAM_REMAP_ADDR7 0x008f // duplicate ++#define mmGFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 0 ++#define mmGFX_MMIOREG_CAM_CNTL 0x0090 // duplicate ++#define mmGFX_MMIOREG_CAM_CNTL_BASE_IDX 0 ++#define mmGFX_MMIOREG_CAM_ZERO_CPL 0x0091 // duplicate ++#define mmGFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 0 ++#define mmGFX_MMIOREG_CAM_ONE_CPL 0x0092 // duplicate ++#define mmGFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 0 ++#define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x0093 // duplicate ++#define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 0 ++ ++ ++// addressBlock: bif_bx_pf_SYSPFVFDEC ++// base address: 0x0 ++#define mmMM_INDEX 0x0000 // duplicate ++#define mmMM_INDEX_BASE_IDX 0 ++#define mmMM_DATA 0x0001 // duplicate ++#define mmMM_DATA_BASE_IDX 0 ++#define mmMM_INDEX_HI 0x0006 // duplicate ++#define mmMM_INDEX_HI_BASE_IDX 0 ++#define mmSYSHUB_INDEX_OVLP 0x0008 // duplicate ++#define mmSYSHUB_INDEX_OVLP_BASE_IDX 0 ++#define mmSYSHUB_DATA_OVLP 0x0009 // duplicate ++#define mmSYSHUB_DATA_OVLP_BASE_IDX 0 ++#define mmPCIE_INDEX 0x000c // duplicate ++#define mmPCIE_INDEX_BASE_IDX 0 ++#define mmPCIE_DATA 0x000d // duplicate ++#define mmPCIE_DATA_BASE_IDX 0 ++#define mmPCIE_INDEX2 0x000e // duplicate ++#define mmPCIE_INDEX2_BASE_IDX 0 ++#define mmPCIE_DATA2 0x000f // duplicate ++#define mmPCIE_DATA2_BASE_IDX 0 ++ ++ ++// addressBlock: rcc_dwn_BIFDEC1 ++// base address: 0x0 ++#define mmDN_PCIE_RESERVED 0x0d60 // duplicate ++#define mmDN_PCIE_RESERVED_BASE_IDX 0 ++#define mmDN_PCIE_SCRATCH 0x0d61 // duplicate ++#define mmDN_PCIE_SCRATCH_BASE_IDX 0 ++#define mmDN_PCIE_CNTL 0x0d63 // duplicate ++#define mmDN_PCIE_CNTL_BASE_IDX 0 ++#define mmDN_PCIE_CONFIG_CNTL 0x0d64 // duplicate ++#define mmDN_PCIE_CONFIG_CNTL_BASE_IDX 0 ++#define mmDN_PCIE_RX_CNTL2 0x0d65 // duplicate ++#define mmDN_PCIE_RX_CNTL2_BASE_IDX 0 ++#define mmDN_PCIE_BUS_CNTL 0x0d66 // duplicate ++#define mmDN_PCIE_BUS_CNTL_BASE_IDX 0 ++#define mmDN_PCIE_CFG_CNTL 0x0d67 // duplicate ++#define mmDN_PCIE_CFG_CNTL_BASE_IDX 0 ++#define mmDN_PCIE_STRAP_F0 0x0d68 // duplicate ++#define mmDN_PCIE_STRAP_F0_BASE_IDX 0 ++#define mmDN_PCIE_STRAP_MISC 0x0d69 // duplicate ++#define mmDN_PCIE_STRAP_MISC_BASE_IDX 0 ++#define mmDN_PCIE_STRAP_MISC2 0x0d6a // duplicate ++#define mmDN_PCIE_STRAP_MISC2_BASE_IDX 0 ++ ++ ++// addressBlock: rcc_dwnp_BIFDEC1 ++// base address: 0x0 ++#define mmPCIEP_RESERVED 0x0d6c // duplicate ++#define mmPCIEP_RESERVED_BASE_IDX 0 ++#define mmPCIEP_SCRATCH 0x0d6d // duplicate ++#define mmPCIEP_SCRATCH_BASE_IDX 0 ++#define mmPCIE_ERR_CNTL 0x0d6f // duplicate ++#define mmPCIE_ERR_CNTL_BASE_IDX 0 ++#define mmPCIE_RX_CNTL 0x0d70 // duplicate ++#define mmPCIE_RX_CNTL_BASE_IDX 0 ++#define mmPCIE_LC_SPEED_CNTL 0x0d71 // duplicate ++#define mmPCIE_LC_SPEED_CNTL_BASE_IDX 0 ++#define mmPCIE_LC_CNTL2 0x0d72 // duplicate ++#define mmPCIE_LC_CNTL2_BASE_IDX 0 ++#define mmPCIEP_STRAP_MISC 0x0d73 // duplicate ++#define mmPCIEP_STRAP_MISC_BASE_IDX 0 ++#define mmLTR_MSG_INFO_FROM_EP 0x0d74 // duplicate ++#define mmLTR_MSG_INFO_FROM_EP_BASE_IDX 0 ++ ++ ++// addressBlock: rcc_ep_BIFDEC1 ++// base address: 0x0 ++#define mmEP_PCIE_SCRATCH 0x0d43 // duplicate ++#define mmEP_PCIE_SCRATCH_BASE_IDX 0 ++#define mmEP_PCIE_CNTL 0x0d45 // duplicate ++#define mmEP_PCIE_CNTL_BASE_IDX 0 ++#define mmEP_PCIE_INT_CNTL 0x0d46 // duplicate ++#define mmEP_PCIE_INT_CNTL_BASE_IDX 0 ++#define mmEP_PCIE_INT_STATUS 0x0d47 // duplicate ++#define mmEP_PCIE_INT_STATUS_BASE_IDX 0 ++#define mmEP_PCIE_RX_CNTL2 0x0d48 // duplicate ++#define mmEP_PCIE_RX_CNTL2_BASE_IDX 0 ++#define mmEP_PCIE_BUS_CNTL 0x0d49 // duplicate ++#define mmEP_PCIE_BUS_CNTL_BASE_IDX 0 ++#define mmEP_PCIE_CFG_CNTL 0x0d4a // duplicate ++#define mmEP_PCIE_CFG_CNTL_BASE_IDX 0 ++#define mmEP_PCIE_OBFF_CNTL 0x0d4b // duplicate ++#define mmEP_PCIE_OBFF_CNTL_BASE_IDX 0 ++#define mmEP_PCIE_TX_LTR_CNTL 0x0d4c // duplicate ++#define mmEP_PCIE_TX_LTR_CNTL_BASE_IDX 0 ++#define mmEP_PCIE_STRAP_MISC 0x0d4f // duplicate ++#define mmEP_PCIE_STRAP_MISC_BASE_IDX 0 ++#define mmEP_PCIE_STRAP_MISC2 0x0d50 // duplicate ++#define mmEP_PCIE_STRAP_MISC2_BASE_IDX 0 ++#define mmEP_PCIE_STRAP_PI 0x0d51 // duplicate ++#define mmEP_PCIE_STRAP_PI_BASE_IDX 0 ++#define mmEP_PCIE_F0_DPA_CAP 0x0d52 // duplicate ++#define mmEP_PCIE_F0_DPA_CAP_BASE_IDX 0 ++#define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR 0x0d53 // duplicate ++#define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 0 ++#define mmEP_PCIE_F0_DPA_CNTL 0x0d53 // duplicate ++#define mmEP_PCIE_F0_DPA_CNTL_BASE_IDX 0 ++#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x0d53 // duplicate ++#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 0 ++#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x0d54 // duplicate ++#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 0 ++#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x0d54 // duplicate ++#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 0 ++#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x0d54 // duplicate ++#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 0 ++#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x0d54 // duplicate ++#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 0 ++#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x0d55 // duplicate ++#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 0 ++#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x0d55 // duplicate ++#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 0 ++#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x0d55 // duplicate ++#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 0 ++#define mmEP_PCIE_PME_CONTROL 0x0d55 // duplicate ++#define mmEP_PCIE_PME_CONTROL_BASE_IDX 0 ++#define mmEP_PCIEP_RESERVED 0x0d56 // duplicate ++#define mmEP_PCIEP_RESERVED_BASE_IDX 0 ++#define mmEP_PCIE_TX_CNTL 0x0d58 // duplicate ++#define mmEP_PCIE_TX_CNTL_BASE_IDX 0 ++#define mmEP_PCIE_TX_REQUESTER_ID 0x0d59 // duplicate ++#define mmEP_PCIE_TX_REQUESTER_ID_BASE_IDX 0 ++#define mmEP_PCIE_ERR_CNTL 0x0d5a // duplicate ++#define mmEP_PCIE_ERR_CNTL_BASE_IDX 0 ++#define mmEP_PCIE_RX_CNTL 0x0d5b // duplicate ++#define mmEP_PCIE_RX_CNTL_BASE_IDX 0 ++#define mmEP_PCIE_LC_SPEED_CNTL 0x0d5c // duplicate ++#define mmEP_PCIE_LC_SPEED_CNTL_BASE_IDX 0 ++ ++ ++// addressBlock: bif_bx_pf_BIFDEC1 ++// base address: 0x0 ++#define mmBIF_MM_INDACCESS_CNTL 0x0e06 // duplicate ++#define mmBIF_MM_INDACCESS_CNTL_BASE_IDX 0 ++#define mmBUS_CNTL 0x0e07 // duplicate ++#define mmBUS_CNTL_BASE_IDX 0 ++#define mmBIF_SCRATCH0 0x0e08 // duplicate ++#define mmBIF_SCRATCH0_BASE_IDX 0 ++#define mmBIF_SCRATCH1 0x0e09 // duplicate ++#define mmBIF_SCRATCH1_BASE_IDX 0 ++#define mmBX_RESET_EN 0x0e0d // duplicate ++#define mmBX_RESET_EN_BASE_IDX 0 ++#define mmMM_CFGREGS_CNTL 0x0e0e // duplicate ++#define mmMM_CFGREGS_CNTL_BASE_IDX 0 ++#define mmBX_RESET_CNTL 0x0e10 // duplicate ++#define mmBX_RESET_CNTL_BASE_IDX 0 ++#define mmINTERRUPT_CNTL 0x0e11 // duplicate ++#define mmINTERRUPT_CNTL_BASE_IDX 0 ++#define mmINTERRUPT_CNTL2 0x0e12 // duplicate ++#define mmINTERRUPT_CNTL2_BASE_IDX 0 ++#define mmCLKREQB_PAD_CNTL 0x0e18 // duplicate ++#define mmCLKREQB_PAD_CNTL_BASE_IDX 0 ++#define mmCLKREQB_PERF_COUNTER 0x0e19 // duplicate ++#define mmCLKREQB_PERF_COUNTER_BASE_IDX 0 ++#define mmBIF_CLK_CTRL 0x0e1a // duplicate ++#define mmBIF_CLK_CTRL_BASE_IDX 0 ++#define mmBIF_FEATURES_CONTROL_MISC 0x0e1b // duplicate ++#define mmBIF_FEATURES_CONTROL_MISC_BASE_IDX 0 ++#define mmBIF_DOORBELL_CNTL 0x0e1c // duplicate ++#define mmBIF_DOORBELL_CNTL_BASE_IDX 0 ++#define mmBIF_DOORBELL_INT_CNTL 0x0e1d // duplicate ++#define mmBIF_DOORBELL_INT_CNTL_BASE_IDX 0 ++#define mmBIF_SLVARB_MODE 0x0e1e // duplicate ++#define mmBIF_SLVARB_MODE_BASE_IDX 0 ++#define mmBIF_FB_EN 0x0e1f // duplicate ++#define mmBIF_FB_EN_BASE_IDX 0 ++#define mmBIF_BUSY_DELAY_CNTR 0x0e20 // duplicate ++#define mmBIF_BUSY_DELAY_CNTR_BASE_IDX 0 ++#define mmBIF_PERFMON_CNTL 0x0e21 // duplicate ++#define mmBIF_PERFMON_CNTL_BASE_IDX 0 ++#define mmBIF_PERFCOUNTER0_RESULT 0x0e22 // duplicate ++#define mmBIF_PERFCOUNTER0_RESULT_BASE_IDX 0 ++#define mmBIF_PERFCOUNTER1_RESULT 0x0e23 // duplicate ++#define mmBIF_PERFCOUNTER1_RESULT_BASE_IDX 0 ++#define mmBIF_MST_TRANS_PENDING_VF 0x0e29 // duplicate ++#define mmBIF_MST_TRANS_PENDING_VF_BASE_IDX 0 ++#define mmBIF_SLV_TRANS_PENDING_VF 0x0e2a // duplicate ++#define mmBIF_SLV_TRANS_PENDING_VF_BASE_IDX 0 ++#define mmBACO_CNTL 0x0e2b // duplicate ++#define mmBACO_CNTL_BASE_IDX 0 ++#define mmBIF_BACO_EXIT_TIME0 0x0e2c // duplicate ++#define mmBIF_BACO_EXIT_TIME0_BASE_IDX 0 ++#define mmBIF_BACO_EXIT_TIMER1 0x0e2d // duplicate ++#define mmBIF_BACO_EXIT_TIMER1_BASE_IDX 0 ++#define mmBIF_BACO_EXIT_TIMER2 0x0e2e // duplicate ++#define mmBIF_BACO_EXIT_TIMER2_BASE_IDX 0 ++#define mmBIF_BACO_EXIT_TIMER3 0x0e2f // duplicate ++#define mmBIF_BACO_EXIT_TIMER3_BASE_IDX 0 ++#define mmBIF_BACO_EXIT_TIMER4 0x0e30 // duplicate ++#define mmBIF_BACO_EXIT_TIMER4_BASE_IDX 0 ++#define mmMEM_TYPE_CNTL 0x0e31 // duplicate ++#define mmMEM_TYPE_CNTL_BASE_IDX 0 ++#define mmSMU_BIF_VDDGFX_PWR_STATUS 0x0e33 // duplicate ++#define mmSMU_BIF_VDDGFX_PWR_STATUS_BASE_IDX 0 ++#define mmBIF_VDDGFX_GFX0_LOWER 0x0e34 // duplicate ++#define mmBIF_VDDGFX_GFX0_LOWER_BASE_IDX 0 ++#define mmBIF_VDDGFX_GFX0_UPPER 0x0e35 // duplicate ++#define mmBIF_VDDGFX_GFX0_UPPER_BASE_IDX 0 ++#define mmBIF_VDDGFX_GFX1_LOWER 0x0e36 // duplicate ++#define mmBIF_VDDGFX_GFX1_LOWER_BASE_IDX 0 ++#define mmBIF_VDDGFX_GFX1_UPPER 0x0e37 // duplicate ++#define mmBIF_VDDGFX_GFX1_UPPER_BASE_IDX 0 ++#define mmBIF_VDDGFX_GFX2_LOWER 0x0e38 // duplicate ++#define mmBIF_VDDGFX_GFX2_LOWER_BASE_IDX 0 ++#define mmBIF_VDDGFX_GFX2_UPPER 0x0e39 // duplicate ++#define mmBIF_VDDGFX_GFX2_UPPER_BASE_IDX 0 ++#define mmBIF_VDDGFX_GFX3_LOWER 0x0e3a // duplicate ++#define mmBIF_VDDGFX_GFX3_LOWER_BASE_IDX 0 ++#define mmBIF_VDDGFX_GFX3_UPPER 0x0e3b // duplicate ++#define mmBIF_VDDGFX_GFX3_UPPER_BASE_IDX 0 ++#define mmBIF_VDDGFX_GFX4_LOWER 0x0e3c // duplicate ++#define mmBIF_VDDGFX_GFX4_LOWER_BASE_IDX 0 ++#define mmBIF_VDDGFX_GFX4_UPPER 0x0e3d // duplicate ++#define mmBIF_VDDGFX_GFX4_UPPER_BASE_IDX 0 ++#define mmBIF_VDDGFX_GFX5_LOWER 0x0e3e // duplicate ++#define mmBIF_VDDGFX_GFX5_LOWER_BASE_IDX 0 ++#define mmBIF_VDDGFX_GFX5_UPPER 0x0e3f // duplicate ++#define mmBIF_VDDGFX_GFX5_UPPER_BASE_IDX 0 ++#define mmBIF_VDDGFX_RSV1_LOWER 0x0e40 // duplicate ++#define mmBIF_VDDGFX_RSV1_LOWER_BASE_IDX 0 ++#define mmBIF_VDDGFX_RSV1_UPPER 0x0e41 // duplicate ++#define mmBIF_VDDGFX_RSV1_UPPER_BASE_IDX 0 ++#define mmBIF_VDDGFX_RSV2_LOWER 0x0e42 // duplicate ++#define mmBIF_VDDGFX_RSV2_LOWER_BASE_IDX 0 ++#define mmBIF_VDDGFX_RSV2_UPPER 0x0e43 // duplicate ++#define mmBIF_VDDGFX_RSV2_UPPER_BASE_IDX 0 ++#define mmBIF_VDDGFX_RSV3_LOWER 0x0e44 // duplicate ++#define mmBIF_VDDGFX_RSV3_LOWER_BASE_IDX 0 ++#define mmBIF_VDDGFX_RSV3_UPPER 0x0e45 // duplicate ++#define mmBIF_VDDGFX_RSV3_UPPER_BASE_IDX 0 ++#define mmBIF_VDDGFX_RSV4_LOWER 0x0e46 // duplicate ++#define mmBIF_VDDGFX_RSV4_LOWER_BASE_IDX 0 ++#define mmBIF_VDDGFX_RSV4_UPPER 0x0e47 // duplicate ++#define mmBIF_VDDGFX_RSV4_UPPER_BASE_IDX 0 ++#define mmBIF_VDDGFX_FB_CMP 0x0e48 // duplicate ++#define mmBIF_VDDGFX_FB_CMP_BASE_IDX 0 ++#define mmBIF_DOORBELL_GBLAPER1_LOWER 0x0e49 // duplicate ++#define mmBIF_DOORBELL_GBLAPER1_LOWER_BASE_IDX 0 ++#define mmBIF_DOORBELL_GBLAPER1_UPPER 0x0e4a // duplicate ++#define mmBIF_DOORBELL_GBLAPER1_UPPER_BASE_IDX 0 ++#define mmBIF_DOORBELL_GBLAPER2_LOWER 0x0e4b // duplicate ++#define mmBIF_DOORBELL_GBLAPER2_LOWER_BASE_IDX 0 ++#define mmBIF_DOORBELL_GBLAPER2_UPPER 0x0e4c // duplicate ++#define mmBIF_DOORBELL_GBLAPER2_UPPER_BASE_IDX 0 ++#define mmREMAP_HDP_MEM_FLUSH_CNTL 0x0e4d // duplicate ++#define mmREMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 0 ++#define mmREMAP_HDP_REG_FLUSH_CNTL 0x0e4e // duplicate ++#define mmREMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 0 ++#define mmBIF_RB_CNTL 0x0e4f // duplicate ++#define mmBIF_RB_CNTL_BASE_IDX 0 ++#define mmBIF_RB_BASE 0x0e50 // duplicate ++#define mmBIF_RB_BASE_BASE_IDX 0 ++#define mmBIF_RB_RPTR 0x0e51 // duplicate ++#define mmBIF_RB_RPTR_BASE_IDX 0 ++#define mmBIF_RB_WPTR 0x0e52 // duplicate ++#define mmBIF_RB_WPTR_BASE_IDX 0 ++#define mmBIF_RB_WPTR_ADDR_HI 0x0e53 // duplicate ++#define mmBIF_RB_WPTR_ADDR_HI_BASE_IDX 0 ++#define mmBIF_RB_WPTR_ADDR_LO 0x0e54 // duplicate ++#define mmBIF_RB_WPTR_ADDR_LO_BASE_IDX 0 ++#define mmMAILBOX_INDEX 0x0e55 // duplicate ++#define mmMAILBOX_INDEX_BASE_IDX 0 ++#define mmBIF_GPUIOV_RESET_NOTIFICATION 0x0e62 // duplicate ++#define mmBIF_GPUIOV_RESET_NOTIFICATION_BASE_IDX 0 ++#define mmBIF_UVD_GPUIOV_CFG_SIZE 0x0e63 // duplicate ++#define mmBIF_UVD_GPUIOV_CFG_SIZE_BASE_IDX 0 ++#define mmBIF_VCE_GPUIOV_CFG_SIZE 0x0e64 // duplicate ++#define mmBIF_VCE_GPUIOV_CFG_SIZE_BASE_IDX 0 ++#define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE 0x0e65 // duplicate ++#define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE_BASE_IDX 0 ++#define mmBIF_GMI_WRR_WEIGHT 0x0e66 // duplicate ++#define mmBIF_GMI_WRR_WEIGHT_BASE_IDX 0 ++#define mmNBIF_STRAP_WRITE_CTRL 0x0e67 // duplicate ++#define mmNBIF_STRAP_WRITE_CTRL_BASE_IDX 0 ++#define mmBIF_PERSTB_PAD_CNTL 0x0e68 // duplicate ++#define mmBIF_PERSTB_PAD_CNTL_BASE_IDX 0 ++#define mmBIF_PX_EN_PAD_CNTL 0x0e69 // duplicate ++#define mmBIF_PX_EN_PAD_CNTL_BASE_IDX 0 ++#define mmBIF_REFPADKIN_PAD_CNTL 0x0e6a // duplicate ++#define mmBIF_REFPADKIN_PAD_CNTL_BASE_IDX 0 ++#define mmBIF_CLKREQB_PAD_CNTL 0x0e6b // duplicate ++#define mmBIF_CLKREQB_PAD_CNTL_BASE_IDX 0 ++ ++ ++// addressBlock: rcc_pf_0_BIFDEC1 ++// base address: 0x0 ++#define mmRCC_BACO_CNTL_MISC 0x0da7 // duplicate ++#define mmRCC_BACO_CNTL_MISC_BASE_IDX 0 ++#define mmRCC_RESET_EN 0x0da8 // duplicate ++#define mmRCC_RESET_EN_BASE_IDX 0 ++#define mmRCC_VDM_SUPPORT 0x0da9 // duplicate ++#define mmRCC_VDM_SUPPORT_BASE_IDX 0 ++#define mmRCC_PEER_REG_RANGE0 0x0dde // duplicate ++#define mmRCC_PEER_REG_RANGE0_BASE_IDX 0 ++#define mmRCC_PEER_REG_RANGE1 0x0ddf // duplicate ++#define mmRCC_PEER_REG_RANGE1_BASE_IDX 0 ++#define mmRCC_BUS_CNTL 0x0de1 // duplicate ++#define mmRCC_BUS_CNTL_BASE_IDX 0 ++#define mmRCC_CONFIG_CNTL 0x0de2 // duplicate ++#define mmRCC_CONFIG_CNTL_BASE_IDX 0 ++#define mmRCC_CONFIG_F0_BASE 0x0de6 // duplicate ++#define mmRCC_CONFIG_F0_BASE_BASE_IDX 0 ++#define mmRCC_CONFIG_APER_SIZE 0x0de7 // duplicate ++#define mmRCC_CONFIG_APER_SIZE_BASE_IDX 0 ++#define mmRCC_CONFIG_REG_APER_SIZE 0x0de8 // duplicate ++#define mmRCC_CONFIG_REG_APER_SIZE_BASE_IDX 0 ++#define mmRCC_XDMA_LO 0x0de9 // duplicate ++#define mmRCC_XDMA_LO_BASE_IDX 0 ++#define mmRCC_XDMA_HI 0x0dea // duplicate ++#define mmRCC_XDMA_HI_BASE_IDX 0 ++#define mmRCC_FEATURES_CONTROL_MISC 0x0deb // duplicate ++#define mmRCC_FEATURES_CONTROL_MISC_BASE_IDX 0 ++#define mmRCC_BUSNUM_CNTL1 0x0dec // duplicate ++#define mmRCC_BUSNUM_CNTL1_BASE_IDX 0 ++#define mmRCC_BUSNUM_LIST0 0x0ded // duplicate ++#define mmRCC_BUSNUM_LIST0_BASE_IDX 0 ++#define mmRCC_BUSNUM_LIST1 0x0dee // duplicate ++#define mmRCC_BUSNUM_LIST1_BASE_IDX 0 ++#define mmRCC_BUSNUM_CNTL2 0x0def // duplicate ++#define mmRCC_BUSNUM_CNTL2_BASE_IDX 0 ++#define mmRCC_CAPTURE_HOST_BUSNUM 0x0df0 // duplicate ++#define mmRCC_CAPTURE_HOST_BUSNUM_BASE_IDX 0 ++#define mmRCC_HOST_BUSNUM 0x0df1 // duplicate ++#define mmRCC_HOST_BUSNUM_BASE_IDX 0 ++#define mmRCC_PEER0_FB_OFFSET_HI 0x0df2 // duplicate ++#define mmRCC_PEER0_FB_OFFSET_HI_BASE_IDX 0 ++#define mmRCC_PEER0_FB_OFFSET_LO 0x0df3 // duplicate ++#define mmRCC_PEER0_FB_OFFSET_LO_BASE_IDX 0 ++#define mmRCC_PEER1_FB_OFFSET_HI 0x0df4 // duplicate ++#define mmRCC_PEER1_FB_OFFSET_HI_BASE_IDX 0 ++#define mmRCC_PEER1_FB_OFFSET_LO 0x0df5 // duplicate ++#define mmRCC_PEER1_FB_OFFSET_LO_BASE_IDX 0 ++#define mmRCC_PEER2_FB_OFFSET_HI 0x0df6 // duplicate ++#define mmRCC_PEER2_FB_OFFSET_HI_BASE_IDX 0 ++#define mmRCC_PEER2_FB_OFFSET_LO 0x0df7 // duplicate ++#define mmRCC_PEER2_FB_OFFSET_LO_BASE_IDX 0 ++#define mmRCC_PEER3_FB_OFFSET_HI 0x0df8 // duplicate ++#define mmRCC_PEER3_FB_OFFSET_HI_BASE_IDX 0 ++#define mmRCC_PEER3_FB_OFFSET_LO 0x0df9 // duplicate ++#define mmRCC_PEER3_FB_OFFSET_LO_BASE_IDX 0 ++#define mmRCC_DEVFUNCNUM_LIST0 0x0dfa // duplicate ++#define mmRCC_DEVFUNCNUM_LIST0_BASE_IDX 0 ++#define mmRCC_DEVFUNCNUM_LIST1 0x0dfb // duplicate ++#define mmRCC_DEVFUNCNUM_LIST1_BASE_IDX 0 ++#define mmRCC_DEV0_LINK_CNTL 0x0dfd // duplicate ++#define mmRCC_DEV0_LINK_CNTL_BASE_IDX 0 ++#define mmRCC_CMN_LINK_CNTL 0x0dfe // duplicate ++#define mmRCC_CMN_LINK_CNTL_BASE_IDX 0 ++#define mmRCC_EP_REQUESTERID_RESTORE 0x0dff // duplicate ++#define mmRCC_EP_REQUESTERID_RESTORE_BASE_IDX 0 ++#define mmRCC_LTR_LSWITCH_CNTL 0x0e00 // duplicate ++#define mmRCC_LTR_LSWITCH_CNTL_BASE_IDX 0 ++#define mmRCC_MH_ARB_CNTL 0x0e01 // duplicate ++#define mmRCC_MH_ARB_CNTL_BASE_IDX 0 ++ ++ ++// addressBlock: rcc_pf_0_BIFDEC2 ++// base address: 0x0 ++#define mmGFXMSIX_VECT0_ADDR_LO 0x10800 // duplicate ++#define mmGFXMSIX_VECT0_ADDR_LO_BASE_IDX 0 ++#define mmGFXMSIX_VECT0_ADDR_HI 0x10801 // duplicate ++#define mmGFXMSIX_VECT0_ADDR_HI_BASE_IDX 0 ++#define mmGFXMSIX_VECT0_MSG_DATA 0x10802 // duplicate ++#define mmGFXMSIX_VECT0_MSG_DATA_BASE_IDX 0 ++#define mmGFXMSIX_VECT0_CONTROL 0x10803 // duplicate ++#define mmGFXMSIX_VECT0_CONTROL_BASE_IDX 0 ++#define mmGFXMSIX_VECT1_ADDR_LO 0x10804 // duplicate ++#define mmGFXMSIX_VECT1_ADDR_LO_BASE_IDX 0 ++#define mmGFXMSIX_VECT1_ADDR_HI 0x10805 // duplicate ++#define mmGFXMSIX_VECT1_ADDR_HI_BASE_IDX 0 ++#define mmGFXMSIX_VECT1_MSG_DATA 0x10806 // duplicate ++#define mmGFXMSIX_VECT1_MSG_DATA_BASE_IDX 0 ++#define mmGFXMSIX_VECT1_CONTROL 0x10807 // duplicate ++#define mmGFXMSIX_VECT1_CONTROL_BASE_IDX 0 ++#define mmGFXMSIX_VECT2_ADDR_LO 0x10808 // duplicate ++#define mmGFXMSIX_VECT2_ADDR_LO_BASE_IDX 0 ++#define mmGFXMSIX_VECT2_ADDR_HI 0x10809 // duplicate ++#define mmGFXMSIX_VECT2_ADDR_HI_BASE_IDX 0 ++#define mmGFXMSIX_VECT2_MSG_DATA 0x1080a // duplicate ++#define mmGFXMSIX_VECT2_MSG_DATA_BASE_IDX 0 ++#define mmGFXMSIX_VECT2_CONTROL 0x1080b // duplicate ++#define mmGFXMSIX_VECT2_CONTROL_BASE_IDX 0 ++#define mmGFXMSIX_PBA 0x10c00 // duplicate ++#define mmGFXMSIX_PBA_BASE_IDX 0 ++ ++ ++// addressBlock: rcc_strap_BIFDEC1 ++// base address: 0x0 ++#define mmRCC_DEV0_PORT_STRAP0 0x0d27 // duplicate ++#define mmRCC_DEV0_PORT_STRAP0_BASE_IDX 0 ++#define mmRCC_DEV0_PORT_STRAP1 0x0d28 // duplicate ++#define mmRCC_DEV0_PORT_STRAP1_BASE_IDX 0 ++#define mmRCC_DEV0_PORT_STRAP2 0x0d29 // duplicate ++#define mmRCC_DEV0_PORT_STRAP2_BASE_IDX 0 ++#define mmRCC_DEV0_PORT_STRAP3 0x0d2a // duplicate ++#define mmRCC_DEV0_PORT_STRAP3_BASE_IDX 0 ++#define mmRCC_DEV0_PORT_STRAP4 0x0d2b // duplicate ++#define mmRCC_DEV0_PORT_STRAP4_BASE_IDX 0 ++#define mmRCC_DEV0_PORT_STRAP5 0x0d2c // duplicate ++#define mmRCC_DEV0_PORT_STRAP5_BASE_IDX 0 ++#define mmRCC_DEV0_PORT_STRAP6 0x0d2d // duplicate ++#define mmRCC_DEV0_PORT_STRAP6_BASE_IDX 0 ++#define mmRCC_DEV0_PORT_STRAP7 0x0d2e // duplicate ++#define mmRCC_DEV0_PORT_STRAP7_BASE_IDX 0 ++#define mmRCC_DEV0_EPF0_STRAP0 0x0d2f // duplicate ++#define mmRCC_DEV0_EPF0_STRAP0_BASE_IDX 0 ++#define mmRCC_DEV0_EPF0_STRAP1 0x0d30 // duplicate ++#define mmRCC_DEV0_EPF0_STRAP1_BASE_IDX 0 ++#define mmRCC_DEV0_EPF0_STRAP13 0x0d31 // duplicate ++#define mmRCC_DEV0_EPF0_STRAP13_BASE_IDX 0 ++#define mmRCC_DEV0_EPF0_STRAP2 0x0d32 // duplicate ++#define mmRCC_DEV0_EPF0_STRAP2_BASE_IDX 0 ++#define mmRCC_DEV0_EPF0_STRAP3 0x0d33 // duplicate ++#define mmRCC_DEV0_EPF0_STRAP3_BASE_IDX 0 ++#define mmRCC_DEV0_EPF0_STRAP4 0x0d34 // duplicate ++#define mmRCC_DEV0_EPF0_STRAP4_BASE_IDX 0 ++#define mmRCC_DEV0_EPF0_STRAP5 0x0d35 // duplicate ++#define mmRCC_DEV0_EPF0_STRAP5_BASE_IDX 0 ++#define mmRCC_DEV0_EPF0_STRAP8 0x0d36 // duplicate ++#define mmRCC_DEV0_EPF0_STRAP8_BASE_IDX 0 ++#define mmRCC_DEV0_EPF0_STRAP9 0x0d37 // duplicate ++#define mmRCC_DEV0_EPF0_STRAP9_BASE_IDX 0 ++#define mmRCC_DEV0_EPF1_STRAP0 0x0d38 // duplicate ++#define mmRCC_DEV0_EPF1_STRAP0_BASE_IDX 0 ++#define mmRCC_DEV0_EPF1_STRAP10 0x0d39 // duplicate ++#define mmRCC_DEV0_EPF1_STRAP10_BASE_IDX 0 ++#define mmRCC_DEV0_EPF1_STRAP11 0x0d3a // duplicate ++#define mmRCC_DEV0_EPF1_STRAP11_BASE_IDX 0 ++#define mmRCC_DEV0_EPF1_STRAP12 0x0d3b // duplicate ++#define mmRCC_DEV0_EPF1_STRAP12_BASE_IDX 0 ++#define mmRCC_DEV0_EPF1_STRAP13 0x0d3c // duplicate ++#define mmRCC_DEV0_EPF1_STRAP13_BASE_IDX 0 ++#define mmRCC_DEV0_EPF1_STRAP2 0x0d3d // duplicate ++#define mmRCC_DEV0_EPF1_STRAP2_BASE_IDX 0 ++#define mmRCC_DEV0_EPF1_STRAP3 0x0d3e // duplicate ++#define mmRCC_DEV0_EPF1_STRAP3_BASE_IDX 0 ++#define mmRCC_DEV0_EPF1_STRAP4 0x0d3f // duplicate ++#define mmRCC_DEV0_EPF1_STRAP4_BASE_IDX 0 ++#define mmRCC_DEV0_EPF1_STRAP5 0x0d40 // duplicate ++#define mmRCC_DEV0_EPF1_STRAP5_BASE_IDX 0 ++#define mmRCC_DEV0_EPF1_STRAP6 0x0d41 // duplicate ++#define mmRCC_DEV0_EPF1_STRAP6_BASE_IDX 0 ++#define mmRCC_DEV0_EPF1_STRAP7 0x0d42 // duplicate ++#define mmRCC_DEV0_EPF1_STRAP7_BASE_IDX 0 ++ ++ ++// addressBlock: bif_bx_pf_BIFPFVFDEC1 ++// base address: 0x0 ++#define mmBIF_BME_STATUS 0x0e0b // duplicate ++#define mmBIF_BME_STATUS_BASE_IDX 0 ++#define mmBIF_ATOMIC_ERR_LOG 0x0e0c // duplicate ++#define mmBIF_ATOMIC_ERR_LOG_BASE_IDX 0 ++#define mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x0e13 // duplicate ++#define mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 0 ++#define mmDOORBELL_SELFRING_GPA_APER_BASE_LOW 0x0e14 // duplicate ++#define mmDOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 0 ++#define mmDOORBELL_SELFRING_GPA_APER_CNTL 0x0e15 // duplicate ++#define mmDOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 0 ++#define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x0e16 // duplicate ++#define mmHDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 0 ++#define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x0e17 // duplicate ++#define mmHDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 0 ++#define mmGPU_HDP_FLUSH_REQ 0x0e26 // duplicate ++#define mmGPU_HDP_FLUSH_REQ_BASE_IDX 0 ++#define mmGPU_HDP_FLUSH_DONE 0x0e27 // duplicate ++#define mmGPU_HDP_FLUSH_DONE_BASE_IDX 0 ++#define mmBIF_TRANS_PENDING 0x0e28 // duplicate ++#define mmBIF_TRANS_PENDING_BASE_IDX 0 ++#define mmMAILBOX_MSGBUF_TRN_DW0 0x0e56 // duplicate ++#define mmMAILBOX_MSGBUF_TRN_DW0_BASE_IDX 0 ++#define mmMAILBOX_MSGBUF_TRN_DW1 0x0e57 // duplicate ++#define mmMAILBOX_MSGBUF_TRN_DW1_BASE_IDX 0 ++#define mmMAILBOX_MSGBUF_TRN_DW2 0x0e58 // duplicate ++#define mmMAILBOX_MSGBUF_TRN_DW2_BASE_IDX 0 ++#define mmMAILBOX_MSGBUF_TRN_DW3 0x0e59 // duplicate ++#define mmMAILBOX_MSGBUF_TRN_DW3_BASE_IDX 0 ++#define mmMAILBOX_MSGBUF_RCV_DW0 0x0e5a // duplicate ++#define mmMAILBOX_MSGBUF_RCV_DW0_BASE_IDX 0 ++#define mmMAILBOX_MSGBUF_RCV_DW1 0x0e5b // duplicate ++#define mmMAILBOX_MSGBUF_RCV_DW1_BASE_IDX 0 ++#define mmMAILBOX_MSGBUF_RCV_DW2 0x0e5c // duplicate ++#define mmMAILBOX_MSGBUF_RCV_DW2_BASE_IDX 0 ++#define mmMAILBOX_MSGBUF_RCV_DW3 0x0e5d // duplicate ++#define mmMAILBOX_MSGBUF_RCV_DW3_BASE_IDX 0 ++#define mmMAILBOX_CONTROL 0x0e5e // duplicate ++#define mmMAILBOX_CONTROL_BASE_IDX 0 ++#define mmMAILBOX_INT_CNTL 0x0e5f // duplicate ++#define mmMAILBOX_INT_CNTL_BASE_IDX 0 ++#define mmBIF_VMHV_MAILBOX 0x0e60 // duplicate ++#define mmBIF_VMHV_MAILBOX_BASE_IDX 0 ++ ++ ++// addressBlock: rcc_pf_0_BIFPFVFDEC1 ++// base address: 0x0 ++#define mmRCC_DOORBELL_APER_EN 0x0de0 // duplicate ++#define mmRCC_DOORBELL_APER_EN_BASE_IDX 0 ++#define mmRCC_CONFIG_MEMSIZE 0x0de3 // duplicate ++#define mmRCC_CONFIG_MEMSIZE_BASE_IDX 0 ++#define mmRCC_CONFIG_RESERVED 0x0de4 // duplicate ++#define mmRCC_CONFIG_RESERVED_BASE_IDX 0 ++#define mmRCC_IOV_FUNC_IDENTIFIER 0x0de5 // duplicate ++#define mmRCC_IOV_FUNC_IDENTIFIER_BASE_IDX 0 ++ ++ ++// addressBlock: syshub_mmreg_ind_syshubdec ++// base address: 0x0 ++#define mmSYSHUB_INDEX 0x0008 ++#define mmSYSHUB_INDEX_BASE_IDX 0 ++#define mmSYSHUB_DATA 0x0009 ++#define mmSYSHUB_DATA_BASE_IDX 0 ++ ++ ++// addressBlock: rcc_strap_rcc_strap_internal ++// base address: 0x10100000 ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0 0x403c000 // duplicate ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0_BASE_IDX 3 ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1 0x403c001 // duplicate ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1_BASE_IDX 3 ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2 0x403c002 // duplicate ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2_BASE_IDX 3 ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3 0x403c003 // duplicate ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3_BASE_IDX 3 ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4 0x403c004 // duplicate ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4_BASE_IDX 3 ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5 0x403c005 // duplicate ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5_BASE_IDX 3 ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6 0x403c006 // duplicate ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6_BASE_IDX 3 ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7 0x403c007 // duplicate ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7_BASE_IDX 3 ++#define mmRCC_DEV1_PORT_STRAP0 0x403c080 ++#define mmRCC_DEV1_PORT_STRAP0_BASE_IDX 3 ++#define mmRCC_DEV1_PORT_STRAP1 0x403c081 ++#define mmRCC_DEV1_PORT_STRAP1_BASE_IDX 3 ++#define mmRCC_DEV1_PORT_STRAP2 0x403c082 ++#define mmRCC_DEV1_PORT_STRAP2_BASE_IDX 3 ++#define mmRCC_DEV1_PORT_STRAP3 0x403c083 ++#define mmRCC_DEV1_PORT_STRAP3_BASE_IDX 3 ++#define mmRCC_DEV1_PORT_STRAP4 0x403c084 ++#define mmRCC_DEV1_PORT_STRAP4_BASE_IDX 3 ++#define mmRCC_DEV1_PORT_STRAP5 0x403c085 ++#define mmRCC_DEV1_PORT_STRAP5_BASE_IDX 3 ++#define mmRCC_DEV1_PORT_STRAP6 0x403c086 ++#define mmRCC_DEV1_PORT_STRAP6_BASE_IDX 3 ++#define mmRCC_DEV1_PORT_STRAP7 0x403c087 ++#define mmRCC_DEV1_PORT_STRAP7_BASE_IDX 3 ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0 0x403cc00 // duplicate ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0_BASE_IDX 3 ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1 0x403cc01 // duplicate ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1_BASE_IDX 3 ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2 0x403cc02 // duplicate ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2_BASE_IDX 3 ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3 0x403cc03 // duplicate ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3_BASE_IDX 3 ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4 0x403cc04 // duplicate ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4_BASE_IDX 3 ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5 0x403cc05 // duplicate ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5_BASE_IDX 3 ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8 0x403cc08 // duplicate ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8_BASE_IDX 3 ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP9 0x403cc09 // duplicate ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP9_BASE_IDX 3 ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13 0x403cc0d // duplicate ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13_BASE_IDX 3 ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0 0x403cc80 // duplicate ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0_BASE_IDX 3 ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2 0x403cc82 // duplicate ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2_BASE_IDX 3 ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3 0x403cc83 // duplicate ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3_BASE_IDX 3 ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4 0x403cc84 // duplicate ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4_BASE_IDX 3 ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5 0x403cc85 // duplicate ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5_BASE_IDX 3 ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6 0x403cc86 // duplicate ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6_BASE_IDX 3 ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7 0x403cc87 // duplicate ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7_BASE_IDX 3 ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10 0x403cc8a // duplicate ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10_BASE_IDX 3 ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11 0x403cc8b // duplicate ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11_BASE_IDX 3 ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12 0x403cc8c // duplicate ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12_BASE_IDX 3 ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13 0x403cc8d // duplicate ++#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13_BASE_IDX 3 ++#define mmRCC_DEV0_EPF2_STRAP0 0x403cd00 ++#define mmRCC_DEV0_EPF2_STRAP0_BASE_IDX 3 ++#define mmRCC_DEV0_EPF2_STRAP2 0x403cd02 ++#define mmRCC_DEV0_EPF2_STRAP2_BASE_IDX 3 ++#define mmRCC_DEV0_EPF2_STRAP3 0x403cd03 ++#define mmRCC_DEV0_EPF2_STRAP3_BASE_IDX 3 ++#define mmRCC_DEV0_EPF2_STRAP4 0x403cd04 ++#define mmRCC_DEV0_EPF2_STRAP4_BASE_IDX 3 ++#define mmRCC_DEV0_EPF2_STRAP5 0x403cd05 ++#define mmRCC_DEV0_EPF2_STRAP5_BASE_IDX 3 ++#define mmRCC_DEV0_EPF2_STRAP6 0x403cd06 ++#define mmRCC_DEV0_EPF2_STRAP6_BASE_IDX 3 ++#define mmRCC_DEV0_EPF2_STRAP13 0x403cd0d ++#define mmRCC_DEV0_EPF2_STRAP13_BASE_IDX 3 ++#define mmRCC_DEV0_EPF3_STRAP0 0x403cd80 ++#define mmRCC_DEV0_EPF3_STRAP0_BASE_IDX 3 ++#define mmRCC_DEV0_EPF3_STRAP2 0x403cd82 ++#define mmRCC_DEV0_EPF3_STRAP2_BASE_IDX 3 ++#define mmRCC_DEV0_EPF3_STRAP3 0x403cd83 ++#define mmRCC_DEV0_EPF3_STRAP3_BASE_IDX 3 ++#define mmRCC_DEV0_EPF3_STRAP4 0x403cd84 ++#define mmRCC_DEV0_EPF3_STRAP4_BASE_IDX 3 ++#define mmRCC_DEV0_EPF3_STRAP5 0x403cd85 ++#define mmRCC_DEV0_EPF3_STRAP5_BASE_IDX 3 ++#define mmRCC_DEV0_EPF3_STRAP6 0x403cd86 ++#define mmRCC_DEV0_EPF3_STRAP6_BASE_IDX 3 ++#define mmRCC_DEV0_EPF3_STRAP13 0x403cd8d ++#define mmRCC_DEV0_EPF3_STRAP13_BASE_IDX 3 ++#define mmRCC_DEV0_EPF4_STRAP0 0x403ce00 ++#define mmRCC_DEV0_EPF4_STRAP0_BASE_IDX 3 ++#define mmRCC_DEV0_EPF4_STRAP2 0x403ce02 ++#define mmRCC_DEV0_EPF4_STRAP2_BASE_IDX 3 ++#define mmRCC_DEV0_EPF4_STRAP3 0x403ce03 ++#define mmRCC_DEV0_EPF4_STRAP3_BASE_IDX 3 ++#define mmRCC_DEV0_EPF4_STRAP4 0x403ce04 ++#define mmRCC_DEV0_EPF4_STRAP4_BASE_IDX 3 ++#define mmRCC_DEV0_EPF4_STRAP5 0x403ce05 ++#define mmRCC_DEV0_EPF4_STRAP5_BASE_IDX 3 ++#define mmRCC_DEV0_EPF4_STRAP6 0x403ce06 ++#define mmRCC_DEV0_EPF4_STRAP6_BASE_IDX 3 ++#define mmRCC_DEV0_EPF4_STRAP13 0x403ce0d ++#define mmRCC_DEV0_EPF4_STRAP13_BASE_IDX 3 ++#define mmRCC_DEV0_EPF5_STRAP0 0x403ce80 ++#define mmRCC_DEV0_EPF5_STRAP0_BASE_IDX 3 ++#define mmRCC_DEV0_EPF5_STRAP2 0x403ce82 ++#define mmRCC_DEV0_EPF5_STRAP2_BASE_IDX 3 ++#define mmRCC_DEV0_EPF5_STRAP3 0x403ce83 ++#define mmRCC_DEV0_EPF5_STRAP3_BASE_IDX 3 ++#define mmRCC_DEV0_EPF5_STRAP4 0x403ce84 ++#define mmRCC_DEV0_EPF5_STRAP4_BASE_IDX 3 ++#define mmRCC_DEV0_EPF5_STRAP5 0x403ce85 ++#define mmRCC_DEV0_EPF5_STRAP5_BASE_IDX 3 ++#define mmRCC_DEV0_EPF5_STRAP6 0x403ce86 ++#define mmRCC_DEV0_EPF5_STRAP6_BASE_IDX 3 ++#define mmRCC_DEV0_EPF5_STRAP13 0x403ce8d ++#define mmRCC_DEV0_EPF5_STRAP13_BASE_IDX 3 ++#define mmRCC_DEV0_EPF6_STRAP0 0x403cf00 ++#define mmRCC_DEV0_EPF6_STRAP0_BASE_IDX 3 ++#define mmRCC_DEV0_EPF6_STRAP2 0x403cf02 ++#define mmRCC_DEV0_EPF6_STRAP2_BASE_IDX 3 ++#define mmRCC_DEV0_EPF6_STRAP3 0x403cf03 ++#define mmRCC_DEV0_EPF6_STRAP3_BASE_IDX 3 ++#define mmRCC_DEV0_EPF6_STRAP4 0x403cf04 ++#define mmRCC_DEV0_EPF6_STRAP4_BASE_IDX 3 ++#define mmRCC_DEV0_EPF6_STRAP5 0x403cf05 ++#define mmRCC_DEV0_EPF6_STRAP5_BASE_IDX 3 ++#define mmRCC_DEV0_EPF6_STRAP6 0x403cf06 ++#define mmRCC_DEV0_EPF6_STRAP6_BASE_IDX 3 ++#define mmRCC_DEV0_EPF6_STRAP13 0x403cf0d ++#define mmRCC_DEV0_EPF6_STRAP13_BASE_IDX 3 ++#define mmRCC_DEV0_EPF7_STRAP0 0x403cf80 ++#define mmRCC_DEV0_EPF7_STRAP0_BASE_IDX 3 ++#define mmRCC_DEV0_EPF7_STRAP2 0x403cf82 ++#define mmRCC_DEV0_EPF7_STRAP2_BASE_IDX 3 ++#define mmRCC_DEV0_EPF7_STRAP3 0x403cf83 ++#define mmRCC_DEV0_EPF7_STRAP3_BASE_IDX 3 ++#define mmRCC_DEV0_EPF7_STRAP4 0x403cf84 ++#define mmRCC_DEV0_EPF7_STRAP4_BASE_IDX 3 ++#define mmRCC_DEV0_EPF7_STRAP5 0x403cf85 ++#define mmRCC_DEV0_EPF7_STRAP5_BASE_IDX 3 ++#define mmRCC_DEV0_EPF7_STRAP6 0x403cf86 ++#define mmRCC_DEV0_EPF7_STRAP6_BASE_IDX 3 ++#define mmRCC_DEV0_EPF7_STRAP13 0x403cf8d ++#define mmRCC_DEV0_EPF7_STRAP13_BASE_IDX 3 ++#define mmRCC_DEV1_EPF0_STRAP0 0x403d000 ++#define mmRCC_DEV1_EPF0_STRAP0_BASE_IDX 3 ++#define mmRCC_DEV1_EPF0_STRAP2 0x403d002 ++#define mmRCC_DEV1_EPF0_STRAP2_BASE_IDX 3 ++#define mmRCC_DEV1_EPF0_STRAP3 0x403d003 ++#define mmRCC_DEV1_EPF0_STRAP3_BASE_IDX 3 ++#define mmRCC_DEV1_EPF0_STRAP4 0x403d004 ++#define mmRCC_DEV1_EPF0_STRAP4_BASE_IDX 3 ++#define mmRCC_DEV1_EPF0_STRAP5 0x403d005 ++#define mmRCC_DEV1_EPF0_STRAP5_BASE_IDX 3 ++#define mmRCC_DEV1_EPF0_STRAP6 0x403d006 ++#define mmRCC_DEV1_EPF0_STRAP6_BASE_IDX 3 ++#define mmRCC_DEV1_EPF0_STRAP13 0x403d00d ++#define mmRCC_DEV1_EPF0_STRAP13_BASE_IDX 3 ++#define mmRCC_DEV1_EPF1_STRAP0 0x403d080 ++#define mmRCC_DEV1_EPF1_STRAP0_BASE_IDX 3 ++#define mmRCC_DEV1_EPF1_STRAP2 0x403d082 ++#define mmRCC_DEV1_EPF1_STRAP2_BASE_IDX 3 ++#define mmRCC_DEV1_EPF1_STRAP3 0x403d083 ++#define mmRCC_DEV1_EPF1_STRAP3_BASE_IDX 3 ++#define mmRCC_DEV1_EPF1_STRAP4 0x403d084 ++#define mmRCC_DEV1_EPF1_STRAP4_BASE_IDX 3 ++#define mmRCC_DEV1_EPF1_STRAP5 0x403d085 ++#define mmRCC_DEV1_EPF1_STRAP5_BASE_IDX 3 ++#define mmRCC_DEV1_EPF1_STRAP6 0x403d086 ++#define mmRCC_DEV1_EPF1_STRAP6_BASE_IDX 3 ++#define mmRCC_DEV1_EPF1_STRAP13 0x403d08d ++#define mmRCC_DEV1_EPF1_STRAP13_BASE_IDX 3 ++#define mmRCC_DEV1_EPF2_STRAP0 0x403d100 ++#define mmRCC_DEV1_EPF2_STRAP0_BASE_IDX 3 ++#define mmRCC_DEV1_EPF2_STRAP2 0x403d102 ++#define mmRCC_DEV1_EPF2_STRAP2_BASE_IDX 3 ++#define mmRCC_DEV1_EPF2_STRAP3 0x403d103 ++#define mmRCC_DEV1_EPF2_STRAP3_BASE_IDX 3 ++#define mmRCC_DEV1_EPF2_STRAP4 0x403d104 ++#define mmRCC_DEV1_EPF2_STRAP4_BASE_IDX 3 ++#define mmRCC_DEV1_EPF2_STRAP5 0x403d105 ++#define mmRCC_DEV1_EPF2_STRAP5_BASE_IDX 3 ++#define mmRCC_DEV1_EPF2_STRAP6 0x403d106 ++#define mmRCC_DEV1_EPF2_STRAP6_BASE_IDX 3 ++#define mmRCC_DEV1_EPF2_STRAP13 0x403d10d ++#define mmRCC_DEV1_EPF2_STRAP13_BASE_IDX 3 ++ ++ ++// addressBlock: bif_rst_bif_rst_regblk ++// base address: 0x10100000 ++#define ixHARD_RST_CTRL 0x38000 ++#define ixRSMU_SOFT_RST_CTRL 0x38004 ++#define ixSELF_SOFT_RST 0x38008 ++#define ixGFX_DRV_MODE1_RST_CTRL 0x3800c ++#define ixBIF_RST_MISC_CTRL 0x38010 ++#define ixBIF_RST_MISC_CTRL2 0x38014 ++#define ixBIF_RST_MISC_CTRL3 0x38018 ++#define ixBIF_RST_GFXVF_FLR_IDLE 0x3801c ++#define ixDEV0_PF0_FLR_RST_CTRL 0x38020 ++#define ixDEV0_PF1_FLR_RST_CTRL 0x38024 ++#define ixDEV0_PF2_FLR_RST_CTRL 0x38028 ++#define ixDEV0_PF3_FLR_RST_CTRL 0x3802c ++#define ixDEV0_PF4_FLR_RST_CTRL 0x38030 ++#define ixDEV0_PF5_FLR_RST_CTRL 0x38034 ++#define ixDEV0_PF6_FLR_RST_CTRL 0x38038 ++#define ixDEV0_PF7_FLR_RST_CTRL 0x3803c ++#define ixBIF_INST_RESET_INTR_STS 0x38040 ++#define ixBIF_PF_FLR_INTR_STS 0x38044 ++#define ixBIF_D3HOTD0_INTR_STS 0x38048 ++#define ixBIF_POWER_INTR_STS 0x38050 ++#define ixBIF_PF_DSTATE_INTR_STS 0x38054 ++#define ixBIF_PF0_VF_FLR_INTR_STS 0x38060 ++#define ixBIF_INST_RESET_INTR_MASK 0x38080 ++#define ixBIF_PF_FLR_INTR_MASK 0x38084 ++#define ixBIF_D3HOTD0_INTR_MASK 0x38088 ++#define ixBIF_POWER_INTR_MASK 0x38090 ++#define ixBIF_PF_DSTATE_INTR_MASK 0x38094 ++#define ixBIF_PF0_VF_FLR_INTR_MASK 0x380a0 ++#define ixBIF_PF_FLR_RST 0x38100 ++#define ixBIF_PF0_VF_FLR_RST 0x38120 ++#define ixBIF_DEV0_PF0_DSTATE_VALUE 0x38140 ++#define ixBIF_DEV0_PF1_DSTATE_VALUE 0x38144 ++#define ixBIF_DEV0_PF2_DSTATE_VALUE 0x38148 ++#define ixBIF_DEV0_PF3_DSTATE_VALUE 0x3814c ++#define ixBIF_DEV0_PF4_DSTATE_VALUE 0x38150 ++#define ixBIF_DEV0_PF5_DSTATE_VALUE 0x38154 ++#define ixBIF_DEV0_PF6_DSTATE_VALUE 0x38158 ++#define ixBIF_DEV0_PF7_DSTATE_VALUE 0x3815c ++#define ixDEV0_PF0_D3HOTD0_RST_CTRL 0x381e0 ++#define ixDEV0_PF1_D3HOTD0_RST_CTRL 0x381e4 ++#define ixDEV0_PF2_D3HOTD0_RST_CTRL 0x381e8 ++#define ixDEV0_PF3_D3HOTD0_RST_CTRL 0x381ec ++#define ixDEV0_PF4_D3HOTD0_RST_CTRL 0x381f0 ++#define ixDEV0_PF5_D3HOTD0_RST_CTRL 0x381f4 ++#define ixDEV0_PF6_D3HOTD0_RST_CTRL 0x381f8 ++#define ixDEV0_PF7_D3HOTD0_RST_CTRL 0x381fc ++#define ixBIF_PORT0_DSTATE_VALUE 0x388c0 ++ ++ ++// addressBlock: bif_misc_bif_misc_regblk ++// base address: 0x10100000 ++#define ixMISC_SCRATCH 0x3a000 ++#define ixINTR_LINE_POLARITY 0x3a004 ++#define ixINTR_LINE_ENABLE 0x3a008 ++#define ixOUTSTANDING_VC_ALLOC 0x3a00c ++#define ixBIFC_MISC_CTRL0 0x3a010 ++#define ixBIFC_MISC_CTRL1 0x3a014 ++#define ixBIFC_BME_ERR_LOG 0x3a018 ++#define ixBIFC_RCCBIH_BME_ERR_LOG 0x3a01c ++#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 0x3a020 ++#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 0x3a024 ++#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 0x3a028 ++#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 0x3a02c ++#define ixNBIF_VWIRE_CTRL 0x3a040 ++#define ixNBIF_SMN_VWR_VCHG_DIS_CTRL 0x3a044 ++#define ixNBIF_SMN_VWR_VCHG_RST_CTRL0 0x3a048 ++#define ixNBIF_SMN_VWR_VCHG_TRIG 0x3a050 ++#define ixNBIF_SMN_VWR_WTRIG_CNTL 0x3a054 ++#define ixNBIF_SMN_VWR_VCHG_DIS_CTRL_1 0x3a058 ++#define ixNBIF_MGCG_CTRL 0x3a05c ++#define ixNBIF_DS_CTRL_LCLK 0x3a060 ++#define ixSMN_MST_CNTL0 0x3a064 ++#define ixSMN_MST_EP_CNTL1 0x3a068 ++#define ixSMN_MST_EP_CNTL2 0x3a06c ++#define ixNBIF_SDP_VWR_VCHG_DIS_CTRL 0x3a070 ++#define ixNBIF_SDP_VWR_VCHG_RST_CTRL0 0x3a074 ++#define ixNBIF_SDP_VWR_VCHG_RST_CTRL1 0x3a078 ++#define ixNBIF_SDP_VWR_VCHG_TRIG 0x3a07c ++#define ixBME_DUMMY_CNTL_0 0x3a098 ++#define ixBIFC_THT_CNTL 0x3a09c ++#define ixBIFC_HSTARB_CNTL 0x3a0a0 ++#define ixBIFC_GSI_CNTL 0x3a0a4 ++#define ixBIFC_PCIEFUNC_CNTL 0x3a0a8 ++#define ixBIFC_SDP_CNTL_0 0x3a0b0 ++#define ixBIFC_PERF_CNTL_0 0x3a0c0 ++#define ixBIFC_PERF_CNTL_1 0x3a0c4 ++#define ixBIFC_PERF_CNT_MMIO_RD 0x3a0c8 ++#define ixBIFC_PERF_CNT_MMIO_WR 0x3a0cc ++#define ixBIFC_PERF_CNT_DMA_RD 0x3a0d0 ++#define ixBIFC_PERF_CNT_DMA_WR 0x3a0d4 ++#define ixNBIF_REGIF_ERRSET_CTRL 0x3a0d8 ++#define ixSMN_MST_EP_CNTL3 0x3a0f0 ++#define ixSMN_MST_EP_CNTL4 0x3a0f4 ++#define ixBIF_SELFRING_BUFFER_VID 0x3a100 ++#define ixBIF_SELFRING_VECTOR_CNTL 0x3a104 ++ ++ ++// addressBlock: bif_ras_bif_ras_regblk ++// base address: 0x10100000 ++#define ixBIF_RAS_LEAF0_CTRL 0x39000 ++#define ixBIF_RAS_LEAF1_CTRL 0x39004 ++#define ixBIF_RAS_LEAF2_CTRL 0x39008 ++#define ixBIF_RAS_MISC_CTRL 0x39100 ++#define ixBIF_IOHUB_RAS_IH_CNTL 0x39ff8 ++#define ixBIF_RAS_VWR_FROM_IOHUB 0x39ffc ++ ++ ++// addressBlock: rcc_pfc_amdgfx_RCCPFCDEC ++// base address: 0x10134000 ++#define ixRCC_PFC_LTR_CNTL 0x0100 // duplicate ++#define ixRCC_PFC_PME_RESTORE 0x0104 // duplicate ++#define ixRCC_PFC_STICKY_RESTORE_0 0x0108 // duplicate ++#define ixRCC_PFC_STICKY_RESTORE_1 0x010c // duplicate ++#define ixRCC_PFC_STICKY_RESTORE_2 0x0110 // duplicate ++#define ixRCC_PFC_STICKY_RESTORE_3 0x0114 // duplicate ++#define ixRCC_PFC_STICKY_RESTORE_4 0x0118 // duplicate ++#define ixRCC_PFC_STICKY_RESTORE_5 0x011c // duplicate ++#define ixRCC_PFC_AUXPWR_CNTL 0x0120 // duplicate ++ ++ ++// addressBlock: rcc_pfc_amdgfxaz_RCCPFCDEC ++// base address: 0x10134200 ++#define ixRCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL 0x0100 // duplicate ++#define ixRCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE 0x0104 // duplicate ++#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0 0x0108 // duplicate ++#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1 0x010c // duplicate ++#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2 0x0110 // duplicate ++#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3 0x0114 // duplicate ++#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4 0x0118 // duplicate ++#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5 0x011c // duplicate ++#define ixRCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL 0x0120 // duplicate ++ ++ ++// addressBlock: pciemsix_amdgfx_MSIXTDEC ++// base address: 0x10170000 ++#define ixPCIEMSIX_VECT0_ADDR_LO 0x0000 ++#define ixPCIEMSIX_VECT0_ADDR_HI 0x0004 ++#define ixPCIEMSIX_VECT0_MSG_DATA 0x0008 ++#define ixPCIEMSIX_VECT0_CONTROL 0x000c ++#define ixPCIEMSIX_VECT1_ADDR_LO 0x0010 ++#define ixPCIEMSIX_VECT1_ADDR_HI 0x0014 ++#define ixPCIEMSIX_VECT1_MSG_DATA 0x0018 ++#define ixPCIEMSIX_VECT1_CONTROL 0x001c ++#define ixPCIEMSIX_VECT2_ADDR_LO 0x0020 ++#define ixPCIEMSIX_VECT2_ADDR_HI 0x0024 ++#define ixPCIEMSIX_VECT2_MSG_DATA 0x0028 ++#define ixPCIEMSIX_VECT2_CONTROL 0x002c ++#define ixPCIEMSIX_VECT3_ADDR_LO 0x0030 ++#define ixPCIEMSIX_VECT3_ADDR_HI 0x0034 ++#define ixPCIEMSIX_VECT3_MSG_DATA 0x0038 ++#define ixPCIEMSIX_VECT3_CONTROL 0x003c ++#define ixPCIEMSIX_VECT4_ADDR_LO 0x0040 ++#define ixPCIEMSIX_VECT4_ADDR_HI 0x0044 ++#define ixPCIEMSIX_VECT4_MSG_DATA 0x0048 ++#define ixPCIEMSIX_VECT4_CONTROL 0x004c ++#define ixPCIEMSIX_VECT5_ADDR_LO 0x0050 ++#define ixPCIEMSIX_VECT5_ADDR_HI 0x0054 ++#define ixPCIEMSIX_VECT5_MSG_DATA 0x0058 ++#define ixPCIEMSIX_VECT5_CONTROL 0x005c ++#define ixPCIEMSIX_VECT6_ADDR_LO 0x0060 ++#define ixPCIEMSIX_VECT6_ADDR_HI 0x0064 ++#define ixPCIEMSIX_VECT6_MSG_DATA 0x0068 ++#define ixPCIEMSIX_VECT6_CONTROL 0x006c ++#define ixPCIEMSIX_VECT7_ADDR_LO 0x0070 ++#define ixPCIEMSIX_VECT7_ADDR_HI 0x0074 ++#define ixPCIEMSIX_VECT7_MSG_DATA 0x0078 ++#define ixPCIEMSIX_VECT7_CONTROL 0x007c ++#define ixPCIEMSIX_VECT8_ADDR_LO 0x0080 ++#define ixPCIEMSIX_VECT8_ADDR_HI 0x0084 ++#define ixPCIEMSIX_VECT8_MSG_DATA 0x0088 ++#define ixPCIEMSIX_VECT8_CONTROL 0x008c ++#define ixPCIEMSIX_VECT9_ADDR_LO 0x0090 ++#define ixPCIEMSIX_VECT9_ADDR_HI 0x0094 ++#define ixPCIEMSIX_VECT9_MSG_DATA 0x0098 ++#define ixPCIEMSIX_VECT9_CONTROL 0x009c ++#define ixPCIEMSIX_VECT10_ADDR_LO 0x00a0 ++#define ixPCIEMSIX_VECT10_ADDR_HI 0x00a4 ++#define ixPCIEMSIX_VECT10_MSG_DATA 0x00a8 ++#define ixPCIEMSIX_VECT10_CONTROL 0x00ac ++#define ixPCIEMSIX_VECT11_ADDR_LO 0x00b0 ++#define ixPCIEMSIX_VECT11_ADDR_HI 0x00b4 ++#define ixPCIEMSIX_VECT11_MSG_DATA 0x00b8 ++#define ixPCIEMSIX_VECT11_CONTROL 0x00bc ++#define ixPCIEMSIX_VECT12_ADDR_LO 0x00c0 ++#define ixPCIEMSIX_VECT12_ADDR_HI 0x00c4 ++#define ixPCIEMSIX_VECT12_MSG_DATA 0x00c8 ++#define ixPCIEMSIX_VECT12_CONTROL 0x00cc ++#define ixPCIEMSIX_VECT13_ADDR_LO 0x00d0 ++#define ixPCIEMSIX_VECT13_ADDR_HI 0x00d4 ++#define ixPCIEMSIX_VECT13_MSG_DATA 0x00d8 ++#define ixPCIEMSIX_VECT13_CONTROL 0x00dc ++#define ixPCIEMSIX_VECT14_ADDR_LO 0x00e0 ++#define ixPCIEMSIX_VECT14_ADDR_HI 0x00e4 ++#define ixPCIEMSIX_VECT14_MSG_DATA 0x00e8 ++#define ixPCIEMSIX_VECT14_CONTROL 0x00ec ++#define ixPCIEMSIX_VECT15_ADDR_LO 0x00f0 ++#define ixPCIEMSIX_VECT15_ADDR_HI 0x00f4 ++#define ixPCIEMSIX_VECT15_MSG_DATA 0x00f8 ++#define ixPCIEMSIX_VECT15_CONTROL 0x00fc ++#define ixPCIEMSIX_VECT16_ADDR_LO 0x0100 ++#define ixPCIEMSIX_VECT16_ADDR_HI 0x0104 ++#define ixPCIEMSIX_VECT16_MSG_DATA 0x0108 ++#define ixPCIEMSIX_VECT16_CONTROL 0x010c ++#define ixPCIEMSIX_VECT17_ADDR_LO 0x0110 ++#define ixPCIEMSIX_VECT17_ADDR_HI 0x0114 ++#define ixPCIEMSIX_VECT17_MSG_DATA 0x0118 ++#define ixPCIEMSIX_VECT17_CONTROL 0x011c ++#define ixPCIEMSIX_VECT18_ADDR_LO 0x0120 ++#define ixPCIEMSIX_VECT18_ADDR_HI 0x0124 ++#define ixPCIEMSIX_VECT18_MSG_DATA 0x0128 ++#define ixPCIEMSIX_VECT18_CONTROL 0x012c ++#define ixPCIEMSIX_VECT19_ADDR_LO 0x0130 ++#define ixPCIEMSIX_VECT19_ADDR_HI 0x0134 ++#define ixPCIEMSIX_VECT19_MSG_DATA 0x0138 ++#define ixPCIEMSIX_VECT19_CONTROL 0x013c ++#define ixPCIEMSIX_VECT20_ADDR_LO 0x0140 ++#define ixPCIEMSIX_VECT20_ADDR_HI 0x0144 ++#define ixPCIEMSIX_VECT20_MSG_DATA 0x0148 ++#define ixPCIEMSIX_VECT20_CONTROL 0x014c ++#define ixPCIEMSIX_VECT21_ADDR_LO 0x0150 ++#define ixPCIEMSIX_VECT21_ADDR_HI 0x0154 ++#define ixPCIEMSIX_VECT21_MSG_DATA 0x0158 ++#define ixPCIEMSIX_VECT21_CONTROL 0x015c ++#define ixPCIEMSIX_VECT22_ADDR_LO 0x0160 ++#define ixPCIEMSIX_VECT22_ADDR_HI 0x0164 ++#define ixPCIEMSIX_VECT22_MSG_DATA 0x0168 ++#define ixPCIEMSIX_VECT22_CONTROL 0x016c ++#define ixPCIEMSIX_VECT23_ADDR_LO 0x0170 ++#define ixPCIEMSIX_VECT23_ADDR_HI 0x0174 ++#define ixPCIEMSIX_VECT23_MSG_DATA 0x0178 ++#define ixPCIEMSIX_VECT23_CONTROL 0x017c ++#define ixPCIEMSIX_VECT24_ADDR_LO 0x0180 ++#define ixPCIEMSIX_VECT24_ADDR_HI 0x0184 ++#define ixPCIEMSIX_VECT24_MSG_DATA 0x0188 ++#define ixPCIEMSIX_VECT24_CONTROL 0x018c ++#define ixPCIEMSIX_VECT25_ADDR_LO 0x0190 ++#define ixPCIEMSIX_VECT25_ADDR_HI 0x0194 ++#define ixPCIEMSIX_VECT25_MSG_DATA 0x0198 ++#define ixPCIEMSIX_VECT25_CONTROL 0x019c ++#define ixPCIEMSIX_VECT26_ADDR_LO 0x01a0 ++#define ixPCIEMSIX_VECT26_ADDR_HI 0x01a4 ++#define ixPCIEMSIX_VECT26_MSG_DATA 0x01a8 ++#define ixPCIEMSIX_VECT26_CONTROL 0x01ac ++#define ixPCIEMSIX_VECT27_ADDR_LO 0x01b0 ++#define ixPCIEMSIX_VECT27_ADDR_HI 0x01b4 ++#define ixPCIEMSIX_VECT27_MSG_DATA 0x01b8 ++#define ixPCIEMSIX_VECT27_CONTROL 0x01bc ++#define ixPCIEMSIX_VECT28_ADDR_LO 0x01c0 ++#define ixPCIEMSIX_VECT28_ADDR_HI 0x01c4 ++#define ixPCIEMSIX_VECT28_MSG_DATA 0x01c8 ++#define ixPCIEMSIX_VECT28_CONTROL 0x01cc ++#define ixPCIEMSIX_VECT29_ADDR_LO 0x01d0 ++#define ixPCIEMSIX_VECT29_ADDR_HI 0x01d4 ++#define ixPCIEMSIX_VECT29_MSG_DATA 0x01d8 ++#define ixPCIEMSIX_VECT29_CONTROL 0x01dc ++#define ixPCIEMSIX_VECT30_ADDR_LO 0x01e0 ++#define ixPCIEMSIX_VECT30_ADDR_HI 0x01e4 ++#define ixPCIEMSIX_VECT30_MSG_DATA 0x01e8 ++#define ixPCIEMSIX_VECT30_CONTROL 0x01ec ++#define ixPCIEMSIX_VECT31_ADDR_LO 0x01f0 ++#define ixPCIEMSIX_VECT31_ADDR_HI 0x01f4 ++#define ixPCIEMSIX_VECT31_MSG_DATA 0x01f8 ++#define ixPCIEMSIX_VECT31_CONTROL 0x01fc ++ ++ ++// addressBlock: pciemsix_amdgfx_MSIXPDEC ++// base address: 0x10171000 ++#define ixPCIEMSIX_PBA 0x0000 ++ ++ ++// addressBlock: syshub_mmreg_ind_syshubind ++// base address: 0x0 ++#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK 0x10000 // duplicate ++#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK 0x10004 // duplicate ++#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK 0x10008 // duplicate ++#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK 0x1000c // duplicate ++#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL 0x10010 // duplicate ++#define ixSYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL 0x10014 // duplicate ++#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL 0x10018 // duplicate ++#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL 0x1001c // duplicate ++#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL 0x10020 // duplicate ++#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL 0x10024 // duplicate ++#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL 0x10028 // duplicate ++#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL 0x1002c // duplicate ++#define ixSYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL 0x10030 // duplicate ++#define ixSYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL 0x10034 // duplicate ++#define ixSYSHUBMMREGIND_SYSHUB_CG_CNTL 0x10300 // duplicate ++#define ixSYSHUBMMREGIND_SYSHUB_TRANS_IDLE 0x10308 // duplicate ++#define ixSYSHUBMMREGIND_SYSHUB_HP_TIMER 0x1030c // duplicate ++#define ixSYSHUBMMREGIND_SYSHUB_SCRATCH 0x10f00 // duplicate ++#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK 0x11000 // duplicate ++#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK 0x11004 // duplicate ++#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK 0x11008 // duplicate ++#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK 0x1100c // duplicate ++#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL 0x11010 // duplicate ++#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL 0x11014 // duplicate ++#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL 0x11018 // duplicate ++#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL 0x1101c // duplicate ++#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL 0x11020 // duplicate ++#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL 0x11024 // duplicate ++#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL 0x11028 // duplicate ++#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL 0x1102c // duplicate ++#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL 0x11030 // duplicate ++#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL 0x11034 // duplicate ++#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL 0x11038 // duplicate ++#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL 0x1103c // duplicate ++ ++#endif +diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_sh_mask.h +new file mode 100644 +index 0000000..c7518b8 +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/asic_reg/nbif/nbif_6_1_sh_mask.h +@@ -0,0 +1,10281 @@ ++/* ++ * Copyright (C) 2017 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#ifndef _nbif_6_1_SH_MASK_HEADER ++#define _nbif_6_1_SH_MASK_HEADER ++ ++ ++// addressBlock: bif_cfg_dev0_epf0_bifcfgdecp ++//VENDOR_ID ++#define VENDOR_ID__VENDOR_ID__SHIFT 0x0 ++//DEVICE_ID ++#define DEVICE_ID__DEVICE_ID__SHIFT 0x0 ++//COMMAND ++#define COMMAND__IO_ACCESS_EN__SHIFT 0x0 ++#define COMMAND__MEM_ACCESS_EN__SHIFT 0x1 ++#define COMMAND__BUS_MASTER_EN__SHIFT 0x2 ++#define COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 ++#define COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 ++#define COMMAND__PAL_SNOOP_EN__SHIFT 0x5 ++#define COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 ++#define COMMAND__AD_STEPPING__SHIFT 0x7 ++#define COMMAND__SERR_EN__SHIFT 0x8 ++#define COMMAND__FAST_B2B_EN__SHIFT 0x9 ++#define COMMAND__INT_DIS__SHIFT 0xa ++//STATUS ++#define STATUS__INT_STATUS__SHIFT 0x3 ++#define STATUS__CAP_LIST__SHIFT 0x4 ++#define STATUS__PCI_66_EN__SHIFT 0x5 ++#define STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 ++#define STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 ++#define STATUS__DEVSEL_TIMING__SHIFT 0x9 ++#define STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb ++#define STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc ++#define STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd ++#define STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe ++#define STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf ++//REVISION_ID ++#define REVISION_ID__MINOR_REV_ID__SHIFT 0x0 ++#define REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 ++//PROG_INTERFACE ++#define PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 ++//SUB_CLASS ++#define SUB_CLASS__SUB_CLASS__SHIFT 0x0 ++//BASE_CLASS ++#define BASE_CLASS__BASE_CLASS__SHIFT 0x0 ++//CACHE_LINE ++#define CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 ++//LATENCY ++#define LATENCY__LATENCY_TIMER__SHIFT 0x0 ++//HEADER ++#define HEADER__HEADER_TYPE__SHIFT 0x0 ++#define HEADER__DEVICE_TYPE__SHIFT 0x7 ++//BIST ++#define BIST__BIST_COMP__SHIFT 0x0 ++#define BIST__BIST_STRT__SHIFT 0x6 ++#define BIST__BIST_CAP__SHIFT 0x7 ++//BASE_ADDR_1 ++#define BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 ++//BASE_ADDR_2 ++#define BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 ++//BASE_ADDR_3 ++#define BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 ++//BASE_ADDR_4 ++#define BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 ++//BASE_ADDR_5 ++#define BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 ++//BASE_ADDR_6 ++#define BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 ++//ADAPTER_ID ++#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 ++#define ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 ++//ROM_BASE_ADDR ++#define ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 ++//CAP_PTR ++#define CAP_PTR__CAP_PTR__SHIFT 0x0 ++//INTERRUPT_LINE ++#define INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 ++//INTERRUPT_PIN ++#define INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 ++//MIN_GRANT ++#define MIN_GRANT__MIN_GNT__SHIFT 0x0 ++//MAX_LATENCY ++#define MAX_LATENCY__MAX_LAT__SHIFT 0x0 ++//VENDOR_CAP_LIST ++#define VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++#define VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 ++//ADAPTER_ID_W ++#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 ++#define ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 ++//PMI_CAP_LIST ++#define PMI_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++//PMI_CAP ++#define PMI_CAP__VERSION__SHIFT 0x0 ++#define PMI_CAP__PME_CLOCK__SHIFT 0x3 ++#define PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 ++#define PMI_CAP__AUX_CURRENT__SHIFT 0x6 ++#define PMI_CAP__D1_SUPPORT__SHIFT 0x9 ++#define PMI_CAP__D2_SUPPORT__SHIFT 0xa ++#define PMI_CAP__PME_SUPPORT__SHIFT 0xb ++//PMI_STATUS_CNTL ++#define PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 ++#define PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 ++#define PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 ++#define PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 ++#define PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd ++#define PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf ++#define PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 ++#define PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 ++#define PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 ++//PCIE_CAP_LIST ++#define PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++//PCIE_CAP ++#define PCIE_CAP__VERSION__SHIFT 0x0 ++#define PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 ++#define PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 ++#define PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 ++//DEVICE_CAP ++#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 ++#define DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 ++#define DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 ++#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 ++#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 ++#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf ++#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 ++#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a ++#define DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c ++//DEVICE_CNTL ++#define DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 ++#define DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 ++#define DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 ++#define DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 ++#define DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 ++#define DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 ++#define DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 ++#define DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 ++#define DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa ++#define DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb ++#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc ++#define DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf ++//DEVICE_STATUS ++#define DEVICE_STATUS__CORR_ERR__SHIFT 0x0 ++#define DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 ++#define DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 ++#define DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 ++#define DEVICE_STATUS__AUX_PWR__SHIFT 0x4 ++#define DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 ++//LINK_CAP ++#define LINK_CAP__LINK_SPEED__SHIFT 0x0 ++#define LINK_CAP__LINK_WIDTH__SHIFT 0x4 ++#define LINK_CAP__PM_SUPPORT__SHIFT 0xa ++#define LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc ++#define LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf ++#define LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 ++#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 ++#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 ++#define LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 ++#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 ++#define LINK_CAP__PORT_NUMBER__SHIFT 0x18 ++//LINK_CNTL ++#define LINK_CNTL__PM_CONTROL__SHIFT 0x0 ++#define LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 ++#define LINK_CNTL__LINK_DIS__SHIFT 0x4 ++#define LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 ++#define LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 ++#define LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 ++#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 ++#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 ++#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa ++#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb ++//LINK_STATUS ++#define LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 ++#define LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 ++#define LINK_STATUS__LINK_TRAINING__SHIFT 0xb ++#define LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc ++#define LINK_STATUS__DL_ACTIVE__SHIFT 0xd ++#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe ++#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf ++//DEVICE_CAP2 ++#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 ++#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 ++#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 ++#define DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 ++#define DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 ++#define DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 ++#define DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 ++#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa ++#define DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb ++#define DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc ++#define DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 ++#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 ++#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 ++#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 ++//DEVICE_CNTL2 ++#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 ++#define DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 ++#define DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 ++#define DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 ++#define DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 ++#define DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 ++#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 ++#define DEVICE_CNTL2__LTR_EN__SHIFT 0xa ++#define DEVICE_CNTL2__OBFF_EN__SHIFT 0xd ++#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf ++//DEVICE_STATUS2 ++#define DEVICE_STATUS2__RESERVED__SHIFT 0x0 ++//LINK_CAP2 ++#define LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 ++#define LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 ++#define LINK_CAP2__RESERVED__SHIFT 0x9 ++//LINK_CNTL2 ++#define LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 ++#define LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 ++#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 ++#define LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 ++#define LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 ++#define LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa ++#define LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb ++#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc ++//LINK_STATUS2 ++#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 ++#define LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 ++#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 ++#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 ++#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 ++#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 ++//SLOT_CAP2 ++#define SLOT_CAP2__RESERVED__SHIFT 0x0 ++//SLOT_CNTL2 ++#define SLOT_CNTL2__RESERVED__SHIFT 0x0 ++//SLOT_STATUS2 ++#define SLOT_STATUS2__RESERVED__SHIFT 0x0 ++//MSI_CAP_LIST ++#define MSI_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++//MSI_MSG_CNTL ++#define MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 ++#define MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 ++#define MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 ++#define MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 ++#define MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 ++//MSI_MSG_ADDR_LO ++#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 ++//MSI_MSG_ADDR_HI ++#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 ++//MSI_MSG_DATA ++#define MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 ++//MSI_MSG_DATA_64 ++#define MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 ++//MSI_MASK ++#define MSI_MASK__MSI_MASK__SHIFT 0x0 ++//MSI_PENDING ++#define MSI_PENDING__MSI_PENDING__SHIFT 0x0 ++//MSI_MASK_64 ++#define MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 ++//MSI_PENDING_64 ++#define MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 ++//MSIX_CAP_LIST ++#define MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++//MSIX_MSG_CNTL ++#define MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 ++#define MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe ++#define MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf ++//MSIX_TABLE ++#define MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 ++#define MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 ++//MSIX_PBA ++#define MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 ++#define MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 ++//PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST ++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++//PCIE_VENDOR_SPECIFIC_HDR ++#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 ++#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 ++#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 ++//PCIE_VENDOR_SPECIFIC1 ++#define PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 ++//PCIE_VENDOR_SPECIFIC2 ++#define PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 ++//PCIE_VC_ENH_CAP_LIST ++#define PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++//PCIE_PORT_VC_CAP_REG1 ++#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 ++#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 ++#define PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 ++#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa ++//PCIE_PORT_VC_CAP_REG2 ++#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 ++#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 ++//PCIE_PORT_VC_CNTL ++#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 ++#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 ++//PCIE_PORT_VC_STATUS ++#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 ++//PCIE_VC0_RESOURCE_CAP ++#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 ++#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf ++#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 ++#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 ++//PCIE_VC0_RESOURCE_CNTL ++#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 ++#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 ++#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 ++#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 ++#define PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 ++#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f ++//PCIE_VC0_RESOURCE_STATUS ++#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 ++#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 ++//PCIE_VC1_RESOURCE_CAP ++#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 ++#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf ++#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 ++#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 ++//PCIE_VC1_RESOURCE_CNTL ++#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 ++#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 ++#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 ++#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 ++#define PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 ++#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f ++//PCIE_VC1_RESOURCE_STATUS ++#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 ++#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 ++//PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST ++#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++//PCIE_DEV_SERIAL_NUM_DW1 ++#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 ++//PCIE_DEV_SERIAL_NUM_DW2 ++#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 ++//PCIE_ADV_ERR_RPT_ENH_CAP_LIST ++#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++//PCIE_UNCORR_ERR_STATUS ++#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 ++#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 ++#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc ++#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd ++#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe ++#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf ++#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 ++#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 ++#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 ++#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 ++#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 ++#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 ++#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 ++#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 ++#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 ++#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 ++//PCIE_UNCORR_ERR_MASK ++#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 ++#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 ++#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc ++#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd ++#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe ++#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf ++#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 ++#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 ++#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 ++#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 ++#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 ++#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 ++#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 ++#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 ++#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 ++#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 ++//PCIE_UNCORR_ERR_SEVERITY ++#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 ++#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 ++#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc ++#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd ++#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe ++#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf ++#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 ++#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 ++#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 ++#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 ++#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 ++#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 ++#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 ++#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 ++#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 ++#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 ++//PCIE_CORR_ERR_STATUS ++#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 ++#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 ++#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 ++#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 ++#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc ++#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd ++#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe ++#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf ++//PCIE_CORR_ERR_MASK ++#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 ++#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 ++#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 ++#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 ++#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc ++#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd ++#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe ++#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf ++//PCIE_ADV_ERR_CAP_CNTL ++#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 ++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 ++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 ++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 ++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 ++#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 ++#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa ++#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb ++//PCIE_HDR_LOG0 ++#define PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 ++//PCIE_HDR_LOG1 ++#define PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 ++//PCIE_HDR_LOG2 ++#define PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 ++//PCIE_HDR_LOG3 ++#define PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 ++//PCIE_ROOT_ERR_CMD ++#define PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 ++#define PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 ++#define PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 ++//PCIE_ROOT_ERR_STATUS ++#define PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 ++#define PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 ++#define PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 ++#define PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 ++#define PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 ++#define PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 ++#define PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 ++#define PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b ++//PCIE_ERR_SRC_ID ++#define PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 ++#define PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 ++//PCIE_TLP_PREFIX_LOG0 ++#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 ++//PCIE_TLP_PREFIX_LOG1 ++#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 ++//PCIE_TLP_PREFIX_LOG2 ++#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 ++//PCIE_TLP_PREFIX_LOG3 ++#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 ++//PCIE_BAR_ENH_CAP_LIST ++#define PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++//PCIE_BAR1_CAP ++#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 ++//PCIE_BAR1_CNTL ++#define PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 ++#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 ++#define PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 ++//PCIE_BAR2_CAP ++#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 ++//PCIE_BAR2_CNTL ++#define PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 ++#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 ++#define PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 ++//PCIE_BAR3_CAP ++#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 ++//PCIE_BAR3_CNTL ++#define PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 ++#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 ++#define PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 ++//PCIE_BAR4_CAP ++#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 ++//PCIE_BAR4_CNTL ++#define PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 ++#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 ++#define PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 ++//PCIE_BAR5_CAP ++#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 ++//PCIE_BAR5_CNTL ++#define PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 ++#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 ++#define PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 ++//PCIE_BAR6_CAP ++#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 ++//PCIE_BAR6_CNTL ++#define PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 ++#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 ++#define PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 ++//PCIE_PWR_BUDGET_ENH_CAP_LIST ++#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++//PCIE_PWR_BUDGET_DATA_SELECT ++#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 ++//PCIE_PWR_BUDGET_DATA ++#define PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 ++#define PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 ++#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa ++#define PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd ++#define PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf ++#define PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 ++//PCIE_PWR_BUDGET_CAP ++#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 ++//PCIE_DPA_ENH_CAP_LIST ++#define PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++//PCIE_DPA_CAP ++#define PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 ++#define PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 ++#define PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc ++#define PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 ++#define PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 ++//PCIE_DPA_LATENCY_INDICATOR ++#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 ++//PCIE_DPA_STATUS ++#define PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 ++#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 ++//PCIE_DPA_CNTL ++#define PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 ++//PCIE_DPA_SUBSTATE_PWR_ALLOC_0 ++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 ++//PCIE_DPA_SUBSTATE_PWR_ALLOC_1 ++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 ++//PCIE_DPA_SUBSTATE_PWR_ALLOC_2 ++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 ++//PCIE_DPA_SUBSTATE_PWR_ALLOC_3 ++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 ++//PCIE_DPA_SUBSTATE_PWR_ALLOC_4 ++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 ++//PCIE_DPA_SUBSTATE_PWR_ALLOC_5 ++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 ++//PCIE_DPA_SUBSTATE_PWR_ALLOC_6 ++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 ++//PCIE_DPA_SUBSTATE_PWR_ALLOC_7 ++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 ++//PCIE_SECONDARY_ENH_CAP_LIST ++#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++//PCIE_LINK_CNTL3 ++#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 ++#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 ++#define PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 ++//PCIE_LANE_ERROR_STATUS ++#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 ++#define PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 ++//PCIE_LANE_0_EQUALIZATION_CNTL ++#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++//PCIE_LANE_1_EQUALIZATION_CNTL ++#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++//PCIE_LANE_2_EQUALIZATION_CNTL ++#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++//PCIE_LANE_3_EQUALIZATION_CNTL ++#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++//PCIE_LANE_4_EQUALIZATION_CNTL ++#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++//PCIE_LANE_5_EQUALIZATION_CNTL ++#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++//PCIE_LANE_6_EQUALIZATION_CNTL ++#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++//PCIE_LANE_7_EQUALIZATION_CNTL ++#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++//PCIE_LANE_8_EQUALIZATION_CNTL ++#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++//PCIE_LANE_9_EQUALIZATION_CNTL ++#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++//PCIE_LANE_10_EQUALIZATION_CNTL ++#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++//PCIE_LANE_11_EQUALIZATION_CNTL ++#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++//PCIE_LANE_12_EQUALIZATION_CNTL ++#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++//PCIE_LANE_13_EQUALIZATION_CNTL ++#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++//PCIE_LANE_14_EQUALIZATION_CNTL ++#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++//PCIE_LANE_15_EQUALIZATION_CNTL ++#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 ++#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 ++#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 ++#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc ++#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf ++//PCIE_ACS_ENH_CAP_LIST ++#define PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++//PCIE_ACS_CAP ++#define PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 ++#define PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 ++#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 ++#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 ++#define PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 ++#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 ++#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 ++#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 ++//PCIE_ACS_CNTL ++#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 ++#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 ++#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 ++#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 ++#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 ++#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 ++#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 ++//PCIE_ATS_ENH_CAP_LIST ++#define PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++//PCIE_ATS_CAP ++#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 ++#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 ++#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 ++//PCIE_ATS_CNTL ++#define PCIE_ATS_CNTL__STU__SHIFT 0x0 ++#define PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf ++//PCIE_PAGE_REQ_ENH_CAP_LIST ++#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++//PCIE_PAGE_REQ_CNTL ++#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 ++#define PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 ++//PCIE_PAGE_REQ_STATUS ++#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 ++#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 ++#define PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 ++#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf ++//PCIE_OUTSTAND_PAGE_REQ_CAPACITY ++#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 ++//PCIE_OUTSTAND_PAGE_REQ_ALLOC ++#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 ++//PCIE_PASID_ENH_CAP_LIST ++#define PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++//PCIE_PASID_CAP ++#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 ++#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 ++#define PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 ++//PCIE_PASID_CNTL ++#define PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 ++#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 ++#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 ++//PCIE_TPH_REQR_ENH_CAP_LIST ++#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++//PCIE_TPH_REQR_CAP ++#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0 ++#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1 ++#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2 ++#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8 ++#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9 ++#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10 ++//PCIE_TPH_REQR_CNTL ++#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0 ++#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8 ++//PCIE_MC_ENH_CAP_LIST ++#define PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++//PCIE_MC_CAP ++#define PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 ++#define PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 ++#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf ++//PCIE_MC_CNTL ++#define PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 ++#define PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf ++//PCIE_MC_ADDR0 ++#define PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 ++#define PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc ++//PCIE_MC_ADDR1 ++#define PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 ++//PCIE_MC_RCV0 ++#define PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 ++//PCIE_MC_RCV1 ++#define PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 ++//PCIE_MC_BLOCK_ALL0 ++#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 ++//PCIE_MC_BLOCK_ALL1 ++#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 ++//PCIE_MC_BLOCK_UNTRANSLATED_0 ++#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 ++//PCIE_MC_BLOCK_UNTRANSLATED_1 ++#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 ++//PCIE_LTR_ENH_CAP_LIST ++#define PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++//PCIE_LTR_CAP ++#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 ++#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa ++#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 ++#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a ++//PCIE_ARI_ENH_CAP_LIST ++#define PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++//PCIE_ARI_CAP ++#define PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 ++#define PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 ++#define PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 ++//PCIE_ARI_CNTL ++#define PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 ++#define PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 ++#define PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 ++//PCIE_SRIOV_ENH_CAP_LIST ++#define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 ++#define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 ++//PCIE_SRIOV_CAP ++#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 ++#define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 ++#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 ++//PCIE_SRIOV_CONTROL ++#define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 ++#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 ++#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 ++#define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 ++#define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 ++//PCIE_SRIOV_STATUS ++#define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 ++//PCIE_SRIOV_INITIAL_VFS ++#define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 ++//PCIE_SRIOV_TOTAL_VFS ++#define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 ++//PCIE_SRIOV_NUM_VFS ++#define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 ++//PCIE_SRIOV_FUNC_DEP_LINK ++#define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 ++//PCIE_SRIOV_FIRST_VF_OFFSET ++#define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 ++//PCIE_SRIOV_VF_STRIDE ++#define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 ++//PCIE_SRIOV_VF_DEVICE_ID ++#define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 ++//PCIE_SRIOV_SUPPORTED_PAGE_SIZE ++#define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 ++//PCIE_SRIOV_SYSTEM_PAGE_SIZE ++#define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 ++//PCIE_SRIOV_VF_BASE_ADDR_0 ++#define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 ++//PCIE_SRIOV_VF_BASE_ADDR_1 ++#define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 ++//PCIE_SRIOV_VF_BASE_ADDR_2 ++#define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 ++//PCIE_SRIOV_VF_BASE_ADDR_3 ++#define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 ++//PCIE_SRIOV_VF_BASE_ADDR_4 ++#define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 ++//PCIE_SRIOV_VF_BASE_ADDR_5 ++#define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 ++//PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET ++#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT 0x0 ++#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 ++//PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV ++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0 ++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10 ++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x0 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0 ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0 ++ ++ ++// addressBlock: bif_cfg_dev0_swds_bifcfgdecp ++//SUB_BUS_NUMBER_LATENCY ++#define SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 ++#define SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 ++#define SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 ++#define SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 ++//IO_BASE_LIMIT ++#define IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 ++#define IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 ++#define IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 ++#define IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc ++//SECONDARY_STATUS ++#define SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 ++#define SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 ++#define SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 ++#define SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 ++#define SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 ++#define SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb ++#define SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc ++#define SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd ++#define SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe ++#define SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf ++//MEM_BASE_LIMIT ++#define MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 ++#define MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 ++#define MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 ++#define MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 ++//PREF_BASE_LIMIT ++#define PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 ++#define PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 ++#define PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 ++#define PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 ++//PREF_BASE_UPPER ++#define PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 ++//PREF_LIMIT_UPPER ++#define PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 ++//IO_BASE_LIMIT_HI ++#define IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 ++#define IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 ++//IRQ_BRIDGE_CNTL ++#define IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 ++#define IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 ++#define IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 ++#define IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 ++#define IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 ++#define IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 ++#define IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 ++#define IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 ++//SLOT_CAP ++#define SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 ++#define SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 ++#define SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 ++#define SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 ++#define SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 ++#define SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 ++#define SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 ++#define SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 ++#define SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf ++#define SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 ++#define SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 ++#define SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 ++//SLOT_CNTL ++#define SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 ++#define SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 ++#define SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 ++#define SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 ++#define SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 ++#define SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 ++#define SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 ++#define SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 ++#define SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa ++#define SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb ++#define SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc ++//SLOT_STATUS ++#define SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 ++#define SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 ++#define SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 ++#define SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 ++#define SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 ++#define SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 ++#define SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 ++#define SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 ++#define SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 ++//SSID_CAP_LIST ++#define SSID_CAP_LIST__CAP_ID__SHIFT 0x0 ++#define SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 ++//SSID_CAP ++#define SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 ++#define SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 ++ ++ ++// addressBlock: rcc_shadow_reg_shadowdec ++//SHADOW_COMMAND ++#define SHADOW_COMMAND__IOEN_UP__SHIFT 0x0 ++#define SHADOW_COMMAND__MEMEN_UP__SHIFT 0x1 ++//SHADOW_BASE_ADDR_1 ++#define SHADOW_BASE_ADDR_1__BAR1_UP__SHIFT 0x0 ++//SHADOW_BASE_ADDR_2 ++#define SHADOW_BASE_ADDR_2__BAR2_UP__SHIFT 0x0 ++//SHADOW_SUB_BUS_NUMBER_LATENCY ++#define SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP__SHIFT 0x8 ++#define SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP__SHIFT 0x10 ++//SHADOW_IO_BASE_LIMIT ++#define SHADOW_IO_BASE_LIMIT__IO_BASE_UP__SHIFT 0x4 ++#define SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP__SHIFT 0xc ++//SHADOW_MEM_BASE_LIMIT ++#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 ++#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP__SHIFT 0x4 ++#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 ++#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP__SHIFT 0x14 ++//SHADOW_PREF_BASE_LIMIT ++#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 ++#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP__SHIFT 0x4 ++#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 ++#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP__SHIFT 0x14 ++//SHADOW_PREF_BASE_UPPER ++#define SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP__SHIFT 0x0 ++//SHADOW_PREF_LIMIT_UPPER ++#define SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP__SHIFT 0x0 ++//SHADOW_IO_BASE_LIMIT_HI ++#define SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP__SHIFT 0x0 ++#define SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP__SHIFT 0x10 ++//SHADOW_IRQ_BRIDGE_CNTL ++#define SHADOW_IRQ_BRIDGE_CNTL__ISA_EN_UP__SHIFT 0x2 ++#define SHADOW_IRQ_BRIDGE_CNTL__VGA_EN_UP__SHIFT 0x3 ++#define SHADOW_IRQ_BRIDGE_CNTL__VGA_DEC_UP__SHIFT 0x4 ++#define SHADOW_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_UP__SHIFT 0x6 ++//SUC_INDEX ++#define SUC_INDEX__SUC_INDEX__SHIFT 0x0 ++//SUC_DATA ++#define SUC_DATA__SUC_DATA__SHIFT 0x0 ++ ++ ++// addressBlock: bif_bx_pf_SUMDEC ++//SUM_INDEX ++#define SUM_INDEX__SUM_INDEX__SHIFT 0x0 ++//SUM_DATA ++#define SUM_DATA__SUM_DATA__SHIFT 0x0 ++ ++ ++// addressBlock: gdc_GDCDEC ++//A2S_CNTL_CL0 ++#define A2S_CNTL_CL0__NSNOOP_MAP__SHIFT 0x0 ++#define A2S_CNTL_CL0__REQPASSPW_VC0_MAP__SHIFT 0x2 ++#define A2S_CNTL_CL0__REQPASSPW_NVC0_MAP__SHIFT 0x4 ++#define A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP__SHIFT 0x6 ++#define A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8 ++#define A2S_CNTL_CL0__BLKLVL_MAP__SHIFT 0xa ++#define A2S_CNTL_CL0__DATERR_MAP__SHIFT 0xc ++#define A2S_CNTL_CL0__EXOKAY_WR_MAP__SHIFT 0xe ++#define A2S_CNTL_CL0__EXOKAY_RD_MAP__SHIFT 0x10 ++#define A2S_CNTL_CL0__RESP_WR_MAP__SHIFT 0x12 ++#define A2S_CNTL_CL0__RESP_RD_MAP__SHIFT 0x14 ++//A2S_CNTL_CL1 ++#define A2S_CNTL_CL1__NSNOOP_MAP__SHIFT 0x0 ++#define A2S_CNTL_CL1__REQPASSPW_VC0_MAP__SHIFT 0x2 ++#define A2S_CNTL_CL1__REQPASSPW_NVC0_MAP__SHIFT 0x4 ++#define A2S_CNTL_CL1__REQRSPPASSPW_VC0_MAP__SHIFT 0x6 ++#define A2S_CNTL_CL1__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8 ++#define A2S_CNTL_CL1__BLKLVL_MAP__SHIFT 0xa ++#define A2S_CNTL_CL1__DATERR_MAP__SHIFT 0xc ++#define A2S_CNTL_CL1__EXOKAY_WR_MAP__SHIFT 0xe ++#define A2S_CNTL_CL1__EXOKAY_RD_MAP__SHIFT 0x10 ++#define A2S_CNTL_CL1__RESP_WR_MAP__SHIFT 0x12 ++#define A2S_CNTL_CL1__RESP_RD_MAP__SHIFT 0x14 ++//A2S_CNTL_CL2 ++#define A2S_CNTL_CL2__NSNOOP_MAP__SHIFT 0x0 ++#define A2S_CNTL_CL2__REQPASSPW_VC0_MAP__SHIFT 0x2 ++#define A2S_CNTL_CL2__REQPASSPW_NVC0_MAP__SHIFT 0x4 ++#define A2S_CNTL_CL2__REQRSPPASSPW_VC0_MAP__SHIFT 0x6 ++#define A2S_CNTL_CL2__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8 ++#define A2S_CNTL_CL2__BLKLVL_MAP__SHIFT 0xa ++#define A2S_CNTL_CL2__DATERR_MAP__SHIFT 0xc ++#define A2S_CNTL_CL2__EXOKAY_WR_MAP__SHIFT 0xe ++#define A2S_CNTL_CL2__EXOKAY_RD_MAP__SHIFT 0x10 ++#define A2S_CNTL_CL2__RESP_WR_MAP__SHIFT 0x12 ++#define A2S_CNTL_CL2__RESP_RD_MAP__SHIFT 0x14 ++//A2S_CNTL_CL3 ++#define A2S_CNTL_CL3__NSNOOP_MAP__SHIFT 0x0 ++#define A2S_CNTL_CL3__REQPASSPW_VC0_MAP__SHIFT 0x2 ++#define A2S_CNTL_CL3__REQPASSPW_NVC0_MAP__SHIFT 0x4 ++#define A2S_CNTL_CL3__REQRSPPASSPW_VC0_MAP__SHIFT 0x6 ++#define A2S_CNTL_CL3__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8 ++#define A2S_CNTL_CL3__BLKLVL_MAP__SHIFT 0xa ++#define A2S_CNTL_CL3__DATERR_MAP__SHIFT 0xc ++#define A2S_CNTL_CL3__EXOKAY_WR_MAP__SHIFT 0xe ++#define A2S_CNTL_CL3__EXOKAY_RD_MAP__SHIFT 0x10 ++#define A2S_CNTL_CL3__RESP_WR_MAP__SHIFT 0x12 ++#define A2S_CNTL_CL3__RESP_RD_MAP__SHIFT 0x14 ++//A2S_CNTL_CL4 ++#define A2S_CNTL_CL4__NSNOOP_MAP__SHIFT 0x0 ++#define A2S_CNTL_CL4__REQPASSPW_VC0_MAP__SHIFT 0x2 ++#define A2S_CNTL_CL4__REQPASSPW_NVC0_MAP__SHIFT 0x4 ++#define A2S_CNTL_CL4__REQRSPPASSPW_VC0_MAP__SHIFT 0x6 ++#define A2S_CNTL_CL4__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8 ++#define A2S_CNTL_CL4__BLKLVL_MAP__SHIFT 0xa ++#define A2S_CNTL_CL4__DATERR_MAP__SHIFT 0xc ++#define A2S_CNTL_CL4__EXOKAY_WR_MAP__SHIFT 0xe ++#define A2S_CNTL_CL4__EXOKAY_RD_MAP__SHIFT 0x10 ++#define A2S_CNTL_CL4__RESP_WR_MAP__SHIFT 0x12 ++#define A2S_CNTL_CL4__RESP_RD_MAP__SHIFT 0x14 ++//A2S_CNTL_SW0 ++#define A2S_CNTL_SW0__WR_TAG_SET_MIN__SHIFT 0x0 ++#define A2S_CNTL_SW0__RD_TAG_SET_MIN__SHIFT 0x3 ++#define A2S_CNTL_SW0__FORCE_RSP_REORDER_EN__SHIFT 0x6 ++#define A2S_CNTL_SW0__RSP_REORDER_DIS__SHIFT 0x7 ++#define A2S_CNTL_SW0__WRRSP_ACCUM_SEL__SHIFT 0x8 ++#define A2S_CNTL_SW0__SDP_WR_CHAIN_DIS__SHIFT 0x9 ++#define A2S_CNTL_SW0__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0xa ++#define A2S_CNTL_SW0__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0xb ++#define A2S_CNTL_SW0__RDRSP_STS_DATSTS_PRIORITY__SHIFT 0xc ++#define A2S_CNTL_SW0__WRR_RD_WEIGHT__SHIFT 0x10 ++#define A2S_CNTL_SW0__WRR_WR_WEIGHT__SHIFT 0x18 ++//A2S_CNTL_SW1 ++#define A2S_CNTL_SW1__WR_TAG_SET_MIN__SHIFT 0x0 ++#define A2S_CNTL_SW1__RD_TAG_SET_MIN__SHIFT 0x3 ++#define A2S_CNTL_SW1__FORCE_RSP_REORDER_EN__SHIFT 0x6 ++#define A2S_CNTL_SW1__RSP_REORDER_DIS__SHIFT 0x7 ++#define A2S_CNTL_SW1__WRRSP_ACCUM_SEL__SHIFT 0x8 ++#define A2S_CNTL_SW1__SDP_WR_CHAIN_DIS__SHIFT 0x9 ++#define A2S_CNTL_SW1__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0xa ++#define A2S_CNTL_SW1__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0xb ++#define A2S_CNTL_SW1__RDRSP_STS_DATSTS_PRIORITY__SHIFT 0xc ++#define A2S_CNTL_SW1__WRR_RD_WEIGHT__SHIFT 0x10 ++#define A2S_CNTL_SW1__WRR_WR_WEIGHT__SHIFT 0x18 ++//A2S_CNTL_SW2 ++#define A2S_CNTL_SW2__WR_TAG_SET_MIN__SHIFT 0x0 ++#define A2S_CNTL_SW2__RD_TAG_SET_MIN__SHIFT 0x3 ++#define A2S_CNTL_SW2__FORCE_RSP_REORDER_EN__SHIFT 0x6 ++#define A2S_CNTL_SW2__RSP_REORDER_DIS__SHIFT 0x7 ++#define A2S_CNTL_SW2__WRRSP_ACCUM_SEL__SHIFT 0x8 ++#define A2S_CNTL_SW2__SDP_WR_CHAIN_DIS__SHIFT 0x9 ++#define A2S_CNTL_SW2__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0xa ++#define A2S_CNTL_SW2__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0xb ++#define A2S_CNTL_SW2__RDRSP_STS_DATSTS_PRIORITY__SHIFT 0xc ++#define A2S_CNTL_SW2__WRR_RD_WEIGHT__SHIFT 0x10 ++#define A2S_CNTL_SW2__WRR_WR_WEIGHT__SHIFT 0x18 ++//NGDC_MGCG_CTRL ++#define NGDC_MGCG_CTRL__NGDC_MGCG_EN__SHIFT 0x0 ++#define NGDC_MGCG_CTRL__NGDC_MGCG_MODE__SHIFT 0x1 ++#define NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__SHIFT 0x2 ++//A2S_MISC_CNTL ++#define A2S_MISC_CNTL__BLKLVL_FOR_MSG__SHIFT 0x0 ++#define A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS__SHIFT 0x2 ++//NGDC_SDP_PORT_CTRL ++#define NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT 0x0 ++//NGDC_RESERVED_0 ++#define NGDC_RESERVED_0__RESERVED__SHIFT 0x0 ++//NGDC_RESERVED_1 ++#define NGDC_RESERVED_1__RESERVED__SHIFT 0x0 ++//BIF_SDMA0_DOORBELL_RANGE ++#define BIF_SDMA0_DOORBELL_RANGE__OFFSET__SHIFT 0x2 ++#define BIF_SDMA0_DOORBELL_RANGE__SIZE__SHIFT 0x10 ++//BIF_SDMA1_DOORBELL_RANGE ++#define BIF_SDMA1_DOORBELL_RANGE__OFFSET__SHIFT 0x2 ++#define BIF_SDMA1_DOORBELL_RANGE__SIZE__SHIFT 0x10 ++//BIF_IH_DOORBELL_RANGE ++#define BIF_IH_DOORBELL_RANGE__OFFSET__SHIFT 0x2 ++#define BIF_IH_DOORBELL_RANGE__SIZE__SHIFT 0x10 ++//BIF_MMSCH0_DOORBELL_RANGE ++#define BIF_MMSCH0_DOORBELL_RANGE__OFFSET__SHIFT 0x2 ++#define BIF_MMSCH0_DOORBELL_RANGE__SIZE__SHIFT 0x10 ++//BIF_DOORBELL_FENCE_CNTL ++#define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE__SHIFT 0x0 ++//S2A_MISC_CNTL ++#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__SHIFT 0x0 ++#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__SHIFT 0x1 ++#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__SHIFT 0x2 ++//A2S_CNTL2_SEC_CL0 ++#define A2S_CNTL2_SEC_CL0__SECLVL_MAP__SHIFT 0x0 ++//A2S_CNTL2_SEC_CL1 ++#define A2S_CNTL2_SEC_CL1__SECLVL_MAP__SHIFT 0x0 ++//A2S_CNTL2_SEC_CL2 ++#define A2S_CNTL2_SEC_CL2__SECLVL_MAP__SHIFT 0x0 ++//A2S_CNTL2_SEC_CL3 ++#define A2S_CNTL2_SEC_CL3__SECLVL_MAP__SHIFT 0x0 ++//A2S_CNTL2_SEC_CL4 ++#define A2S_CNTL2_SEC_CL4__SECLVL_MAP__SHIFT 0x0 ++ ++ ++// addressBlock: nbif_sion_SIONDEC ++//SION_CL0_RdRsp_BurstTarget_REG0 ++#define SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 ++//SION_CL0_RdRsp_BurstTarget_REG1 ++#define SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 ++//SION_CL0_RdRsp_TimeSlot_REG0 ++#define SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 ++//SION_CL0_RdRsp_TimeSlot_REG1 ++#define SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 ++//SION_CL0_WrRsp_BurstTarget_REG0 ++#define SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 ++//SION_CL0_WrRsp_BurstTarget_REG1 ++#define SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 ++//SION_CL0_WrRsp_TimeSlot_REG0 ++#define SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 ++//SION_CL0_WrRsp_TimeSlot_REG1 ++#define SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 ++//SION_CL0_Req_BurstTarget_REG0 ++#define SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 ++//SION_CL0_Req_BurstTarget_REG1 ++#define SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 ++//SION_CL0_Req_TimeSlot_REG0 ++#define SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 ++//SION_CL0_Req_TimeSlot_REG1 ++#define SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 ++//SION_CL0_ReqPoolCredit_Alloc_REG0 ++#define SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 ++//SION_CL0_ReqPoolCredit_Alloc_REG1 ++#define SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 ++//SION_CL0_DataPoolCredit_Alloc_REG0 ++#define SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 ++//SION_CL0_DataPoolCredit_Alloc_REG1 ++#define SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 ++//SION_CL0_RdRspPoolCredit_Alloc_REG0 ++#define SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 ++//SION_CL0_RdRspPoolCredit_Alloc_REG1 ++#define SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 ++//SION_CL0_WrRspPoolCredit_Alloc_REG0 ++#define SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 ++//SION_CL0_WrRspPoolCredit_Alloc_REG1 ++#define SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 ++//SION_CL1_RdRsp_BurstTarget_REG0 ++#define SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 ++//SION_CL1_RdRsp_BurstTarget_REG1 ++#define SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 ++//SION_CL1_RdRsp_TimeSlot_REG0 ++#define SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 ++//SION_CL1_RdRsp_TimeSlot_REG1 ++#define SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 ++//SION_CL1_WrRsp_BurstTarget_REG0 ++#define SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 ++//SION_CL1_WrRsp_BurstTarget_REG1 ++#define SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 ++//SION_CL1_WrRsp_TimeSlot_REG0 ++#define SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 ++//SION_CL1_WrRsp_TimeSlot_REG1 ++#define SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 ++//SION_CL1_Req_BurstTarget_REG0 ++#define SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 ++//SION_CL1_Req_BurstTarget_REG1 ++#define SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 ++//SION_CL1_Req_TimeSlot_REG0 ++#define SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 ++//SION_CL1_Req_TimeSlot_REG1 ++#define SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 ++//SION_CL1_ReqPoolCredit_Alloc_REG0 ++#define SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 ++//SION_CL1_ReqPoolCredit_Alloc_REG1 ++#define SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 ++//SION_CL1_DataPoolCredit_Alloc_REG0 ++#define SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 ++//SION_CL1_DataPoolCredit_Alloc_REG1 ++#define SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 ++//SION_CL1_RdRspPoolCredit_Alloc_REG0 ++#define SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 ++//SION_CL1_RdRspPoolCredit_Alloc_REG1 ++#define SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 ++//SION_CL1_WrRspPoolCredit_Alloc_REG0 ++#define SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 ++//SION_CL1_WrRspPoolCredit_Alloc_REG1 ++#define SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 ++//SION_CL2_RdRsp_BurstTarget_REG0 ++#define SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 ++//SION_CL2_RdRsp_BurstTarget_REG1 ++#define SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 ++//SION_CL2_RdRsp_TimeSlot_REG0 ++#define SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 ++//SION_CL2_RdRsp_TimeSlot_REG1 ++#define SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 ++//SION_CL2_WrRsp_BurstTarget_REG0 ++#define SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 ++//SION_CL2_WrRsp_BurstTarget_REG1 ++#define SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 ++//SION_CL2_WrRsp_TimeSlot_REG0 ++#define SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 ++//SION_CL2_WrRsp_TimeSlot_REG1 ++#define SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 ++//SION_CL2_Req_BurstTarget_REG0 ++#define SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 ++//SION_CL2_Req_BurstTarget_REG1 ++#define SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 ++//SION_CL2_Req_TimeSlot_REG0 ++#define SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 ++//SION_CL2_Req_TimeSlot_REG1 ++#define SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 ++//SION_CL2_ReqPoolCredit_Alloc_REG0 ++#define SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 ++//SION_CL2_ReqPoolCredit_Alloc_REG1 ++#define SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 ++//SION_CL2_DataPoolCredit_Alloc_REG0 ++#define SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 ++//SION_CL2_DataPoolCredit_Alloc_REG1 ++#define SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 ++//SION_CL2_RdRspPoolCredit_Alloc_REG0 ++#define SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 ++//SION_CL2_RdRspPoolCredit_Alloc_REG1 ++#define SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 ++//SION_CL2_WrRspPoolCredit_Alloc_REG0 ++#define SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 ++//SION_CL2_WrRspPoolCredit_Alloc_REG1 ++#define SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 ++//SION_CL3_RdRsp_BurstTarget_REG0 ++#define SION_CL3_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 ++//SION_CL3_RdRsp_BurstTarget_REG1 ++#define SION_CL3_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 ++//SION_CL3_RdRsp_TimeSlot_REG0 ++#define SION_CL3_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 ++//SION_CL3_RdRsp_TimeSlot_REG1 ++#define SION_CL3_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 ++//SION_CL3_WrRsp_BurstTarget_REG0 ++#define SION_CL3_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 ++//SION_CL3_WrRsp_BurstTarget_REG1 ++#define SION_CL3_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 ++//SION_CL3_WrRsp_TimeSlot_REG0 ++#define SION_CL3_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 ++//SION_CL3_WrRsp_TimeSlot_REG1 ++#define SION_CL3_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 ++//SION_CL3_Req_BurstTarget_REG0 ++#define SION_CL3_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 ++//SION_CL3_Req_BurstTarget_REG1 ++#define SION_CL3_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 ++//SION_CL3_Req_TimeSlot_REG0 ++#define SION_CL3_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 ++//SION_CL3_Req_TimeSlot_REG1 ++#define SION_CL3_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 ++//SION_CL3_ReqPoolCredit_Alloc_REG0 ++#define SION_CL3_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 ++//SION_CL3_ReqPoolCredit_Alloc_REG1 ++#define SION_CL3_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 ++//SION_CL3_DataPoolCredit_Alloc_REG0 ++#define SION_CL3_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 ++//SION_CL3_DataPoolCredit_Alloc_REG1 ++#define SION_CL3_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 ++//SION_CL3_RdRspPoolCredit_Alloc_REG0 ++#define SION_CL3_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 ++//SION_CL3_RdRspPoolCredit_Alloc_REG1 ++#define SION_CL3_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 ++//SION_CL3_WrRspPoolCredit_Alloc_REG0 ++#define SION_CL3_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 ++//SION_CL3_WrRspPoolCredit_Alloc_REG1 ++#define SION_CL3_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 ++//SION_CL4_RdRsp_BurstTarget_REG0 ++#define SION_CL4_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 ++//SION_CL4_RdRsp_BurstTarget_REG1 ++#define SION_CL4_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 ++//SION_CL4_RdRsp_TimeSlot_REG0 ++#define SION_CL4_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 ++//SION_CL4_RdRsp_TimeSlot_REG1 ++#define SION_CL4_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 ++//SION_CL4_WrRsp_BurstTarget_REG0 ++#define SION_CL4_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 ++//SION_CL4_WrRsp_BurstTarget_REG1 ++#define SION_CL4_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 ++//SION_CL4_WrRsp_TimeSlot_REG0 ++#define SION_CL4_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 ++//SION_CL4_WrRsp_TimeSlot_REG1 ++#define SION_CL4_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 ++//SION_CL4_Req_BurstTarget_REG0 ++#define SION_CL4_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 ++//SION_CL4_Req_BurstTarget_REG1 ++#define SION_CL4_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 ++//SION_CL4_Req_TimeSlot_REG0 ++#define SION_CL4_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 ++//SION_CL4_Req_TimeSlot_REG1 ++#define SION_CL4_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 ++//SION_CL4_ReqPoolCredit_Alloc_REG0 ++#define SION_CL4_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 ++//SION_CL4_ReqPoolCredit_Alloc_REG1 ++#define SION_CL4_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 ++//SION_CL4_DataPoolCredit_Alloc_REG0 ++#define SION_CL4_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 ++//SION_CL4_DataPoolCredit_Alloc_REG1 ++#define SION_CL4_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 ++//SION_CL4_RdRspPoolCredit_Alloc_REG0 ++#define SION_CL4_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 ++//SION_CL4_RdRspPoolCredit_Alloc_REG1 ++#define SION_CL4_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 ++//SION_CL4_WrRspPoolCredit_Alloc_REG0 ++#define SION_CL4_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 ++//SION_CL4_WrRspPoolCredit_Alloc_REG1 ++#define SION_CL4_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 ++//SION_CL5_RdRsp_BurstTarget_REG0 ++#define SION_CL5_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 ++//SION_CL5_RdRsp_BurstTarget_REG1 ++#define SION_CL5_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 ++//SION_CL5_RdRsp_TimeSlot_REG0 ++#define SION_CL5_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 ++//SION_CL5_RdRsp_TimeSlot_REG1 ++#define SION_CL5_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 ++//SION_CL5_WrRsp_BurstTarget_REG0 ++#define SION_CL5_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 ++//SION_CL5_WrRsp_BurstTarget_REG1 ++#define SION_CL5_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 ++//SION_CL5_WrRsp_TimeSlot_REG0 ++#define SION_CL5_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 ++//SION_CL5_WrRsp_TimeSlot_REG1 ++#define SION_CL5_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 ++//SION_CL5_Req_BurstTarget_REG0 ++#define SION_CL5_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 ++//SION_CL5_Req_BurstTarget_REG1 ++#define SION_CL5_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 ++//SION_CL5_Req_TimeSlot_REG0 ++#define SION_CL5_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 ++//SION_CL5_Req_TimeSlot_REG1 ++#define SION_CL5_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 ++//SION_CL5_ReqPoolCredit_Alloc_REG0 ++#define SION_CL5_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 ++//SION_CL5_ReqPoolCredit_Alloc_REG1 ++#define SION_CL5_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 ++//SION_CL5_DataPoolCredit_Alloc_REG0 ++#define SION_CL5_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 ++//SION_CL5_DataPoolCredit_Alloc_REG1 ++#define SION_CL5_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 ++//SION_CL5_RdRspPoolCredit_Alloc_REG0 ++#define SION_CL5_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 ++//SION_CL5_RdRspPoolCredit_Alloc_REG1 ++#define SION_CL5_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 ++//SION_CL5_WrRspPoolCredit_Alloc_REG0 ++#define SION_CL5_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 ++//SION_CL5_WrRspPoolCredit_Alloc_REG1 ++#define SION_CL5_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 ++//SION_CNTL_REG0 ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT 0x0 ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT 0x1 ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT 0x2 ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT 0x3 ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT 0x4 ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT 0x5 ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT 0x6 ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT 0x7 ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT 0x8 ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT 0x9 ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__SHIFT 0xa ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__SHIFT 0xb ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__SHIFT 0xc ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__SHIFT 0xd ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__SHIFT 0xe ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__SHIFT 0xf ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__SHIFT 0x10 ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__SHIFT 0x11 ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__SHIFT 0x12 ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__SHIFT 0x13 ++//SION_CNTL_REG1 ++#define SION_CNTL_REG1__LIVELOCK_WATCHDOG_THRESHOLD__SHIFT 0x0 ++#define SION_CNTL_REG1__CG_OFF_HYSTERESIS__SHIFT 0x8 ++ ++ ++// addressBlock: syshub_mmreg_direct_syshubdirect ++//SYSHUB_DS_CTRL_SOCCLK ++#define SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0 ++#define SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1 ++#define SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2 ++#define SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3 ++#define SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4 ++#define SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5 ++#define SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6 ++#define SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7 ++#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10 ++#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11 ++#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12 ++#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13 ++#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14 ++#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15 ++#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16 ++#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17 ++#define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c ++#define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__SHIFT 0x1f ++//SYSHUB_DS_CTRL2_SOCCLK ++#define SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__SHIFT 0x0 ++//SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK ++#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en__SHIFT 0x0 ++#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en__SHIFT 0x1 ++#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__SHIFT 0xf ++#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en__SHIFT 0x10 ++#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en__SHIFT 0x11 ++//SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK ++#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en__SHIFT 0x0 ++#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en__SHIFT 0x1 ++#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__SHIFT 0xf ++#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en__SHIFT 0x10 ++#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en__SHIFT 0x11 ++//DMA_CLK0_SW0_SYSHUB_QOS_CNTL ++#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 ++#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 ++#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 ++//DMA_CLK0_SW1_SYSHUB_QOS_CNTL ++#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 ++#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 ++#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 ++//DMA_CLK0_SW0_CL0_CNTL ++#define DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 ++#define DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 ++#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 ++#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 ++#define DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 ++#define DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 ++//DMA_CLK0_SW0_CL1_CNTL ++#define DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 ++#define DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 ++#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 ++#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 ++#define DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 ++#define DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 ++//DMA_CLK0_SW0_CL2_CNTL ++#define DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 ++#define DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 ++#define DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 ++#define DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 ++#define DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 ++#define DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 ++//DMA_CLK0_SW0_CL3_CNTL ++#define DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 ++#define DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 ++#define DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 ++#define DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 ++#define DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 ++#define DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 ++//DMA_CLK0_SW0_CL4_CNTL ++#define DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 ++#define DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 ++#define DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 ++#define DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 ++#define DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 ++#define DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 ++//DMA_CLK0_SW0_CL5_CNTL ++#define DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 ++#define DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 ++#define DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 ++#define DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 ++#define DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 ++#define DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 ++//DMA_CLK0_SW1_CL0_CNTL ++#define DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 ++#define DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 ++#define DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 ++#define DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 ++#define DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 ++#define DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 ++//DMA_CLK0_SW2_CL0_CNTL ++#define DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 ++#define DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 ++#define DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 ++#define DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 ++#define DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 ++#define DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 ++//SYSHUB_CG_CNTL ++#define SYSHUB_CG_CNTL__SYSHUB_CG_EN__SHIFT 0x0 ++#define SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER__SHIFT 0x8 ++#define SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER__SHIFT 0x10 ++//SYSHUB_TRANS_IDLE ++#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0__SHIFT 0x0 ++#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1__SHIFT 0x1 ++#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2__SHIFT 0x2 ++#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3__SHIFT 0x3 ++#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4__SHIFT 0x4 ++#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5__SHIFT 0x5 ++#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6__SHIFT 0x6 ++#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7__SHIFT 0x7 ++#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8__SHIFT 0x8 ++#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9__SHIFT 0x9 ++#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10__SHIFT 0xa ++#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11__SHIFT 0xb ++#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12__SHIFT 0xc ++#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13__SHIFT 0xd ++#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14__SHIFT 0xe ++#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15__SHIFT 0xf ++#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF__SHIFT 0x10 ++//SYSHUB_HP_TIMER ++#define SYSHUB_HP_TIMER__SYSHUB_HP_TIMER__SHIFT 0x0 ++//SYSHUB_SCRATCH ++#define SYSHUB_SCRATCH__SCRATCH__SHIFT 0x0 ++//SYSHUB_DS_CTRL_SHUBCLK ++#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0 ++#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1 ++#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2 ++#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3 ++#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4 ++#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5 ++#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6 ++#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7 ++#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10 ++#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11 ++#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12 ++#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13 ++#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14 ++#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15 ++#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16 ++#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17 ++#define SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c ++#define SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN__SHIFT 0x1f ++//SYSHUB_DS_CTRL2_SHUBCLK ++#define SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER__SHIFT 0x0 ++//SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK ++#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en__SHIFT 0xf ++#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en__SHIFT 0x10 ++//SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK ++#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en__SHIFT 0xf ++#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en__SHIFT 0x10 ++//DMA_CLK1_SW0_SYSHUB_QOS_CNTL ++#define DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 ++#define DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 ++#define DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 ++//DMA_CLK1_SW1_SYSHUB_QOS_CNTL ++#define DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 ++#define DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 ++#define DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 ++//DMA_CLK1_SW0_CL0_CNTL ++#define DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 ++#define DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 ++#define DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 ++#define DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 ++#define DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 ++#define DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 ++//DMA_CLK1_SW0_CL1_CNTL ++#define DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 ++#define DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 ++#define DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 ++#define DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 ++#define DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 ++#define DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 ++//DMA_CLK1_SW0_CL2_CNTL ++#define DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 ++#define DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 ++#define DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 ++#define DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 ++#define DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 ++#define DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 ++//DMA_CLK1_SW0_CL3_CNTL ++#define DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 ++#define DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 ++#define DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 ++#define DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 ++#define DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 ++#define DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 ++//DMA_CLK1_SW0_CL4_CNTL ++#define DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 ++#define DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 ++#define DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 ++#define DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 ++#define DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 ++#define DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 ++//DMA_CLK1_SW1_CL0_CNTL ++#define DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 ++#define DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 ++#define DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 ++#define DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 ++#define DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 ++#define DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 ++//DMA_CLK1_SW1_CL1_CNTL ++#define DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 ++#define DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 ++#define DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 ++#define DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 ++#define DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 ++#define DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 ++//DMA_CLK1_SW1_CL2_CNTL ++#define DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 ++#define DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 ++#define DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 ++#define DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 ++#define DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 ++#define DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 ++//DMA_CLK1_SW1_CL3_CNTL ++#define DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 ++#define DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 ++#define DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 ++#define DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 ++#define DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 ++#define DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 ++//DMA_CLK1_SW1_CL4_CNTL ++#define DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 ++#define DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 ++#define DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 ++#define DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 ++#define DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 ++#define DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 ++ ++ ++// addressBlock: gdc_ras_gdc_ras_regblk ++//GDC_RAS_LEAF0_CTRL ++#define GDC_RAS_LEAF0_CTRL__POISON_DET_EN__SHIFT 0x0 ++#define GDC_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 ++#define GDC_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT 0x2 ++#define GDC_RAS_LEAF0_CTRL__PARITY_DET_EN__SHIFT 0x4 ++#define GDC_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 ++#define GDC_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT 0x6 ++#define GDC_RAS_LEAF0_CTRL__ERR_EVENT_RECV__SHIFT 0x10 ++#define GDC_RAS_LEAF0_CTRL__LINK_DIS_RECV__SHIFT 0x11 ++#define GDC_RAS_LEAF0_CTRL__POISON_ERR_DET__SHIFT 0x12 ++#define GDC_RAS_LEAF0_CTRL__PARITY_ERR_DET__SHIFT 0x13 ++#define GDC_RAS_LEAF0_CTRL__ERR_EVENT_SENT__SHIFT 0x14 ++#define GDC_RAS_LEAF0_CTRL__EGRESS_STALLED__SHIFT 0x15 ++//GDC_RAS_LEAF1_CTRL ++#define GDC_RAS_LEAF1_CTRL__POISON_DET_EN__SHIFT 0x0 ++#define GDC_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 ++#define GDC_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT 0x2 ++#define GDC_RAS_LEAF1_CTRL__PARITY_DET_EN__SHIFT 0x4 ++#define GDC_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 ++#define GDC_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT 0x6 ++#define GDC_RAS_LEAF1_CTRL__ERR_EVENT_RECV__SHIFT 0x10 ++#define GDC_RAS_LEAF1_CTRL__LINK_DIS_RECV__SHIFT 0x11 ++#define GDC_RAS_LEAF1_CTRL__POISON_ERR_DET__SHIFT 0x12 ++#define GDC_RAS_LEAF1_CTRL__PARITY_ERR_DET__SHIFT 0x13 ++#define GDC_RAS_LEAF1_CTRL__ERR_EVENT_SENT__SHIFT 0x14 ++#define GDC_RAS_LEAF1_CTRL__EGRESS_STALLED__SHIFT 0x15 ++//GDC_RAS_LEAF2_CTRL ++#define GDC_RAS_LEAF2_CTRL__POISON_DET_EN__SHIFT 0x0 ++#define GDC_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 ++#define GDC_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT 0x2 ++#define GDC_RAS_LEAF2_CTRL__PARITY_DET_EN__SHIFT 0x4 ++#define GDC_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 ++#define GDC_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT 0x6 ++#define GDC_RAS_LEAF2_CTRL__ERR_EVENT_RECV__SHIFT 0x10 ++#define GDC_RAS_LEAF2_CTRL__LINK_DIS_RECV__SHIFT 0x11 ++#define GDC_RAS_LEAF2_CTRL__POISON_ERR_DET__SHIFT 0x12 ++#define GDC_RAS_LEAF2_CTRL__PARITY_ERR_DET__SHIFT 0x13 ++#define GDC_RAS_LEAF2_CTRL__ERR_EVENT_SENT__SHIFT 0x14 ++#define GDC_RAS_LEAF2_CTRL__EGRESS_STALLED__SHIFT 0x15 ++//GDC_RAS_LEAF3_CTRL ++#define GDC_RAS_LEAF3_CTRL__POISON_DET_EN__SHIFT 0x0 ++#define GDC_RAS_LEAF3_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 ++#define GDC_RAS_LEAF3_CTRL__POISON_STALL_EN__SHIFT 0x2 ++#define GDC_RAS_LEAF3_CTRL__PARITY_DET_EN__SHIFT 0x4 ++#define GDC_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 ++#define GDC_RAS_LEAF3_CTRL__PARITY_STALL_EN__SHIFT 0x6 ++#define GDC_RAS_LEAF3_CTRL__ERR_EVENT_RECV__SHIFT 0x10 ++#define GDC_RAS_LEAF3_CTRL__LINK_DIS_RECV__SHIFT 0x11 ++#define GDC_RAS_LEAF3_CTRL__POISON_ERR_DET__SHIFT 0x12 ++#define GDC_RAS_LEAF3_CTRL__PARITY_ERR_DET__SHIFT 0x13 ++#define GDC_RAS_LEAF3_CTRL__ERR_EVENT_SENT__SHIFT 0x14 ++#define GDC_RAS_LEAF3_CTRL__EGRESS_STALLED__SHIFT 0x15 ++//GDC_RAS_LEAF4_CTRL ++#define GDC_RAS_LEAF4_CTRL__POISON_DET_EN__SHIFT 0x0 ++#define GDC_RAS_LEAF4_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 ++#define GDC_RAS_LEAF4_CTRL__POISON_STALL_EN__SHIFT 0x2 ++#define GDC_RAS_LEAF4_CTRL__PARITY_DET_EN__SHIFT 0x4 ++#define GDC_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 ++#define GDC_RAS_LEAF4_CTRL__PARITY_STALL_EN__SHIFT 0x6 ++#define GDC_RAS_LEAF4_CTRL__ERR_EVENT_RECV__SHIFT 0x10 ++#define GDC_RAS_LEAF4_CTRL__LINK_DIS_RECV__SHIFT 0x11 ++#define GDC_RAS_LEAF4_CTRL__POISON_ERR_DET__SHIFT 0x12 ++#define GDC_RAS_LEAF4_CTRL__PARITY_ERR_DET__SHIFT 0x13 ++#define GDC_RAS_LEAF4_CTRL__ERR_EVENT_SENT__SHIFT 0x14 ++#define GDC_RAS_LEAF4_CTRL__EGRESS_STALLED__SHIFT 0x15 ++//GDC_RAS_LEAF5_CTRL ++#define GDC_RAS_LEAF5_CTRL__POISON_DET_EN__SHIFT 0x0 ++#define GDC_RAS_LEAF5_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 ++#define GDC_RAS_LEAF5_CTRL__POISON_STALL_EN__SHIFT 0x2 ++#define GDC_RAS_LEAF5_CTRL__PARITY_DET_EN__SHIFT 0x4 ++#define GDC_RAS_LEAF5_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 ++#define GDC_RAS_LEAF5_CTRL__PARITY_STALL_EN__SHIFT 0x6 ++#define GDC_RAS_LEAF5_CTRL__ERR_EVENT_RECV__SHIFT 0x10 ++#define GDC_RAS_LEAF5_CTRL__LINK_DIS_RECV__SHIFT 0x11 ++#define GDC_RAS_LEAF5_CTRL__POISON_ERR_DET__SHIFT 0x12 ++#define GDC_RAS_LEAF5_CTRL__PARITY_ERR_DET__SHIFT 0x13 ++#define GDC_RAS_LEAF5_CTRL__ERR_EVENT_SENT__SHIFT 0x14 ++#define GDC_RAS_LEAF5_CTRL__EGRESS_STALLED__SHIFT 0x15 ++ ++ ++// addressBlock: gdc_rst_GDCRST_DEC ++//SHUB_PF_FLR_RST ++#define SHUB_PF_FLR_RST__PF0_FLR_RST__SHIFT 0x0 ++#define SHUB_PF_FLR_RST__PF1_FLR_RST__SHIFT 0x1 ++#define SHUB_PF_FLR_RST__PF2_FLR_RST__SHIFT 0x2 ++#define SHUB_PF_FLR_RST__PF3_FLR_RST__SHIFT 0x3 ++#define SHUB_PF_FLR_RST__PF4_FLR_RST__SHIFT 0x4 ++#define SHUB_PF_FLR_RST__PF5_FLR_RST__SHIFT 0x5 ++#define SHUB_PF_FLR_RST__PF6_FLR_RST__SHIFT 0x6 ++#define SHUB_PF_FLR_RST__PF7_FLR_RST__SHIFT 0x7 ++//SHUB_GFX_DRV_MODE1_RST ++#define SHUB_GFX_DRV_MODE1_RST__GFX_DRV_MODE1_RST__SHIFT 0x0 ++//SHUB_LINK_RESET ++#define SHUB_LINK_RESET__LINK_RESET__SHIFT 0x0 ++//SHUB_PF0_VF_FLR_RST ++#define SHUB_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__SHIFT 0x0 ++#define SHUB_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__SHIFT 0x1 ++#define SHUB_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__SHIFT 0x2 ++#define SHUB_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__SHIFT 0x3 ++#define SHUB_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__SHIFT 0x4 ++#define SHUB_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__SHIFT 0x5 ++#define SHUB_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__SHIFT 0x6 ++#define SHUB_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__SHIFT 0x7 ++#define SHUB_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__SHIFT 0x8 ++#define SHUB_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__SHIFT 0x9 ++#define SHUB_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__SHIFT 0xa ++#define SHUB_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__SHIFT 0xb ++#define SHUB_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__SHIFT 0xc ++#define SHUB_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__SHIFT 0xd ++#define SHUB_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__SHIFT 0xe ++#define SHUB_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__SHIFT 0xf ++#define SHUB_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__SHIFT 0x1f ++//SHUB_HARD_RST_CTRL ++#define SHUB_HARD_RST_CTRL__COR_RESET_EN__SHIFT 0x0 ++#define SHUB_HARD_RST_CTRL__REG_RESET_EN__SHIFT 0x1 ++#define SHUB_HARD_RST_CTRL__STY_RESET_EN__SHIFT 0x2 ++#define SHUB_HARD_RST_CTRL__NIC400_RESET_EN__SHIFT 0x3 ++#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4 ++//SHUB_SOFT_RST_CTRL ++#define SHUB_SOFT_RST_CTRL__COR_RESET_EN__SHIFT 0x0 ++#define SHUB_SOFT_RST_CTRL__REG_RESET_EN__SHIFT 0x1 ++#define SHUB_SOFT_RST_CTRL__STY_RESET_EN__SHIFT 0x2 ++#define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN__SHIFT 0x3 ++#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4 ++//SHUB_SDP_PORT_RST ++#define SHUB_SDP_PORT_RST__SDP_PORT_RST__SHIFT 0x0 ++ ++ ++// addressBlock: bif_bx_pf_SYSDEC ++//SBIOS_SCRATCH_0 ++#define SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__SHIFT 0x0 ++//SBIOS_SCRATCH_1 ++#define SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__SHIFT 0x0 ++//SBIOS_SCRATCH_2 ++#define SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__SHIFT 0x0 ++//SBIOS_SCRATCH_3 ++#define SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__SHIFT 0x0 ++//BIOS_SCRATCH_0 ++#define BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0 ++//BIOS_SCRATCH_1 ++#define BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0 ++//BIOS_SCRATCH_2 ++#define BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 ++//BIOS_SCRATCH_3 ++#define BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 ++//BIOS_SCRATCH_4 ++#define BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0 ++//BIOS_SCRATCH_5 ++#define BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0 ++//BIOS_SCRATCH_6 ++#define BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 ++//BIOS_SCRATCH_7 ++#define BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0 ++//BIOS_SCRATCH_8 ++#define BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0 ++//BIOS_SCRATCH_9 ++#define BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0 ++//BIOS_SCRATCH_10 ++#define BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0 ++//BIOS_SCRATCH_11 ++#define BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0 ++//BIOS_SCRATCH_12 ++#define BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0 ++//BIOS_SCRATCH_13 ++#define BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0 ++//BIOS_SCRATCH_14 ++#define BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0 ++//BIOS_SCRATCH_15 ++#define BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0 ++//BIF_RLC_INTR_CNTL ++#define BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__SHIFT 0x0 ++#define BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__SHIFT 0x1 ++#define BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__SHIFT 0x2 ++#define BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__SHIFT 0x3 ++//BIF_VCE_INTR_CNTL ++#define BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__SHIFT 0x0 ++#define BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__SHIFT 0x1 ++#define BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__SHIFT 0x2 ++#define BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__SHIFT 0x3 ++//BIF_UVD_INTR_CNTL ++#define BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__SHIFT 0x0 ++#define BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__SHIFT 0x1 ++#define BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__SHIFT 0x2 ++#define BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__SHIFT 0x3 ++//GFX_MMIOREG_CAM_ADDR0 ++#define GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0 ++//GFX_MMIOREG_CAM_REMAP_ADDR0 ++#define GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0 ++//GFX_MMIOREG_CAM_ADDR1 ++#define GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0 ++//GFX_MMIOREG_CAM_REMAP_ADDR1 ++#define GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0 ++//GFX_MMIOREG_CAM_ADDR2 ++#define GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0 ++//GFX_MMIOREG_CAM_REMAP_ADDR2 ++#define GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0 ++//GFX_MMIOREG_CAM_ADDR3 ++#define GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0 ++//GFX_MMIOREG_CAM_REMAP_ADDR3 ++#define GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0 ++//GFX_MMIOREG_CAM_ADDR4 ++#define GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0 ++//GFX_MMIOREG_CAM_REMAP_ADDR4 ++#define GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0 ++//GFX_MMIOREG_CAM_ADDR5 ++#define GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0 ++//GFX_MMIOREG_CAM_REMAP_ADDR5 ++#define GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0 ++//GFX_MMIOREG_CAM_ADDR6 ++#define GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0 ++//GFX_MMIOREG_CAM_REMAP_ADDR6 ++#define GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0 ++//GFX_MMIOREG_CAM_ADDR7 ++#define GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0 ++//GFX_MMIOREG_CAM_REMAP_ADDR7 ++#define GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0 ++//GFX_MMIOREG_CAM_CNTL ++#define GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0 ++//GFX_MMIOREG_CAM_ZERO_CPL ++#define GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0 ++//GFX_MMIOREG_CAM_ONE_CPL ++#define GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0 ++//GFX_MMIOREG_CAM_PROGRAMMABLE_CPL ++#define GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0 ++ ++ ++// addressBlock: bif_bx_pf_SYSPFVFDEC ++//MM_INDEX ++#define MM_INDEX__MM_OFFSET__SHIFT 0x0 ++#define MM_INDEX__MM_APER__SHIFT 0x1f ++//MM_DATA ++#define MM_DATA__MM_DATA__SHIFT 0x0 ++//MM_INDEX_HI ++#define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 ++//SYSHUB_INDEX_OVLP ++#define SYSHUB_INDEX_OVLP__SYSHUB_OFFSET__SHIFT 0x0 ++//SYSHUB_DATA_OVLP ++#define SYSHUB_DATA_OVLP__SYSHUB_DATA__SHIFT 0x0 ++//PCIE_INDEX ++#define PCIE_INDEX__PCIE_INDEX__SHIFT 0x0 ++//PCIE_DATA ++#define PCIE_DATA__PCIE_DATA__SHIFT 0x0 ++//PCIE_INDEX2 ++#define PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0 ++//PCIE_DATA2 ++#define PCIE_DATA2__PCIE_DATA2__SHIFT 0x0 ++ ++ ++// addressBlock: rcc_dwn_BIFDEC1 ++//DN_PCIE_RESERVED ++#define DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 ++//DN_PCIE_SCRATCH ++#define DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 ++//DN_PCIE_CNTL ++#define DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 ++#define DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 ++#define DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e ++//DN_PCIE_CONFIG_CNTL ++#define DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 ++//DN_PCIE_RX_CNTL2 ++#define DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c ++//DN_PCIE_BUS_CNTL ++#define DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 ++#define DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 ++//DN_PCIE_CFG_CNTL ++#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 ++#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 ++#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 ++//DN_PCIE_STRAP_F0 ++#define DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0 ++#define DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11 ++#define DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15 ++//DN_PCIE_STRAP_MISC ++#define DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18 ++#define DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d ++//DN_PCIE_STRAP_MISC2 ++#define DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2 ++ ++ ++// addressBlock: rcc_dwnp_BIFDEC1 ++//PCIEP_RESERVED ++#define PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 ++//PCIEP_SCRATCH ++#define PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 ++//PCIE_ERR_CNTL ++#define PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 ++#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 ++#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb ++#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 ++//PCIE_RX_CNTL ++#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 ++#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 ++#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 ++#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 ++#define PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b ++//PCIE_LC_SPEED_CNTL ++#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 ++#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 ++//PCIE_LC_CNTL2 ++#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b ++//PCIEP_STRAP_MISC ++#define PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa ++//LTR_MSG_INFO_FROM_EP ++#define LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 ++ ++ ++// addressBlock: rcc_ep_BIFDEC1 ++//EP_PCIE_SCRATCH ++#define EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 ++//EP_PCIE_CNTL ++#define EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 ++#define EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 ++#define EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e ++//EP_PCIE_INT_CNTL ++#define EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 ++#define EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 ++#define EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 ++#define EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 ++#define EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 ++#define EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 ++//EP_PCIE_INT_STATUS ++#define EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 ++#define EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 ++#define EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 ++#define EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 ++#define EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 ++#define EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 ++//EP_PCIE_RX_CNTL2 ++#define EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 ++//EP_PCIE_BUS_CNTL ++#define EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 ++//EP_PCIE_CFG_CNTL ++#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 ++#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 ++#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 ++//EP_PCIE_OBFF_CNTL ++#define EP_PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE__SHIFT 0x0 ++#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN__SHIFT 0x1 ++#define EP_PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE__SHIFT 0x2 ++#define EP_PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE__SHIFT 0x3 ++#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH__SHIFT 0x4 ++#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH__SHIFT 0x8 ++#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD__SHIFT 0xc ++#define EP_PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE__SHIFT 0x10 ++#define EP_PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE__SHIFT 0x11 ++#define EP_PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE__SHIFT 0x12 ++#define EP_PCIE_OBFF_CNTL__TX_OBFF_ACCEPT_IN_NOND0__SHIFT 0x13 ++#define EP_PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE__SHIFT 0x14 ++//EP_PCIE_TX_LTR_CNTL ++#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 ++#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 ++#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 ++#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 ++#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa ++#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd ++#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe ++#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf ++#define EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 ++//EP_PCIE_STRAP_MISC ++#define EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d ++//EP_PCIE_STRAP_MISC2 ++#define EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4 ++//EP_PCIE_STRAP_PI ++//EP_PCIE_F0_DPA_CAP ++#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 ++#define EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc ++#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 ++#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 ++//EP_PCIE_F0_DPA_LATENCY_INDICATOR ++#define EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 ++//EP_PCIE_F0_DPA_CNTL ++#define EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 ++#define EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 ++//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 ++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 ++//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 ++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 ++//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 ++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 ++//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 ++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 ++//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 ++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 ++//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 ++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 ++//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 ++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 ++//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 ++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 ++//EP_PCIE_PME_CONTROL ++#define EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 ++//EP_PCIEP_RESERVED ++#define EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 ++//EP_PCIE_TX_CNTL ++#define EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa ++#define EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc ++#define EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 ++#define EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 ++#define EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a ++//EP_PCIE_TX_REQUESTER_ID ++#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 ++#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 ++#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 ++//EP_PCIE_ERR_CNTL ++#define EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 ++#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 ++#define EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 ++#define EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 ++#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18 ++#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19 ++#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a ++#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b ++#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c ++#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d ++#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e ++#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f ++//EP_PCIE_RX_CNTL ++#define EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 ++#define EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 ++#define EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 ++#define EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 ++#define EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 ++#define EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 ++#define EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 ++#define EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a ++//EP_PCIE_LC_SPEED_CNTL ++#define EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 ++#define EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 ++ ++ ++// addressBlock: bif_bx_pf_BIFDEC1 ++//BIF_MM_INDACCESS_CNTL ++#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1 ++//BUS_CNTL ++#define BUS_CNTL__PMI_INT_DIS_EP__SHIFT 0x3 ++#define BUS_CNTL__PMI_INT_DIS_DN__SHIFT 0x4 ++#define BUS_CNTL__PMI_INT_DIS_SWUS__SHIFT 0x5 ++#define BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6 ++#define BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7 ++#define BUS_CNTL__SET_AZ_TC__SHIFT 0xa ++#define BUS_CNTL__SET_MC_TC__SHIFT 0xd ++#define BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10 ++#define BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11 ++#define BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12 ++#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT 0x13 ++#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT 0x14 ++#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT 0x15 ++#define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT 0x16 ++#define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT 0x17 ++#define BUS_CNTL__UR_OVRD_FOR_ECRC_EN__SHIFT 0x18 ++//BIF_SCRATCH0 ++#define BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0 ++//BIF_SCRATCH1 ++#define BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0 ++//BX_RESET_EN ++#define BX_RESET_EN__COR_RESET_EN__SHIFT 0x0 ++#define BX_RESET_EN__REG_RESET_EN__SHIFT 0x1 ++#define BX_RESET_EN__STY_RESET_EN__SHIFT 0x2 ++#define BX_RESET_EN__FLR_TWICE_EN__SHIFT 0x8 ++#define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10 ++//MM_CFGREGS_CNTL ++#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0 ++#define MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6 ++#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f ++//BX_RESET_CNTL ++#define BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0 ++//INTERRUPT_CNTL ++#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0 ++#define INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1 ++#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3 ++#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4 ++#define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8 ++#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf ++//INTERRUPT_CNTL2 ++#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0 ++//CLKREQB_PAD_CNTL ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0 ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1 ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2 ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3 ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5 ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6 ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7 ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8 ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9 ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd ++#define CLKREQB_PAD_CNTL__CLKREQB_PERF_COUNTER_UPPER__SHIFT 0x18 ++//CLKREQB_PERF_COUNTER ++#define CLKREQB_PERF_COUNTER__CLKREQB_PERF_COUNTER_LOWER__SHIFT 0x0 ++//BIF_CLK_CTRL ++#define BIF_CLK_CTRL__BIF_XSTCLK_READY__SHIFT 0x0 ++#define BIF_CLK_CTRL__BACO_XSTCLK_SWITCH_BYPASS__SHIFT 0x1 ++//BIF_FEATURES_CONTROL_MISC ++#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0 ++#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1 ++#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2 ++#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3 ++#define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS__SHIFT 0x9 ++#define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS__SHIFT 0xa ++#define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0xb ++#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc ++#define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd ++#define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf ++#define BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS__SHIFT 0x11 ++#define BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS__SHIFT 0x12 ++#define BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x18 ++//BIF_DOORBELL_CNTL ++#define BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0 ++#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1 ++#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2 ++#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3 ++#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4 ++#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18 ++#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19 ++#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a ++#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b ++//BIF_DOORBELL_INT_CNTL ++#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0 ++#define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS__SHIFT 0x1 ++#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10 ++#define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR__SHIFT 0x11 ++//BIF_SLVARB_MODE ++#define BIF_SLVARB_MODE__SLVARB_MODE__SHIFT 0x0 ++//BIF_FB_EN ++#define BIF_FB_EN__FB_READ_EN__SHIFT 0x0 ++#define BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1 ++//BIF_BUSY_DELAY_CNTR ++#define BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x0 ++//BIF_PERFMON_CNTL ++#define BIF_PERFMON_CNTL__PERFCOUNTER_EN__SHIFT 0x0 ++#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0__SHIFT 0x1 ++#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__SHIFT 0x2 ++#define BIF_PERFMON_CNTL__PERF_SEL0__SHIFT 0x8 ++#define BIF_PERFMON_CNTL__PERF_SEL1__SHIFT 0xd ++//BIF_PERFCOUNTER0_RESULT ++#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0 ++//BIF_PERFCOUNTER1_RESULT ++#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0 ++//BIF_MST_TRANS_PENDING_VF ++#define BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0 ++//BIF_SLV_TRANS_PENDING_VF ++#define BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0 ++//BACO_CNTL ++#define BACO_CNTL__BACO_EN__SHIFT 0x0 ++#define BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT 0x1 ++#define BACO_CNTL__BACO_DUMMY_EN__SHIFT 0x2 ++#define BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3 ++#define BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT 0x5 ++#define BACO_CNTL__BACO_RST_INTR_MASK__SHIFT 0x6 ++#define BACO_CNTL__BACO_MODE__SHIFT 0x8 ++#define BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x9 ++#define BACO_CNTL__BACO_AUTO_EXIT__SHIFT 0x1f ++//BIF_BACO_EXIT_TIME0 ++#define BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT 0x0 ++//BIF_BACO_EXIT_TIMER1 ++#define BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT 0x0 ++#define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT 0x1a ++#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT 0x1b ++#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT 0x1c ++#define BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT 0x1d ++#define BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT 0x1f ++//BIF_BACO_EXIT_TIMER2 ++#define BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT 0x0 ++//BIF_BACO_EXIT_TIMER3 ++#define BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT 0x0 ++//BIF_BACO_EXIT_TIMER4 ++#define BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT 0x0 ++//MEM_TYPE_CNTL ++#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0 ++//SMU_BIF_VDDGFX_PWR_STATUS ++#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__SHIFT 0x0 ++//BIF_VDDGFX_GFX0_LOWER ++#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__SHIFT 0x2 ++#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__SHIFT 0x1e ++#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__SHIFT 0x1f ++//BIF_VDDGFX_GFX0_UPPER ++#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__SHIFT 0x2 ++//BIF_VDDGFX_GFX1_LOWER ++#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__SHIFT 0x2 ++#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__SHIFT 0x1e ++#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__SHIFT 0x1f ++//BIF_VDDGFX_GFX1_UPPER ++#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__SHIFT 0x2 ++//BIF_VDDGFX_GFX2_LOWER ++#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__SHIFT 0x2 ++#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__SHIFT 0x1e ++#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__SHIFT 0x1f ++//BIF_VDDGFX_GFX2_UPPER ++#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__SHIFT 0x2 ++//BIF_VDDGFX_GFX3_LOWER ++#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__SHIFT 0x2 ++#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__SHIFT 0x1e ++#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__SHIFT 0x1f ++//BIF_VDDGFX_GFX3_UPPER ++#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__SHIFT 0x2 ++//BIF_VDDGFX_GFX4_LOWER ++#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__SHIFT 0x2 ++#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__SHIFT 0x1e ++#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__SHIFT 0x1f ++//BIF_VDDGFX_GFX4_UPPER ++#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2 ++//BIF_VDDGFX_GFX5_LOWER ++#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__SHIFT 0x2 ++#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__SHIFT 0x1e ++#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__SHIFT 0x1f ++//BIF_VDDGFX_GFX5_UPPER ++#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__SHIFT 0x2 ++//BIF_VDDGFX_RSV1_LOWER ++#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__SHIFT 0x2 ++#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__SHIFT 0x1e ++#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__SHIFT 0x1f ++//BIF_VDDGFX_RSV1_UPPER ++#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__SHIFT 0x2 ++//BIF_VDDGFX_RSV2_LOWER ++#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__SHIFT 0x2 ++#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__SHIFT 0x1e ++#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__SHIFT 0x1f ++//BIF_VDDGFX_RSV2_UPPER ++#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__SHIFT 0x2 ++//BIF_VDDGFX_RSV3_LOWER ++#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__SHIFT 0x2 ++#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT 0x1e ++#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__SHIFT 0x1f ++//BIF_VDDGFX_RSV3_UPPER ++#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__SHIFT 0x2 ++//BIF_VDDGFX_RSV4_LOWER ++#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__SHIFT 0x2 ++#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__SHIFT 0x1e ++#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__SHIFT 0x1f ++//BIF_VDDGFX_RSV4_UPPER ++#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__SHIFT 0x2 ++//BIF_VDDGFX_FB_CMP ++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__SHIFT 0x0 ++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__SHIFT 0x1 ++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__SHIFT 0x2 ++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__SHIFT 0x3 ++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__SHIFT 0x4 ++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__SHIFT 0x5 ++//BIF_DOORBELL_GBLAPER1_LOWER ++#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__SHIFT 0x2 ++#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__SHIFT 0x1f ++//BIF_DOORBELL_GBLAPER1_UPPER ++#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__SHIFT 0x2 ++//BIF_DOORBELL_GBLAPER2_LOWER ++#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__SHIFT 0x2 ++#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__SHIFT 0x1f ++//BIF_DOORBELL_GBLAPER2_UPPER ++#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__SHIFT 0x2 ++//REMAP_HDP_MEM_FLUSH_CNTL ++#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2 ++//REMAP_HDP_REG_FLUSH_CNTL ++#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2 ++//BIF_RB_CNTL ++#define BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0 ++#define BIF_RB_CNTL__RB_SIZE__SHIFT 0x1 ++#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 ++#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9 ++#define BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11 ++#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f ++//BIF_RB_BASE ++#define BIF_RB_BASE__ADDR__SHIFT 0x0 ++//BIF_RB_RPTR ++#define BIF_RB_RPTR__OFFSET__SHIFT 0x2 ++//BIF_RB_WPTR ++#define BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0 ++#define BIF_RB_WPTR__OFFSET__SHIFT 0x2 ++//BIF_RB_WPTR_ADDR_HI ++#define BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 ++//BIF_RB_WPTR_ADDR_LO ++#define BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 ++//MAILBOX_INDEX ++#define MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0 ++//BIF_GPUIOV_RESET_NOTIFICATION ++#define BIF_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION__SHIFT 0x0 ++//BIF_UVD_GPUIOV_CFG_SIZE ++#define BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE__SHIFT 0x0 ++//BIF_VCE_GPUIOV_CFG_SIZE ++#define BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE__SHIFT 0x0 ++//BIF_GFX_SDMA_GPUIOV_CFG_SIZE ++#define BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT 0x0 ++//BIF_GMI_WRR_WEIGHT ++#define BIF_GMI_WRR_WEIGHT__GMI_REQ_REALTIME_WEIGHT__SHIFT 0x0 ++#define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_P_WEIGHT__SHIFT 0x8 ++#define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_NP_WEIGHT__SHIFT 0x10 ++//NBIF_STRAP_WRITE_CTRL ++#define NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE__SHIFT 0x0 ++//BIF_PERSTB_PAD_CNTL ++#define BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT 0x0 ++//BIF_PX_EN_PAD_CNTL ++#define BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT 0x0 ++//BIF_REFPADKIN_PAD_CNTL ++#define BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT 0x0 ++//BIF_CLKREQB_PAD_CNTL ++#define BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT 0x0 ++ ++ ++// addressBlock: rcc_pf_0_BIFDEC1 ++//RCC_BACO_CNTL_MISC ++#define RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0 ++#define RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1 ++//RCC_RESET_EN ++#define RCC_RESET_EN__DB_APER_RESET_EN__SHIFT 0xf ++//RCC_VDM_SUPPORT ++#define RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0 ++#define RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1 ++#define RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2 ++#define RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3 ++#define RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4 ++//RCC_PEER_REG_RANGE0 ++#define RCC_PEER_REG_RANGE0__START_ADDR__SHIFT 0x0 ++#define RCC_PEER_REG_RANGE0__END_ADDR__SHIFT 0x10 ++//RCC_PEER_REG_RANGE1 ++#define RCC_PEER_REG_RANGE1__START_ADDR__SHIFT 0x0 ++#define RCC_PEER_REG_RANGE1__END_ADDR__SHIFT 0x10 ++//RCC_BUS_CNTL ++#define RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2 ++#define RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3 ++#define RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4 ++#define RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5 ++#define RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6 ++#define RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7 ++#define RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8 ++#define RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc ++#define RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd ++#define RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10 ++#define RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11 ++#define RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12 ++#define RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13 ++#define RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14 ++#define RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15 ++#define RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18 ++#define RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19 ++#define RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c ++#define RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d ++//RCC_CONFIG_CNTL ++#define RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0 ++#define RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2 ++#define RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3 ++//RCC_CONFIG_F0_BASE ++#define RCC_CONFIG_F0_BASE__F0_BASE__SHIFT 0x0 ++//RCC_CONFIG_APER_SIZE ++#define RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0 ++//RCC_CONFIG_REG_APER_SIZE ++#define RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0 ++//RCC_XDMA_LO ++#define RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0 ++#define RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f ++//RCC_XDMA_HI ++#define RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0 ++//RCC_FEATURES_CONTROL_MISC ++#define RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x4 ++#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x5 ++#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x6 ++#define RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8 ++#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9 ++#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa ++#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb ++#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc ++#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd ++#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe ++#define RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT 0xf ++#define RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10 ++#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11 ++#define RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12 ++//RCC_BUSNUM_CNTL1 ++#define RCC_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0 ++//RCC_BUSNUM_LIST0 ++#define RCC_BUSNUM_LIST0__ID0__SHIFT 0x0 ++#define RCC_BUSNUM_LIST0__ID1__SHIFT 0x8 ++#define RCC_BUSNUM_LIST0__ID2__SHIFT 0x10 ++#define RCC_BUSNUM_LIST0__ID3__SHIFT 0x18 ++//RCC_BUSNUM_LIST1 ++#define RCC_BUSNUM_LIST1__ID4__SHIFT 0x0 ++#define RCC_BUSNUM_LIST1__ID5__SHIFT 0x8 ++#define RCC_BUSNUM_LIST1__ID6__SHIFT 0x10 ++#define RCC_BUSNUM_LIST1__ID7__SHIFT 0x18 ++//RCC_BUSNUM_CNTL2 ++#define RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0 ++#define RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8 ++#define RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10 ++#define RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11 ++//RCC_CAPTURE_HOST_BUSNUM ++#define RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0 ++//RCC_HOST_BUSNUM ++#define RCC_HOST_BUSNUM__HOST_ID__SHIFT 0x0 ++//RCC_PEER0_FB_OFFSET_HI ++#define RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0 ++//RCC_PEER0_FB_OFFSET_LO ++#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0 ++#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f ++//RCC_PEER1_FB_OFFSET_HI ++#define RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0 ++//RCC_PEER1_FB_OFFSET_LO ++#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0 ++#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f ++//RCC_PEER2_FB_OFFSET_HI ++#define RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0 ++//RCC_PEER2_FB_OFFSET_LO ++#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0 ++#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f ++//RCC_PEER3_FB_OFFSET_HI ++#define RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0 ++//RCC_PEER3_FB_OFFSET_LO ++#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0 ++#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f ++//RCC_DEVFUNCNUM_LIST0 ++#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0 ++#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8 ++#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10 ++#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18 ++//RCC_DEVFUNCNUM_LIST1 ++#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0 ++#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8 ++#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10 ++#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18 ++//RCC_DEV0_LINK_CNTL ++#define RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x0 ++#define RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x8 ++//RCC_CMN_LINK_CNTL ++#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0 ++#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1 ++#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2 ++#define RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3 ++//RCC_EP_REQUESTERID_RESTORE ++#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0 ++#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8 ++//RCC_LTR_LSWITCH_CNTL ++#define RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0 ++//RCC_MH_ARB_CNTL ++#define RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0 ++#define RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1 ++ ++ ++// addressBlock: rcc_pf_0_BIFDEC2 ++//GFXMSIX_VECT0_ADDR_LO ++#define GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 ++//GFXMSIX_VECT0_ADDR_HI ++#define GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 ++//GFXMSIX_VECT0_MSG_DATA ++#define GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 ++//GFXMSIX_VECT0_CONTROL ++#define GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 ++//GFXMSIX_VECT1_ADDR_LO ++#define GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 ++//GFXMSIX_VECT1_ADDR_HI ++#define GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 ++//GFXMSIX_VECT1_MSG_DATA ++#define GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 ++//GFXMSIX_VECT1_CONTROL ++#define GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 ++//GFXMSIX_VECT2_ADDR_LO ++#define GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 ++//GFXMSIX_VECT2_ADDR_HI ++#define GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 ++//GFXMSIX_VECT2_MSG_DATA ++#define GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 ++//GFXMSIX_VECT2_CONTROL ++#define GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 ++//GFXMSIX_PBA ++#define GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 ++#define GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 ++#define GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 ++ ++ ++// addressBlock: rcc_strap_BIFDEC1 ++//RCC_DEV0_PORT_STRAP0 ++#define RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x1 ++#define RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x2 ++#define RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x3 ++#define RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x4 ++#define RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x5 ++#define RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15 ++#define RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18 ++#define RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19 ++#define RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c ++#define RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f ++//RCC_DEV0_PORT_STRAP1 ++#define RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0 ++#define RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10 ++//RCC_DEV0_PORT_STRAP2 ++#define RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0 ++#define RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1 ++#define RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2 ++#define RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3 ++#define RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4 ++#define RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5 ++#define RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT 0x6 ++#define RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7 ++#define RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8 ++#define RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9 ++#define RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc ++#define RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd ++#define RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe ++#define RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf ++#define RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10 ++#define RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x11 ++#define RCC_DEV0_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x13 ++#define RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14 ++#define RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17 ++#define RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a ++#define RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d ++//RCC_DEV0_PORT_STRAP3 ++#define RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0 ++#define RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1 ++#define RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2 ++#define RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3 ++#define RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6 ++#define RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7 ++#define RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8 ++#define RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9 ++#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb ++#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe ++#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12 ++#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15 ++#define RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19 ++#define RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b ++#define RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d ++#define RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0__SHIFT 0x1e ++#define RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f ++//RCC_DEV0_PORT_STRAP4 ++#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0 ++#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8 ++#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10 ++#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18 ++//RCC_DEV0_PORT_STRAP5 ++#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0 ++#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8 ++#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10 ++#define RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11 ++#define RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12 ++#define RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13 ++#define RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14 ++#define RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15 ++#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17 ++#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18 ++#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19 ++#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a ++#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b ++#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c ++#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d ++#define RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT 0x1e ++#define RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f ++//RCC_DEV0_PORT_STRAP6 ++#define RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0 ++#define RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1 ++//RCC_DEV0_PORT_STRAP7 ++#define RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0 ++#define RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8 ++#define RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc ++#define RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10 ++#define RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18 ++#define RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d ++//RCC_DEV0_EPF0_STRAP0 ++#define RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 ++#define RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 ++#define RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 ++#define RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 ++#define RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c ++#define RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d ++#define RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e ++#define RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f ++//RCC_DEV0_EPF0_STRAP1 ++#define RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0 ++#define RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10 ++//RCC_DEV0_EPF0_STRAP13 ++#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0 ++#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8 ++#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10 ++//RCC_DEV0_EPF0_STRAP2 ++#define RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0 ++#define RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x1 ++#define RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6 ++#define RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7 ++#define RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8 ++#define RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9 ++#define RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe ++#define RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf ++#define RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10 ++#define RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11 ++#define RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12 ++#define RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14 ++#define RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15 ++#define RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16 ++#define RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17 ++#define RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18 ++#define RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b ++#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c ++#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d ++#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e ++#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f ++//RCC_DEV0_EPF0_STRAP3 ++#define RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x0 ++#define RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x1 ++#define RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x2 ++#define RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12 ++#define RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13 ++#define RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14 ++#define RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15 ++#define RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18 ++#define RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0__SHIFT 0x19 ++#define RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a ++#define RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b ++//RCC_DEV0_EPF0_STRAP4 ++#define RCC_DEV0_EPF0_STRAP4__STRAP_MSIX_TABLE_OFFSET_DEV0_F0__SHIFT 0x0 ++#define RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14 ++#define RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15 ++#define RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16 ++#define RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17 ++#define RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c ++#define RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT 0x1f ++//RCC_DEV0_EPF0_STRAP5 ++#define RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0 ++//RCC_DEV0_EPF0_STRAP8 ++#define RCC_DEV0_EPF0_STRAP8__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x0 ++#define RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x1 ++#define RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3 ++#define RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x4 ++#define RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x5 ++#define RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7 ++#define RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8 ++#define RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0x9 ++#define RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xc ++#define RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0xe ++#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x10 ++#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x13 ++#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x16 ++#define RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT 0x18 ++#define RCC_DEV0_EPF0_STRAP8__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x19 ++#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x1a ++#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b ++#define RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e ++//RCC_DEV0_EPF0_STRAP9 ++//RCC_DEV0_EPF1_STRAP0 ++#define RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0 ++#define RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10 ++#define RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14 ++#define RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c ++#define RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d ++#define RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e ++#define RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f ++//RCC_DEV0_EPF1_STRAP10 ++#define RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1__SHIFT 0x0 ++#define RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1 ++//RCC_DEV0_EPF1_STRAP11 ++#define RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1__SHIFT 0x0 ++#define RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1 ++//RCC_DEV0_EPF1_STRAP12 ++#define RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1__SHIFT 0x0 ++#define RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1 ++//RCC_DEV0_EPF1_STRAP13 ++#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT 0x0 ++#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT 0x8 ++#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT 0x10 ++//RCC_DEV0_EPF1_STRAP2 ++#define RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7 ++#define RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8 ++#define RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe ++#define RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10 ++#define RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11 ++#define RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT 0x12 ++#define RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14 ++#define RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15 ++#define RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT 0x16 ++#define RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT 0x17 ++#define RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18 ++//RCC_DEV0_EPF1_STRAP3 ++#define RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x0 ++#define RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x1 ++#define RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x2 ++#define RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12 ++#define RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13 ++#define RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14 ++#define RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18 ++#define RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1__SHIFT 0x19 ++#define RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a ++#define RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b ++//RCC_DEV0_EPF1_STRAP4 ++#define RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14 ++#define RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15 ++#define RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16 ++#define RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17 ++#define RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c ++#define RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x1f ++//RCC_DEV0_EPF1_STRAP5 ++#define RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0 ++//RCC_DEV0_EPF1_STRAP6 ++#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT 0x0 ++#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x1 ++#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT 0x2 ++#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1__SHIFT 0x4 ++#define RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__SHIFT 0x8 ++#define RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x9 ++#define RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__SHIFT 0x10 ++#define RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x11 ++#define RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__SHIFT 0x18 ++#define RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x19 ++//RCC_DEV0_EPF1_STRAP7 ++#define RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1__SHIFT 0x0 ++#define RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1__SHIFT 0x1 ++ ++ ++// addressBlock: bif_bx_pf_BIFPFVFDEC1 ++//BIF_BME_STATUS ++#define BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 ++#define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 ++//BIF_ATOMIC_ERR_LOG ++#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 ++#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 ++#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 ++#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 ++//DOORBELL_SELFRING_GPA_APER_BASE_HIGH ++#define DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 ++//DOORBELL_SELFRING_GPA_APER_BASE_LOW ++#define DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 ++//DOORBELL_SELFRING_GPA_APER_CNTL ++#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 ++#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 ++//HDP_REG_COHERENCY_FLUSH_CNTL ++#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 ++//HDP_MEM_COHERENCY_FLUSH_CNTL ++#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 ++//GPU_HDP_FLUSH_REQ ++#define GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 ++#define GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 ++#define GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 ++#define GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 ++#define GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 ++#define GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 ++#define GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 ++#define GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 ++#define GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 ++#define GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 ++#define GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa ++#define GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb ++//GPU_HDP_FLUSH_DONE ++#define GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 ++#define GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 ++#define GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 ++#define GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 ++#define GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 ++#define GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 ++#define GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 ++#define GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 ++#define GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 ++#define GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 ++#define GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa ++#define GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb ++//BIF_TRANS_PENDING ++#define BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 ++#define BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 ++//MAILBOX_MSGBUF_TRN_DW0 ++#define MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 ++//MAILBOX_MSGBUF_TRN_DW1 ++#define MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 ++//MAILBOX_MSGBUF_TRN_DW2 ++#define MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 ++//MAILBOX_MSGBUF_TRN_DW3 ++#define MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 ++//MAILBOX_MSGBUF_RCV_DW0 ++#define MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 ++//MAILBOX_MSGBUF_RCV_DW1 ++#define MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 ++//MAILBOX_MSGBUF_RCV_DW2 ++#define MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 ++//MAILBOX_MSGBUF_RCV_DW3 ++#define MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 ++//MAILBOX_CONTROL ++#define MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 ++#define MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 ++#define MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 ++#define MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 ++//MAILBOX_INT_CNTL ++#define MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 ++#define MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 ++//BIF_VMHV_MAILBOX ++#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 ++#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 ++#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 ++#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf ++#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 ++#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 ++#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 ++#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 ++ ++ ++// addressBlock: rcc_pf_0_BIFPFVFDEC1 ++//RCC_DOORBELL_APER_EN ++#define RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 ++//RCC_CONFIG_MEMSIZE ++#define RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 ++//RCC_CONFIG_RESERVED ++#define RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 ++//RCC_IOV_FUNC_IDENTIFIER ++#define RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 ++#define RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f ++ ++ ++// addressBlock: syshub_mmreg_ind_syshubdec ++//SYSHUB_INDEX ++#define SYSHUB_INDEX__INDEX__SHIFT 0x0 ++//SYSHUB_DATA ++#define SYSHUB_DATA__DATA__SHIFT 0x0 ++ ++ ++// addressBlock: rcc_strap_rcc_strap_internal ++//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x1 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x2 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x3 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x4 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x5 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f ++//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10 ++//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT 0x6 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x11 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x13 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d ++//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0__SHIFT 0x1e ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f ++//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18 ++//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT 0x1e ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f ++//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1 ++//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d ++//RCC_DEV1_PORT_STRAP0 ++#define RCC_DEV1_PORT_STRAP0__STRAP_ARI_EN_DN_DEV1__SHIFT 0x1 ++#define RCC_DEV1_PORT_STRAP0__STRAP_ACS_EN_DN_DEV1__SHIFT 0x2 ++#define RCC_DEV1_PORT_STRAP0__STRAP_AER_EN_DN_DEV1__SHIFT 0x3 ++#define RCC_DEV1_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV1__SHIFT 0x4 ++#define RCC_DEV1_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV1__SHIFT 0x5 ++#define RCC_DEV1_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV1__SHIFT 0x15 ++#define RCC_DEV1_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV1__SHIFT 0x18 ++#define RCC_DEV1_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV1__SHIFT 0x19 ++#define RCC_DEV1_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV1__SHIFT 0x1c ++#define RCC_DEV1_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV1__SHIFT 0x1f ++//RCC_DEV1_PORT_STRAP1 ++#define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV1__SHIFT 0x0 ++#define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV1__SHIFT 0x10 ++//RCC_DEV1_PORT_STRAP2 ++#define RCC_DEV1_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV1__SHIFT 0x0 ++#define RCC_DEV1_PORT_STRAP2__STRAP_DSN_EN_DN_DEV1__SHIFT 0x1 ++#define RCC_DEV1_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV1__SHIFT 0x2 ++#define RCC_DEV1_PORT_STRAP2__STRAP_ECN1P1_EN_DEV1__SHIFT 0x3 ++#define RCC_DEV1_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV1__SHIFT 0x4 ++#define RCC_DEV1_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV1__SHIFT 0x5 ++#define RCC_DEV1_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV1__SHIFT 0x6 ++#define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV1__SHIFT 0x7 ++#define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV1__SHIFT 0x8 ++#define RCC_DEV1_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV1__SHIFT 0x9 ++#define RCC_DEV1_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV1__SHIFT 0xc ++#define RCC_DEV1_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV1__SHIFT 0xd ++#define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV1__SHIFT 0xe ++#define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_EN_DEV1__SHIFT 0xf ++#define RCC_DEV1_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV1__SHIFT 0x10 ++#define RCC_DEV1_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV1__SHIFT 0x11 ++#define RCC_DEV1_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV1__SHIFT 0x13 ++#define RCC_DEV1_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV1__SHIFT 0x14 ++#define RCC_DEV1_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV1__SHIFT 0x17 ++#define RCC_DEV1_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV1__SHIFT 0x1a ++#define RCC_DEV1_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV1__SHIFT 0x1d ++//RCC_DEV1_PORT_STRAP3 ++#define RCC_DEV1_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV1__SHIFT 0x0 ++#define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DEV1__SHIFT 0x1 ++#define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DN_DEV1__SHIFT 0x2 ++#define RCC_DEV1_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV1__SHIFT 0x3 ++#define RCC_DEV1_PORT_STRAP3__STRAP_MSI_EN_DN_DEV1__SHIFT 0x6 ++#define RCC_DEV1_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV1__SHIFT 0x7 ++#define RCC_DEV1_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV1__SHIFT 0x8 ++#define RCC_DEV1_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV1__SHIFT 0x9 ++#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV1__SHIFT 0xb ++#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV1__SHIFT 0xe ++#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV1__SHIFT 0x12 ++#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV1__SHIFT 0x15 ++#define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DEV1__SHIFT 0x19 ++#define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV1__SHIFT 0x1b ++#define RCC_DEV1_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV1__SHIFT 0x1d ++#define RCC_DEV1_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV1__SHIFT 0x1e ++#define RCC_DEV1_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV1__SHIFT 0x1f ++//RCC_DEV1_PORT_STRAP4 ++#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV1__SHIFT 0x0 ++#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV1__SHIFT 0x8 ++#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV1__SHIFT 0x10 ++#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV1__SHIFT 0x18 ++//RCC_DEV1_PORT_STRAP5 ++#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV1__SHIFT 0x0 ++#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV1__SHIFT 0x8 ++#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV1__SHIFT 0x10 ++#define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV1__SHIFT 0x11 ++#define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV1__SHIFT 0x12 ++#define RCC_DEV1_PORT_STRAP5__STRAP_VC_EN_DN_DEV1__SHIFT 0x13 ++#define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DEV1__SHIFT 0x14 ++#define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV1__SHIFT 0x15 ++#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV1__SHIFT 0x17 ++#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV1__SHIFT 0x18 ++#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV1__SHIFT 0x19 ++#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV1__SHIFT 0x1a ++#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV1__SHIFT 0x1b ++#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV1__SHIFT 0x1c ++#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV1__SHIFT 0x1d ++#define RCC_DEV1_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV1__SHIFT 0x1e ++#define RCC_DEV1_PORT_STRAP5__STRAP_SSID_EN_DEV1__SHIFT 0x1f ++//RCC_DEV1_PORT_STRAP6 ++#define RCC_DEV1_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV1__SHIFT 0x0 ++#define RCC_DEV1_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV1__SHIFT 0x1 ++//RCC_DEV1_PORT_STRAP7 ++#define RCC_DEV1_PORT_STRAP7__STRAP_PORT_NUMBER_DEV1__SHIFT 0x0 ++#define RCC_DEV1_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV1__SHIFT 0x8 ++#define RCC_DEV1_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV1__SHIFT 0xc ++#define RCC_DEV1_PORT_STRAP7__STRAP_RP_BUSNUM_DEV1__SHIFT 0x10 ++#define RCC_DEV1_PORT_STRAP7__STRAP_DN_DEVNUM_DEV1__SHIFT 0x18 ++#define RCC_DEV1_PORT_STRAP7__STRAP_DN_FUNCID_DEV1__SHIFT 0x1d ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10 ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x1 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x0 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x1 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x2 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0__SHIFT 0x19 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_MSIX_TABLE_OFFSET_DEV0_F0__SHIFT 0x0 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT 0x1f ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0 ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x0 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x1 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x4 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x5 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0x9 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xc ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0xe ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x10 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x13 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x16 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT 0x18 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x19 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x1a ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP9 ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10 ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT 0x12 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT 0x16 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT 0x17 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18 ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x0 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x1 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x2 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1__SHIFT 0x19 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x1f ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0 ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT 0x0 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x1 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT 0x2 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1__SHIFT 0x4 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__SHIFT 0x8 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x9 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__SHIFT 0x10 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x11 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__SHIFT 0x18 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x19 ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1__SHIFT 0x0 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1__SHIFT 0x1 ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1__SHIFT 0x0 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1 ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1__SHIFT 0x0 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1 ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1__SHIFT 0x0 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1 ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT 0x0 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT 0x8 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT 0x10 ++//RCC_DEV0_EPF2_STRAP0 ++#define RCC_DEV0_EPF2_STRAP0__STRAP_DEVICE_ID_DEV0_F2__SHIFT 0x0 ++#define RCC_DEV0_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F2__SHIFT 0x10 ++#define RCC_DEV0_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV0_F2__SHIFT 0x14 ++#define RCC_DEV0_EPF2_STRAP0__STRAP_FUNC_EN_DEV0_F2__SHIFT 0x1c ++#define RCC_DEV0_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F2__SHIFT 0x1d ++#define RCC_DEV0_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV0_F2__SHIFT 0x1e ++#define RCC_DEV0_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV0_F2__SHIFT 0x1f ++//RCC_DEV0_EPF2_STRAP2 ++#define RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2__SHIFT 0x7 ++#define RCC_DEV0_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F2__SHIFT 0x8 ++#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2__SHIFT 0xe ++#define RCC_DEV0_EPF2_STRAP2__STRAP_AER_EN_DEV0_F2__SHIFT 0x10 ++#define RCC_DEV0_EPF2_STRAP2__STRAP_ACS_EN_DEV0_F2__SHIFT 0x11 ++#define RCC_DEV0_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F2__SHIFT 0x14 ++#define RCC_DEV0_EPF2_STRAP2__STRAP_DPA_EN_DEV0_F2__SHIFT 0x15 ++#define RCC_DEV0_EPF2_STRAP2__STRAP_VC_EN_DEV0_F2__SHIFT 0x17 ++#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F2__SHIFT 0x18 ++//RCC_DEV0_EPF2_STRAP3 ++#define RCC_DEV0_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F2__SHIFT 0x0 ++#define RCC_DEV0_EPF2_STRAP3__STRAP_PWR_EN_DEV0_F2__SHIFT 0x1 ++#define RCC_DEV0_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV0_F2__SHIFT 0x2 ++#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_EN_DEV0_F2__SHIFT 0x12 ++#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F2__SHIFT 0x13 ++#define RCC_DEV0_EPF2_STRAP3__STRAP_MSIX_EN_DEV0_F2__SHIFT 0x14 ++#define RCC_DEV0_EPF2_STRAP3__STRAP_PMC_DSI_DEV0_F2__SHIFT 0x18 ++#define RCC_DEV0_EPF2_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F2__SHIFT 0x19 ++#define RCC_DEV0_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F2__SHIFT 0x1a ++#define RCC_DEV0_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F2__SHIFT 0x1b ++//RCC_DEV0_EPF2_STRAP4 ++#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F2__SHIFT 0x14 ++#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV0_F2__SHIFT 0x15 ++#define RCC_DEV0_EPF2_STRAP4__STRAP_FLR_EN_DEV0_F2__SHIFT 0x16 ++#define RCC_DEV0_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV0_F2__SHIFT 0x17 ++#define RCC_DEV0_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F2__SHIFT 0x1c ++#define RCC_DEV0_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F2__SHIFT 0x1f ++//RCC_DEV0_EPF2_STRAP5 ++#define RCC_DEV0_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F2__SHIFT 0x0 ++#define RCC_DEV0_EPF2_STRAP5__STRAP_SATAIDP_EN_DEV0_F2__SHIFT 0x18 ++//RCC_DEV0_EPF2_STRAP6 ++#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_EN_DEV0_F2__SHIFT 0x0 ++#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F2__SHIFT 0x1 ++#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F2__SHIFT 0x4 ++#define RCC_DEV0_EPF2_STRAP6__STRAP_APER1_EN_DEV0_F2__SHIFT 0x8 ++#define RCC_DEV0_EPF2_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F2__SHIFT 0x9 ++//RCC_DEV0_EPF2_STRAP13 ++#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F2__SHIFT 0x0 ++#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F2__SHIFT 0x8 ++#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F2__SHIFT 0x10 ++//RCC_DEV0_EPF3_STRAP0 ++#define RCC_DEV0_EPF3_STRAP0__STRAP_DEVICE_ID_DEV0_F3__SHIFT 0x0 ++#define RCC_DEV0_EPF3_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F3__SHIFT 0x10 ++#define RCC_DEV0_EPF3_STRAP0__STRAP_MINOR_REV_ID_DEV0_F3__SHIFT 0x14 ++#define RCC_DEV0_EPF3_STRAP0__STRAP_FUNC_EN_DEV0_F3__SHIFT 0x1c ++#define RCC_DEV0_EPF3_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F3__SHIFT 0x1d ++#define RCC_DEV0_EPF3_STRAP0__STRAP_D1_SUPPORT_DEV0_F3__SHIFT 0x1e ++#define RCC_DEV0_EPF3_STRAP0__STRAP_D2_SUPPORT_DEV0_F3__SHIFT 0x1f ++//RCC_DEV0_EPF3_STRAP2 ++#define RCC_DEV0_EPF3_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F3__SHIFT 0x7 ++#define RCC_DEV0_EPF3_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F3__SHIFT 0x8 ++#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F3__SHIFT 0xe ++#define RCC_DEV0_EPF3_STRAP2__STRAP_AER_EN_DEV0_F3__SHIFT 0x10 ++#define RCC_DEV0_EPF3_STRAP2__STRAP_ACS_EN_DEV0_F3__SHIFT 0x11 ++#define RCC_DEV0_EPF3_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F3__SHIFT 0x14 ++#define RCC_DEV0_EPF3_STRAP2__STRAP_DPA_EN_DEV0_F3__SHIFT 0x15 ++#define RCC_DEV0_EPF3_STRAP2__STRAP_VC_EN_DEV0_F3__SHIFT 0x17 ++#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F3__SHIFT 0x18 ++//RCC_DEV0_EPF3_STRAP3 ++#define RCC_DEV0_EPF3_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F3__SHIFT 0x0 ++#define RCC_DEV0_EPF3_STRAP3__STRAP_PWR_EN_DEV0_F3__SHIFT 0x1 ++#define RCC_DEV0_EPF3_STRAP3__STRAP_SUBSYS_ID_DEV0_F3__SHIFT 0x2 ++#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_EN_DEV0_F3__SHIFT 0x12 ++#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F3__SHIFT 0x13 ++#define RCC_DEV0_EPF3_STRAP3__STRAP_MSIX_EN_DEV0_F3__SHIFT 0x14 ++#define RCC_DEV0_EPF3_STRAP3__STRAP_PMC_DSI_DEV0_F3__SHIFT 0x18 ++#define RCC_DEV0_EPF3_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F3__SHIFT 0x19 ++#define RCC_DEV0_EPF3_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F3__SHIFT 0x1a ++#define RCC_DEV0_EPF3_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F3__SHIFT 0x1b ++//RCC_DEV0_EPF3_STRAP4 ++#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F3__SHIFT 0x14 ++#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_EN_DEV0_F3__SHIFT 0x15 ++#define RCC_DEV0_EPF3_STRAP4__STRAP_FLR_EN_DEV0_F3__SHIFT 0x16 ++#define RCC_DEV0_EPF3_STRAP4__STRAP_PME_SUPPORT_DEV0_F3__SHIFT 0x17 ++#define RCC_DEV0_EPF3_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F3__SHIFT 0x1c ++#define RCC_DEV0_EPF3_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F3__SHIFT 0x1f ++//RCC_DEV0_EPF3_STRAP5 ++#define RCC_DEV0_EPF3_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F3__SHIFT 0x0 ++#define RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESEL_DEV0_F3__SHIFT 0x10 ++#define RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESELD_DEV0_F3__SHIFT 0x14 ++//RCC_DEV0_EPF3_STRAP6 ++#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_EN_DEV0_F3__SHIFT 0x0 ++#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F3__SHIFT 0x1 ++#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F3__SHIFT 0x4 ++//RCC_DEV0_EPF3_STRAP13 ++#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F3__SHIFT 0x0 ++#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F3__SHIFT 0x8 ++#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F3__SHIFT 0x10 ++//RCC_DEV0_EPF4_STRAP0 ++#define RCC_DEV0_EPF4_STRAP0__STRAP_DEVICE_ID_DEV0_F4__SHIFT 0x0 ++#define RCC_DEV0_EPF4_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F4__SHIFT 0x10 ++#define RCC_DEV0_EPF4_STRAP0__STRAP_MINOR_REV_ID_DEV0_F4__SHIFT 0x14 ++#define RCC_DEV0_EPF4_STRAP0__STRAP_FUNC_EN_DEV0_F4__SHIFT 0x1c ++#define RCC_DEV0_EPF4_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F4__SHIFT 0x1d ++#define RCC_DEV0_EPF4_STRAP0__STRAP_D1_SUPPORT_DEV0_F4__SHIFT 0x1e ++#define RCC_DEV0_EPF4_STRAP0__STRAP_D2_SUPPORT_DEV0_F4__SHIFT 0x1f ++//RCC_DEV0_EPF4_STRAP2 ++#define RCC_DEV0_EPF4_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F4__SHIFT 0x7 ++#define RCC_DEV0_EPF4_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F4__SHIFT 0x8 ++#define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F4__SHIFT 0xe ++#define RCC_DEV0_EPF4_STRAP2__STRAP_AER_EN_DEV0_F4__SHIFT 0x10 ++#define RCC_DEV0_EPF4_STRAP2__STRAP_ACS_EN_DEV0_F4__SHIFT 0x11 ++#define RCC_DEV0_EPF4_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F4__SHIFT 0x14 ++#define RCC_DEV0_EPF4_STRAP2__STRAP_DPA_EN_DEV0_F4__SHIFT 0x15 ++#define RCC_DEV0_EPF4_STRAP2__STRAP_VC_EN_DEV0_F4__SHIFT 0x17 ++#define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F4__SHIFT 0x18 ++//RCC_DEV0_EPF4_STRAP3 ++#define RCC_DEV0_EPF4_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F4__SHIFT 0x0 ++#define RCC_DEV0_EPF4_STRAP3__STRAP_PWR_EN_DEV0_F4__SHIFT 0x1 ++#define RCC_DEV0_EPF4_STRAP3__STRAP_SUBSYS_ID_DEV0_F4__SHIFT 0x2 ++#define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_EN_DEV0_F4__SHIFT 0x12 ++#define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F4__SHIFT 0x13 ++#define RCC_DEV0_EPF4_STRAP3__STRAP_MSIX_EN_DEV0_F4__SHIFT 0x14 ++#define RCC_DEV0_EPF4_STRAP3__STRAP_PMC_DSI_DEV0_F4__SHIFT 0x18 ++#define RCC_DEV0_EPF4_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F4__SHIFT 0x19 ++#define RCC_DEV0_EPF4_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F4__SHIFT 0x1a ++#define RCC_DEV0_EPF4_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F4__SHIFT 0x1b ++//RCC_DEV0_EPF4_STRAP4 ++#define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F4__SHIFT 0x14 ++#define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_EN_DEV0_F4__SHIFT 0x15 ++#define RCC_DEV0_EPF4_STRAP4__STRAP_FLR_EN_DEV0_F4__SHIFT 0x16 ++#define RCC_DEV0_EPF4_STRAP4__STRAP_PME_SUPPORT_DEV0_F4__SHIFT 0x17 ++#define RCC_DEV0_EPF4_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F4__SHIFT 0x1c ++#define RCC_DEV0_EPF4_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F4__SHIFT 0x1f ++//RCC_DEV0_EPF4_STRAP5 ++#define RCC_DEV0_EPF4_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F4__SHIFT 0x0 ++#define RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESEL_DEV0_F4__SHIFT 0x10 ++#define RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESELD_DEV0_F4__SHIFT 0x14 ++//RCC_DEV0_EPF4_STRAP6 ++#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_EN_DEV0_F4__SHIFT 0x0 ++#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F4__SHIFT 0x1 ++#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F4__SHIFT 0x4 ++#define RCC_DEV0_EPF4_STRAP6__STRAP_APER1_EN_DEV0_F4__SHIFT 0x8 ++#define RCC_DEV0_EPF4_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F4__SHIFT 0x9 ++#define RCC_DEV0_EPF4_STRAP6__STRAP_APER2_EN_DEV0_F4__SHIFT 0x10 ++#define RCC_DEV0_EPF4_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F4__SHIFT 0x11 ++//RCC_DEV0_EPF4_STRAP13 ++#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F4__SHIFT 0x0 ++#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F4__SHIFT 0x8 ++#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F4__SHIFT 0x10 ++//RCC_DEV0_EPF5_STRAP0 ++#define RCC_DEV0_EPF5_STRAP0__STRAP_DEVICE_ID_DEV0_F5__SHIFT 0x0 ++#define RCC_DEV0_EPF5_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F5__SHIFT 0x10 ++#define RCC_DEV0_EPF5_STRAP0__STRAP_MINOR_REV_ID_DEV0_F5__SHIFT 0x14 ++#define RCC_DEV0_EPF5_STRAP0__STRAP_FUNC_EN_DEV0_F5__SHIFT 0x1c ++#define RCC_DEV0_EPF5_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F5__SHIFT 0x1d ++#define RCC_DEV0_EPF5_STRAP0__STRAP_D1_SUPPORT_DEV0_F5__SHIFT 0x1e ++#define RCC_DEV0_EPF5_STRAP0__STRAP_D2_SUPPORT_DEV0_F5__SHIFT 0x1f ++//RCC_DEV0_EPF5_STRAP2 ++#define RCC_DEV0_EPF5_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F5__SHIFT 0x7 ++#define RCC_DEV0_EPF5_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F5__SHIFT 0x8 ++#define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F5__SHIFT 0xe ++#define RCC_DEV0_EPF5_STRAP2__STRAP_AER_EN_DEV0_F5__SHIFT 0x10 ++#define RCC_DEV0_EPF5_STRAP2__STRAP_ACS_EN_DEV0_F5__SHIFT 0x11 ++#define RCC_DEV0_EPF5_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F5__SHIFT 0x14 ++#define RCC_DEV0_EPF5_STRAP2__STRAP_DPA_EN_DEV0_F5__SHIFT 0x15 ++#define RCC_DEV0_EPF5_STRAP2__STRAP_VC_EN_DEV0_F5__SHIFT 0x17 ++#define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F5__SHIFT 0x18 ++//RCC_DEV0_EPF5_STRAP3 ++#define RCC_DEV0_EPF5_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F5__SHIFT 0x0 ++#define RCC_DEV0_EPF5_STRAP3__STRAP_PWR_EN_DEV0_F5__SHIFT 0x1 ++#define RCC_DEV0_EPF5_STRAP3__STRAP_SUBSYS_ID_DEV0_F5__SHIFT 0x2 ++#define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_EN_DEV0_F5__SHIFT 0x12 ++#define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F5__SHIFT 0x13 ++#define RCC_DEV0_EPF5_STRAP3__STRAP_MSIX_EN_DEV0_F5__SHIFT 0x14 ++#define RCC_DEV0_EPF5_STRAP3__STRAP_PMC_DSI_DEV0_F5__SHIFT 0x18 ++#define RCC_DEV0_EPF5_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F5__SHIFT 0x19 ++#define RCC_DEV0_EPF5_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F5__SHIFT 0x1a ++#define RCC_DEV0_EPF5_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F5__SHIFT 0x1b ++//RCC_DEV0_EPF5_STRAP4 ++#define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F5__SHIFT 0x14 ++#define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_EN_DEV0_F5__SHIFT 0x15 ++#define RCC_DEV0_EPF5_STRAP4__STRAP_FLR_EN_DEV0_F5__SHIFT 0x16 ++#define RCC_DEV0_EPF5_STRAP4__STRAP_PME_SUPPORT_DEV0_F5__SHIFT 0x17 ++#define RCC_DEV0_EPF5_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F5__SHIFT 0x1c ++#define RCC_DEV0_EPF5_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F5__SHIFT 0x1f ++//RCC_DEV0_EPF5_STRAP5 ++#define RCC_DEV0_EPF5_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F5__SHIFT 0x0 ++//RCC_DEV0_EPF5_STRAP6 ++#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_EN_DEV0_F5__SHIFT 0x0 ++#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F5__SHIFT 0x1 ++#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F5__SHIFT 0x4 ++#define RCC_DEV0_EPF5_STRAP6__STRAP_APER1_EN_DEV0_F5__SHIFT 0x8 ++#define RCC_DEV0_EPF5_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F5__SHIFT 0x9 ++#define RCC_DEV0_EPF5_STRAP6__STRAP_APER2_EN_DEV0_F5__SHIFT 0x10 ++#define RCC_DEV0_EPF5_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F5__SHIFT 0x11 ++//RCC_DEV0_EPF5_STRAP13 ++#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F5__SHIFT 0x0 ++#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F5__SHIFT 0x8 ++#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F5__SHIFT 0x10 ++//RCC_DEV0_EPF6_STRAP0 ++#define RCC_DEV0_EPF6_STRAP0__STRAP_DEVICE_ID_DEV0_F6__SHIFT 0x0 ++#define RCC_DEV0_EPF6_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F6__SHIFT 0x10 ++#define RCC_DEV0_EPF6_STRAP0__STRAP_MINOR_REV_ID_DEV0_F6__SHIFT 0x14 ++#define RCC_DEV0_EPF6_STRAP0__STRAP_FUNC_EN_DEV0_F6__SHIFT 0x1c ++#define RCC_DEV0_EPF6_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F6__SHIFT 0x1d ++#define RCC_DEV0_EPF6_STRAP0__STRAP_D1_SUPPORT_DEV0_F6__SHIFT 0x1e ++#define RCC_DEV0_EPF6_STRAP0__STRAP_D2_SUPPORT_DEV0_F6__SHIFT 0x1f ++//RCC_DEV0_EPF6_STRAP2 ++#define RCC_DEV0_EPF6_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F6__SHIFT 0x7 ++#define RCC_DEV0_EPF6_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F6__SHIFT 0x8 ++#define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F6__SHIFT 0xe ++#define RCC_DEV0_EPF6_STRAP2__STRAP_AER_EN_DEV0_F6__SHIFT 0x10 ++#define RCC_DEV0_EPF6_STRAP2__STRAP_ACS_EN_DEV0_F6__SHIFT 0x11 ++#define RCC_DEV0_EPF6_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F6__SHIFT 0x14 ++#define RCC_DEV0_EPF6_STRAP2__STRAP_DPA_EN_DEV0_F6__SHIFT 0x15 ++#define RCC_DEV0_EPF6_STRAP2__STRAP_VC_EN_DEV0_F6__SHIFT 0x17 ++#define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F6__SHIFT 0x18 ++//RCC_DEV0_EPF6_STRAP3 ++#define RCC_DEV0_EPF6_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F6__SHIFT 0x0 ++#define RCC_DEV0_EPF6_STRAP3__STRAP_PWR_EN_DEV0_F6__SHIFT 0x1 ++#define RCC_DEV0_EPF6_STRAP3__STRAP_SUBSYS_ID_DEV0_F6__SHIFT 0x2 ++#define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_EN_DEV0_F6__SHIFT 0x12 ++#define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F6__SHIFT 0x13 ++#define RCC_DEV0_EPF6_STRAP3__STRAP_MSIX_EN_DEV0_F6__SHIFT 0x14 ++#define RCC_DEV0_EPF6_STRAP3__STRAP_PMC_DSI_DEV0_F6__SHIFT 0x18 ++#define RCC_DEV0_EPF6_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F6__SHIFT 0x19 ++#define RCC_DEV0_EPF6_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F6__SHIFT 0x1a ++#define RCC_DEV0_EPF6_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F6__SHIFT 0x1b ++//RCC_DEV0_EPF6_STRAP4 ++#define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F6__SHIFT 0x14 ++#define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_EN_DEV0_F6__SHIFT 0x15 ++#define RCC_DEV0_EPF6_STRAP4__STRAP_FLR_EN_DEV0_F6__SHIFT 0x16 ++#define RCC_DEV0_EPF6_STRAP4__STRAP_PME_SUPPORT_DEV0_F6__SHIFT 0x17 ++#define RCC_DEV0_EPF6_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F6__SHIFT 0x1c ++#define RCC_DEV0_EPF6_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F6__SHIFT 0x1f ++//RCC_DEV0_EPF6_STRAP5 ++#define RCC_DEV0_EPF6_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F6__SHIFT 0x0 ++//RCC_DEV0_EPF6_STRAP6 ++#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_EN_DEV0_F6__SHIFT 0x0 ++#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F6__SHIFT 0x1 ++#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F6__SHIFT 0x4 ++#define RCC_DEV0_EPF6_STRAP6__STRAP_APER1_EN_DEV0_F6__SHIFT 0x8 ++#define RCC_DEV0_EPF6_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F6__SHIFT 0x9 ++#define RCC_DEV0_EPF6_STRAP6__STRAP_APER2_EN_DEV0_F6__SHIFT 0x10 ++#define RCC_DEV0_EPF6_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F6__SHIFT 0x11 ++//RCC_DEV0_EPF6_STRAP13 ++#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F6__SHIFT 0x0 ++#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F6__SHIFT 0x8 ++#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F6__SHIFT 0x10 ++//RCC_DEV0_EPF7_STRAP0 ++#define RCC_DEV0_EPF7_STRAP0__STRAP_DEVICE_ID_DEV0_F7__SHIFT 0x0 ++#define RCC_DEV0_EPF7_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F7__SHIFT 0x10 ++#define RCC_DEV0_EPF7_STRAP0__STRAP_MINOR_REV_ID_DEV0_F7__SHIFT 0x14 ++#define RCC_DEV0_EPF7_STRAP0__STRAP_FUNC_EN_DEV0_F7__SHIFT 0x1c ++#define RCC_DEV0_EPF7_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F7__SHIFT 0x1d ++#define RCC_DEV0_EPF7_STRAP0__STRAP_D1_SUPPORT_DEV0_F7__SHIFT 0x1e ++#define RCC_DEV0_EPF7_STRAP0__STRAP_D2_SUPPORT_DEV0_F7__SHIFT 0x1f ++//RCC_DEV0_EPF7_STRAP2 ++#define RCC_DEV0_EPF7_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F7__SHIFT 0x7 ++#define RCC_DEV0_EPF7_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F7__SHIFT 0x8 ++#define RCC_DEV0_EPF7_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F7__SHIFT 0xe ++#define RCC_DEV0_EPF7_STRAP2__STRAP_AER_EN_DEV0_F7__SHIFT 0x10 ++#define RCC_DEV0_EPF7_STRAP2__STRAP_ACS_EN_DEV0_F7__SHIFT 0x11 ++#define RCC_DEV0_EPF7_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F7__SHIFT 0x14 ++#define RCC_DEV0_EPF7_STRAP2__STRAP_DPA_EN_DEV0_F7__SHIFT 0x15 ++#define RCC_DEV0_EPF7_STRAP2__STRAP_VC_EN_DEV0_F7__SHIFT 0x17 ++#define RCC_DEV0_EPF7_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F7__SHIFT 0x18 ++//RCC_DEV0_EPF7_STRAP3 ++#define RCC_DEV0_EPF7_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F7__SHIFT 0x0 ++#define RCC_DEV0_EPF7_STRAP3__STRAP_PWR_EN_DEV0_F7__SHIFT 0x1 ++#define RCC_DEV0_EPF7_STRAP3__STRAP_SUBSYS_ID_DEV0_F7__SHIFT 0x2 ++#define RCC_DEV0_EPF7_STRAP3__STRAP_MSI_EN_DEV0_F7__SHIFT 0x12 ++#define RCC_DEV0_EPF7_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F7__SHIFT 0x13 ++#define RCC_DEV0_EPF7_STRAP3__STRAP_MSIX_EN_DEV0_F7__SHIFT 0x14 ++#define RCC_DEV0_EPF7_STRAP3__STRAP_PMC_DSI_DEV0_F7__SHIFT 0x18 ++#define RCC_DEV0_EPF7_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F7__SHIFT 0x19 ++#define RCC_DEV0_EPF7_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F7__SHIFT 0x1a ++#define RCC_DEV0_EPF7_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F7__SHIFT 0x1b ++//RCC_DEV0_EPF7_STRAP4 ++#define RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F7__SHIFT 0x14 ++#define RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_EN_DEV0_F7__SHIFT 0x15 ++#define RCC_DEV0_EPF7_STRAP4__STRAP_FLR_EN_DEV0_F7__SHIFT 0x16 ++#define RCC_DEV0_EPF7_STRAP4__STRAP_PME_SUPPORT_DEV0_F7__SHIFT 0x17 ++#define RCC_DEV0_EPF7_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F7__SHIFT 0x1c ++#define RCC_DEV0_EPF7_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F7__SHIFT 0x1f ++//RCC_DEV0_EPF7_STRAP5 ++#define RCC_DEV0_EPF7_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F7__SHIFT 0x0 ++//RCC_DEV0_EPF7_STRAP6 ++#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_EN_DEV0_F7__SHIFT 0x0 ++#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F7__SHIFT 0x1 ++#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F7__SHIFT 0x4 ++#define RCC_DEV0_EPF7_STRAP6__STRAP_APER1_EN_DEV0_F7__SHIFT 0x8 ++#define RCC_DEV0_EPF7_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F7__SHIFT 0x9 ++#define RCC_DEV0_EPF7_STRAP6__STRAP_APER2_EN_DEV0_F7__SHIFT 0x10 ++#define RCC_DEV0_EPF7_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F7__SHIFT 0x11 ++//RCC_DEV0_EPF7_STRAP13 ++#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F7__SHIFT 0x0 ++#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F7__SHIFT 0x8 ++#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F7__SHIFT 0x10 ++//RCC_DEV1_EPF0_STRAP0 ++#define RCC_DEV1_EPF0_STRAP0__STRAP_DEVICE_ID_DEV1_F0__SHIFT 0x0 ++#define RCC_DEV1_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F0__SHIFT 0x10 ++#define RCC_DEV1_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV1_F0__SHIFT 0x14 ++#define RCC_DEV1_EPF0_STRAP0__STRAP_FUNC_EN_DEV1_F0__SHIFT 0x1c ++#define RCC_DEV1_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F0__SHIFT 0x1d ++#define RCC_DEV1_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV1_F0__SHIFT 0x1e ++#define RCC_DEV1_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV1_F0__SHIFT 0x1f ++//RCC_DEV1_EPF0_STRAP2 ++#define RCC_DEV1_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F0__SHIFT 0x7 ++#define RCC_DEV1_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F0__SHIFT 0x8 ++#define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F0__SHIFT 0xe ++#define RCC_DEV1_EPF0_STRAP2__STRAP_ARI_EN_DEV1_F0__SHIFT 0xf ++#define RCC_DEV1_EPF0_STRAP2__STRAP_AER_EN_DEV1_F0__SHIFT 0x10 ++#define RCC_DEV1_EPF0_STRAP2__STRAP_ACS_EN_DEV1_F0__SHIFT 0x11 ++#define RCC_DEV1_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F0__SHIFT 0x14 ++#define RCC_DEV1_EPF0_STRAP2__STRAP_DPA_EN_DEV1_F0__SHIFT 0x15 ++#define RCC_DEV1_EPF0_STRAP2__STRAP_VC_EN_DEV1_F0__SHIFT 0x17 ++#define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F0__SHIFT 0x18 ++//RCC_DEV1_EPF0_STRAP3 ++#define RCC_DEV1_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F0__SHIFT 0x0 ++#define RCC_DEV1_EPF0_STRAP3__STRAP_PWR_EN_DEV1_F0__SHIFT 0x1 ++#define RCC_DEV1_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV1_F0__SHIFT 0x2 ++#define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_EN_DEV1_F0__SHIFT 0x12 ++#define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F0__SHIFT 0x13 ++#define RCC_DEV1_EPF0_STRAP3__STRAP_MSIX_EN_DEV1_F0__SHIFT 0x14 ++#define RCC_DEV1_EPF0_STRAP3__STRAP_PMC_DSI_DEV1_F0__SHIFT 0x18 ++#define RCC_DEV1_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F0__SHIFT 0x19 ++#define RCC_DEV1_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F0__SHIFT 0x1a ++#define RCC_DEV1_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F0__SHIFT 0x1b ++//RCC_DEV1_EPF0_STRAP4 ++#define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F0__SHIFT 0x14 ++#define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV1_F0__SHIFT 0x15 ++#define RCC_DEV1_EPF0_STRAP4__STRAP_FLR_EN_DEV1_F0__SHIFT 0x16 ++#define RCC_DEV1_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV1_F0__SHIFT 0x17 ++#define RCC_DEV1_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F0__SHIFT 0x1c ++#define RCC_DEV1_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F0__SHIFT 0x1f ++//RCC_DEV1_EPF0_STRAP5 ++#define RCC_DEV1_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F0__SHIFT 0x0 ++#define RCC_DEV1_EPF0_STRAP5__STRAP_SATAIDP_EN_DEV1_F0__SHIFT 0x18 ++//RCC_DEV1_EPF0_STRAP6 ++#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_EN_DEV1_F0__SHIFT 0x0 ++#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F0__SHIFT 0x1 ++#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F0__SHIFT 0x4 ++//RCC_DEV1_EPF0_STRAP13 ++#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F0__SHIFT 0x0 ++#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F0__SHIFT 0x8 ++#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F0__SHIFT 0x10 ++//RCC_DEV1_EPF1_STRAP0 ++#define RCC_DEV1_EPF1_STRAP0__STRAP_DEVICE_ID_DEV1_F1__SHIFT 0x0 ++#define RCC_DEV1_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F1__SHIFT 0x10 ++#define RCC_DEV1_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV1_F1__SHIFT 0x14 ++#define RCC_DEV1_EPF1_STRAP0__STRAP_FUNC_EN_DEV1_F1__SHIFT 0x1c ++#define RCC_DEV1_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F1__SHIFT 0x1d ++#define RCC_DEV1_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV1_F1__SHIFT 0x1e ++#define RCC_DEV1_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV1_F1__SHIFT 0x1f ++//RCC_DEV1_EPF1_STRAP2 ++#define RCC_DEV1_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F1__SHIFT 0x7 ++#define RCC_DEV1_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F1__SHIFT 0x8 ++#define RCC_DEV1_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F1__SHIFT 0xe ++#define RCC_DEV1_EPF1_STRAP2__STRAP_AER_EN_DEV1_F1__SHIFT 0x10 ++#define RCC_DEV1_EPF1_STRAP2__STRAP_ACS_EN_DEV1_F1__SHIFT 0x11 ++#define RCC_DEV1_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F1__SHIFT 0x14 ++#define RCC_DEV1_EPF1_STRAP2__STRAP_DPA_EN_DEV1_F1__SHIFT 0x15 ++#define RCC_DEV1_EPF1_STRAP2__STRAP_VC_EN_DEV1_F1__SHIFT 0x17 ++#define RCC_DEV1_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F1__SHIFT 0x18 ++//RCC_DEV1_EPF1_STRAP3 ++#define RCC_DEV1_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F1__SHIFT 0x0 ++#define RCC_DEV1_EPF1_STRAP3__STRAP_PWR_EN_DEV1_F1__SHIFT 0x1 ++#define RCC_DEV1_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV1_F1__SHIFT 0x2 ++#define RCC_DEV1_EPF1_STRAP3__STRAP_MSI_EN_DEV1_F1__SHIFT 0x12 ++#define RCC_DEV1_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F1__SHIFT 0x13 ++#define RCC_DEV1_EPF1_STRAP3__STRAP_MSIX_EN_DEV1_F1__SHIFT 0x14 ++#define RCC_DEV1_EPF1_STRAP3__STRAP_PMC_DSI_DEV1_F1__SHIFT 0x18 ++#define RCC_DEV1_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F1__SHIFT 0x19 ++#define RCC_DEV1_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F1__SHIFT 0x1a ++#define RCC_DEV1_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F1__SHIFT 0x1b ++//RCC_DEV1_EPF1_STRAP4 ++#define RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F1__SHIFT 0x14 ++#define RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV1_F1__SHIFT 0x15 ++#define RCC_DEV1_EPF1_STRAP4__STRAP_FLR_EN_DEV1_F1__SHIFT 0x16 ++#define RCC_DEV1_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV1_F1__SHIFT 0x17 ++#define RCC_DEV1_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F1__SHIFT 0x1c ++#define RCC_DEV1_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F1__SHIFT 0x1f ++//RCC_DEV1_EPF1_STRAP5 ++#define RCC_DEV1_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F1__SHIFT 0x0 ++//RCC_DEV1_EPF1_STRAP6 ++#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_EN_DEV1_F1__SHIFT 0x0 ++#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F1__SHIFT 0x1 ++#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F1__SHIFT 0x4 ++#define RCC_DEV1_EPF1_STRAP6__STRAP_APER1_EN_DEV1_F1__SHIFT 0x8 ++#define RCC_DEV1_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV1_F1__SHIFT 0x9 ++#define RCC_DEV1_EPF1_STRAP6__STRAP_APER2_EN_DEV1_F1__SHIFT 0x10 ++#define RCC_DEV1_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV1_F1__SHIFT 0x11 ++#define RCC_DEV1_EPF1_STRAP6__STRAP_APER3_EN_DEV1_F1__SHIFT 0x18 ++#define RCC_DEV1_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV1_F1__SHIFT 0x19 ++//RCC_DEV1_EPF1_STRAP13 ++#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F1__SHIFT 0x0 ++#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F1__SHIFT 0x8 ++#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F1__SHIFT 0x10 ++//RCC_DEV1_EPF2_STRAP0 ++#define RCC_DEV1_EPF2_STRAP0__STRAP_DEVICE_ID_DEV1_F2__SHIFT 0x0 ++#define RCC_DEV1_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F2__SHIFT 0x10 ++#define RCC_DEV1_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV1_F2__SHIFT 0x14 ++#define RCC_DEV1_EPF2_STRAP0__STRAP_FUNC_EN_DEV1_F2__SHIFT 0x1c ++#define RCC_DEV1_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F2__SHIFT 0x1d ++#define RCC_DEV1_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV1_F2__SHIFT 0x1e ++#define RCC_DEV1_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV1_F2__SHIFT 0x1f ++//RCC_DEV1_EPF2_STRAP2 ++#define RCC_DEV1_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F2__SHIFT 0x7 ++#define RCC_DEV1_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F2__SHIFT 0x8 ++#define RCC_DEV1_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F2__SHIFT 0xe ++#define RCC_DEV1_EPF2_STRAP2__STRAP_AER_EN_DEV1_F2__SHIFT 0x10 ++#define RCC_DEV1_EPF2_STRAP2__STRAP_ACS_EN_DEV1_F2__SHIFT 0x11 ++#define RCC_DEV1_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F2__SHIFT 0x14 ++#define RCC_DEV1_EPF2_STRAP2__STRAP_DPA_EN_DEV1_F2__SHIFT 0x15 ++#define RCC_DEV1_EPF2_STRAP2__STRAP_VC_EN_DEV1_F2__SHIFT 0x17 ++#define RCC_DEV1_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F2__SHIFT 0x18 ++//RCC_DEV1_EPF2_STRAP3 ++#define RCC_DEV1_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F2__SHIFT 0x0 ++#define RCC_DEV1_EPF2_STRAP3__STRAP_PWR_EN_DEV1_F2__SHIFT 0x1 ++#define RCC_DEV1_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV1_F2__SHIFT 0x2 ++#define RCC_DEV1_EPF2_STRAP3__STRAP_MSI_EN_DEV1_F2__SHIFT 0x12 ++#define RCC_DEV1_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F2__SHIFT 0x13 ++#define RCC_DEV1_EPF2_STRAP3__STRAP_MSIX_EN_DEV1_F2__SHIFT 0x14 ++#define RCC_DEV1_EPF2_STRAP3__STRAP_PMC_DSI_DEV1_F2__SHIFT 0x18 ++#define RCC_DEV1_EPF2_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F2__SHIFT 0x19 ++#define RCC_DEV1_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F2__SHIFT 0x1a ++#define RCC_DEV1_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F2__SHIFT 0x1b ++//RCC_DEV1_EPF2_STRAP4 ++#define RCC_DEV1_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F2__SHIFT 0x14 ++#define RCC_DEV1_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV1_F2__SHIFT 0x15 ++#define RCC_DEV1_EPF2_STRAP4__STRAP_FLR_EN_DEV1_F2__SHIFT 0x16 ++#define RCC_DEV1_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV1_F2__SHIFT 0x17 ++#define RCC_DEV1_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F2__SHIFT 0x1c ++#define RCC_DEV1_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F2__SHIFT 0x1f ++//RCC_DEV1_EPF2_STRAP5 ++#define RCC_DEV1_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F2__SHIFT 0x0 ++//RCC_DEV1_EPF2_STRAP6 ++#define RCC_DEV1_EPF2_STRAP6__STRAP_APER0_EN_DEV1_F2__SHIFT 0x0 ++#define RCC_DEV1_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F2__SHIFT 0x1 ++#define RCC_DEV1_EPF2_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F2__SHIFT 0x4 ++#define RCC_DEV1_EPF2_STRAP6__STRAP_APER1_EN_DEV1_F2__SHIFT 0x8 ++#define RCC_DEV1_EPF2_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV1_F2__SHIFT 0x9 ++#define RCC_DEV1_EPF2_STRAP6__STRAP_APER2_EN_DEV1_F2__SHIFT 0x10 ++#define RCC_DEV1_EPF2_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV1_F2__SHIFT 0x11 ++#define RCC_DEV1_EPF2_STRAP6__STRAP_APER3_EN_DEV1_F2__SHIFT 0x18 ++#define RCC_DEV1_EPF2_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV1_F2__SHIFT 0x19 ++//RCC_DEV1_EPF2_STRAP13 ++#define RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F2__SHIFT 0x0 ++#define RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F2__SHIFT 0x8 ++#define RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F2__SHIFT 0x10 ++ ++ ++// addressBlock: bif_rst_bif_rst_regblk ++//HARD_RST_CTRL ++#define HARD_RST_CTRL__DSPT_CFG_RST_EN__SHIFT 0x0 ++#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT 0x1 ++#define HARD_RST_CTRL__DSPT_PRV_RST_EN__SHIFT 0x2 ++#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT 0x3 ++#define HARD_RST_CTRL__EP_CFG_RST_EN__SHIFT 0x4 ++#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT 0x5 ++#define HARD_RST_CTRL__EP_PRV_RST_EN__SHIFT 0x6 ++#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT 0x7 ++#define HARD_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT 0x1c ++#define HARD_RST_CTRL__CORE_STICKY_RST_EN__SHIFT 0x1d ++#define HARD_RST_CTRL__RELOAD_STRAP_EN__SHIFT 0x1e ++#define HARD_RST_CTRL__CORE_RST_EN__SHIFT 0x1f ++//RSMU_SOFT_RST_CTRL ++#define RSMU_SOFT_RST_CTRL__DSPT_CFG_RST_EN__SHIFT 0x0 ++#define RSMU_SOFT_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT 0x1 ++#define RSMU_SOFT_RST_CTRL__DSPT_PRV_RST_EN__SHIFT 0x2 ++#define RSMU_SOFT_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT 0x3 ++#define RSMU_SOFT_RST_CTRL__EP_CFG_RST_EN__SHIFT 0x4 ++#define RSMU_SOFT_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT 0x5 ++#define RSMU_SOFT_RST_CTRL__EP_PRV_RST_EN__SHIFT 0x6 ++#define RSMU_SOFT_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT 0x7 ++#define RSMU_SOFT_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT 0x1c ++#define RSMU_SOFT_RST_CTRL__CORE_STICKY_RST_EN__SHIFT 0x1d ++#define RSMU_SOFT_RST_CTRL__RELOAD_STRAP_EN__SHIFT 0x1e ++#define RSMU_SOFT_RST_CTRL__CORE_RST_EN__SHIFT 0x1f ++//SELF_SOFT_RST ++#define SELF_SOFT_RST__DSPT0_CFG_RST__SHIFT 0x0 ++#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST__SHIFT 0x1 ++#define SELF_SOFT_RST__DSPT0_PRV_RST__SHIFT 0x2 ++#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST__SHIFT 0x3 ++#define SELF_SOFT_RST__EP0_CFG_RST__SHIFT 0x4 ++#define SELF_SOFT_RST__EP0_CFG_STICKY_RST__SHIFT 0x5 ++#define SELF_SOFT_RST__EP0_PRV_RST__SHIFT 0x6 ++#define SELF_SOFT_RST__EP0_PRV_STICKY_RST__SHIFT 0x7 ++#define SELF_SOFT_RST__SDP_PORT_RST__SHIFT 0x1b ++#define SELF_SOFT_RST__SWUS_SHADOW_RST__SHIFT 0x1c ++#define SELF_SOFT_RST__CORE_STICKY_RST__SHIFT 0x1d ++#define SELF_SOFT_RST__RELOAD_STRAP__SHIFT 0x1e ++#define SELF_SOFT_RST__CORE_RST__SHIFT 0x1f ++//GFX_DRV_MODE1_RST_CTRL ++#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_RST__SHIFT 0x0 ++#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_FLR_EXC_RST__SHIFT 0x1 ++#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_STICKY_RST__SHIFT 0x2 ++#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_PRV_RST__SHIFT 0x3 ++#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_PRV_STICKY_RST__SHIFT 0x4 ++#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_CFG_RST__SHIFT 0x5 ++#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_CFG_STICKY_RST__SHIFT 0x6 ++#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_PRV_RST__SHIFT 0x7 ++//BIF_RST_MISC_CTRL ++#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB__SHIFT 0x0 ++#define BIF_RST_MISC_CTRL__DRV_RST_MODE__SHIFT 0x2 ++#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK__SHIFT 0x4 ++#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR__SHIFT 0x5 ++#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR__SHIFT 0x6 ++#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN__SHIFT 0x8 ++#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE__SHIFT 0x9 ++#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT__SHIFT 0xa ++#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL__SHIFT 0xd ++#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL__SHIFT 0xf ++#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT 0x11 ++#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS__SHIFT 0x17 ++#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS__SHIFT 0x18 ++//BIF_RST_MISC_CTRL2 ++#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE__SHIFT 0x10 ++#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE__SHIFT 0x11 ++#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE__SHIFT 0x12 ++#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE__SHIFT 0x1f ++//BIF_RST_MISC_CTRL3 ++#define BIF_RST_MISC_CTRL3__TIMER_SCALE__SHIFT 0x0 ++#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT__SHIFT 0x4 ++#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE__SHIFT 0x6 ++#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD__SHIFT 0x7 ++#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT__SHIFT 0xa ++#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF__SHIFT 0xd ++//BIF_RST_GFXVF_FLR_IDLE ++#define BIF_RST_GFXVF_FLR_IDLE__VF0_TRANS_IDLE__SHIFT 0x0 ++#define BIF_RST_GFXVF_FLR_IDLE__VF1_TRANS_IDLE__SHIFT 0x1 ++#define BIF_RST_GFXVF_FLR_IDLE__VF2_TRANS_IDLE__SHIFT 0x2 ++#define BIF_RST_GFXVF_FLR_IDLE__VF3_TRANS_IDLE__SHIFT 0x3 ++#define BIF_RST_GFXVF_FLR_IDLE__VF4_TRANS_IDLE__SHIFT 0x4 ++#define BIF_RST_GFXVF_FLR_IDLE__VF5_TRANS_IDLE__SHIFT 0x5 ++#define BIF_RST_GFXVF_FLR_IDLE__VF6_TRANS_IDLE__SHIFT 0x6 ++#define BIF_RST_GFXVF_FLR_IDLE__VF7_TRANS_IDLE__SHIFT 0x7 ++#define BIF_RST_GFXVF_FLR_IDLE__VF8_TRANS_IDLE__SHIFT 0x8 ++#define BIF_RST_GFXVF_FLR_IDLE__VF9_TRANS_IDLE__SHIFT 0x9 ++#define BIF_RST_GFXVF_FLR_IDLE__VF10_TRANS_IDLE__SHIFT 0xa ++#define BIF_RST_GFXVF_FLR_IDLE__VF11_TRANS_IDLE__SHIFT 0xb ++#define BIF_RST_GFXVF_FLR_IDLE__VF12_TRANS_IDLE__SHIFT 0xc ++#define BIF_RST_GFXVF_FLR_IDLE__VF13_TRANS_IDLE__SHIFT 0xd ++#define BIF_RST_GFXVF_FLR_IDLE__VF14_TRANS_IDLE__SHIFT 0xe ++#define BIF_RST_GFXVF_FLR_IDLE__VF15_TRANS_IDLE__SHIFT 0xf ++#define BIF_RST_GFXVF_FLR_IDLE__SOFTPF_TRANS_IDLE__SHIFT 0x1f ++//DEV0_PF0_FLR_RST_CTRL ++#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 ++#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 ++#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 ++#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 ++#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 ++#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN__SHIFT 0x5 ++#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN__SHIFT 0x6 ++#define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN__SHIFT 0x7 ++#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN__SHIFT 0x8 ++#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN__SHIFT 0x9 ++#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN__SHIFT 0xa ++#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN__SHIFT 0xb ++#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN__SHIFT 0xc ++#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN__SHIFT 0xd ++#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN__SHIFT 0xe ++#define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN__SHIFT 0xf ++#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN__SHIFT 0x10 ++#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 ++#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 ++#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 ++#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 ++//DEV0_PF1_FLR_RST_CTRL ++#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 ++#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 ++#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 ++#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 ++#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 ++#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 ++#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 ++#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 ++#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 ++//DEV0_PF2_FLR_RST_CTRL ++#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 ++#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 ++#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 ++#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 ++#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 ++#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 ++#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 ++#define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 ++#define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 ++//DEV0_PF3_FLR_RST_CTRL ++#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 ++#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 ++#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 ++#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 ++#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 ++#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 ++#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 ++#define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 ++#define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 ++//DEV0_PF4_FLR_RST_CTRL ++#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 ++#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 ++#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 ++#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 ++#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 ++#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 ++#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 ++#define DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 ++#define DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 ++//DEV0_PF5_FLR_RST_CTRL ++#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 ++#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 ++#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 ++#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 ++#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 ++#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 ++#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 ++#define DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 ++#define DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 ++//DEV0_PF6_FLR_RST_CTRL ++#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 ++#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 ++#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 ++#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 ++#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 ++#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 ++#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 ++#define DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 ++#define DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 ++//DEV0_PF7_FLR_RST_CTRL ++#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 ++#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 ++#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 ++#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 ++#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 ++#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 ++#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 ++#define DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 ++#define DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 ++//BIF_INST_RESET_INTR_STS ++#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS__SHIFT 0x0 ++#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT 0x1 ++#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS__SHIFT 0x2 ++#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS__SHIFT 0x3 ++#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS__SHIFT 0x4 ++//BIF_PF_FLR_INTR_STS ++#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS__SHIFT 0x0 ++#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS__SHIFT 0x1 ++#define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS__SHIFT 0x2 ++#define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS__SHIFT 0x3 ++#define BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS__SHIFT 0x4 ++#define BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS__SHIFT 0x5 ++#define BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS__SHIFT 0x6 ++#define BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS__SHIFT 0x7 ++//BIF_D3HOTD0_INTR_STS ++#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS__SHIFT 0x0 ++#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS__SHIFT 0x1 ++#define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS__SHIFT 0x2 ++#define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS__SHIFT 0x3 ++#define BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS__SHIFT 0x4 ++#define BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS__SHIFT 0x5 ++#define BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS__SHIFT 0x6 ++#define BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS__SHIFT 0x7 ++//BIF_POWER_INTR_STS ++#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS__SHIFT 0x0 ++#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS__SHIFT 0x10 ++//BIF_PF_DSTATE_INTR_STS ++#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS__SHIFT 0x0 ++#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS__SHIFT 0x1 ++#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS__SHIFT 0x2 ++#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS__SHIFT 0x3 ++#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS__SHIFT 0x4 ++#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS__SHIFT 0x5 ++#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS__SHIFT 0x6 ++#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS__SHIFT 0x7 ++//BIF_PF0_VF_FLR_INTR_STS ++#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF0_FLR_INTR_STS__SHIFT 0x0 ++#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF1_FLR_INTR_STS__SHIFT 0x1 ++#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF2_FLR_INTR_STS__SHIFT 0x2 ++#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF3_FLR_INTR_STS__SHIFT 0x3 ++#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF4_FLR_INTR_STS__SHIFT 0x4 ++#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF5_FLR_INTR_STS__SHIFT 0x5 ++#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF6_FLR_INTR_STS__SHIFT 0x6 ++#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF7_FLR_INTR_STS__SHIFT 0x7 ++#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF8_FLR_INTR_STS__SHIFT 0x8 ++#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF9_FLR_INTR_STS__SHIFT 0x9 ++#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF10_FLR_INTR_STS__SHIFT 0xa ++#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF11_FLR_INTR_STS__SHIFT 0xb ++#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF12_FLR_INTR_STS__SHIFT 0xc ++#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF13_FLR_INTR_STS__SHIFT 0xd ++#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF14_FLR_INTR_STS__SHIFT 0xe ++#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF15_FLR_INTR_STS__SHIFT 0xf ++#define BIF_PF0_VF_FLR_INTR_STS__PF0_SOFTPF_FLR_INTR_STS__SHIFT 0x1f ++//BIF_INST_RESET_INTR_MASK ++#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK__SHIFT 0x0 ++#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT 0x1 ++#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK__SHIFT 0x2 ++#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK__SHIFT 0x3 ++#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK__SHIFT 0x4 ++//BIF_PF_FLR_INTR_MASK ++#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK__SHIFT 0x0 ++#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK__SHIFT 0x1 ++#define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK__SHIFT 0x2 ++#define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK__SHIFT 0x3 ++#define BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK__SHIFT 0x4 ++#define BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK__SHIFT 0x5 ++#define BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK__SHIFT 0x6 ++#define BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK__SHIFT 0x7 ++//BIF_D3HOTD0_INTR_MASK ++#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK__SHIFT 0x0 ++#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK__SHIFT 0x1 ++#define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK__SHIFT 0x2 ++#define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK__SHIFT 0x3 ++#define BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK__SHIFT 0x4 ++#define BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK__SHIFT 0x5 ++#define BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK__SHIFT 0x6 ++#define BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK__SHIFT 0x7 ++//BIF_POWER_INTR_MASK ++#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK__SHIFT 0x0 ++#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__SHIFT 0x10 ++//BIF_PF_DSTATE_INTR_MASK ++#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK__SHIFT 0x0 ++#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK__SHIFT 0x1 ++#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK__SHIFT 0x2 ++#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK__SHIFT 0x3 ++#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK__SHIFT 0x4 ++#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK__SHIFT 0x5 ++#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK__SHIFT 0x6 ++#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK__SHIFT 0x7 ++//BIF_PF0_VF_FLR_INTR_MASK ++#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF0_FLR_INTR_MASK__SHIFT 0x0 ++#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF1_FLR_INTR_MASK__SHIFT 0x1 ++#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF2_FLR_INTR_MASK__SHIFT 0x2 ++#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF3_FLR_INTR_MASK__SHIFT 0x3 ++#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF4_FLR_INTR_MASK__SHIFT 0x4 ++#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF5_FLR_INTR_MASK__SHIFT 0x5 ++#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF6_FLR_INTR_MASK__SHIFT 0x6 ++#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF7_FLR_INTR_MASK__SHIFT 0x7 ++#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF8_FLR_INTR_MASK__SHIFT 0x8 ++#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF9_FLR_INTR_MASK__SHIFT 0x9 ++#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF10_FLR_INTR_MASK__SHIFT 0xa ++#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF11_FLR_INTR_MASK__SHIFT 0xb ++#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF12_FLR_INTR_MASK__SHIFT 0xc ++#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF13_FLR_INTR_MASK__SHIFT 0xd ++#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF14_FLR_INTR_MASK__SHIFT 0xe ++#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF15_FLR_INTR_MASK__SHIFT 0xf ++#define BIF_PF0_VF_FLR_INTR_MASK__PF0_SOFTPF_FLR_INTR_MASK__SHIFT 0x1f ++//BIF_PF_FLR_RST ++#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT 0x0 ++#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT 0x1 ++#define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST__SHIFT 0x2 ++#define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST__SHIFT 0x3 ++#define BIF_PF_FLR_RST__DEV0_PF4_FLR_RST__SHIFT 0x4 ++#define BIF_PF_FLR_RST__DEV0_PF5_FLR_RST__SHIFT 0x5 ++#define BIF_PF_FLR_RST__DEV0_PF6_FLR_RST__SHIFT 0x6 ++#define BIF_PF_FLR_RST__DEV0_PF7_FLR_RST__SHIFT 0x7 ++//BIF_PF0_VF_FLR_RST ++#define BIF_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__SHIFT 0x0 ++#define BIF_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__SHIFT 0x1 ++#define BIF_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__SHIFT 0x2 ++#define BIF_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__SHIFT 0x3 ++#define BIF_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__SHIFT 0x4 ++#define BIF_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__SHIFT 0x5 ++#define BIF_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__SHIFT 0x6 ++#define BIF_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__SHIFT 0x7 ++#define BIF_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__SHIFT 0x8 ++#define BIF_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__SHIFT 0x9 ++#define BIF_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__SHIFT 0xa ++#define BIF_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__SHIFT 0xb ++#define BIF_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__SHIFT 0xc ++#define BIF_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__SHIFT 0xd ++#define BIF_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__SHIFT 0xe ++#define BIF_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__SHIFT 0xf ++#define BIF_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__SHIFT 0x1f ++//BIF_DEV0_PF0_DSTATE_VALUE ++#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE__SHIFT 0x0 ++#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 ++#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE__SHIFT 0x10 ++//BIF_DEV0_PF1_DSTATE_VALUE ++#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE__SHIFT 0x0 ++#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 ++#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE__SHIFT 0x10 ++//BIF_DEV0_PF2_DSTATE_VALUE ++#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE__SHIFT 0x0 ++#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 ++#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE__SHIFT 0x10 ++//BIF_DEV0_PF3_DSTATE_VALUE ++#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE__SHIFT 0x0 ++#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 ++#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE__SHIFT 0x10 ++//BIF_DEV0_PF4_DSTATE_VALUE ++#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE__SHIFT 0x0 ++#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 ++#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE__SHIFT 0x10 ++//BIF_DEV0_PF5_DSTATE_VALUE ++#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE__SHIFT 0x0 ++#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 ++#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE__SHIFT 0x10 ++//BIF_DEV0_PF6_DSTATE_VALUE ++#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE__SHIFT 0x0 ++#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 ++#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE__SHIFT 0x10 ++//BIF_DEV0_PF7_DSTATE_VALUE ++#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE__SHIFT 0x0 ++#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 ++#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE__SHIFT 0x10 ++//DEV0_PF0_D3HOTD0_RST_CTRL ++#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 ++#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 ++#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 ++#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 ++#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 ++//DEV0_PF1_D3HOTD0_RST_CTRL ++#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 ++#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 ++#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 ++#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 ++#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 ++//DEV0_PF2_D3HOTD0_RST_CTRL ++#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 ++#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 ++#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 ++#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 ++#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 ++//DEV0_PF3_D3HOTD0_RST_CTRL ++#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 ++#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 ++#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 ++#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 ++#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 ++//DEV0_PF4_D3HOTD0_RST_CTRL ++#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 ++#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 ++#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 ++#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 ++#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 ++//DEV0_PF5_D3HOTD0_RST_CTRL ++#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 ++#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 ++#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 ++#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 ++#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 ++//DEV0_PF6_D3HOTD0_RST_CTRL ++#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 ++#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 ++#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 ++#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 ++#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 ++//DEV0_PF7_D3HOTD0_RST_CTRL ++#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 ++#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 ++#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 ++#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 ++#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 ++//BIF_PORT0_DSTATE_VALUE ++#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE__SHIFT 0x0 ++#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE__SHIFT 0x10 ++ ++ ++// addressBlock: bif_misc_bif_misc_regblk ++//MISC_SCRATCH ++#define MISC_SCRATCH__MISC_SCRATCH0__SHIFT 0x0 ++//INTR_LINE_POLARITY ++#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0__SHIFT 0x0 ++//INTR_LINE_ENABLE ++#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0__SHIFT 0x0 ++//OUTSTANDING_VC_ALLOC ++#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC__SHIFT 0x0 ++#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC__SHIFT 0x2 ++#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC__SHIFT 0x4 ++#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC__SHIFT 0x6 ++#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC__SHIFT 0x8 ++#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC__SHIFT 0xa ++#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC__SHIFT 0xc ++#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC__SHIFT 0xe ++#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD__SHIFT 0x10 ++#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC__SHIFT 0x18 ++#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC__SHIFT 0x1a ++#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD__SHIFT 0x1c ++//BIFC_MISC_CTRL0 ++#define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN__SHIFT 0x0 ++#define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN__SHIFT 0x1 ++#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE__SHIFT 0x8 ++#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK__SHIFT 0x9 ++#define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK__SHIFT 0xa ++#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS__SHIFT 0x10 ++#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL__SHIFT 0x11 ++#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS__SHIFT 0x18 ++#define BIFC_MISC_CTRL0__VC7_DMA_IOCFG_DIS__SHIFT 0x19 ++#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS__SHIFT 0x1a ++#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE__SHIFT 0x1b ++#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE__SHIFT 0x1c ++#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION__SHIFT 0x1f ++//BIFC_MISC_CTRL1 ++#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT__SHIFT 0x0 ++#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT__SHIFT 0x1 ++#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT__SHIFT 0x2 ++#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT__SHIFT 0x3 ++#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS__SHIFT 0x4 ++#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR__SHIFT 0x5 ++#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS__SHIFT 0x6 ++#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL__SHIFT 0x7 ++#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS__SHIFT 0x8 ++#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS__SHIFT 0xa ++#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ__SHIFT 0xc ++#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE__SHIFT 0xd ++#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE__SHIFT 0xe ++#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1__SHIFT 0xf ++#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS__SHIFT 0x10 ++#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS__SHIFT 0x11 ++#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS__SHIFT 0x12 ++#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS__SHIFT 0x13 ++//BIFC_BME_ERR_LOG ++#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x0 ++#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x1 ++#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F2__SHIFT 0x2 ++#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F3__SHIFT 0x3 ++#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F4__SHIFT 0x4 ++#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F5__SHIFT 0x5 ++#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F6__SHIFT 0x6 ++#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F7__SHIFT 0x7 ++#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x10 ++#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x11 ++#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F2__SHIFT 0x12 ++#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F3__SHIFT 0x13 ++#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F4__SHIFT 0x14 ++#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F5__SHIFT 0x15 ++#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F6__SHIFT 0x16 ++#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F7__SHIFT 0x17 ++//BIFC_RCCBIH_BME_ERR_LOG ++#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x0 ++#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x1 ++#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT 0x2 ++#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT 0x3 ++#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT 0x4 ++#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT 0x5 ++#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT 0x6 ++#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT 0x7 ++#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x10 ++#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x11 ++#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT 0x12 ++#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT 0x13 ++#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT 0x14 ++#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT 0x15 ++#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT 0x16 ++#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT 0x17 ++//BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0__SHIFT 0x0 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0__SHIFT 0x2 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0__SHIFT 0x6 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0__SHIFT 0x8 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0__SHIFT 0xa ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0__SHIFT 0xc ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1__SHIFT 0x10 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1__SHIFT 0x12 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1__SHIFT 0x16 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1__SHIFT 0x18 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1__SHIFT 0x1a ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1__SHIFT 0x1c ++//BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2__SHIFT 0x0 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2__SHIFT 0x2 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2__SHIFT 0x6 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2__SHIFT 0x8 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2__SHIFT 0xa ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2__SHIFT 0xc ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3__SHIFT 0x10 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3__SHIFT 0x12 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3__SHIFT 0x16 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3__SHIFT 0x18 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3__SHIFT 0x1a ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3__SHIFT 0x1c ++//BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4__SHIFT 0x0 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4__SHIFT 0x2 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4__SHIFT 0x6 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4__SHIFT 0x8 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4__SHIFT 0xa ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4__SHIFT 0xc ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5__SHIFT 0x10 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5__SHIFT 0x12 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5__SHIFT 0x16 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5__SHIFT 0x18 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5__SHIFT 0x1a ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5__SHIFT 0x1c ++//BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6__SHIFT 0x0 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6__SHIFT 0x2 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6__SHIFT 0x6 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6__SHIFT 0x8 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6__SHIFT 0xa ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6__SHIFT 0xc ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7__SHIFT 0x10 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7__SHIFT 0x12 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7__SHIFT 0x16 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7__SHIFT 0x18 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7__SHIFT 0x1a ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7__SHIFT 0x1c ++//NBIF_VWIRE_CTRL ++#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT__SHIFT 0x4 ++#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED__SHIFT 0x8 ++#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT__SHIFT 0x14 ++#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL__SHIFT 0x1a ++//NBIF_SMN_VWR_VCHG_DIS_CTRL ++#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS__SHIFT 0x0 ++#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS__SHIFT 0x1 ++#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS__SHIFT 0x2 ++#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS__SHIFT 0x3 ++#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS__SHIFT 0x4 ++#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS__SHIFT 0x5 ++#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS__SHIFT 0x6 ++//NBIF_SMN_VWR_VCHG_RST_CTRL0 ++#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV__SHIFT 0x0 ++#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV__SHIFT 0x1 ++#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV__SHIFT 0x2 ++#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV__SHIFT 0x3 ++#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV__SHIFT 0x4 ++#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV__SHIFT 0x5 ++#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV__SHIFT 0x6 ++//NBIF_SMN_VWR_VCHG_TRIG ++#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG__SHIFT 0x0 ++#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG__SHIFT 0x1 ++#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG__SHIFT 0x2 ++#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG__SHIFT 0x3 ++#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG__SHIFT 0x4 ++#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG__SHIFT 0x5 ++#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG__SHIFT 0x6 ++//NBIF_SMN_VWR_WTRIG_CNTL ++#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS__SHIFT 0x0 ++#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS__SHIFT 0x1 ++#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS__SHIFT 0x2 ++#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS__SHIFT 0x3 ++#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS__SHIFT 0x4 ++#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS__SHIFT 0x5 ++#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS__SHIFT 0x6 ++//NBIF_SMN_VWR_VCHG_DIS_CTRL_1 ++#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV__SHIFT 0x0 ++#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV__SHIFT 0x1 ++#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV__SHIFT 0x2 ++#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV__SHIFT 0x3 ++#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV__SHIFT 0x4 ++#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV__SHIFT 0x5 ++#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV__SHIFT 0x6 ++//NBIF_MGCG_CTRL ++#define NBIF_MGCG_CTRL__NBIF_MGCG_EN__SHIFT 0x0 ++#define NBIF_MGCG_CTRL__NBIF_MGCG_MODE__SHIFT 0x1 ++#define NBIF_MGCG_CTRL__NBIF_MGCG_HYSTERESIS__SHIFT 0x2 ++//NBIF_DS_CTRL_LCLK ++#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN__SHIFT 0x0 ++#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER__SHIFT 0x10 ++//SMN_MST_CNTL0 ++#define SMN_MST_CNTL0__SMN_ARB_MODE__SHIFT 0x0 ++#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS__SHIFT 0x8 ++#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS__SHIFT 0x9 ++#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS__SHIFT 0xa ++#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS__SHIFT 0xb ++#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0__SHIFT 0x10 ++#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0__SHIFT 0x14 ++#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0__SHIFT 0x18 ++#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0__SHIFT 0x1c ++//SMN_MST_EP_CNTL1 ++#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0__SHIFT 0x0 ++#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1__SHIFT 0x1 ++#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2__SHIFT 0x2 ++#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3__SHIFT 0x3 ++#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4__SHIFT 0x4 ++#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5__SHIFT 0x5 ++#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6__SHIFT 0x6 ++#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7__SHIFT 0x7 ++//SMN_MST_EP_CNTL2 ++#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0__SHIFT 0x0 ++#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1__SHIFT 0x1 ++#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2__SHIFT 0x2 ++#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3__SHIFT 0x3 ++#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4__SHIFT 0x4 ++#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5__SHIFT 0x5 ++#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6__SHIFT 0x6 ++#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7__SHIFT 0x7 ++//NBIF_SDP_VWR_VCHG_DIS_CTRL ++#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS__SHIFT 0x0 ++#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS__SHIFT 0x1 ++#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS__SHIFT 0x2 ++#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS__SHIFT 0x3 ++#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS__SHIFT 0x4 ++#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS__SHIFT 0x5 ++#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS__SHIFT 0x6 ++#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS__SHIFT 0x7 ++#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS__SHIFT 0x18 ++//NBIF_SDP_VWR_VCHG_RST_CTRL0 ++#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN__SHIFT 0x0 ++#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN__SHIFT 0x1 ++#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN__SHIFT 0x2 ++#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN__SHIFT 0x3 ++#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN__SHIFT 0x4 ++#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN__SHIFT 0x5 ++#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN__SHIFT 0x6 ++#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN__SHIFT 0x7 ++#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN__SHIFT 0x18 ++//NBIF_SDP_VWR_VCHG_RST_CTRL1 ++#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL__SHIFT 0x0 ++#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL__SHIFT 0x1 ++#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL__SHIFT 0x2 ++#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL__SHIFT 0x3 ++#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL__SHIFT 0x4 ++#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL__SHIFT 0x5 ++#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL__SHIFT 0x6 ++#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL__SHIFT 0x7 ++#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL__SHIFT 0x18 ++//NBIF_SDP_VWR_VCHG_TRIG ++#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG__SHIFT 0x0 ++#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG__SHIFT 0x1 ++#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG__SHIFT 0x2 ++#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG__SHIFT 0x3 ++#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG__SHIFT 0x4 ++#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG__SHIFT 0x5 ++#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG__SHIFT 0x6 ++#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG__SHIFT 0x7 ++#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG__SHIFT 0x18 ++//BME_DUMMY_CNTL_0 ++#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0__SHIFT 0x0 ++#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1__SHIFT 0x2 ++#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2__SHIFT 0x4 ++#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3__SHIFT 0x6 ++#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4__SHIFT 0x8 ++#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5__SHIFT 0xa ++#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6__SHIFT 0xc ++#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7__SHIFT 0xe ++//BIFC_THT_CNTL ++#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0__SHIFT 0x0 ++#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0__SHIFT 0x4 ++#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1__SHIFT 0x8 ++//BIFC_HSTARB_CNTL ++#define BIFC_HSTARB_CNTL__SLVARB_MODE__SHIFT 0x0 ++//BIFC_GSI_CNTL ++#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE__SHIFT 0x0 ++#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE__SHIFT 0x2 ++#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN__SHIFT 0x5 ++#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN__SHIFT 0x6 ++#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN__SHIFT 0x7 ++#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN__SHIFT 0x8 ++#define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN__SHIFT 0x9 ++#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE__SHIFT 0xa ++#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE__SHIFT 0xc ++//BIFC_PCIEFUNC_CNTL ++#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC__SHIFT 0x0 ++#define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC__SHIFT 0x10 ++//BIFC_SDP_CNTL_0 ++#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS__SHIFT 0x0 ++#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS__SHIFT 0x6 ++#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS__SHIFT 0xc ++#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS__SHIFT 0x12 ++//BIFC_PERF_CNTL_0 ++#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN__SHIFT 0x0 ++#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN__SHIFT 0x1 ++#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET__SHIFT 0x8 ++#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET__SHIFT 0x9 ++#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL__SHIFT 0x10 ++#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL__SHIFT 0x18 ++//BIFC_PERF_CNTL_1 ++#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN__SHIFT 0x0 ++#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN__SHIFT 0x1 ++#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET__SHIFT 0x8 ++#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET__SHIFT 0x9 ++#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL__SHIFT 0x10 ++#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL__SHIFT 0x18 ++//BIFC_PERF_CNT_MMIO_RD ++#define BIFC_PERF_CNT_MMIO_RD__PERF_CNT_MMIO_RD_VALUE__SHIFT 0x0 ++//BIFC_PERF_CNT_MMIO_WR ++#define BIFC_PERF_CNT_MMIO_WR__PERF_CNT_MMIO_WR_VALUE__SHIFT 0x0 ++//BIFC_PERF_CNT_DMA_RD ++#define BIFC_PERF_CNT_DMA_RD__PERF_CNT_DMA_RD_VALUE__SHIFT 0x0 ++//BIFC_PERF_CNT_DMA_WR ++#define BIFC_PERF_CNT_DMA_WR__PERF_CNT_DMA_WR_VALUE__SHIFT 0x0 ++//NBIF_REGIF_ERRSET_CTRL ++#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0 ++//SMN_MST_EP_CNTL3 ++#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0__SHIFT 0x0 ++#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1__SHIFT 0x1 ++#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2__SHIFT 0x2 ++#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3__SHIFT 0x3 ++#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4__SHIFT 0x4 ++#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5__SHIFT 0x5 ++#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6__SHIFT 0x6 ++#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7__SHIFT 0x7 ++//SMN_MST_EP_CNTL4 ++#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0__SHIFT 0x0 ++#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1__SHIFT 0x1 ++#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2__SHIFT 0x2 ++#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3__SHIFT 0x3 ++#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4__SHIFT 0x4 ++#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5__SHIFT 0x5 ++#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6__SHIFT 0x6 ++#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7__SHIFT 0x7 ++//BIF_SELFRING_BUFFER_VID ++#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID__SHIFT 0x0 ++#define BIF_SELFRING_BUFFER_VID__IOHUB_RAS_INTR_CID__SHIFT 0x8 ++//BIF_SELFRING_VECTOR_CNTL ++#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS__SHIFT 0x0 ++ ++ ++// addressBlock: bif_ras_bif_ras_regblk ++//BIF_RAS_LEAF0_CTRL ++#define BIF_RAS_LEAF0_CTRL__POISON_DET_EN__SHIFT 0x0 ++#define BIF_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 ++#define BIF_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT 0x2 ++#define BIF_RAS_LEAF0_CTRL__PARITY_DET_EN__SHIFT 0x4 ++#define BIF_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 ++#define BIF_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT 0x6 ++#define BIF_RAS_LEAF0_CTRL__ERR_EVENT_RECV__SHIFT 0x10 ++#define BIF_RAS_LEAF0_CTRL__LINK_DIS_RECV__SHIFT 0x11 ++#define BIF_RAS_LEAF0_CTRL__POISON_ERR_DET__SHIFT 0x12 ++#define BIF_RAS_LEAF0_CTRL__PARITY_ERR_DET__SHIFT 0x13 ++#define BIF_RAS_LEAF0_CTRL__ERR_EVENT_SENT__SHIFT 0x14 ++#define BIF_RAS_LEAF0_CTRL__EGRESS_STALLED__SHIFT 0x15 ++//BIF_RAS_LEAF1_CTRL ++#define BIF_RAS_LEAF1_CTRL__POISON_DET_EN__SHIFT 0x0 ++#define BIF_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 ++#define BIF_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT 0x2 ++#define BIF_RAS_LEAF1_CTRL__PARITY_DET_EN__SHIFT 0x4 ++#define BIF_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 ++#define BIF_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT 0x6 ++#define BIF_RAS_LEAF1_CTRL__ERR_EVENT_RECV__SHIFT 0x10 ++#define BIF_RAS_LEAF1_CTRL__LINK_DIS_RECV__SHIFT 0x11 ++#define BIF_RAS_LEAF1_CTRL__POISON_ERR_DET__SHIFT 0x12 ++#define BIF_RAS_LEAF1_CTRL__PARITY_ERR_DET__SHIFT 0x13 ++#define BIF_RAS_LEAF1_CTRL__ERR_EVENT_SENT__SHIFT 0x14 ++#define BIF_RAS_LEAF1_CTRL__EGRESS_STALLED__SHIFT 0x15 ++//BIF_RAS_LEAF2_CTRL ++#define BIF_RAS_LEAF2_CTRL__POISON_DET_EN__SHIFT 0x0 ++#define BIF_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 ++#define BIF_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT 0x2 ++#define BIF_RAS_LEAF2_CTRL__PARITY_DET_EN__SHIFT 0x4 ++#define BIF_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 ++#define BIF_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT 0x6 ++#define BIF_RAS_LEAF2_CTRL__ERR_EVENT_RECV__SHIFT 0x10 ++#define BIF_RAS_LEAF2_CTRL__LINK_DIS_RECV__SHIFT 0x11 ++#define BIF_RAS_LEAF2_CTRL__POISON_ERR_DET__SHIFT 0x12 ++#define BIF_RAS_LEAF2_CTRL__PARITY_ERR_DET__SHIFT 0x13 ++#define BIF_RAS_LEAF2_CTRL__ERR_EVENT_SENT__SHIFT 0x14 ++#define BIF_RAS_LEAF2_CTRL__EGRESS_STALLED__SHIFT 0x15 ++//BIF_RAS_MISC_CTRL ++#define BIF_RAS_MISC_CTRL__LINKDIS_TRIG_ERREVENT_EN__SHIFT 0x0 ++//BIF_IOHUB_RAS_IH_CNTL ++#define BIF_IOHUB_RAS_IH_CNTL__RAS_IH_INTR_EN__SHIFT 0x0 ++//BIF_RAS_VWR_FROM_IOHUB ++#define BIF_RAS_VWR_FROM_IOHUB__RAS_IH_INTR_TRIG__SHIFT 0x0 ++ ++ ++// addressBlock: rcc_pfc_amdgfx_RCCPFCDEC ++//RCC_PFC_LTR_CNTL ++#define RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 ++#define RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa ++#define RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf ++#define RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 ++#define RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a ++#define RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f ++//RCC_PFC_PME_RESTORE ++#define RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 ++#define RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 ++//RCC_PFC_STICKY_RESTORE_0 ++#define RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 ++#define RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 ++#define RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 ++#define RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 ++#define RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 ++#define RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 ++#define RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 ++#define RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 ++//RCC_PFC_STICKY_RESTORE_1 ++#define RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 ++//RCC_PFC_STICKY_RESTORE_2 ++#define RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 ++//RCC_PFC_STICKY_RESTORE_3 ++#define RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 ++//RCC_PFC_STICKY_RESTORE_4 ++#define RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 ++//RCC_PFC_STICKY_RESTORE_5 ++#define RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 ++//RCC_PFC_AUXPWR_CNTL ++#define RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 ++#define RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 ++ ++ ++// addressBlock: rcc_pfc_amdgfxaz_RCCPFCDEC ++//RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL ++#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 ++#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa ++#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf ++#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 ++#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a ++#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f ++//RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE ++#define RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 ++#define RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 ++//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0 ++#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 ++#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 ++#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 ++#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 ++#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 ++#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 ++#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 ++#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 ++//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1 ++#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 ++//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2 ++#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 ++//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3 ++#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 ++//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4 ++#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 ++//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5 ++#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 ++//RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL ++#define RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 ++#define RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 ++ ++ ++// addressBlock: pciemsix_amdgfx_MSIXTDEC ++//PCIEMSIX_VECT0_ADDR_LO ++#define PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 ++//PCIEMSIX_VECT0_ADDR_HI ++#define PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 ++//PCIEMSIX_VECT0_MSG_DATA ++#define PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 ++//PCIEMSIX_VECT0_CONTROL ++#define PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 ++//PCIEMSIX_VECT1_ADDR_LO ++#define PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 ++//PCIEMSIX_VECT1_ADDR_HI ++#define PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 ++//PCIEMSIX_VECT1_MSG_DATA ++#define PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 ++//PCIEMSIX_VECT1_CONTROL ++#define PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 ++//PCIEMSIX_VECT2_ADDR_LO ++#define PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 ++//PCIEMSIX_VECT2_ADDR_HI ++#define PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 ++//PCIEMSIX_VECT2_MSG_DATA ++#define PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 ++//PCIEMSIX_VECT2_CONTROL ++#define PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 ++//PCIEMSIX_VECT3_ADDR_LO ++#define PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 ++//PCIEMSIX_VECT3_ADDR_HI ++#define PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 ++//PCIEMSIX_VECT3_MSG_DATA ++#define PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 ++//PCIEMSIX_VECT3_CONTROL ++#define PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 ++//PCIEMSIX_VECT4_ADDR_LO ++#define PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 ++//PCIEMSIX_VECT4_ADDR_HI ++#define PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 ++//PCIEMSIX_VECT4_MSG_DATA ++#define PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 ++//PCIEMSIX_VECT4_CONTROL ++#define PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 ++//PCIEMSIX_VECT5_ADDR_LO ++#define PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 ++//PCIEMSIX_VECT5_ADDR_HI ++#define PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 ++//PCIEMSIX_VECT5_MSG_DATA ++#define PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 ++//PCIEMSIX_VECT5_CONTROL ++#define PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 ++//PCIEMSIX_VECT6_ADDR_LO ++#define PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 ++//PCIEMSIX_VECT6_ADDR_HI ++#define PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 ++//PCIEMSIX_VECT6_MSG_DATA ++#define PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 ++//PCIEMSIX_VECT6_CONTROL ++#define PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 ++//PCIEMSIX_VECT7_ADDR_LO ++#define PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 ++//PCIEMSIX_VECT7_ADDR_HI ++#define PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 ++//PCIEMSIX_VECT7_MSG_DATA ++#define PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 ++//PCIEMSIX_VECT7_CONTROL ++#define PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 ++//PCIEMSIX_VECT8_ADDR_LO ++#define PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 ++//PCIEMSIX_VECT8_ADDR_HI ++#define PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 ++//PCIEMSIX_VECT8_MSG_DATA ++#define PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 ++//PCIEMSIX_VECT8_CONTROL ++#define PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 ++//PCIEMSIX_VECT9_ADDR_LO ++#define PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 ++//PCIEMSIX_VECT9_ADDR_HI ++#define PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 ++//PCIEMSIX_VECT9_MSG_DATA ++#define PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT 0x0 ++//PCIEMSIX_VECT9_CONTROL ++#define PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT 0x0 ++//PCIEMSIX_VECT10_ADDR_LO ++#define PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 ++//PCIEMSIX_VECT10_ADDR_HI ++#define PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 ++//PCIEMSIX_VECT10_MSG_DATA ++#define PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT 0x0 ++//PCIEMSIX_VECT10_CONTROL ++#define PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT 0x0 ++//PCIEMSIX_VECT11_ADDR_LO ++#define PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 ++//PCIEMSIX_VECT11_ADDR_HI ++#define PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 ++//PCIEMSIX_VECT11_MSG_DATA ++#define PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT 0x0 ++//PCIEMSIX_VECT11_CONTROL ++#define PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT 0x0 ++//PCIEMSIX_VECT12_ADDR_LO ++#define PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 ++//PCIEMSIX_VECT12_ADDR_HI ++#define PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 ++//PCIEMSIX_VECT12_MSG_DATA ++#define PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT 0x0 ++//PCIEMSIX_VECT12_CONTROL ++#define PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT 0x0 ++//PCIEMSIX_VECT13_ADDR_LO ++#define PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 ++//PCIEMSIX_VECT13_ADDR_HI ++#define PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 ++//PCIEMSIX_VECT13_MSG_DATA ++#define PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT 0x0 ++//PCIEMSIX_VECT13_CONTROL ++#define PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT 0x0 ++//PCIEMSIX_VECT14_ADDR_LO ++#define PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 ++//PCIEMSIX_VECT14_ADDR_HI ++#define PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 ++//PCIEMSIX_VECT14_MSG_DATA ++#define PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT 0x0 ++//PCIEMSIX_VECT14_CONTROL ++#define PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT 0x0 ++//PCIEMSIX_VECT15_ADDR_LO ++#define PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 ++//PCIEMSIX_VECT15_ADDR_HI ++#define PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 ++//PCIEMSIX_VECT15_MSG_DATA ++#define PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT 0x0 ++//PCIEMSIX_VECT15_CONTROL ++#define PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT 0x0 ++//PCIEMSIX_VECT16_ADDR_LO ++#define PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 ++//PCIEMSIX_VECT16_ADDR_HI ++#define PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 ++//PCIEMSIX_VECT16_MSG_DATA ++#define PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT 0x0 ++//PCIEMSIX_VECT16_CONTROL ++#define PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT 0x0 ++//PCIEMSIX_VECT17_ADDR_LO ++#define PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 ++//PCIEMSIX_VECT17_ADDR_HI ++#define PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 ++//PCIEMSIX_VECT17_MSG_DATA ++#define PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT 0x0 ++//PCIEMSIX_VECT17_CONTROL ++#define PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT 0x0 ++//PCIEMSIX_VECT18_ADDR_LO ++#define PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 ++//PCIEMSIX_VECT18_ADDR_HI ++#define PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 ++//PCIEMSIX_VECT18_MSG_DATA ++#define PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT 0x0 ++//PCIEMSIX_VECT18_CONTROL ++#define PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT 0x0 ++//PCIEMSIX_VECT19_ADDR_LO ++#define PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 ++//PCIEMSIX_VECT19_ADDR_HI ++#define PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 ++//PCIEMSIX_VECT19_MSG_DATA ++#define PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT 0x0 ++//PCIEMSIX_VECT19_CONTROL ++#define PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT 0x0 ++//PCIEMSIX_VECT20_ADDR_LO ++#define PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 ++//PCIEMSIX_VECT20_ADDR_HI ++#define PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 ++//PCIEMSIX_VECT20_MSG_DATA ++#define PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT 0x0 ++//PCIEMSIX_VECT20_CONTROL ++#define PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT 0x0 ++//PCIEMSIX_VECT21_ADDR_LO ++#define PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 ++//PCIEMSIX_VECT21_ADDR_HI ++#define PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 ++//PCIEMSIX_VECT21_MSG_DATA ++#define PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT 0x0 ++//PCIEMSIX_VECT21_CONTROL ++#define PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT 0x0 ++//PCIEMSIX_VECT22_ADDR_LO ++#define PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 ++//PCIEMSIX_VECT22_ADDR_HI ++#define PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 ++//PCIEMSIX_VECT22_MSG_DATA ++#define PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT 0x0 ++//PCIEMSIX_VECT22_CONTROL ++#define PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT 0x0 ++//PCIEMSIX_VECT23_ADDR_LO ++#define PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 ++//PCIEMSIX_VECT23_ADDR_HI ++#define PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 ++//PCIEMSIX_VECT23_MSG_DATA ++#define PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT 0x0 ++//PCIEMSIX_VECT23_CONTROL ++#define PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT 0x0 ++//PCIEMSIX_VECT24_ADDR_LO ++#define PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 ++//PCIEMSIX_VECT24_ADDR_HI ++#define PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 ++//PCIEMSIX_VECT24_MSG_DATA ++#define PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT 0x0 ++//PCIEMSIX_VECT24_CONTROL ++#define PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT 0x0 ++//PCIEMSIX_VECT25_ADDR_LO ++#define PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 ++//PCIEMSIX_VECT25_ADDR_HI ++#define PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 ++//PCIEMSIX_VECT25_MSG_DATA ++#define PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT 0x0 ++//PCIEMSIX_VECT25_CONTROL ++#define PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT 0x0 ++//PCIEMSIX_VECT26_ADDR_LO ++#define PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 ++//PCIEMSIX_VECT26_ADDR_HI ++#define PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 ++//PCIEMSIX_VECT26_MSG_DATA ++#define PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT 0x0 ++//PCIEMSIX_VECT26_CONTROL ++#define PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT 0x0 ++//PCIEMSIX_VECT27_ADDR_LO ++#define PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 ++//PCIEMSIX_VECT27_ADDR_HI ++#define PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 ++//PCIEMSIX_VECT27_MSG_DATA ++#define PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT 0x0 ++//PCIEMSIX_VECT27_CONTROL ++#define PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT 0x0 ++//PCIEMSIX_VECT28_ADDR_LO ++#define PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 ++//PCIEMSIX_VECT28_ADDR_HI ++#define PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 ++//PCIEMSIX_VECT28_MSG_DATA ++#define PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT 0x0 ++//PCIEMSIX_VECT28_CONTROL ++#define PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT 0x0 ++//PCIEMSIX_VECT29_ADDR_LO ++#define PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 ++//PCIEMSIX_VECT29_ADDR_HI ++#define PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 ++//PCIEMSIX_VECT29_MSG_DATA ++#define PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT 0x0 ++//PCIEMSIX_VECT29_CONTROL ++#define PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT 0x0 ++//PCIEMSIX_VECT30_ADDR_LO ++#define PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 ++//PCIEMSIX_VECT30_ADDR_HI ++#define PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 ++//PCIEMSIX_VECT30_MSG_DATA ++#define PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT 0x0 ++//PCIEMSIX_VECT30_CONTROL ++#define PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT 0x0 ++//PCIEMSIX_VECT31_ADDR_LO ++#define PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 ++//PCIEMSIX_VECT31_ADDR_HI ++#define PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 ++//PCIEMSIX_VECT31_MSG_DATA ++#define PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT 0x0 ++//PCIEMSIX_VECT31_CONTROL ++#define PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT 0x0 ++ ++ ++// addressBlock: pciemsix_amdgfx_MSIXPDEC ++//PCIEMSIX_PBA ++#define PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT 0x0 ++ ++ ++// addressBlock: syshub_mmreg_ind_syshubind ++//SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0 ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1 ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2 ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3 ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4 ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5 ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6 ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7 ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10 ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11 ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12 ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13 ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14 ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15 ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16 ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17 ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__SHIFT 0x1f ++//SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__SHIFT 0x0 ++//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK ++#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en__SHIFT 0x0 ++#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en__SHIFT 0x1 ++#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__SHIFT 0xf ++#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en__SHIFT 0x10 ++#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en__SHIFT 0x11 ++//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK ++#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en__SHIFT 0x0 ++#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en__SHIFT 0x1 ++#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__SHIFT 0xf ++#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en__SHIFT 0x10 ++#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en__SHIFT 0x11 ++//SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 ++//SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL ++#define SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 ++#define SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 ++#define SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 ++//SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 ++//SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 ++//SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 ++//SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 ++//SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 ++//SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 ++//SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL ++#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 ++#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 ++#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 ++#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 ++#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 ++#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 ++//SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL ++#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 ++#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 ++#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 ++#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 ++#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 ++#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 ++//SYSHUBMMREGIND_SYSHUB_CG_CNTL ++#define SYSHUBMMREGIND_SYSHUB_CG_CNTL__SYSHUB_CG_EN__SHIFT 0x0 ++#define SYSHUBMMREGIND_SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER__SHIFT 0x8 ++#define SYSHUBMMREGIND_SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER__SHIFT 0x10 ++//SYSHUBMMREGIND_SYSHUB_TRANS_IDLE ++#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0__SHIFT 0x0 ++#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1__SHIFT 0x1 ++#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2__SHIFT 0x2 ++#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3__SHIFT 0x3 ++#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4__SHIFT 0x4 ++#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5__SHIFT 0x5 ++#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6__SHIFT 0x6 ++#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7__SHIFT 0x7 ++#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8__SHIFT 0x8 ++#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9__SHIFT 0x9 ++#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10__SHIFT 0xa ++#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11__SHIFT 0xb ++#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12__SHIFT 0xc ++#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13__SHIFT 0xd ++#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14__SHIFT 0xe ++#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15__SHIFT 0xf ++#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF__SHIFT 0x10 ++//SYSHUBMMREGIND_SYSHUB_HP_TIMER ++#define SYSHUBMMREGIND_SYSHUB_HP_TIMER__SYSHUB_HP_TIMER__SHIFT 0x0 ++//SYSHUBMMREGIND_SYSHUB_SCRATCH ++#define SYSHUBMMREGIND_SYSHUB_SCRATCH__SCRATCH__SHIFT 0x0 ++//SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0 ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1 ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2 ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3 ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4 ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5 ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6 ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7 ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10 ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11 ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12 ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13 ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14 ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15 ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16 ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17 ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN__SHIFT 0x1f ++//SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER__SHIFT 0x0 ++//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK ++#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en__SHIFT 0xf ++#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en__SHIFT 0x10 ++//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK ++#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en__SHIFT 0xf ++#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en__SHIFT 0x10 ++//SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 ++//SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 ++//SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 ++//SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 ++//SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 ++//SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 ++//SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 ++//SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 ++//SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 ++//SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 ++//SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 ++//SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 ++//MASK ++ ++ ++// addressBlock: bif_cfg_dev0_epf0_bifcfgdecp ++//VENDOR_ID ++#define VENDOR_ID__VENDOR_ID__MASK 0xFFFFL ++//DEVICE_ID ++#define DEVICE_ID__DEVICE_ID__MASK 0xFFFFL ++//COMMAND ++#define COMMAND__IO_ACCESS_EN__MASK 0x0001L ++#define COMMAND__MEM_ACCESS_EN__MASK 0x0002L ++#define COMMAND__BUS_MASTER_EN__MASK 0x0004L ++#define COMMAND__SPECIAL_CYCLE_EN__MASK 0x0008L ++#define COMMAND__MEM_WRITE_INVALIDATE_EN__MASK 0x0010L ++#define COMMAND__PAL_SNOOP_EN__MASK 0x0020L ++#define COMMAND__PARITY_ERROR_RESPONSE__MASK 0x0040L ++#define COMMAND__AD_STEPPING__MASK 0x0080L ++#define COMMAND__SERR_EN__MASK 0x0100L ++#define COMMAND__FAST_B2B_EN__MASK 0x0200L ++#define COMMAND__INT_DIS__MASK 0x0400L ++//STATUS ++#define STATUS__INT_STATUS__MASK 0x0008L ++#define STATUS__CAP_LIST__MASK 0x0010L ++#define STATUS__PCI_66_EN__MASK 0x0020L ++#define STATUS__FAST_BACK_CAPABLE__MASK 0x0080L ++#define STATUS__MASTER_DATA_PARITY_ERROR__MASK 0x0100L ++#define STATUS__DEVSEL_TIMING__MASK 0x0600L ++#define STATUS__SIGNAL_TARGET_ABORT__MASK 0x0800L ++#define STATUS__RECEIVED_TARGET_ABORT__MASK 0x1000L ++#define STATUS__RECEIVED_MASTER_ABORT__MASK 0x2000L ++#define STATUS__SIGNALED_SYSTEM_ERROR__MASK 0x4000L ++#define STATUS__PARITY_ERROR_DETECTED__MASK 0x8000L ++//REVISION_ID ++#define REVISION_ID__MINOR_REV_ID__MASK 0x0FL ++#define REVISION_ID__MAJOR_REV_ID__MASK 0xF0L ++//PROG_INTERFACE ++#define PROG_INTERFACE__PROG_INTERFACE__MASK 0xFFL ++//SUB_CLASS ++#define SUB_CLASS__SUB_CLASS__MASK 0xFFL ++//BASE_CLASS ++#define BASE_CLASS__BASE_CLASS__MASK 0xFFL ++//CACHE_LINE ++#define CACHE_LINE__CACHE_LINE_SIZE__MASK 0xFFL ++//LATENCY ++#define LATENCY__LATENCY_TIMER__MASK 0xFFL ++//HEADER ++#define HEADER__HEADER_TYPE__MASK 0x7FL ++#define HEADER__DEVICE_TYPE__MASK 0x80L ++//BIST ++#define BIST__BIST_COMP__MASK 0x0FL ++#define BIST__BIST_STRT__MASK 0x40L ++#define BIST__BIST_CAP__MASK 0x80L ++//BASE_ADDR_1 ++#define BASE_ADDR_1__BASE_ADDR__MASK 0xFFFFFFFFL ++//BASE_ADDR_2 ++#define BASE_ADDR_2__BASE_ADDR__MASK 0xFFFFFFFFL ++//BASE_ADDR_3 ++#define BASE_ADDR_3__BASE_ADDR__MASK 0xFFFFFFFFL ++//BASE_ADDR_4 ++#define BASE_ADDR_4__BASE_ADDR__MASK 0xFFFFFFFFL ++//BASE_ADDR_5 ++#define BASE_ADDR_5__BASE_ADDR__MASK 0xFFFFFFFFL ++//BASE_ADDR_6 ++#define BASE_ADDR_6__BASE_ADDR__MASK 0xFFFFFFFFL ++//ADAPTER_ID ++#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID__MASK 0x0000FFFFL ++#define ADAPTER_ID__SUBSYSTEM_ID__MASK 0xFFFF0000L ++//ROM_BASE_ADDR ++#define ROM_BASE_ADDR__BASE_ADDR__MASK 0xFFFFFFFFL ++//CAP_PTR ++#define CAP_PTR__CAP_PTR__MASK 0x000000FFL ++//INTERRUPT_LINE ++#define INTERRUPT_LINE__INTERRUPT_LINE__MASK 0xFFL ++//INTERRUPT_PIN ++#define INTERRUPT_PIN__INTERRUPT_PIN__MASK 0xFFL ++//MIN_GRANT ++#define MIN_GRANT__MIN_GNT__MASK 0xFFL ++//MAX_LATENCY ++#define MAX_LATENCY__MAX_LAT__MASK 0xFFL ++//VENDOR_CAP_LIST ++#define VENDOR_CAP_LIST__CAP_ID__MASK 0x000000FFL ++#define VENDOR_CAP_LIST__NEXT_PTR__MASK 0x0000FF00L ++#define VENDOR_CAP_LIST__LENGTH__MASK 0x00FF0000L ++//ADAPTER_ID_W ++#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__MASK 0x0000FFFFL ++#define ADAPTER_ID_W__SUBSYSTEM_ID__MASK 0xFFFF0000L ++//PMI_CAP_LIST ++#define PMI_CAP_LIST__CAP_ID__MASK 0x00FFL ++#define PMI_CAP_LIST__NEXT_PTR__MASK 0xFF00L ++//PMI_CAP ++#define PMI_CAP__VERSION__MASK 0x0007L ++#define PMI_CAP__PME_CLOCK__MASK 0x0008L ++#define PMI_CAP__DEV_SPECIFIC_INIT__MASK 0x0020L ++#define PMI_CAP__AUX_CURRENT__MASK 0x01C0L ++#define PMI_CAP__D1_SUPPORT__MASK 0x0200L ++#define PMI_CAP__D2_SUPPORT__MASK 0x0400L ++#define PMI_CAP__PME_SUPPORT__MASK 0xF800L ++//PMI_STATUS_CNTL ++#define PMI_STATUS_CNTL__POWER_STATE__MASK 0x00000003L ++#define PMI_STATUS_CNTL__NO_SOFT_RESET__MASK 0x00000008L ++#define PMI_STATUS_CNTL__PME_EN__MASK 0x00000100L ++#define PMI_STATUS_CNTL__DATA_SELECT__MASK 0x00001E00L ++#define PMI_STATUS_CNTL__DATA_SCALE__MASK 0x00006000L ++#define PMI_STATUS_CNTL__PME_STATUS__MASK 0x00008000L ++#define PMI_STATUS_CNTL__B2_B3_SUPPORT__MASK 0x00400000L ++#define PMI_STATUS_CNTL__BUS_PWR_EN__MASK 0x00800000L ++#define PMI_STATUS_CNTL__PMI_DATA__MASK 0xFF000000L ++//PCIE_CAP_LIST ++#define PCIE_CAP_LIST__CAP_ID__MASK 0x00FFL ++#define PCIE_CAP_LIST__NEXT_PTR__MASK 0xFF00L ++//PCIE_CAP ++#define PCIE_CAP__VERSION__MASK 0x000FL ++#define PCIE_CAP__DEVICE_TYPE__MASK 0x00F0L ++#define PCIE_CAP__SLOT_IMPLEMENTED__MASK 0x0100L ++#define PCIE_CAP__INT_MESSAGE_NUM__MASK 0x3E00L ++//DEVICE_CAP ++#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT__MASK 0x00000007L ++#define DEVICE_CAP__PHANTOM_FUNC__MASK 0x00000018L ++#define DEVICE_CAP__EXTENDED_TAG__MASK 0x00000020L ++#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__MASK 0x000001C0L ++#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY__MASK 0x00000E00L ++#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING__MASK 0x00008000L ++#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__MASK 0x03FC0000L ++#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__MASK 0x0C000000L ++#define DEVICE_CAP__FLR_CAPABLE__MASK 0x10000000L ++//DEVICE_CNTL ++#define DEVICE_CNTL__CORR_ERR_EN__MASK 0x0001L ++#define DEVICE_CNTL__NON_FATAL_ERR_EN__MASK 0x0002L ++#define DEVICE_CNTL__FATAL_ERR_EN__MASK 0x0004L ++#define DEVICE_CNTL__USR_REPORT_EN__MASK 0x0008L ++#define DEVICE_CNTL__RELAXED_ORD_EN__MASK 0x0010L ++#define DEVICE_CNTL__MAX_PAYLOAD_SIZE__MASK 0x00E0L ++#define DEVICE_CNTL__EXTENDED_TAG_EN__MASK 0x0100L ++#define DEVICE_CNTL__PHANTOM_FUNC_EN__MASK 0x0200L ++#define DEVICE_CNTL__AUX_POWER_PM_EN__MASK 0x0400L ++#define DEVICE_CNTL__NO_SNOOP_EN__MASK 0x0800L ++#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE__MASK 0x7000L ++#define DEVICE_CNTL__INITIATE_FLR__MASK 0x8000L ++//DEVICE_STATUS ++#define DEVICE_STATUS__CORR_ERR__MASK 0x0001L ++#define DEVICE_STATUS__NON_FATAL_ERR__MASK 0x0002L ++#define DEVICE_STATUS__FATAL_ERR__MASK 0x0004L ++#define DEVICE_STATUS__USR_DETECTED__MASK 0x0008L ++#define DEVICE_STATUS__AUX_PWR__MASK 0x0010L ++#define DEVICE_STATUS__TRANSACTIONS_PEND__MASK 0x0020L ++//LINK_CAP ++#define LINK_CAP__LINK_SPEED__MASK 0x0000000FL ++#define LINK_CAP__LINK_WIDTH__MASK 0x000003F0L ++#define LINK_CAP__PM_SUPPORT__MASK 0x00000C00L ++#define LINK_CAP__L0S_EXIT_LATENCY__MASK 0x00007000L ++#define LINK_CAP__L1_EXIT_LATENCY__MASK 0x00038000L ++#define LINK_CAP__CLOCK_POWER_MANAGEMENT__MASK 0x00040000L ++#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__MASK 0x00080000L ++#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__MASK 0x00100000L ++#define LINK_CAP__LINK_BW_NOTIFICATION_CAP__MASK 0x00200000L ++#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__MASK 0x00400000L ++#define LINK_CAP__PORT_NUMBER__MASK 0xFF000000L ++//LINK_CNTL ++#define LINK_CNTL__PM_CONTROL__MASK 0x0003L ++#define LINK_CNTL__READ_CPL_BOUNDARY__MASK 0x0008L ++#define LINK_CNTL__LINK_DIS__MASK 0x0010L ++#define LINK_CNTL__RETRAIN_LINK__MASK 0x0020L ++#define LINK_CNTL__COMMON_CLOCK_CFG__MASK 0x0040L ++#define LINK_CNTL__EXTENDED_SYNC__MASK 0x0080L ++#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__MASK 0x0100L ++#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__MASK 0x0200L ++#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__MASK 0x0400L ++#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__MASK 0x0800L ++//LINK_STATUS ++#define LINK_STATUS__CURRENT_LINK_SPEED__MASK 0x000FL ++#define LINK_STATUS__NEGOTIATED_LINK_WIDTH__MASK 0x03F0L ++#define LINK_STATUS__LINK_TRAINING__MASK 0x0800L ++#define LINK_STATUS__SLOT_CLOCK_CFG__MASK 0x1000L ++#define LINK_STATUS__DL_ACTIVE__MASK 0x2000L ++#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__MASK 0x4000L ++#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__MASK 0x8000L ++//DEVICE_CAP2 ++#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__MASK 0x0000000FL ++#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__MASK 0x00000010L ++#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__MASK 0x00000020L ++#define DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__MASK 0x00000040L ++#define DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__MASK 0x00000080L ++#define DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__MASK 0x00000100L ++#define DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__MASK 0x00000200L ++#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__MASK 0x00000400L ++#define DEVICE_CAP2__LTR_SUPPORTED__MASK 0x00000800L ++#define DEVICE_CAP2__TPH_CPLR_SUPPORTED__MASK 0x00003000L ++#define DEVICE_CAP2__OBFF_SUPPORTED__MASK 0x000C0000L ++#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__MASK 0x00100000L ++#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__MASK 0x00200000L ++#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__MASK 0x00C00000L ++//DEVICE_CNTL2 ++#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE__MASK 0x000FL ++#define DEVICE_CNTL2__CPL_TIMEOUT_DIS__MASK 0x0010L ++#define DEVICE_CNTL2__ARI_FORWARDING_EN__MASK 0x0020L ++#define DEVICE_CNTL2__ATOMICOP_REQUEST_EN__MASK 0x0040L ++#define DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__MASK 0x0080L ++#define DEVICE_CNTL2__IDO_REQUEST_ENABLE__MASK 0x0100L ++#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE__MASK 0x0200L ++#define DEVICE_CNTL2__LTR_EN__MASK 0x0400L ++#define DEVICE_CNTL2__OBFF_EN__MASK 0x6000L ++#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__MASK 0x8000L ++//DEVICE_STATUS2 ++#define DEVICE_STATUS2__RESERVED__MASK 0xFFFFL ++//LINK_CAP2 ++#define LINK_CAP2__SUPPORTED_LINK_SPEED__MASK 0x000000FEL ++#define LINK_CAP2__CROSSLINK_SUPPORTED__MASK 0x00000100L ++#define LINK_CAP2__RESERVED__MASK 0xFFFFFE00L ++//LINK_CNTL2 ++#define LINK_CNTL2__TARGET_LINK_SPEED__MASK 0x000FL ++#define LINK_CNTL2__ENTER_COMPLIANCE__MASK 0x0010L ++#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__MASK 0x0020L ++#define LINK_CNTL2__SELECTABLE_DEEMPHASIS__MASK 0x0040L ++#define LINK_CNTL2__XMIT_MARGIN__MASK 0x0380L ++#define LINK_CNTL2__ENTER_MOD_COMPLIANCE__MASK 0x0400L ++#define LINK_CNTL2__COMPLIANCE_SOS__MASK 0x0800L ++#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS__MASK 0xF000L ++//LINK_STATUS2 ++#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__MASK 0x0001L ++#define LINK_STATUS2__EQUALIZATION_COMPLETE__MASK 0x0002L ++#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__MASK 0x0004L ++#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__MASK 0x0008L ++#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__MASK 0x0010L ++#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST__MASK 0x0020L ++//SLOT_CAP2 ++#define SLOT_CAP2__RESERVED__MASK 0xFFFFFFFFL ++//SLOT_CNTL2 ++#define SLOT_CNTL2__RESERVED__MASK 0xFFFFL ++//SLOT_STATUS2 ++#define SLOT_STATUS2__RESERVED__MASK 0xFFFFL ++//MSI_CAP_LIST ++#define MSI_CAP_LIST__CAP_ID__MASK 0x00FFL ++#define MSI_CAP_LIST__NEXT_PTR__MASK 0xFF00L ++//MSI_MSG_CNTL ++#define MSI_MSG_CNTL__MSI_EN__MASK 0x0001L ++#define MSI_MSG_CNTL__MSI_MULTI_CAP__MASK 0x000EL ++#define MSI_MSG_CNTL__MSI_MULTI_EN__MASK 0x0070L ++#define MSI_MSG_CNTL__MSI_64BIT__MASK 0x0080L ++#define MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__MASK 0x0100L ++//MSI_MSG_ADDR_LO ++#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__MASK 0xFFFFFFFCL ++//MSI_MSG_ADDR_HI ++#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__MASK 0xFFFFFFFFL ++//MSI_MSG_DATA ++#define MSI_MSG_DATA__MSI_DATA__MASK 0x0000FFFFL ++//MSI_MSG_DATA_64 ++#define MSI_MSG_DATA_64__MSI_DATA_64__MASK 0x0000FFFFL ++//MSI_MASK ++#define MSI_MASK__MSI_MASK__MASK 0xFFFFFFFFL ++//MSI_PENDING ++#define MSI_PENDING__MSI_PENDING__MASK 0xFFFFFFFFL ++//MSI_MASK_64 ++#define MSI_MASK_64__MSI_MASK_64__MASK 0xFFFFFFFFL ++//MSI_PENDING_64 ++#define MSI_PENDING_64__MSI_PENDING_64__MASK 0xFFFFFFFFL ++//MSIX_CAP_LIST ++#define MSIX_CAP_LIST__CAP_ID__MASK 0x00FFL ++#define MSIX_CAP_LIST__NEXT_PTR__MASK 0xFF00L ++//MSIX_MSG_CNTL ++#define MSIX_MSG_CNTL__MSIX_TABLE_SIZE__MASK 0x07FFL ++#define MSIX_MSG_CNTL__MSIX_FUNC_MASK__MASK 0x4000L ++#define MSIX_MSG_CNTL__MSIX_EN__MASK 0x8000L ++//MSIX_TABLE ++#define MSIX_TABLE__MSIX_TABLE_BIR__MASK 0x00000007L ++#define MSIX_TABLE__MSIX_TABLE_OFFSET__MASK 0xFFFFFFF8L ++//MSIX_PBA ++#define MSIX_PBA__MSIX_PBA_BIR__MASK 0x00000007L ++#define MSIX_PBA__MSIX_PBA_OFFSET__MASK 0xFFFFFFF8L ++//PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST ++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL ++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L ++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L ++//PCIE_VENDOR_SPECIFIC_HDR ++#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__MASK 0x0000FFFFL ++#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__MASK 0x000F0000L ++#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__MASK 0xFFF00000L ++//PCIE_VENDOR_SPECIFIC1 ++#define PCIE_VENDOR_SPECIFIC1__SCRATCH__MASK 0xFFFFFFFFL ++//PCIE_VENDOR_SPECIFIC2 ++#define PCIE_VENDOR_SPECIFIC2__SCRATCH__MASK 0xFFFFFFFFL ++//PCIE_VC_ENH_CAP_LIST ++#define PCIE_VC_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL ++#define PCIE_VC_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L ++#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L ++//PCIE_PORT_VC_CAP_REG1 ++#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__MASK 0x00000007L ++#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__MASK 0x00000070L ++#define PCIE_PORT_VC_CAP_REG1__REF_CLK__MASK 0x00000300L ++#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__MASK 0x00000C00L ++//PCIE_PORT_VC_CAP_REG2 ++#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__MASK 0x000000FFL ++#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__MASK 0xFF000000L ++//PCIE_PORT_VC_CNTL ++#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__MASK 0x0001L ++#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT__MASK 0x000EL ++//PCIE_PORT_VC_STATUS ++#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__MASK 0x0001L ++//PCIE_VC0_RESOURCE_CAP ++#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__MASK 0x000000FFL ++#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__MASK 0x00008000L ++#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__MASK 0x003F0000L ++#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__MASK 0xFF000000L ++//PCIE_VC0_RESOURCE_CNTL ++#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__MASK 0x00000001L ++#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__MASK 0x000000FEL ++#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__MASK 0x00010000L ++#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__MASK 0x000E0000L ++#define PCIE_VC0_RESOURCE_CNTL__VC_ID__MASK 0x07000000L ++#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__MASK 0x80000000L ++//PCIE_VC0_RESOURCE_STATUS ++#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__MASK 0x0001L ++#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__MASK 0x0002L ++//PCIE_VC1_RESOURCE_CAP ++#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__MASK 0x000000FFL ++#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__MASK 0x00008000L ++#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__MASK 0x003F0000L ++#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__MASK 0xFF000000L ++//PCIE_VC1_RESOURCE_CNTL ++#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__MASK 0x00000001L ++#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__MASK 0x000000FEL ++#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__MASK 0x00010000L ++#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__MASK 0x000E0000L ++#define PCIE_VC1_RESOURCE_CNTL__VC_ID__MASK 0x07000000L ++#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__MASK 0x80000000L ++//PCIE_VC1_RESOURCE_STATUS ++#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__MASK 0x0001L ++#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__MASK 0x0002L ++//PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST ++#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL ++#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L ++#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L ++//PCIE_DEV_SERIAL_NUM_DW1 ++#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__MASK 0xFFFFFFFFL ++//PCIE_DEV_SERIAL_NUM_DW2 ++#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__MASK 0xFFFFFFFFL ++//PCIE_ADV_ERR_RPT_ENH_CAP_LIST ++#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL ++#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L ++#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L ++//PCIE_UNCORR_ERR_STATUS ++#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__MASK 0x00000010L ++#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__MASK 0x00000020L ++#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__MASK 0x00001000L ++#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__MASK 0x00002000L ++#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__MASK 0x00004000L ++#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__MASK 0x00008000L ++#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__MASK 0x00010000L ++#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__MASK 0x00020000L ++#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__MASK 0x00040000L ++#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__MASK 0x00080000L ++#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__MASK 0x00100000L ++#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__MASK 0x00200000L ++#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__MASK 0x00400000L ++#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__MASK 0x00800000L ++#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__MASK 0x01000000L ++#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__MASK 0x02000000L ++//PCIE_UNCORR_ERR_MASK ++#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__MASK 0x00000010L ++#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__MASK 0x00000020L ++#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__MASK 0x00001000L ++#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__MASK 0x00002000L ++#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__MASK 0x00004000L ++#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__MASK 0x00008000L ++#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__MASK 0x00010000L ++#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__MASK 0x00020000L ++#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__MASK 0x00040000L ++#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__MASK 0x00080000L ++#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__MASK 0x00100000L ++#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__MASK 0x00200000L ++#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__MASK 0x00400000L ++#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__MASK 0x00800000L ++#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__MASK 0x01000000L ++#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__MASK 0x02000000L ++//PCIE_UNCORR_ERR_SEVERITY ++#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__MASK 0x00000010L ++#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__MASK 0x00000020L ++#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__MASK 0x00001000L ++#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__MASK 0x00002000L ++#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__MASK 0x00004000L ++#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__MASK 0x00008000L ++#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__MASK 0x00010000L ++#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__MASK 0x00020000L ++#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__MASK 0x00040000L ++#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__MASK 0x00080000L ++#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__MASK 0x00100000L ++#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__MASK 0x00200000L ++#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__MASK 0x00400000L ++#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__MASK 0x00800000L ++#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__MASK 0x01000000L ++#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__MASK 0x02000000L ++//PCIE_CORR_ERR_STATUS ++#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__MASK 0x00000001L ++#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__MASK 0x00000040L ++#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__MASK 0x00000080L ++#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__MASK 0x00000100L ++#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__MASK 0x00001000L ++#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__MASK 0x00002000L ++#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__MASK 0x00004000L ++#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__MASK 0x00008000L ++//PCIE_CORR_ERR_MASK ++#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK__MASK 0x00000001L ++#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK__MASK 0x00000040L ++#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__MASK 0x00000080L ++#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__MASK 0x00000100L ++#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__MASK 0x00001000L ++#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__MASK 0x00002000L ++#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__MASK 0x00004000L ++#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__MASK 0x00008000L ++//PCIE_ADV_ERR_CAP_CNTL ++#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__MASK 0x0000001FL ++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__MASK 0x00000020L ++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__MASK 0x00000040L ++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__MASK 0x00000080L ++#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__MASK 0x00000100L ++#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__MASK 0x00000200L ++#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__MASK 0x00000400L ++#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__MASK 0x00000800L ++//PCIE_HDR_LOG0 ++#define PCIE_HDR_LOG0__TLP_HDR__MASK 0xFFFFFFFFL ++//PCIE_HDR_LOG1 ++#define PCIE_HDR_LOG1__TLP_HDR__MASK 0xFFFFFFFFL ++//PCIE_HDR_LOG2 ++#define PCIE_HDR_LOG2__TLP_HDR__MASK 0xFFFFFFFFL ++//PCIE_HDR_LOG3 ++#define PCIE_HDR_LOG3__TLP_HDR__MASK 0xFFFFFFFFL ++//PCIE_ROOT_ERR_CMD ++#define PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__MASK 0x00000001L ++#define PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__MASK 0x00000002L ++#define PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__MASK 0x00000004L ++//PCIE_ROOT_ERR_STATUS ++#define PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__MASK 0x00000001L ++#define PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__MASK 0x00000002L ++#define PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__MASK 0x00000004L ++#define PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__MASK 0x00000008L ++#define PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__MASK 0x00000010L ++#define PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__MASK 0x00000020L ++#define PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__MASK 0x00000040L ++#define PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__MASK 0xF8000000L ++//PCIE_ERR_SRC_ID ++#define PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__MASK 0x0000FFFFL ++#define PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__MASK 0xFFFF0000L ++//PCIE_TLP_PREFIX_LOG0 ++#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__MASK 0xFFFFFFFFL ++//PCIE_TLP_PREFIX_LOG1 ++#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__MASK 0xFFFFFFFFL ++//PCIE_TLP_PREFIX_LOG2 ++#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__MASK 0xFFFFFFFFL ++//PCIE_TLP_PREFIX_LOG3 ++#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__MASK 0xFFFFFFFFL ++//PCIE_BAR_ENH_CAP_LIST ++#define PCIE_BAR_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL ++#define PCIE_BAR_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L ++#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L ++//PCIE_BAR1_CAP ++#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__MASK 0x00FFFFF0L ++//PCIE_BAR1_CNTL ++#define PCIE_BAR1_CNTL__BAR_INDEX__MASK 0x0007L ++#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM__MASK 0x00E0L ++#define PCIE_BAR1_CNTL__BAR_SIZE__MASK 0x1F00L ++//PCIE_BAR2_CAP ++#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__MASK 0x00FFFFF0L ++//PCIE_BAR2_CNTL ++#define PCIE_BAR2_CNTL__BAR_INDEX__MASK 0x0007L ++#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM__MASK 0x00E0L ++#define PCIE_BAR2_CNTL__BAR_SIZE__MASK 0x1F00L ++//PCIE_BAR3_CAP ++#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__MASK 0x00FFFFF0L ++//PCIE_BAR3_CNTL ++#define PCIE_BAR3_CNTL__BAR_INDEX__MASK 0x0007L ++#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM__MASK 0x00E0L ++#define PCIE_BAR3_CNTL__BAR_SIZE__MASK 0x1F00L ++//PCIE_BAR4_CAP ++#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__MASK 0x00FFFFF0L ++//PCIE_BAR4_CNTL ++#define PCIE_BAR4_CNTL__BAR_INDEX__MASK 0x0007L ++#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM__MASK 0x00E0L ++#define PCIE_BAR4_CNTL__BAR_SIZE__MASK 0x1F00L ++//PCIE_BAR5_CAP ++#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__MASK 0x00FFFFF0L ++//PCIE_BAR5_CNTL ++#define PCIE_BAR5_CNTL__BAR_INDEX__MASK 0x0007L ++#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM__MASK 0x00E0L ++#define PCIE_BAR5_CNTL__BAR_SIZE__MASK 0x1F00L ++//PCIE_BAR6_CAP ++#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__MASK 0x00FFFFF0L ++//PCIE_BAR6_CNTL ++#define PCIE_BAR6_CNTL__BAR_INDEX__MASK 0x0007L ++#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM__MASK 0x00E0L ++#define PCIE_BAR6_CNTL__BAR_SIZE__MASK 0x1F00L ++//PCIE_PWR_BUDGET_ENH_CAP_LIST ++#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL ++#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L ++#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L ++//PCIE_PWR_BUDGET_DATA_SELECT ++#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__MASK 0xFFL ++//PCIE_PWR_BUDGET_DATA ++#define PCIE_PWR_BUDGET_DATA__BASE_POWER__MASK 0x000000FFL ++#define PCIE_PWR_BUDGET_DATA__DATA_SCALE__MASK 0x00000300L ++#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__MASK 0x00001C00L ++#define PCIE_PWR_BUDGET_DATA__PM_STATE__MASK 0x00006000L ++#define PCIE_PWR_BUDGET_DATA__TYPE__MASK 0x00038000L ++#define PCIE_PWR_BUDGET_DATA__POWER_RAIL__MASK 0x001C0000L ++//PCIE_PWR_BUDGET_CAP ++#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__MASK 0x01L ++//PCIE_DPA_ENH_CAP_LIST ++#define PCIE_DPA_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL ++#define PCIE_DPA_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L ++#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L ++//PCIE_DPA_CAP ++#define PCIE_DPA_CAP__SUBSTATE_MAX__MASK 0x0000001FL ++#define PCIE_DPA_CAP__TRANS_LAT_UNIT__MASK 0x00000300L ++#define PCIE_DPA_CAP__PWR_ALLOC_SCALE__MASK 0x00003000L ++#define PCIE_DPA_CAP__TRANS_LAT_VAL_0__MASK 0x00FF0000L ++#define PCIE_DPA_CAP__TRANS_LAT_VAL_1__MASK 0xFF000000L ++//PCIE_DPA_LATENCY_INDICATOR ++#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__MASK 0xFFL ++//PCIE_DPA_STATUS ++#define PCIE_DPA_STATUS__SUBSTATE_STATUS__MASK 0x001FL ++#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__MASK 0x0100L ++//PCIE_DPA_CNTL ++#define PCIE_DPA_CNTL__SUBSTATE_CNTL__MASK 0x1FL ++//PCIE_DPA_SUBSTATE_PWR_ALLOC_0 ++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__MASK 0xFFL ++//PCIE_DPA_SUBSTATE_PWR_ALLOC_1 ++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__MASK 0xFFL ++//PCIE_DPA_SUBSTATE_PWR_ALLOC_2 ++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__MASK 0xFFL ++//PCIE_DPA_SUBSTATE_PWR_ALLOC_3 ++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__MASK 0xFFL ++//PCIE_DPA_SUBSTATE_PWR_ALLOC_4 ++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__MASK 0xFFL ++//PCIE_DPA_SUBSTATE_PWR_ALLOC_5 ++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__MASK 0xFFL ++//PCIE_DPA_SUBSTATE_PWR_ALLOC_6 ++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__MASK 0xFFL ++//PCIE_DPA_SUBSTATE_PWR_ALLOC_7 ++#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__MASK 0xFFL ++//PCIE_SECONDARY_ENH_CAP_LIST ++#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL ++#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L ++#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L ++//PCIE_LINK_CNTL3 ++#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__MASK 0x00000001L ++#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__MASK 0x00000002L ++#define PCIE_LINK_CNTL3__RESERVED__MASK 0xFFFFFFFCL ++//PCIE_LANE_ERROR_STATUS ++#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__MASK 0x0000FFFFL ++#define PCIE_LANE_ERROR_STATUS__RESERVED__MASK 0xFFFF0000L ++//PCIE_LANE_0_EQUALIZATION_CNTL ++#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL ++#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L ++#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L ++#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L ++#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L ++//PCIE_LANE_1_EQUALIZATION_CNTL ++#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL ++#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L ++#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L ++#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L ++#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L ++//PCIE_LANE_2_EQUALIZATION_CNTL ++#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL ++#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L ++#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L ++#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L ++#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L ++//PCIE_LANE_3_EQUALIZATION_CNTL ++#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL ++#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L ++#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L ++#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L ++#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L ++//PCIE_LANE_4_EQUALIZATION_CNTL ++#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL ++#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L ++#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L ++#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L ++#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L ++//PCIE_LANE_5_EQUALIZATION_CNTL ++#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL ++#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L ++#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L ++#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L ++#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L ++//PCIE_LANE_6_EQUALIZATION_CNTL ++#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL ++#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L ++#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L ++#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L ++#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L ++//PCIE_LANE_7_EQUALIZATION_CNTL ++#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL ++#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L ++#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L ++#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L ++#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L ++//PCIE_LANE_8_EQUALIZATION_CNTL ++#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL ++#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L ++#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L ++#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L ++#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L ++//PCIE_LANE_9_EQUALIZATION_CNTL ++#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL ++#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L ++#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L ++#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L ++#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L ++//PCIE_LANE_10_EQUALIZATION_CNTL ++#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL ++#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L ++#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L ++#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L ++#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L ++//PCIE_LANE_11_EQUALIZATION_CNTL ++#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL ++#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L ++#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L ++#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L ++#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L ++//PCIE_LANE_12_EQUALIZATION_CNTL ++#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL ++#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L ++#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L ++#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L ++#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L ++//PCIE_LANE_13_EQUALIZATION_CNTL ++#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL ++#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L ++#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L ++#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L ++#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L ++//PCIE_LANE_14_EQUALIZATION_CNTL ++#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL ++#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L ++#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L ++#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L ++#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L ++//PCIE_LANE_15_EQUALIZATION_CNTL ++#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL ++#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L ++#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L ++#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L ++#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L ++//PCIE_ACS_ENH_CAP_LIST ++#define PCIE_ACS_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL ++#define PCIE_ACS_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L ++#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L ++//PCIE_ACS_CAP ++#define PCIE_ACS_CAP__SOURCE_VALIDATION__MASK 0x0001L ++#define PCIE_ACS_CAP__TRANSLATION_BLOCKING__MASK 0x0002L ++#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__MASK 0x0004L ++#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__MASK 0x0008L ++#define PCIE_ACS_CAP__UPSTREAM_FORWARDING__MASK 0x0010L ++#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL__MASK 0x0020L ++#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__MASK 0x0040L ++#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__MASK 0xFF00L ++//PCIE_ACS_CNTL ++#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__MASK 0x0001L ++#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__MASK 0x0002L ++#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__MASK 0x0004L ++#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__MASK 0x0008L ++#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__MASK 0x0010L ++#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__MASK 0x0020L ++#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__MASK 0x0040L ++//PCIE_ATS_ENH_CAP_LIST ++#define PCIE_ATS_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL ++#define PCIE_ATS_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L ++#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L ++//PCIE_ATS_CAP ++#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__MASK 0x001FL ++#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__MASK 0x0020L ++#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__MASK 0x0040L ++//PCIE_ATS_CNTL ++#define PCIE_ATS_CNTL__STU__MASK 0x001FL ++#define PCIE_ATS_CNTL__ATC_ENABLE__MASK 0x8000L ++//PCIE_PAGE_REQ_ENH_CAP_LIST ++#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL ++#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L ++#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L ++//PCIE_PAGE_REQ_CNTL ++#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE__MASK 0x0001L ++#define PCIE_PAGE_REQ_CNTL__PRI_RESET__MASK 0x0002L ++//PCIE_PAGE_REQ_STATUS ++#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__MASK 0x0001L ++#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__MASK 0x0002L ++#define PCIE_PAGE_REQ_STATUS__STOPPED__MASK 0x0100L ++#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__MASK 0x8000L ++//PCIE_OUTSTAND_PAGE_REQ_CAPACITY ++#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__MASK 0xFFFFFFFFL ++//PCIE_OUTSTAND_PAGE_REQ_ALLOC ++#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__MASK 0xFFFFFFFFL ++//PCIE_PASID_ENH_CAP_LIST ++#define PCIE_PASID_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL ++#define PCIE_PASID_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L ++#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L ++//PCIE_PASID_CAP ++#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__MASK 0x0002L ++#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__MASK 0x0004L ++#define PCIE_PASID_CAP__MAX_PASID_WIDTH__MASK 0x1F00L ++//PCIE_PASID_CNTL ++#define PCIE_PASID_CNTL__PASID_ENABLE__MASK 0x0001L ++#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__MASK 0x0002L ++#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__MASK 0x0004L ++//PCIE_TPH_REQR_ENH_CAP_LIST ++#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL ++#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L ++#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L ++//PCIE_TPH_REQR_CAP ++#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__MASK 0x00000001L ++#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__MASK 0x00000002L ++#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__MASK 0x00000004L ++#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__MASK 0x00000100L ++#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__MASK 0x00000600L ++#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__MASK 0x07FF0000L ++//PCIE_TPH_REQR_CNTL ++#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__MASK 0x00000007L ++#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN__MASK 0x00000300L ++//PCIE_MC_ENH_CAP_LIST ++#define PCIE_MC_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL ++#define PCIE_MC_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L ++#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L ++//PCIE_MC_CAP ++#define PCIE_MC_CAP__MC_MAX_GROUP__MASK 0x003FL ++#define PCIE_MC_CAP__MC_WIN_SIZE_REQ__MASK 0x3F00L ++#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__MASK 0x8000L ++//PCIE_MC_CNTL ++#define PCIE_MC_CNTL__MC_NUM_GROUP__MASK 0x003FL ++#define PCIE_MC_CNTL__MC_ENABLE__MASK 0x8000L ++//PCIE_MC_ADDR0 ++#define PCIE_MC_ADDR0__MC_INDEX_POS__MASK 0x0000003FL ++#define PCIE_MC_ADDR0__MC_BASE_ADDR_0__MASK 0xFFFFF000L ++//PCIE_MC_ADDR1 ++#define PCIE_MC_ADDR1__MC_BASE_ADDR_1__MASK 0xFFFFFFFFL ++//PCIE_MC_RCV0 ++#define PCIE_MC_RCV0__MC_RECEIVE_0__MASK 0xFFFFFFFFL ++//PCIE_MC_RCV1 ++#define PCIE_MC_RCV1__MC_RECEIVE_1__MASK 0xFFFFFFFFL ++//PCIE_MC_BLOCK_ALL0 ++#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__MASK 0xFFFFFFFFL ++//PCIE_MC_BLOCK_ALL1 ++#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__MASK 0xFFFFFFFFL ++//PCIE_MC_BLOCK_UNTRANSLATED_0 ++#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__MASK 0xFFFFFFFFL ++//PCIE_MC_BLOCK_UNTRANSLATED_1 ++#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__MASK 0xFFFFFFFFL ++//PCIE_LTR_ENH_CAP_LIST ++#define PCIE_LTR_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL ++#define PCIE_LTR_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L ++#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L ++//PCIE_LTR_CAP ++#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__MASK 0x000003FFL ++#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__MASK 0x00001C00L ++#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__MASK 0x03FF0000L ++#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__MASK 0x1C000000L ++//PCIE_ARI_ENH_CAP_LIST ++#define PCIE_ARI_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL ++#define PCIE_ARI_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L ++#define PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L ++//PCIE_ARI_CAP ++#define PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__MASK 0x0001L ++#define PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__MASK 0x0002L ++#define PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__MASK 0xFF00L ++//PCIE_ARI_CNTL ++#define PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__MASK 0x0001L ++#define PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__MASK 0x0002L ++#define PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__MASK 0x0070L ++//PCIE_SRIOV_ENH_CAP_LIST ++#define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL ++#define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L ++#define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L ++//PCIE_SRIOV_CAP ++#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__MASK 0x00000001L ++#define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__MASK 0x00000002L ++#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__MASK 0xFFE00000L ++//PCIE_SRIOV_CONTROL ++#define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__MASK 0x0001L ++#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__MASK 0x0002L ++#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__MASK 0x0004L ++#define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__MASK 0x0008L ++#define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__MASK 0x0010L ++//PCIE_SRIOV_STATUS ++#define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__MASK 0x0001L ++//PCIE_SRIOV_INITIAL_VFS ++#define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__MASK 0xFFFFL ++//PCIE_SRIOV_TOTAL_VFS ++#define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__MASK 0xFFFFL ++//PCIE_SRIOV_NUM_VFS ++#define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__MASK 0xFFFFL ++//PCIE_SRIOV_FUNC_DEP_LINK ++#define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__MASK 0x00FFL ++//PCIE_SRIOV_FIRST_VF_OFFSET ++#define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__MASK 0xFFFFL ++//PCIE_SRIOV_VF_STRIDE ++#define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__MASK 0xFFFFL ++//PCIE_SRIOV_VF_DEVICE_ID ++#define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__MASK 0xFFFFL ++//PCIE_SRIOV_SUPPORTED_PAGE_SIZE ++#define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__MASK 0xFFFFFFFFL ++//PCIE_SRIOV_SYSTEM_PAGE_SIZE ++#define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__MASK 0xFFFFFFFFL ++//PCIE_SRIOV_VF_BASE_ADDR_0 ++#define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__MASK 0xFFFFFFFFL ++//PCIE_SRIOV_VF_BASE_ADDR_1 ++#define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__MASK 0xFFFFFFFFL ++//PCIE_SRIOV_VF_BASE_ADDR_2 ++#define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__MASK 0xFFFFFFFFL ++//PCIE_SRIOV_VF_BASE_ADDR_3 ++#define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__MASK 0xFFFFFFFFL ++//PCIE_SRIOV_VF_BASE_ADDR_4 ++#define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__MASK 0xFFFFFFFFL ++//PCIE_SRIOV_VF_BASE_ADDR_5 ++#define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__MASK 0xFFFFFFFFL ++//PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET ++#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__MASK 0x00000007L ++#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__MASK 0xFFFFFFF8L ++//PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV ++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__MASK 0x0000FFFFL ++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__MASK 0x000F0000L ++#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__MASK 0xFFF00000L ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__MASK 0x0000FFFFL ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__MASK 0x000F0000L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__MASK 0xFFF00000L ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__MASK 0x00000001L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__MASK 0xFFFF0000L ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__MASK 0x00000001L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__MASK 0x00000002L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__MASK 0x00000004L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__MASK 0x00000008L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__MASK 0x00000100L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__MASK 0x00000200L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__MASK 0x00000400L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__MASK 0x00000800L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__MASK 0x00010000L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__MASK 0x00020000L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__MASK 0x00040000L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__MASK 0x00080000L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__MASK 0x01000000L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__MASK 0x02000000L ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__MASK 0x00000001L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__MASK 0x00000002L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__MASK 0x00000004L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__MASK 0x00000008L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__MASK 0x00000100L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__MASK 0x00000200L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__MASK 0x00000400L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__MASK 0x00000800L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__MASK 0x00010000L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__MASK 0x00020000L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__MASK 0x00040000L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__MASK 0x00080000L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__MASK 0x01000000L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__MASK 0x02000000L ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__MASK 0x0001L ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__MASK 0x000000FFL ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__MASK 0x00000F00L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__MASK 0x00008000L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__MASK 0x000F0000L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__MASK 0x01000000L ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__MASK 0x00000001L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__MASK 0x00000002L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__MASK 0x00000004L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__MASK 0x00000008L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__MASK 0x00000010L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__MASK 0x00000020L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__MASK 0x00000040L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__MASK 0x00000080L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__MASK 0x00000100L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__MASK 0x00000200L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__MASK 0x00000400L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__MASK 0x00000800L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__MASK 0x00001000L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__MASK 0x00002000L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__MASK 0x00004000L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__MASK 0x00008000L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__MASK 0x00010000L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__MASK 0x00020000L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__MASK 0x00040000L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__MASK 0x00080000L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__MASK 0x00100000L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__MASK 0x00200000L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__MASK 0x00400000L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__MASK 0x00800000L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__MASK 0x01000000L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__MASK 0x02000000L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__MASK 0x04000000L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__MASK 0x08000000L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__MASK 0x10000000L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__MASK 0x20000000L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__MASK 0x40000000L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__MASK 0x80000000L ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__MASK 0x00000001L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__MASK 0x00000002L ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__MASK 0x0000007FL ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__MASK 0x00000080L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__MASK 0xFFFFFC00L ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__MASK 0x0000FFFFL ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__MASK 0xFFFF0000L ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__MASK 0x000000FFL ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__MASK 0x0000FF00L ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__MASK 0x00FF0000L ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__MASK 0x0000FFFFL ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__MASK 0xFFFF0000L ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__MASK 0x0000FFFFL ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__MASK 0xFFFF0000L ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__MASK 0x0000FFFFL ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__MASK 0xFFFF0000L ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__MASK 0x0000FFFFL ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__MASK 0xFFFF0000L ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__MASK 0x0000FFFFL ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__MASK 0xFFFF0000L ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__MASK 0x0000FFFFL ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__MASK 0xFFFF0000L ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__MASK 0x0000FFFFL ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__MASK 0xFFFF0000L ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__MASK 0x0000FFFFL ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__MASK 0xFFFF0000L ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__MASK 0x0000FFFFL ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__MASK 0xFFFF0000L ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__MASK 0x0000FFFFL ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__MASK 0xFFFF0000L ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__MASK 0x0000FFFFL ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__MASK 0xFFFF0000L ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__MASK 0x0000FFFFL ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__MASK 0xFFFF0000L ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__MASK 0x0000FFFFL ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__MASK 0xFFFF0000L ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__MASK 0x0000FFFFL ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__MASK 0xFFFF0000L ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__MASK 0x0000FFFFL ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__MASK 0xFFFF0000L ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__MASK 0x0000FFFFL ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__MASK 0xFFFF0000L ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__MASK 0xFFFFFFFFL ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__MASK 0xFFFFFFFFL ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__MASK 0xFFFFFFFFL ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__MASK 0xFFFFFFFFL ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__MASK 0xFFFFFFFFL ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__MASK 0xFFFFFFFFL ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__MASK 0xFFFFFFFFL ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__MASK 0xFFFFFFFFL ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__MASK 0xFFFFFFFFL ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__MASK 0xFFFFFFFFL ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__MASK 0xFFFFFFFFL ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__MASK 0xFFFFFFFFL ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__MASK 0xFFFFFFFFL ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__MASK 0xFFFFFFFFL ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__MASK 0xFFFFFFFFL ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__MASK 0xFFFFFFFFL ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__MASK 0xFFFFFFFFL ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__MASK 0xFFFFFFFFL ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__MASK 0xFFFFFFFFL ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__MASK 0xFFFFFFFFL ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__MASK 0xFFFFFFFFL ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__MASK 0xFFFFFFFFL ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__MASK 0xFFFFFFFFL ++//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 ++#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__MASK 0xFFFFFFFFL ++ ++ ++// addressBlock: bif_cfg_dev0_swds_bifcfgdecp ++//SUB_BUS_NUMBER_LATENCY ++#define SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__MASK 0x000000FFL ++#define SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__MASK 0x0000FF00L ++#define SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__MASK 0x00FF0000L ++#define SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__MASK 0xFF000000L ++//IO_BASE_LIMIT ++#define IO_BASE_LIMIT__IO_BASE_TYPE__MASK 0x000FL ++#define IO_BASE_LIMIT__IO_BASE__MASK 0x00F0L ++#define IO_BASE_LIMIT__IO_LIMIT_TYPE__MASK 0x0F00L ++#define IO_BASE_LIMIT__IO_LIMIT__MASK 0xF000L ++//SECONDARY_STATUS ++#define SECONDARY_STATUS__CAP_LIST__MASK 0x0010L ++#define SECONDARY_STATUS__PCI_66_EN__MASK 0x0020L ++#define SECONDARY_STATUS__FAST_BACK_CAPABLE__MASK 0x0080L ++#define SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__MASK 0x0100L ++#define SECONDARY_STATUS__DEVSEL_TIMING__MASK 0x0600L ++#define SECONDARY_STATUS__SIGNAL_TARGET_ABORT__MASK 0x0800L ++#define SECONDARY_STATUS__RECEIVED_TARGET_ABORT__MASK 0x1000L ++#define SECONDARY_STATUS__RECEIVED_MASTER_ABORT__MASK 0x2000L ++#define SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__MASK 0x4000L ++#define SECONDARY_STATUS__PARITY_ERROR_DETECTED__MASK 0x8000L ++//MEM_BASE_LIMIT ++#define MEM_BASE_LIMIT__MEM_BASE_TYPE__MASK 0x0000000FL ++#define MEM_BASE_LIMIT__MEM_BASE_31_20__MASK 0x0000FFF0L ++#define MEM_BASE_LIMIT__MEM_LIMIT_TYPE__MASK 0x000F0000L ++#define MEM_BASE_LIMIT__MEM_LIMIT_31_20__MASK 0xFFF00000L ++//PREF_BASE_LIMIT ++#define PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__MASK 0x0000000FL ++#define PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__MASK 0x0000FFF0L ++#define PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__MASK 0x000F0000L ++#define PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__MASK 0xFFF00000L ++//PREF_BASE_UPPER ++#define PREF_BASE_UPPER__PREF_BASE_UPPER__MASK 0xFFFFFFFFL ++//PREF_LIMIT_UPPER ++#define PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__MASK 0xFFFFFFFFL ++//IO_BASE_LIMIT_HI ++#define IO_BASE_LIMIT_HI__IO_BASE_31_16__MASK 0x0000FFFFL ++#define IO_BASE_LIMIT_HI__IO_LIMIT_31_16__MASK 0xFFFF0000L ++//IRQ_BRIDGE_CNTL ++#define IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__MASK 0x0001L ++#define IRQ_BRIDGE_CNTL__SERR_EN__MASK 0x0002L ++#define IRQ_BRIDGE_CNTL__ISA_EN__MASK 0x0004L ++#define IRQ_BRIDGE_CNTL__VGA_EN__MASK 0x0008L ++#define IRQ_BRIDGE_CNTL__VGA_DEC__MASK 0x0010L ++#define IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__MASK 0x0020L ++#define IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__MASK 0x0040L ++#define IRQ_BRIDGE_CNTL__FAST_B2B_EN__MASK 0x0080L ++//SLOT_CAP ++#define SLOT_CAP__ATTN_BUTTON_PRESENT__MASK 0x00000001L ++#define SLOT_CAP__PWR_CONTROLLER_PRESENT__MASK 0x00000002L ++#define SLOT_CAP__MRL_SENSOR_PRESENT__MASK 0x00000004L ++#define SLOT_CAP__ATTN_INDICATOR_PRESENT__MASK 0x00000008L ++#define SLOT_CAP__PWR_INDICATOR_PRESENT__MASK 0x00000010L ++#define SLOT_CAP__HOTPLUG_SURPRISE__MASK 0x00000020L ++#define SLOT_CAP__HOTPLUG_CAPABLE__MASK 0x00000040L ++#define SLOT_CAP__SLOT_PWR_LIMIT_VALUE__MASK 0x00007F80L ++#define SLOT_CAP__SLOT_PWR_LIMIT_SCALE__MASK 0x00018000L ++#define SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__MASK 0x00020000L ++#define SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__MASK 0x00040000L ++#define SLOT_CAP__PHYSICAL_SLOT_NUM__MASK 0xFFF80000L ++//SLOT_CNTL ++#define SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__MASK 0x0001L ++#define SLOT_CNTL__PWR_FAULT_DETECTED_EN__MASK 0x0002L ++#define SLOT_CNTL__MRL_SENSOR_CHANGED_EN__MASK 0x0004L ++#define SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__MASK 0x0008L ++#define SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__MASK 0x0010L ++#define SLOT_CNTL__HOTPLUG_INTR_EN__MASK 0x0020L ++#define SLOT_CNTL__ATTN_INDICATOR_CNTL__MASK 0x00C0L ++#define SLOT_CNTL__PWR_INDICATOR_CNTL__MASK 0x0300L ++#define SLOT_CNTL__PWR_CONTROLLER_CNTL__MASK 0x0400L ++#define SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__MASK 0x0800L ++#define SLOT_CNTL__DL_STATE_CHANGED_EN__MASK 0x1000L ++//SLOT_STATUS ++#define SLOT_STATUS__ATTN_BUTTON_PRESSED__MASK 0x0001L ++#define SLOT_STATUS__PWR_FAULT_DETECTED__MASK 0x0002L ++#define SLOT_STATUS__MRL_SENSOR_CHANGED__MASK 0x0004L ++#define SLOT_STATUS__PRESENCE_DETECT_CHANGED__MASK 0x0008L ++#define SLOT_STATUS__COMMAND_COMPLETED__MASK 0x0010L ++#define SLOT_STATUS__MRL_SENSOR_STATE__MASK 0x0020L ++#define SLOT_STATUS__PRESENCE_DETECT_STATE__MASK 0x0040L ++#define SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__MASK 0x0080L ++#define SLOT_STATUS__DL_STATE_CHANGED__MASK 0x0100L ++//SSID_CAP_LIST ++#define SSID_CAP_LIST__CAP_ID__MASK 0x00FFL ++#define SSID_CAP_LIST__NEXT_PTR__MASK 0xFF00L ++//SSID_CAP ++#define SSID_CAP__SUBSYSTEM_VENDOR_ID__MASK 0x0000FFFFL ++#define SSID_CAP__SUBSYSTEM_ID__MASK 0xFFFF0000L ++ ++ ++// addressBlock: rcc_shadow_reg_shadowdec ++//SHADOW_COMMAND ++#define SHADOW_COMMAND__IOEN_UP__MASK 0x0001L ++#define SHADOW_COMMAND__MEMEN_UP__MASK 0x0002L ++//SHADOW_BASE_ADDR_1 ++#define SHADOW_BASE_ADDR_1__BAR1_UP__MASK 0xFFFFFFFFL ++//SHADOW_BASE_ADDR_2 ++#define SHADOW_BASE_ADDR_2__BAR2_UP__MASK 0xFFFFFFFFL ++//SHADOW_SUB_BUS_NUMBER_LATENCY ++#define SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP__MASK 0x0000FF00L ++#define SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP__MASK 0x00FF0000L ++//SHADOW_IO_BASE_LIMIT ++#define SHADOW_IO_BASE_LIMIT__IO_BASE_UP__MASK 0x00F0L ++#define SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP__MASK 0xF000L ++//SHADOW_MEM_BASE_LIMIT ++#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE__MASK 0x0000000FL ++#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP__MASK 0x0000FFF0L ++#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__MASK 0x000F0000L ++#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP__MASK 0xFFF00000L ++//SHADOW_PREF_BASE_LIMIT ++#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__MASK 0x0000000FL ++#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP__MASK 0x0000FFF0L ++#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__MASK 0x000F0000L ++#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP__MASK 0xFFF00000L ++//SHADOW_PREF_BASE_UPPER ++#define SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP__MASK 0xFFFFFFFFL ++//SHADOW_PREF_LIMIT_UPPER ++#define SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP__MASK 0xFFFFFFFFL ++//SHADOW_IO_BASE_LIMIT_HI ++#define SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP__MASK 0x0000FFFFL ++#define SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP__MASK 0xFFFF0000L ++//SHADOW_IRQ_BRIDGE_CNTL ++#define SHADOW_IRQ_BRIDGE_CNTL__ISA_EN_UP__MASK 0x0004L ++#define SHADOW_IRQ_BRIDGE_CNTL__VGA_EN_UP__MASK 0x0008L ++#define SHADOW_IRQ_BRIDGE_CNTL__VGA_DEC_UP__MASK 0x0010L ++#define SHADOW_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_UP__MASK 0x0040L ++//SUC_INDEX ++#define SUC_INDEX__SUC_INDEX__MASK 0xFFFFFFFFL ++//SUC_DATA ++#define SUC_DATA__SUC_DATA__MASK 0xFFFFFFFFL ++ ++ ++// addressBlock: bif_bx_pf_SUMDEC ++//SUM_INDEX ++#define SUM_INDEX__SUM_INDEX__MASK 0xFFFFFFFFL ++//SUM_DATA ++#define SUM_DATA__SUM_DATA__MASK 0xFFFFFFFFL ++ ++ ++// addressBlock: gdc_GDCDEC ++//A2S_CNTL_CL0 ++#define A2S_CNTL_CL0__NSNOOP_MAP__MASK 0x00000003L ++#define A2S_CNTL_CL0__REQPASSPW_VC0_MAP__MASK 0x0000000CL ++#define A2S_CNTL_CL0__REQPASSPW_NVC0_MAP__MASK 0x00000030L ++#define A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP__MASK 0x000000C0L ++#define A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP__MASK 0x00000300L ++#define A2S_CNTL_CL0__BLKLVL_MAP__MASK 0x00000C00L ++#define A2S_CNTL_CL0__DATERR_MAP__MASK 0x00003000L ++#define A2S_CNTL_CL0__EXOKAY_WR_MAP__MASK 0x0000C000L ++#define A2S_CNTL_CL0__EXOKAY_RD_MAP__MASK 0x00030000L ++#define A2S_CNTL_CL0__RESP_WR_MAP__MASK 0x000C0000L ++#define A2S_CNTL_CL0__RESP_RD_MAP__MASK 0x00300000L ++//A2S_CNTL_CL1 ++#define A2S_CNTL_CL1__NSNOOP_MAP__MASK 0x00000003L ++#define A2S_CNTL_CL1__REQPASSPW_VC0_MAP__MASK 0x0000000CL ++#define A2S_CNTL_CL1__REQPASSPW_NVC0_MAP__MASK 0x00000030L ++#define A2S_CNTL_CL1__REQRSPPASSPW_VC0_MAP__MASK 0x000000C0L ++#define A2S_CNTL_CL1__REQRSPPASSPW_NVC0_MAP__MASK 0x00000300L ++#define A2S_CNTL_CL1__BLKLVL_MAP__MASK 0x00000C00L ++#define A2S_CNTL_CL1__DATERR_MAP__MASK 0x00003000L ++#define A2S_CNTL_CL1__EXOKAY_WR_MAP__MASK 0x0000C000L ++#define A2S_CNTL_CL1__EXOKAY_RD_MAP__MASK 0x00030000L ++#define A2S_CNTL_CL1__RESP_WR_MAP__MASK 0x000C0000L ++#define A2S_CNTL_CL1__RESP_RD_MAP__MASK 0x00300000L ++//A2S_CNTL_CL2 ++#define A2S_CNTL_CL2__NSNOOP_MAP__MASK 0x00000003L ++#define A2S_CNTL_CL2__REQPASSPW_VC0_MAP__MASK 0x0000000CL ++#define A2S_CNTL_CL2__REQPASSPW_NVC0_MAP__MASK 0x00000030L ++#define A2S_CNTL_CL2__REQRSPPASSPW_VC0_MAP__MASK 0x000000C0L ++#define A2S_CNTL_CL2__REQRSPPASSPW_NVC0_MAP__MASK 0x00000300L ++#define A2S_CNTL_CL2__BLKLVL_MAP__MASK 0x00000C00L ++#define A2S_CNTL_CL2__DATERR_MAP__MASK 0x00003000L ++#define A2S_CNTL_CL2__EXOKAY_WR_MAP__MASK 0x0000C000L ++#define A2S_CNTL_CL2__EXOKAY_RD_MAP__MASK 0x00030000L ++#define A2S_CNTL_CL2__RESP_WR_MAP__MASK 0x000C0000L ++#define A2S_CNTL_CL2__RESP_RD_MAP__MASK 0x00300000L ++//A2S_CNTL_CL3 ++#define A2S_CNTL_CL3__NSNOOP_MAP__MASK 0x00000003L ++#define A2S_CNTL_CL3__REQPASSPW_VC0_MAP__MASK 0x0000000CL ++#define A2S_CNTL_CL3__REQPASSPW_NVC0_MAP__MASK 0x00000030L ++#define A2S_CNTL_CL3__REQRSPPASSPW_VC0_MAP__MASK 0x000000C0L ++#define A2S_CNTL_CL3__REQRSPPASSPW_NVC0_MAP__MASK 0x00000300L ++#define A2S_CNTL_CL3__BLKLVL_MAP__MASK 0x00000C00L ++#define A2S_CNTL_CL3__DATERR_MAP__MASK 0x00003000L ++#define A2S_CNTL_CL3__EXOKAY_WR_MAP__MASK 0x0000C000L ++#define A2S_CNTL_CL3__EXOKAY_RD_MAP__MASK 0x00030000L ++#define A2S_CNTL_CL3__RESP_WR_MAP__MASK 0x000C0000L ++#define A2S_CNTL_CL3__RESP_RD_MAP__MASK 0x00300000L ++//A2S_CNTL_CL4 ++#define A2S_CNTL_CL4__NSNOOP_MAP__MASK 0x00000003L ++#define A2S_CNTL_CL4__REQPASSPW_VC0_MAP__MASK 0x0000000CL ++#define A2S_CNTL_CL4__REQPASSPW_NVC0_MAP__MASK 0x00000030L ++#define A2S_CNTL_CL4__REQRSPPASSPW_VC0_MAP__MASK 0x000000C0L ++#define A2S_CNTL_CL4__REQRSPPASSPW_NVC0_MAP__MASK 0x00000300L ++#define A2S_CNTL_CL4__BLKLVL_MAP__MASK 0x00000C00L ++#define A2S_CNTL_CL4__DATERR_MAP__MASK 0x00003000L ++#define A2S_CNTL_CL4__EXOKAY_WR_MAP__MASK 0x0000C000L ++#define A2S_CNTL_CL4__EXOKAY_RD_MAP__MASK 0x00030000L ++#define A2S_CNTL_CL4__RESP_WR_MAP__MASK 0x000C0000L ++#define A2S_CNTL_CL4__RESP_RD_MAP__MASK 0x00300000L ++//A2S_CNTL_SW0 ++#define A2S_CNTL_SW0__WR_TAG_SET_MIN__MASK 0x00000007L ++#define A2S_CNTL_SW0__RD_TAG_SET_MIN__MASK 0x00000038L ++#define A2S_CNTL_SW0__FORCE_RSP_REORDER_EN__MASK 0x00000040L ++#define A2S_CNTL_SW0__RSP_REORDER_DIS__MASK 0x00000080L ++#define A2S_CNTL_SW0__WRRSP_ACCUM_SEL__MASK 0x00000100L ++#define A2S_CNTL_SW0__SDP_WR_CHAIN_DIS__MASK 0x00000200L ++#define A2S_CNTL_SW0__WRRSP_TAGFIFO_CONT_RD_DIS__MASK 0x00000400L ++#define A2S_CNTL_SW0__RDRSP_TAGFIFO_CONT_RD_DIS__MASK 0x00000800L ++#define A2S_CNTL_SW0__RDRSP_STS_DATSTS_PRIORITY__MASK 0x00001000L ++#define A2S_CNTL_SW0__WRR_RD_WEIGHT__MASK 0x00FF0000L ++#define A2S_CNTL_SW0__WRR_WR_WEIGHT__MASK 0xFF000000L ++//A2S_CNTL_SW1 ++#define A2S_CNTL_SW1__WR_TAG_SET_MIN__MASK 0x00000007L ++#define A2S_CNTL_SW1__RD_TAG_SET_MIN__MASK 0x00000038L ++#define A2S_CNTL_SW1__FORCE_RSP_REORDER_EN__MASK 0x00000040L ++#define A2S_CNTL_SW1__RSP_REORDER_DIS__MASK 0x00000080L ++#define A2S_CNTL_SW1__WRRSP_ACCUM_SEL__MASK 0x00000100L ++#define A2S_CNTL_SW1__SDP_WR_CHAIN_DIS__MASK 0x00000200L ++#define A2S_CNTL_SW1__WRRSP_TAGFIFO_CONT_RD_DIS__MASK 0x00000400L ++#define A2S_CNTL_SW1__RDRSP_TAGFIFO_CONT_RD_DIS__MASK 0x00000800L ++#define A2S_CNTL_SW1__RDRSP_STS_DATSTS_PRIORITY__MASK 0x00001000L ++#define A2S_CNTL_SW1__WRR_RD_WEIGHT__MASK 0x00FF0000L ++#define A2S_CNTL_SW1__WRR_WR_WEIGHT__MASK 0xFF000000L ++//A2S_CNTL_SW2 ++#define A2S_CNTL_SW2__WR_TAG_SET_MIN__MASK 0x00000007L ++#define A2S_CNTL_SW2__RD_TAG_SET_MIN__MASK 0x00000038L ++#define A2S_CNTL_SW2__FORCE_RSP_REORDER_EN__MASK 0x00000040L ++#define A2S_CNTL_SW2__RSP_REORDER_DIS__MASK 0x00000080L ++#define A2S_CNTL_SW2__WRRSP_ACCUM_SEL__MASK 0x00000100L ++#define A2S_CNTL_SW2__SDP_WR_CHAIN_DIS__MASK 0x00000200L ++#define A2S_CNTL_SW2__WRRSP_TAGFIFO_CONT_RD_DIS__MASK 0x00000400L ++#define A2S_CNTL_SW2__RDRSP_TAGFIFO_CONT_RD_DIS__MASK 0x00000800L ++#define A2S_CNTL_SW2__RDRSP_STS_DATSTS_PRIORITY__MASK 0x00001000L ++#define A2S_CNTL_SW2__WRR_RD_WEIGHT__MASK 0x00FF0000L ++#define A2S_CNTL_SW2__WRR_WR_WEIGHT__MASK 0xFF000000L ++//NGDC_MGCG_CTRL ++#define NGDC_MGCG_CTRL__NGDC_MGCG_EN__MASK 0x00000001L ++#define NGDC_MGCG_CTRL__NGDC_MGCG_MODE__MASK 0x00000002L ++#define NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__MASK 0x000003FCL ++//A2S_MISC_CNTL ++#define A2S_MISC_CNTL__BLKLVL_FOR_MSG__MASK 0x00000003L ++#define A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS__MASK 0x00000004L ++//NGDC_SDP_PORT_CTRL ++#define NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__MASK 0x0000003FL ++//NGDC_RESERVED_0 ++#define NGDC_RESERVED_0__RESERVED__MASK 0xFFFFFFFFL ++//NGDC_RESERVED_1 ++#define NGDC_RESERVED_1__RESERVED__MASK 0xFFFFFFFFL ++//BIF_SDMA0_DOORBELL_RANGE ++#define BIF_SDMA0_DOORBELL_RANGE__OFFSET__MASK 0x00000FFCL ++#define BIF_SDMA0_DOORBELL_RANGE__SIZE__MASK 0x001F0000L ++//BIF_SDMA1_DOORBELL_RANGE ++#define BIF_SDMA1_DOORBELL_RANGE__OFFSET__MASK 0x00000FFCL ++#define BIF_SDMA1_DOORBELL_RANGE__SIZE__MASK 0x001F0000L ++//BIF_IH_DOORBELL_RANGE ++#define BIF_IH_DOORBELL_RANGE__OFFSET__MASK 0x00000FFCL ++#define BIF_IH_DOORBELL_RANGE__SIZE__MASK 0x001F0000L ++//BIF_MMSCH0_DOORBELL_RANGE ++#define BIF_MMSCH0_DOORBELL_RANGE__OFFSET__MASK 0x00000FFCL ++#define BIF_MMSCH0_DOORBELL_RANGE__SIZE__MASK 0x001F0000L ++//BIF_DOORBELL_FENCE_CNTL ++#define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE__MASK 0x00000001L ++//S2A_MISC_CNTL ++#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__MASK 0x00000001L ++#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__MASK 0x00000002L ++#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__MASK 0x00000004L ++//A2S_CNTL2_SEC_CL0 ++#define A2S_CNTL2_SEC_CL0__SECLVL_MAP__MASK 0x00000007L ++//A2S_CNTL2_SEC_CL1 ++#define A2S_CNTL2_SEC_CL1__SECLVL_MAP__MASK 0x00000007L ++//A2S_CNTL2_SEC_CL2 ++#define A2S_CNTL2_SEC_CL2__SECLVL_MAP__MASK 0x00000007L ++//A2S_CNTL2_SEC_CL3 ++#define A2S_CNTL2_SEC_CL3__SECLVL_MAP__MASK 0x00000007L ++//A2S_CNTL2_SEC_CL4 ++#define A2S_CNTL2_SEC_CL4__SECLVL_MAP__MASK 0x00000007L ++ ++ ++// addressBlock: nbif_sion_SIONDEC ++//SION_CL0_RdRsp_BurstTarget_REG0 ++#define SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL ++//SION_CL0_RdRsp_BurstTarget_REG1 ++#define SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL ++//SION_CL0_RdRsp_TimeSlot_REG0 ++#define SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL ++//SION_CL0_RdRsp_TimeSlot_REG1 ++#define SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL ++//SION_CL0_WrRsp_BurstTarget_REG0 ++#define SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL ++//SION_CL0_WrRsp_BurstTarget_REG1 ++#define SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL ++//SION_CL0_WrRsp_TimeSlot_REG0 ++#define SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL ++//SION_CL0_WrRsp_TimeSlot_REG1 ++#define SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL ++//SION_CL0_Req_BurstTarget_REG0 ++#define SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__MASK 0xFFFFFFFFL ++//SION_CL0_Req_BurstTarget_REG1 ++#define SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__MASK 0xFFFFFFFFL ++//SION_CL0_Req_TimeSlot_REG0 ++#define SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__MASK 0xFFFFFFFFL ++//SION_CL0_Req_TimeSlot_REG1 ++#define SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__MASK 0xFFFFFFFFL ++//SION_CL0_ReqPoolCredit_Alloc_REG0 ++#define SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL ++//SION_CL0_ReqPoolCredit_Alloc_REG1 ++#define SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL ++//SION_CL0_DataPoolCredit_Alloc_REG0 ++#define SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL ++//SION_CL0_DataPoolCredit_Alloc_REG1 ++#define SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL ++//SION_CL0_RdRspPoolCredit_Alloc_REG0 ++#define SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL ++//SION_CL0_RdRspPoolCredit_Alloc_REG1 ++#define SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL ++//SION_CL0_WrRspPoolCredit_Alloc_REG0 ++#define SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL ++//SION_CL0_WrRspPoolCredit_Alloc_REG1 ++#define SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL ++//SION_CL1_RdRsp_BurstTarget_REG0 ++#define SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL ++//SION_CL1_RdRsp_BurstTarget_REG1 ++#define SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL ++//SION_CL1_RdRsp_TimeSlot_REG0 ++#define SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL ++//SION_CL1_RdRsp_TimeSlot_REG1 ++#define SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL ++//SION_CL1_WrRsp_BurstTarget_REG0 ++#define SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL ++//SION_CL1_WrRsp_BurstTarget_REG1 ++#define SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL ++//SION_CL1_WrRsp_TimeSlot_REG0 ++#define SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL ++//SION_CL1_WrRsp_TimeSlot_REG1 ++#define SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL ++//SION_CL1_Req_BurstTarget_REG0 ++#define SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__MASK 0xFFFFFFFFL ++//SION_CL1_Req_BurstTarget_REG1 ++#define SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__MASK 0xFFFFFFFFL ++//SION_CL1_Req_TimeSlot_REG0 ++#define SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__MASK 0xFFFFFFFFL ++//SION_CL1_Req_TimeSlot_REG1 ++#define SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__MASK 0xFFFFFFFFL ++//SION_CL1_ReqPoolCredit_Alloc_REG0 ++#define SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL ++//SION_CL1_ReqPoolCredit_Alloc_REG1 ++#define SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL ++//SION_CL1_DataPoolCredit_Alloc_REG0 ++#define SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL ++//SION_CL1_DataPoolCredit_Alloc_REG1 ++#define SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL ++//SION_CL1_RdRspPoolCredit_Alloc_REG0 ++#define SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL ++//SION_CL1_RdRspPoolCredit_Alloc_REG1 ++#define SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL ++//SION_CL1_WrRspPoolCredit_Alloc_REG0 ++#define SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL ++//SION_CL1_WrRspPoolCredit_Alloc_REG1 ++#define SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL ++//SION_CL2_RdRsp_BurstTarget_REG0 ++#define SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL ++//SION_CL2_RdRsp_BurstTarget_REG1 ++#define SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL ++//SION_CL2_RdRsp_TimeSlot_REG0 ++#define SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL ++//SION_CL2_RdRsp_TimeSlot_REG1 ++#define SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL ++//SION_CL2_WrRsp_BurstTarget_REG0 ++#define SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL ++//SION_CL2_WrRsp_BurstTarget_REG1 ++#define SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL ++//SION_CL2_WrRsp_TimeSlot_REG0 ++#define SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL ++//SION_CL2_WrRsp_TimeSlot_REG1 ++#define SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL ++//SION_CL2_Req_BurstTarget_REG0 ++#define SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0__MASK 0xFFFFFFFFL ++//SION_CL2_Req_BurstTarget_REG1 ++#define SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32__MASK 0xFFFFFFFFL ++//SION_CL2_Req_TimeSlot_REG0 ++#define SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0__MASK 0xFFFFFFFFL ++//SION_CL2_Req_TimeSlot_REG1 ++#define SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32__MASK 0xFFFFFFFFL ++//SION_CL2_ReqPoolCredit_Alloc_REG0 ++#define SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL ++//SION_CL2_ReqPoolCredit_Alloc_REG1 ++#define SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL ++//SION_CL2_DataPoolCredit_Alloc_REG0 ++#define SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL ++//SION_CL2_DataPoolCredit_Alloc_REG1 ++#define SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL ++//SION_CL2_RdRspPoolCredit_Alloc_REG0 ++#define SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL ++//SION_CL2_RdRspPoolCredit_Alloc_REG1 ++#define SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL ++//SION_CL2_WrRspPoolCredit_Alloc_REG0 ++#define SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL ++//SION_CL2_WrRspPoolCredit_Alloc_REG1 ++#define SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL ++//SION_CL3_RdRsp_BurstTarget_REG0 ++#define SION_CL3_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL ++//SION_CL3_RdRsp_BurstTarget_REG1 ++#define SION_CL3_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL ++//SION_CL3_RdRsp_TimeSlot_REG0 ++#define SION_CL3_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL ++//SION_CL3_RdRsp_TimeSlot_REG1 ++#define SION_CL3_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL ++//SION_CL3_WrRsp_BurstTarget_REG0 ++#define SION_CL3_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL ++//SION_CL3_WrRsp_BurstTarget_REG1 ++#define SION_CL3_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL ++//SION_CL3_WrRsp_TimeSlot_REG0 ++#define SION_CL3_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL ++//SION_CL3_WrRsp_TimeSlot_REG1 ++#define SION_CL3_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL ++//SION_CL3_Req_BurstTarget_REG0 ++#define SION_CL3_Req_BurstTarget_REG0__Req_BurstTarget_31_0__MASK 0xFFFFFFFFL ++//SION_CL3_Req_BurstTarget_REG1 ++#define SION_CL3_Req_BurstTarget_REG1__Req_BurstTarget_63_32__MASK 0xFFFFFFFFL ++//SION_CL3_Req_TimeSlot_REG0 ++#define SION_CL3_Req_TimeSlot_REG0__Req_TimeSlot_31_0__MASK 0xFFFFFFFFL ++//SION_CL3_Req_TimeSlot_REG1 ++#define SION_CL3_Req_TimeSlot_REG1__Req_TimeSlot_63_32__MASK 0xFFFFFFFFL ++//SION_CL3_ReqPoolCredit_Alloc_REG0 ++#define SION_CL3_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL ++//SION_CL3_ReqPoolCredit_Alloc_REG1 ++#define SION_CL3_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL ++//SION_CL3_DataPoolCredit_Alloc_REG0 ++#define SION_CL3_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL ++//SION_CL3_DataPoolCredit_Alloc_REG1 ++#define SION_CL3_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL ++//SION_CL3_RdRspPoolCredit_Alloc_REG0 ++#define SION_CL3_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL ++//SION_CL3_RdRspPoolCredit_Alloc_REG1 ++#define SION_CL3_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL ++//SION_CL3_WrRspPoolCredit_Alloc_REG0 ++#define SION_CL3_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL ++//SION_CL3_WrRspPoolCredit_Alloc_REG1 ++#define SION_CL3_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL ++//SION_CL4_RdRsp_BurstTarget_REG0 ++#define SION_CL4_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL ++//SION_CL4_RdRsp_BurstTarget_REG1 ++#define SION_CL4_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL ++//SION_CL4_RdRsp_TimeSlot_REG0 ++#define SION_CL4_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL ++//SION_CL4_RdRsp_TimeSlot_REG1 ++#define SION_CL4_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL ++//SION_CL4_WrRsp_BurstTarget_REG0 ++#define SION_CL4_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL ++//SION_CL4_WrRsp_BurstTarget_REG1 ++#define SION_CL4_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL ++//SION_CL4_WrRsp_TimeSlot_REG0 ++#define SION_CL4_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL ++//SION_CL4_WrRsp_TimeSlot_REG1 ++#define SION_CL4_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL ++//SION_CL4_Req_BurstTarget_REG0 ++#define SION_CL4_Req_BurstTarget_REG0__Req_BurstTarget_31_0__MASK 0xFFFFFFFFL ++//SION_CL4_Req_BurstTarget_REG1 ++#define SION_CL4_Req_BurstTarget_REG1__Req_BurstTarget_63_32__MASK 0xFFFFFFFFL ++//SION_CL4_Req_TimeSlot_REG0 ++#define SION_CL4_Req_TimeSlot_REG0__Req_TimeSlot_31_0__MASK 0xFFFFFFFFL ++//SION_CL4_Req_TimeSlot_REG1 ++#define SION_CL4_Req_TimeSlot_REG1__Req_TimeSlot_63_32__MASK 0xFFFFFFFFL ++//SION_CL4_ReqPoolCredit_Alloc_REG0 ++#define SION_CL4_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL ++//SION_CL4_ReqPoolCredit_Alloc_REG1 ++#define SION_CL4_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL ++//SION_CL4_DataPoolCredit_Alloc_REG0 ++#define SION_CL4_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL ++//SION_CL4_DataPoolCredit_Alloc_REG1 ++#define SION_CL4_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL ++//SION_CL4_RdRspPoolCredit_Alloc_REG0 ++#define SION_CL4_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL ++//SION_CL4_RdRspPoolCredit_Alloc_REG1 ++#define SION_CL4_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL ++//SION_CL4_WrRspPoolCredit_Alloc_REG0 ++#define SION_CL4_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL ++//SION_CL4_WrRspPoolCredit_Alloc_REG1 ++#define SION_CL4_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL ++//SION_CL5_RdRsp_BurstTarget_REG0 ++#define SION_CL5_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL ++//SION_CL5_RdRsp_BurstTarget_REG1 ++#define SION_CL5_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL ++//SION_CL5_RdRsp_TimeSlot_REG0 ++#define SION_CL5_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL ++//SION_CL5_RdRsp_TimeSlot_REG1 ++#define SION_CL5_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL ++//SION_CL5_WrRsp_BurstTarget_REG0 ++#define SION_CL5_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL ++//SION_CL5_WrRsp_BurstTarget_REG1 ++#define SION_CL5_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL ++//SION_CL5_WrRsp_TimeSlot_REG0 ++#define SION_CL5_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL ++//SION_CL5_WrRsp_TimeSlot_REG1 ++#define SION_CL5_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL ++//SION_CL5_Req_BurstTarget_REG0 ++#define SION_CL5_Req_BurstTarget_REG0__Req_BurstTarget_31_0__MASK 0xFFFFFFFFL ++//SION_CL5_Req_BurstTarget_REG1 ++#define SION_CL5_Req_BurstTarget_REG1__Req_BurstTarget_63_32__MASK 0xFFFFFFFFL ++//SION_CL5_Req_TimeSlot_REG0 ++#define SION_CL5_Req_TimeSlot_REG0__Req_TimeSlot_31_0__MASK 0xFFFFFFFFL ++//SION_CL5_Req_TimeSlot_REG1 ++#define SION_CL5_Req_TimeSlot_REG1__Req_TimeSlot_63_32__MASK 0xFFFFFFFFL ++//SION_CL5_ReqPoolCredit_Alloc_REG0 ++#define SION_CL5_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL ++//SION_CL5_ReqPoolCredit_Alloc_REG1 ++#define SION_CL5_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL ++//SION_CL5_DataPoolCredit_Alloc_REG0 ++#define SION_CL5_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL ++//SION_CL5_DataPoolCredit_Alloc_REG1 ++#define SION_CL5_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL ++//SION_CL5_RdRspPoolCredit_Alloc_REG0 ++#define SION_CL5_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL ++//SION_CL5_RdRspPoolCredit_Alloc_REG1 ++#define SION_CL5_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL ++//SION_CL5_WrRspPoolCredit_Alloc_REG0 ++#define SION_CL5_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL ++//SION_CL5_WrRspPoolCredit_Alloc_REG1 ++#define SION_CL5_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL ++//SION_CNTL_REG0 ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__MASK 0x00000001L ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__MASK 0x00000002L ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__MASK 0x00000004L ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__MASK 0x00000008L ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__MASK 0x00000010L ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__MASK 0x00000020L ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__MASK 0x00000040L ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__MASK 0x00000080L ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__MASK 0x00000100L ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__MASK 0x00000200L ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__MASK 0x00000400L ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__MASK 0x00000800L ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__MASK 0x00001000L ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__MASK 0x00002000L ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__MASK 0x00004000L ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__MASK 0x00008000L ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__MASK 0x00010000L ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__MASK 0x00020000L ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__MASK 0x00040000L ++#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__MASK 0x00080000L ++//SION_CNTL_REG1 ++#define SION_CNTL_REG1__LIVELOCK_WATCHDOG_THRESHOLD__MASK 0x000000FFL ++#define SION_CNTL_REG1__CG_OFF_HYSTERESIS__MASK 0x0000FF00L ++ ++ ++// addressBlock: syshub_mmreg_direct_syshubdirect ++//SYSHUB_DS_CTRL_SOCCLK ++#define SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000001L ++#define SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000002L ++#define SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000004L ++#define SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000008L ++#define SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000010L ++#define SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000020L ++#define SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000040L ++#define SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000080L ++#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00010000L ++#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00020000L ++#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00040000L ++#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00080000L ++#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00100000L ++#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00200000L ++#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00400000L ++#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00800000L ++#define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x10000000L ++#define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__MASK 0x80000000L ++//SYSHUB_DS_CTRL2_SOCCLK ++#define SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__MASK 0x0000FFFFL ++//SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK ++#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en__MASK 0x00000001L ++#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en__MASK 0x00000002L ++#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__MASK 0x00008000L ++#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en__MASK 0x00010000L ++#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en__MASK 0x00020000L ++//SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK ++#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en__MASK 0x00000001L ++#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en__MASK 0x00000002L ++#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__MASK 0x00008000L ++#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en__MASK 0x00010000L ++#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en__MASK 0x00020000L ++//DMA_CLK0_SW0_SYSHUB_QOS_CNTL ++#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L ++#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL ++#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L ++//DMA_CLK0_SW1_SYSHUB_QOS_CNTL ++#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L ++#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL ++#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L ++//DMA_CLK0_SW0_CL0_CNTL ++#define DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L ++#define DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L ++#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L ++#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L ++#define DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L ++#define DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L ++//DMA_CLK0_SW0_CL1_CNTL ++#define DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L ++#define DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L ++#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L ++#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L ++#define DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L ++#define DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L ++//DMA_CLK0_SW0_CL2_CNTL ++#define DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L ++#define DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L ++#define DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L ++#define DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L ++#define DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L ++#define DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L ++//DMA_CLK0_SW0_CL3_CNTL ++#define DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L ++#define DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L ++#define DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L ++#define DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L ++#define DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L ++#define DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L ++//DMA_CLK0_SW0_CL4_CNTL ++#define DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L ++#define DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L ++#define DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L ++#define DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L ++#define DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L ++#define DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L ++//DMA_CLK0_SW0_CL5_CNTL ++#define DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L ++#define DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L ++#define DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L ++#define DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L ++#define DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L ++#define DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L ++//DMA_CLK0_SW1_CL0_CNTL ++#define DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L ++#define DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L ++#define DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L ++#define DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L ++#define DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L ++#define DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L ++//DMA_CLK0_SW2_CL0_CNTL ++#define DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L ++#define DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L ++#define DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L ++#define DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L ++#define DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L ++#define DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L ++//SYSHUB_CG_CNTL ++#define SYSHUB_CG_CNTL__SYSHUB_CG_EN__MASK 0x00000001L ++#define SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER__MASK 0x0000FF00L ++#define SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER__MASK 0x00FF0000L ++//SYSHUB_TRANS_IDLE ++#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0__MASK 0x00000001L ++#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1__MASK 0x00000002L ++#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2__MASK 0x00000004L ++#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3__MASK 0x00000008L ++#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4__MASK 0x00000010L ++#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5__MASK 0x00000020L ++#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6__MASK 0x00000040L ++#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7__MASK 0x00000080L ++#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8__MASK 0x00000100L ++#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9__MASK 0x00000200L ++#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10__MASK 0x00000400L ++#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11__MASK 0x00000800L ++#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12__MASK 0x00001000L ++#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13__MASK 0x00002000L ++#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14__MASK 0x00004000L ++#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15__MASK 0x00008000L ++#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF__MASK 0x00010000L ++//SYSHUB_HP_TIMER ++#define SYSHUB_HP_TIMER__SYSHUB_HP_TIMER__MASK 0xFFFFFFFFL ++//SYSHUB_SCRATCH ++#define SYSHUB_SCRATCH__SCRATCH__MASK 0xFFFFFFFFL ++//SYSHUB_DS_CTRL_SHUBCLK ++#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000001L ++#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000002L ++#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000004L ++#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000008L ++#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000010L ++#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000020L ++#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000040L ++#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000080L ++#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00010000L ++#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00020000L ++#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00040000L ++#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00080000L ++#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00100000L ++#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00200000L ++#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00400000L ++#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00800000L ++#define SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x10000000L ++#define SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN__MASK 0x80000000L ++//SYSHUB_DS_CTRL2_SHUBCLK ++#define SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER__MASK 0x0000FFFFL ++//SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK ++#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en__MASK 0x00008000L ++#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en__MASK 0x00010000L ++//SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK ++#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en__MASK 0x00008000L ++#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en__MASK 0x00010000L ++//DMA_CLK1_SW0_SYSHUB_QOS_CNTL ++#define DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L ++#define DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL ++#define DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L ++//DMA_CLK1_SW1_SYSHUB_QOS_CNTL ++#define DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L ++#define DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL ++#define DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L ++//DMA_CLK1_SW0_CL0_CNTL ++#define DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L ++#define DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L ++#define DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L ++#define DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L ++#define DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L ++#define DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L ++//DMA_CLK1_SW0_CL1_CNTL ++#define DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L ++#define DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L ++#define DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L ++#define DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L ++#define DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L ++#define DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L ++//DMA_CLK1_SW0_CL2_CNTL ++#define DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L ++#define DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L ++#define DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L ++#define DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L ++#define DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L ++#define DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L ++//DMA_CLK1_SW0_CL3_CNTL ++#define DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L ++#define DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L ++#define DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L ++#define DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L ++#define DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L ++#define DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L ++//DMA_CLK1_SW0_CL4_CNTL ++#define DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L ++#define DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L ++#define DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L ++#define DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L ++#define DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L ++#define DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L ++//DMA_CLK1_SW1_CL0_CNTL ++#define DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L ++#define DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L ++#define DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L ++#define DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L ++#define DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L ++#define DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L ++//DMA_CLK1_SW1_CL1_CNTL ++#define DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L ++#define DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L ++#define DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L ++#define DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L ++#define DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L ++#define DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L ++//DMA_CLK1_SW1_CL2_CNTL ++#define DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L ++#define DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L ++#define DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L ++#define DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L ++#define DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L ++#define DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L ++//DMA_CLK1_SW1_CL3_CNTL ++#define DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L ++#define DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L ++#define DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L ++#define DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L ++#define DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L ++#define DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L ++//DMA_CLK1_SW1_CL4_CNTL ++#define DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L ++#define DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L ++#define DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L ++#define DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L ++#define DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L ++#define DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L ++ ++ ++// addressBlock: gdc_ras_gdc_ras_regblk ++//GDC_RAS_LEAF0_CTRL ++#define GDC_RAS_LEAF0_CTRL__POISON_DET_EN__MASK 0x00000001L ++#define GDC_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L ++#define GDC_RAS_LEAF0_CTRL__POISON_STALL_EN__MASK 0x00000004L ++#define GDC_RAS_LEAF0_CTRL__PARITY_DET_EN__MASK 0x00000010L ++#define GDC_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L ++#define GDC_RAS_LEAF0_CTRL__PARITY_STALL_EN__MASK 0x00000040L ++#define GDC_RAS_LEAF0_CTRL__ERR_EVENT_RECV__MASK 0x00010000L ++#define GDC_RAS_LEAF0_CTRL__LINK_DIS_RECV__MASK 0x00020000L ++#define GDC_RAS_LEAF0_CTRL__POISON_ERR_DET__MASK 0x00040000L ++#define GDC_RAS_LEAF0_CTRL__PARITY_ERR_DET__MASK 0x00080000L ++#define GDC_RAS_LEAF0_CTRL__ERR_EVENT_SENT__MASK 0x00100000L ++#define GDC_RAS_LEAF0_CTRL__EGRESS_STALLED__MASK 0x00200000L ++//GDC_RAS_LEAF1_CTRL ++#define GDC_RAS_LEAF1_CTRL__POISON_DET_EN__MASK 0x00000001L ++#define GDC_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L ++#define GDC_RAS_LEAF1_CTRL__POISON_STALL_EN__MASK 0x00000004L ++#define GDC_RAS_LEAF1_CTRL__PARITY_DET_EN__MASK 0x00000010L ++#define GDC_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L ++#define GDC_RAS_LEAF1_CTRL__PARITY_STALL_EN__MASK 0x00000040L ++#define GDC_RAS_LEAF1_CTRL__ERR_EVENT_RECV__MASK 0x00010000L ++#define GDC_RAS_LEAF1_CTRL__LINK_DIS_RECV__MASK 0x00020000L ++#define GDC_RAS_LEAF1_CTRL__POISON_ERR_DET__MASK 0x00040000L ++#define GDC_RAS_LEAF1_CTRL__PARITY_ERR_DET__MASK 0x00080000L ++#define GDC_RAS_LEAF1_CTRL__ERR_EVENT_SENT__MASK 0x00100000L ++#define GDC_RAS_LEAF1_CTRL__EGRESS_STALLED__MASK 0x00200000L ++//GDC_RAS_LEAF2_CTRL ++#define GDC_RAS_LEAF2_CTRL__POISON_DET_EN__MASK 0x00000001L ++#define GDC_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L ++#define GDC_RAS_LEAF2_CTRL__POISON_STALL_EN__MASK 0x00000004L ++#define GDC_RAS_LEAF2_CTRL__PARITY_DET_EN__MASK 0x00000010L ++#define GDC_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L ++#define GDC_RAS_LEAF2_CTRL__PARITY_STALL_EN__MASK 0x00000040L ++#define GDC_RAS_LEAF2_CTRL__ERR_EVENT_RECV__MASK 0x00010000L ++#define GDC_RAS_LEAF2_CTRL__LINK_DIS_RECV__MASK 0x00020000L ++#define GDC_RAS_LEAF2_CTRL__POISON_ERR_DET__MASK 0x00040000L ++#define GDC_RAS_LEAF2_CTRL__PARITY_ERR_DET__MASK 0x00080000L ++#define GDC_RAS_LEAF2_CTRL__ERR_EVENT_SENT__MASK 0x00100000L ++#define GDC_RAS_LEAF2_CTRL__EGRESS_STALLED__MASK 0x00200000L ++//GDC_RAS_LEAF3_CTRL ++#define GDC_RAS_LEAF3_CTRL__POISON_DET_EN__MASK 0x00000001L ++#define GDC_RAS_LEAF3_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L ++#define GDC_RAS_LEAF3_CTRL__POISON_STALL_EN__MASK 0x00000004L ++#define GDC_RAS_LEAF3_CTRL__PARITY_DET_EN__MASK 0x00000010L ++#define GDC_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L ++#define GDC_RAS_LEAF3_CTRL__PARITY_STALL_EN__MASK 0x00000040L ++#define GDC_RAS_LEAF3_CTRL__ERR_EVENT_RECV__MASK 0x00010000L ++#define GDC_RAS_LEAF3_CTRL__LINK_DIS_RECV__MASK 0x00020000L ++#define GDC_RAS_LEAF3_CTRL__POISON_ERR_DET__MASK 0x00040000L ++#define GDC_RAS_LEAF3_CTRL__PARITY_ERR_DET__MASK 0x00080000L ++#define GDC_RAS_LEAF3_CTRL__ERR_EVENT_SENT__MASK 0x00100000L ++#define GDC_RAS_LEAF3_CTRL__EGRESS_STALLED__MASK 0x00200000L ++//GDC_RAS_LEAF4_CTRL ++#define GDC_RAS_LEAF4_CTRL__POISON_DET_EN__MASK 0x00000001L ++#define GDC_RAS_LEAF4_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L ++#define GDC_RAS_LEAF4_CTRL__POISON_STALL_EN__MASK 0x00000004L ++#define GDC_RAS_LEAF4_CTRL__PARITY_DET_EN__MASK 0x00000010L ++#define GDC_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L ++#define GDC_RAS_LEAF4_CTRL__PARITY_STALL_EN__MASK 0x00000040L ++#define GDC_RAS_LEAF4_CTRL__ERR_EVENT_RECV__MASK 0x00010000L ++#define GDC_RAS_LEAF4_CTRL__LINK_DIS_RECV__MASK 0x00020000L ++#define GDC_RAS_LEAF4_CTRL__POISON_ERR_DET__MASK 0x00040000L ++#define GDC_RAS_LEAF4_CTRL__PARITY_ERR_DET__MASK 0x00080000L ++#define GDC_RAS_LEAF4_CTRL__ERR_EVENT_SENT__MASK 0x00100000L ++#define GDC_RAS_LEAF4_CTRL__EGRESS_STALLED__MASK 0x00200000L ++//GDC_RAS_LEAF5_CTRL ++#define GDC_RAS_LEAF5_CTRL__POISON_DET_EN__MASK 0x00000001L ++#define GDC_RAS_LEAF5_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L ++#define GDC_RAS_LEAF5_CTRL__POISON_STALL_EN__MASK 0x00000004L ++#define GDC_RAS_LEAF5_CTRL__PARITY_DET_EN__MASK 0x00000010L ++#define GDC_RAS_LEAF5_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L ++#define GDC_RAS_LEAF5_CTRL__PARITY_STALL_EN__MASK 0x00000040L ++#define GDC_RAS_LEAF5_CTRL__ERR_EVENT_RECV__MASK 0x00010000L ++#define GDC_RAS_LEAF5_CTRL__LINK_DIS_RECV__MASK 0x00020000L ++#define GDC_RAS_LEAF5_CTRL__POISON_ERR_DET__MASK 0x00040000L ++#define GDC_RAS_LEAF5_CTRL__PARITY_ERR_DET__MASK 0x00080000L ++#define GDC_RAS_LEAF5_CTRL__ERR_EVENT_SENT__MASK 0x00100000L ++#define GDC_RAS_LEAF5_CTRL__EGRESS_STALLED__MASK 0x00200000L ++ ++ ++// addressBlock: gdc_rst_GDCRST_DEC ++//SHUB_PF_FLR_RST ++#define SHUB_PF_FLR_RST__PF0_FLR_RST__MASK 0x00000001L ++#define SHUB_PF_FLR_RST__PF1_FLR_RST__MASK 0x00000002L ++#define SHUB_PF_FLR_RST__PF2_FLR_RST__MASK 0x00000004L ++#define SHUB_PF_FLR_RST__PF3_FLR_RST__MASK 0x00000008L ++#define SHUB_PF_FLR_RST__PF4_FLR_RST__MASK 0x00000010L ++#define SHUB_PF_FLR_RST__PF5_FLR_RST__MASK 0x00000020L ++#define SHUB_PF_FLR_RST__PF6_FLR_RST__MASK 0x00000040L ++#define SHUB_PF_FLR_RST__PF7_FLR_RST__MASK 0x00000080L ++//SHUB_GFX_DRV_MODE1_RST ++#define SHUB_GFX_DRV_MODE1_RST__GFX_DRV_MODE1_RST__MASK 0x00000001L ++//SHUB_LINK_RESET ++#define SHUB_LINK_RESET__LINK_RESET__MASK 0x00000001L ++//SHUB_PF0_VF_FLR_RST ++#define SHUB_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__MASK 0x00000001L ++#define SHUB_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__MASK 0x00000002L ++#define SHUB_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__MASK 0x00000004L ++#define SHUB_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__MASK 0x00000008L ++#define SHUB_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__MASK 0x00000010L ++#define SHUB_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__MASK 0x00000020L ++#define SHUB_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__MASK 0x00000040L ++#define SHUB_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__MASK 0x00000080L ++#define SHUB_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__MASK 0x00000100L ++#define SHUB_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__MASK 0x00000200L ++#define SHUB_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__MASK 0x00000400L ++#define SHUB_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__MASK 0x00000800L ++#define SHUB_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__MASK 0x00001000L ++#define SHUB_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__MASK 0x00002000L ++#define SHUB_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__MASK 0x00004000L ++#define SHUB_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__MASK 0x00008000L ++#define SHUB_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__MASK 0x80000000L ++//SHUB_HARD_RST_CTRL ++#define SHUB_HARD_RST_CTRL__COR_RESET_EN__MASK 0x00000001L ++#define SHUB_HARD_RST_CTRL__REG_RESET_EN__MASK 0x00000002L ++#define SHUB_HARD_RST_CTRL__STY_RESET_EN__MASK 0x00000004L ++#define SHUB_HARD_RST_CTRL__NIC400_RESET_EN__MASK 0x00000008L ++#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN__MASK 0x00000010L ++//SHUB_SOFT_RST_CTRL ++#define SHUB_SOFT_RST_CTRL__COR_RESET_EN__MASK 0x00000001L ++#define SHUB_SOFT_RST_CTRL__REG_RESET_EN__MASK 0x00000002L ++#define SHUB_SOFT_RST_CTRL__STY_RESET_EN__MASK 0x00000004L ++#define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN__MASK 0x00000008L ++#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN__MASK 0x00000010L ++//SHUB_SDP_PORT_RST ++#define SHUB_SDP_PORT_RST__SDP_PORT_RST__MASK 0x00000001L ++ ++ ++// addressBlock: bif_bx_pf_SYSDEC ++//SBIOS_SCRATCH_0 ++#define SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__MASK 0xFFFFFFFFL ++//SBIOS_SCRATCH_1 ++#define SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__MASK 0xFFFFFFFFL ++//SBIOS_SCRATCH_2 ++#define SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__MASK 0xFFFFFFFFL ++//SBIOS_SCRATCH_3 ++#define SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__MASK 0xFFFFFFFFL ++//BIOS_SCRATCH_0 ++#define BIOS_SCRATCH_0__BIOS_SCRATCH_0__MASK 0xFFFFFFFFL ++//BIOS_SCRATCH_1 ++#define BIOS_SCRATCH_1__BIOS_SCRATCH_1__MASK 0xFFFFFFFFL ++//BIOS_SCRATCH_2 ++#define BIOS_SCRATCH_2__BIOS_SCRATCH_2__MASK 0xFFFFFFFFL ++//BIOS_SCRATCH_3 ++#define BIOS_SCRATCH_3__BIOS_SCRATCH_3__MASK 0xFFFFFFFFL ++//BIOS_SCRATCH_4 ++#define BIOS_SCRATCH_4__BIOS_SCRATCH_4__MASK 0xFFFFFFFFL ++//BIOS_SCRATCH_5 ++#define BIOS_SCRATCH_5__BIOS_SCRATCH_5__MASK 0xFFFFFFFFL ++//BIOS_SCRATCH_6 ++#define BIOS_SCRATCH_6__BIOS_SCRATCH_6__MASK 0xFFFFFFFFL ++//BIOS_SCRATCH_7 ++#define BIOS_SCRATCH_7__BIOS_SCRATCH_7__MASK 0xFFFFFFFFL ++//BIOS_SCRATCH_8 ++#define BIOS_SCRATCH_8__BIOS_SCRATCH_8__MASK 0xFFFFFFFFL ++//BIOS_SCRATCH_9 ++#define BIOS_SCRATCH_9__BIOS_SCRATCH_9__MASK 0xFFFFFFFFL ++//BIOS_SCRATCH_10 ++#define BIOS_SCRATCH_10__BIOS_SCRATCH_10__MASK 0xFFFFFFFFL ++//BIOS_SCRATCH_11 ++#define BIOS_SCRATCH_11__BIOS_SCRATCH_11__MASK 0xFFFFFFFFL ++//BIOS_SCRATCH_12 ++#define BIOS_SCRATCH_12__BIOS_SCRATCH_12__MASK 0xFFFFFFFFL ++//BIOS_SCRATCH_13 ++#define BIOS_SCRATCH_13__BIOS_SCRATCH_13__MASK 0xFFFFFFFFL ++//BIOS_SCRATCH_14 ++#define BIOS_SCRATCH_14__BIOS_SCRATCH_14__MASK 0xFFFFFFFFL ++//BIOS_SCRATCH_15 ++#define BIOS_SCRATCH_15__BIOS_SCRATCH_15__MASK 0xFFFFFFFFL ++//BIF_RLC_INTR_CNTL ++#define BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__MASK 0x00000001L ++#define BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__MASK 0x00000002L ++#define BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__MASK 0x00000004L ++#define BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__MASK 0x00000008L ++//BIF_VCE_INTR_CNTL ++#define BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__MASK 0x00000001L ++#define BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__MASK 0x00000002L ++#define BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__MASK 0x00000004L ++#define BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__MASK 0x00000008L ++//BIF_UVD_INTR_CNTL ++#define BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__MASK 0x00000001L ++#define BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__MASK 0x00000002L ++#define BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__MASK 0x00000004L ++#define BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__MASK 0x00000008L ++//GFX_MMIOREG_CAM_ADDR0 ++#define GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__MASK 0x000FFFFFL ++//GFX_MMIOREG_CAM_REMAP_ADDR0 ++#define GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__MASK 0x000FFFFFL ++//GFX_MMIOREG_CAM_ADDR1 ++#define GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__MASK 0x000FFFFFL ++//GFX_MMIOREG_CAM_REMAP_ADDR1 ++#define GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__MASK 0x000FFFFFL ++//GFX_MMIOREG_CAM_ADDR2 ++#define GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__MASK 0x000FFFFFL ++//GFX_MMIOREG_CAM_REMAP_ADDR2 ++#define GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__MASK 0x000FFFFFL ++//GFX_MMIOREG_CAM_ADDR3 ++#define GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__MASK 0x000FFFFFL ++//GFX_MMIOREG_CAM_REMAP_ADDR3 ++#define GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__MASK 0x000FFFFFL ++//GFX_MMIOREG_CAM_ADDR4 ++#define GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__MASK 0x000FFFFFL ++//GFX_MMIOREG_CAM_REMAP_ADDR4 ++#define GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__MASK 0x000FFFFFL ++//GFX_MMIOREG_CAM_ADDR5 ++#define GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__MASK 0x000FFFFFL ++//GFX_MMIOREG_CAM_REMAP_ADDR5 ++#define GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__MASK 0x000FFFFFL ++//GFX_MMIOREG_CAM_ADDR6 ++#define GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__MASK 0x000FFFFFL ++//GFX_MMIOREG_CAM_REMAP_ADDR6 ++#define GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__MASK 0x000FFFFFL ++//GFX_MMIOREG_CAM_ADDR7 ++#define GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__MASK 0x000FFFFFL ++//GFX_MMIOREG_CAM_REMAP_ADDR7 ++#define GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__MASK 0x000FFFFFL ++//GFX_MMIOREG_CAM_CNTL ++#define GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__MASK 0x000000FFL ++//GFX_MMIOREG_CAM_ZERO_CPL ++#define GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__MASK 0xFFFFFFFFL ++//GFX_MMIOREG_CAM_ONE_CPL ++#define GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__MASK 0xFFFFFFFFL ++//GFX_MMIOREG_CAM_PROGRAMMABLE_CPL ++#define GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__MASK 0xFFFFFFFFL ++ ++ ++// addressBlock: bif_bx_pf_SYSPFVFDEC ++//MM_INDEX ++#define MM_INDEX__MM_OFFSET__MASK 0x7FFFFFFFL ++#define MM_INDEX__MM_APER__MASK 0x80000000L ++//MM_DATA ++#define MM_DATA__MM_DATA__MASK 0xFFFFFFFFL ++//MM_INDEX_HI ++#define MM_INDEX_HI__MM_OFFSET_HI__MASK 0xFFFFFFFFL ++//SYSHUB_INDEX_OVLP ++#define SYSHUB_INDEX_OVLP__SYSHUB_OFFSET__MASK 0x003FFFFFL ++//SYSHUB_DATA_OVLP ++#define SYSHUB_DATA_OVLP__SYSHUB_DATA__MASK 0xFFFFFFFFL ++//PCIE_INDEX ++#define PCIE_INDEX__PCIE_INDEX__MASK 0xFFFFFFFFL ++//PCIE_DATA ++#define PCIE_DATA__PCIE_DATA__MASK 0xFFFFFFFFL ++//PCIE_INDEX2 ++#define PCIE_INDEX2__PCIE_INDEX2__MASK 0xFFFFFFFFL ++//PCIE_DATA2 ++#define PCIE_DATA2__PCIE_DATA2__MASK 0xFFFFFFFFL ++ ++ ++// addressBlock: rcc_dwn_BIFDEC1 ++//DN_PCIE_RESERVED ++#define DN_PCIE_RESERVED__PCIE_RESERVED__MASK 0xFFFFFFFFL ++//DN_PCIE_SCRATCH ++#define DN_PCIE_SCRATCH__PCIE_SCRATCH__MASK 0xFFFFFFFFL ++//DN_PCIE_CNTL ++#define DN_PCIE_CNTL__HWINIT_WR_LOCK__MASK 0x00000001L ++#define DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__MASK 0x00000080L ++#define DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__MASK 0x40000000L ++//DN_PCIE_CONFIG_CNTL ++#define DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__MASK 0x06000000L ++//DN_PCIE_RX_CNTL2 ++#define DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__MASK 0x70000000L ++//DN_PCIE_BUS_CNTL ++#define DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__MASK 0x00000080L ++#define DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__MASK 0x00000100L ++//DN_PCIE_CFG_CNTL ++#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__MASK 0x00000001L ++#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__MASK 0x00000002L ++#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__MASK 0x00000004L ++//DN_PCIE_STRAP_F0 ++#define DN_PCIE_STRAP_F0__STRAP_F0_EN__MASK 0x00000001L ++#define DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__MASK 0x00020000L ++#define DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__MASK 0x00E00000L ++//DN_PCIE_STRAP_MISC ++#define DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__MASK 0x01000000L ++#define DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__MASK 0x20000000L ++//DN_PCIE_STRAP_MISC2 ++#define DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__MASK 0x00000004L ++ ++ ++// addressBlock: rcc_dwnp_BIFDEC1 ++//PCIEP_RESERVED ++#define PCIEP_RESERVED__PCIEP_RESERVED__MASK 0xFFFFFFFFL ++//PCIEP_SCRATCH ++#define PCIEP_SCRATCH__PCIEP_SCRATCH__MASK 0xFFFFFFFFL ++//PCIE_ERR_CNTL ++#define PCIE_ERR_CNTL__ERR_REPORTING_DIS__MASK 0x00000001L ++#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__MASK 0x00000700L ++#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__MASK 0x00000800L ++#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__MASK 0x00020000L ++//PCIE_RX_CNTL ++#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__MASK 0x00000100L ++#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__MASK 0x00000200L ++#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__MASK 0x00100000L ++#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__MASK 0x00200000L ++#define PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__MASK 0x08000000L ++//PCIE_LC_SPEED_CNTL ++#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__MASK 0x00000001L ++#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__MASK 0x00000002L ++//PCIE_LC_CNTL2 ++#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__MASK 0x08000000L ++//PCIEP_STRAP_MISC ++#define PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__MASK 0x00000400L ++//LTR_MSG_INFO_FROM_EP ++#define LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__MASK 0xFFFFFFFFL ++ ++ ++// addressBlock: rcc_ep_BIFDEC1 ++//EP_PCIE_SCRATCH ++#define EP_PCIE_SCRATCH__PCIE_SCRATCH__MASK 0xFFFFFFFFL ++//EP_PCIE_CNTL ++#define EP_PCIE_CNTL__UR_ERR_REPORT_DIS__MASK 0x00000080L ++#define EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__MASK 0x00000100L ++#define EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__MASK 0x40000000L ++//EP_PCIE_INT_CNTL ++#define EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__MASK 0x00000001L ++#define EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__MASK 0x00000002L ++#define EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__MASK 0x00000004L ++#define EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__MASK 0x00000008L ++#define EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__MASK 0x00000010L ++#define EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__MASK 0x00000040L ++//EP_PCIE_INT_STATUS ++#define EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__MASK 0x00000001L ++#define EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__MASK 0x00000002L ++#define EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__MASK 0x00000004L ++#define EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__MASK 0x00000008L ++#define EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__MASK 0x00000010L ++#define EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__MASK 0x00000040L ++//EP_PCIE_RX_CNTL2 ++#define EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__MASK 0x00000001L ++//EP_PCIE_BUS_CNTL ++#define EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__MASK 0x00000080L ++//EP_PCIE_CFG_CNTL ++#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__MASK 0x00000001L ++#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__MASK 0x00000002L ++#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__MASK 0x00000004L ++//EP_PCIE_OBFF_CNTL ++#define EP_PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE__MASK 0x00000001L ++#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN__MASK 0x00000002L ++#define EP_PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE__MASK 0x00000004L ++#define EP_PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE__MASK 0x00000008L ++#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH__MASK 0x000000F0L ++#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH__MASK 0x00000F00L ++#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD__MASK 0x0000F000L ++#define EP_PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE__MASK 0x00010000L ++#define EP_PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE__MASK 0x00020000L ++#define EP_PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE__MASK 0x00040000L ++#define EP_PCIE_OBFF_CNTL__TX_OBFF_ACCEPT_IN_NOND0__MASK 0x00080000L ++#define EP_PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE__MASK 0x00F00000L ++//EP_PCIE_TX_LTR_CNTL ++#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__MASK 0x00000007L ++#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__MASK 0x00000038L ++#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__MASK 0x00000040L ++#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__MASK 0x00000380L ++#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__MASK 0x00001C00L ++#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__MASK 0x00002000L ++#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__MASK 0x00004000L ++#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__MASK 0x00008000L ++#define EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__MASK 0x00010000L ++//EP_PCIE_STRAP_MISC ++#define EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__MASK 0x20000000L ++//EP_PCIE_STRAP_MISC2 ++#define EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__MASK 0x00000010L ++//EP_PCIE_STRAP_PI ++//EP_PCIE_F0_DPA_CAP ++#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__MASK 0x00000300L ++#define EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__MASK 0x00003000L ++#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__MASK 0x00FF0000L ++#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__MASK 0xFF000000L ++//EP_PCIE_F0_DPA_LATENCY_INDICATOR ++#define EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__MASK 0xFFL ++//EP_PCIE_F0_DPA_CNTL ++#define EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__MASK 0x001FL ++#define EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__MASK 0x0100L ++//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 ++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__MASK 0xFFL ++//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 ++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__MASK 0xFFL ++//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 ++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__MASK 0xFFL ++//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 ++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__MASK 0xFFL ++//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 ++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__MASK 0xFFL ++//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 ++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__MASK 0xFFL ++//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 ++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__MASK 0xFFL ++//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 ++#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__MASK 0xFFL ++//EP_PCIE_PME_CONTROL ++#define EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__MASK 0x1FL ++//EP_PCIEP_RESERVED ++#define EP_PCIEP_RESERVED__PCIEP_RESERVED__MASK 0xFFFFFFFFL ++//EP_PCIE_TX_CNTL ++#define EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__MASK 0x00000C00L ++#define EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__MASK 0x00003000L ++#define EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__MASK 0x01000000L ++#define EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__MASK 0x02000000L ++#define EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__MASK 0x04000000L ++//EP_PCIE_TX_REQUESTER_ID ++#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__MASK 0x00000007L ++#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__MASK 0x000000F8L ++#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__MASK 0x0000FF00L ++//EP_PCIE_ERR_CNTL ++#define EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__MASK 0x00000001L ++#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__MASK 0x00000700L ++#define EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__MASK 0x00020000L ++#define EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__MASK 0x00040000L ++#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__MASK 0x01000000L ++#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__MASK 0x02000000L ++#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__MASK 0x04000000L ++#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__MASK 0x08000000L ++#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__MASK 0x10000000L ++#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__MASK 0x20000000L ++#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__MASK 0x40000000L ++#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__MASK 0x80000000L ++//EP_PCIE_RX_CNTL ++#define EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__MASK 0x00000100L ++#define EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__MASK 0x00000200L ++#define EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__MASK 0x00100000L ++#define EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__MASK 0x00200000L ++#define EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__MASK 0x00400000L ++#define EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__MASK 0x01000000L ++#define EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__MASK 0x02000000L ++#define EP_PCIE_RX_CNTL__RX_TPH_DIS__MASK 0x04000000L ++//EP_PCIE_LC_SPEED_CNTL ++#define EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__MASK 0x00000001L ++#define EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__MASK 0x00000002L ++ ++ ++// addressBlock: bif_bx_pf_BIFDEC1 ++//BIF_MM_INDACCESS_CNTL ++#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__MASK 0x00000002L ++//BUS_CNTL ++#define BUS_CNTL__PMI_INT_DIS_EP__MASK 0x00000008L ++#define BUS_CNTL__PMI_INT_DIS_DN__MASK 0x00000010L ++#define BUS_CNTL__PMI_INT_DIS_SWUS__MASK 0x00000020L ++#define BUS_CNTL__VGA_REG_COHERENCY_DIS__MASK 0x00000040L ++#define BUS_CNTL__VGA_MEM_COHERENCY_DIS__MASK 0x00000080L ++#define BUS_CNTL__SET_AZ_TC__MASK 0x00001C00L ++#define BUS_CNTL__SET_MC_TC__MASK 0x0000E000L ++#define BUS_CNTL__ZERO_BE_WR_EN__MASK 0x00010000L ++#define BUS_CNTL__ZERO_BE_RD_EN__MASK 0x00020000L ++#define BUS_CNTL__RD_STALL_IO_WR__MASK 0x00040000L ++#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__MASK 0x00080000L ++#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__MASK 0x00100000L ++#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__MASK 0x00200000L ++#define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__MASK 0x00400000L ++#define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__MASK 0x00800000L ++#define BUS_CNTL__UR_OVRD_FOR_ECRC_EN__MASK 0x01000000L ++//BIF_SCRATCH0 ++#define BIF_SCRATCH0__BIF_SCRATCH0__MASK 0xFFFFFFFFL ++//BIF_SCRATCH1 ++#define BIF_SCRATCH1__BIF_SCRATCH1__MASK 0xFFFFFFFFL ++//BX_RESET_EN ++#define BX_RESET_EN__COR_RESET_EN__MASK 0x00000001L ++#define BX_RESET_EN__REG_RESET_EN__MASK 0x00000002L ++#define BX_RESET_EN__STY_RESET_EN__MASK 0x00000004L ++#define BX_RESET_EN__FLR_TWICE_EN__MASK 0x00000100L ++#define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__MASK 0x00010000L ++//MM_CFGREGS_CNTL ++#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__MASK 0x00000007L ++#define MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__MASK 0x000000C0L ++#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__MASK 0x80000000L ++//BX_RESET_CNTL ++#define BX_RESET_CNTL__LINK_TRAIN_EN__MASK 0x00000001L ++//INTERRUPT_CNTL ++#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__MASK 0x00000001L ++#define INTERRUPT_CNTL__IH_DUMMY_RD_EN__MASK 0x00000002L ++#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__MASK 0x00000008L ++#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__MASK 0x000000F0L ++#define INTERRUPT_CNTL__GEN_IH_INT_EN__MASK 0x00000100L ++#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__MASK 0x00008000L ++//INTERRUPT_CNTL2 ++#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__MASK 0xFFFFFFFFL ++//CLKREQB_PAD_CNTL ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__MASK 0x00000001L ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__MASK 0x00000002L ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__MASK 0x00000004L ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__MASK 0x00000018L ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__MASK 0x00000020L ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__MASK 0x00000040L ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__MASK 0x00000080L ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__MASK 0x00000100L ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__MASK 0x00000200L ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__MASK 0x00000400L ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__MASK 0x00000800L ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__MASK 0x00001000L ++#define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__MASK 0x00002000L ++#define CLKREQB_PAD_CNTL__CLKREQB_PERF_COUNTER_UPPER__MASK 0xFF000000L ++//CLKREQB_PERF_COUNTER ++#define CLKREQB_PERF_COUNTER__CLKREQB_PERF_COUNTER_LOWER__MASK 0xFFFFFFFFL ++//BIF_CLK_CTRL ++#define BIF_CLK_CTRL__BIF_XSTCLK_READY__MASK 0x00000001L ++#define BIF_CLK_CTRL__BACO_XSTCLK_SWITCH_BYPASS__MASK 0x00000002L ++//BIF_FEATURES_CONTROL_MISC ++#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__MASK 0x00000001L ++#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__MASK 0x00000002L ++#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__MASK 0x00000004L ++#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__MASK 0x00000008L ++#define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS__MASK 0x00000200L ++#define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS__MASK 0x00000400L ++#define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__MASK 0x00000800L ++#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__MASK 0x00001000L ++#define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__MASK 0x00002000L ++#define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__MASK 0x00008000L ++#define BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS__MASK 0x00020000L ++#define BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS__MASK 0x00040000L ++#define BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__MASK 0x01000000L ++//BIF_DOORBELL_CNTL ++#define BIF_DOORBELL_CNTL__SELF_RING_DIS__MASK 0x00000001L ++#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__MASK 0x00000002L ++#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__MASK 0x00000004L ++#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__MASK 0x00000008L ++#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__MASK 0x00000010L ++#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__MASK 0x01000000L ++#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__MASK 0x02000000L ++#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__MASK 0x04000000L ++#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__MASK 0x08000000L ++//BIF_DOORBELL_INT_CNTL ++#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__MASK 0x00000001L ++#define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS__MASK 0x00000002L ++#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__MASK 0x00010000L ++#define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR__MASK 0x00020000L ++//BIF_SLVARB_MODE ++#define BIF_SLVARB_MODE__SLVARB_MODE__MASK 0x00000003L ++//BIF_FB_EN ++#define BIF_FB_EN__FB_READ_EN__MASK 0x00000001L ++#define BIF_FB_EN__FB_WRITE_EN__MASK 0x00000002L ++//BIF_BUSY_DELAY_CNTR ++#define BIF_BUSY_DELAY_CNTR__DELAY_CNT__MASK 0x0000003FL ++//BIF_PERFMON_CNTL ++#define BIF_PERFMON_CNTL__PERFCOUNTER_EN__MASK 0x00000001L ++#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0__MASK 0x00000002L ++#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__MASK 0x00000004L ++#define BIF_PERFMON_CNTL__PERF_SEL0__MASK 0x00001F00L ++#define BIF_PERFMON_CNTL__PERF_SEL1__MASK 0x0003E000L ++//BIF_PERFCOUNTER0_RESULT ++#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT__MASK 0xFFFFFFFFL ++//BIF_PERFCOUNTER1_RESULT ++#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT__MASK 0xFFFFFFFFL ++//BIF_MST_TRANS_PENDING_VF ++#define BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__MASK 0x0000FFFFL ++//BIF_SLV_TRANS_PENDING_VF ++#define BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__MASK 0x0000FFFFL ++//BACO_CNTL ++#define BACO_CNTL__BACO_EN__MASK 0x00000001L ++#define BACO_CNTL__BACO_BIF_LCLK_SWITCH__MASK 0x00000002L ++#define BACO_CNTL__BACO_DUMMY_EN__MASK 0x00000004L ++#define BACO_CNTL__BACO_POWER_OFF__MASK 0x00000008L ++#define BACO_CNTL__BACO_DSTATE_BYPASS__MASK 0x00000020L ++#define BACO_CNTL__BACO_RST_INTR_MASK__MASK 0x00000040L ++#define BACO_CNTL__BACO_MODE__MASK 0x00000100L ++#define BACO_CNTL__RCU_BIF_CONFIG_DONE__MASK 0x00000200L ++#define BACO_CNTL__BACO_AUTO_EXIT__MASK 0x80000000L ++//BIF_BACO_EXIT_TIME0 ++#define BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__MASK 0x000FFFFFL ++//BIF_BACO_EXIT_TIMER1 ++#define BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__MASK 0x000FFFFFL ++#define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__MASK 0x04000000L ++#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__MASK 0x08000000L ++#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__MASK 0x10000000L ++#define BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__MASK 0x60000000L ++#define BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__MASK 0x80000000L ++//BIF_BACO_EXIT_TIMER2 ++#define BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__MASK 0x000FFFFFL ++//BIF_BACO_EXIT_TIMER3 ++#define BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__MASK 0x000FFFFFL ++//BIF_BACO_EXIT_TIMER4 ++#define BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__MASK 0x000FFFFFL ++//MEM_TYPE_CNTL ++#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__MASK 0x00000001L ++//SMU_BIF_VDDGFX_PWR_STATUS ++#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__MASK 0x00000001L ++//BIF_VDDGFX_GFX0_LOWER ++#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__MASK 0x0003FFFCL ++#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__MASK 0x40000000L ++#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__MASK 0x80000000L ++//BIF_VDDGFX_GFX0_UPPER ++#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__MASK 0x0003FFFCL ++//BIF_VDDGFX_GFX1_LOWER ++#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__MASK 0x0003FFFCL ++#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__MASK 0x40000000L ++#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__MASK 0x80000000L ++//BIF_VDDGFX_GFX1_UPPER ++#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__MASK 0x0003FFFCL ++//BIF_VDDGFX_GFX2_LOWER ++#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__MASK 0x0003FFFCL ++#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__MASK 0x40000000L ++#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__MASK 0x80000000L ++//BIF_VDDGFX_GFX2_UPPER ++#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__MASK 0x0003FFFCL ++//BIF_VDDGFX_GFX3_LOWER ++#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__MASK 0x0003FFFCL ++#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__MASK 0x40000000L ++#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__MASK 0x80000000L ++//BIF_VDDGFX_GFX3_UPPER ++#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__MASK 0x0003FFFCL ++//BIF_VDDGFX_GFX4_LOWER ++#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__MASK 0x0003FFFCL ++#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__MASK 0x40000000L ++#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__MASK 0x80000000L ++//BIF_VDDGFX_GFX4_UPPER ++#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__MASK 0x0003FFFCL ++//BIF_VDDGFX_GFX5_LOWER ++#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__MASK 0x0003FFFCL ++#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__MASK 0x40000000L ++#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__MASK 0x80000000L ++//BIF_VDDGFX_GFX5_UPPER ++#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__MASK 0x0003FFFCL ++//BIF_VDDGFX_RSV1_LOWER ++#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__MASK 0x0003FFFCL ++#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__MASK 0x40000000L ++#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__MASK 0x80000000L ++//BIF_VDDGFX_RSV1_UPPER ++#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__MASK 0x0003FFFCL ++//BIF_VDDGFX_RSV2_LOWER ++#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__MASK 0x0003FFFCL ++#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__MASK 0x40000000L ++#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__MASK 0x80000000L ++//BIF_VDDGFX_RSV2_UPPER ++#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__MASK 0x0003FFFCL ++//BIF_VDDGFX_RSV3_LOWER ++#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__MASK 0x0003FFFCL ++#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__MASK 0x40000000L ++#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__MASK 0x80000000L ++//BIF_VDDGFX_RSV3_UPPER ++#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__MASK 0x0003FFFCL ++//BIF_VDDGFX_RSV4_LOWER ++#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__MASK 0x0003FFFCL ++#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__MASK 0x40000000L ++#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__MASK 0x80000000L ++//BIF_VDDGFX_RSV4_UPPER ++#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__MASK 0x0003FFFCL ++//BIF_VDDGFX_FB_CMP ++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__MASK 0x00000001L ++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__MASK 0x00000002L ++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__MASK 0x00000004L ++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__MASK 0x00000008L ++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__MASK 0x00000010L ++#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__MASK 0x00000020L ++//BIF_DOORBELL_GBLAPER1_LOWER ++#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__MASK 0x00000FFCL ++#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__MASK 0x80000000L ++//BIF_DOORBELL_GBLAPER1_UPPER ++#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__MASK 0x00000FFCL ++//BIF_DOORBELL_GBLAPER2_LOWER ++#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__MASK 0x00000FFCL ++#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__MASK 0x80000000L ++//BIF_DOORBELL_GBLAPER2_UPPER ++#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__MASK 0x00000FFCL ++//REMAP_HDP_MEM_FLUSH_CNTL ++#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__MASK 0x0007FFFCL ++//REMAP_HDP_REG_FLUSH_CNTL ++#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__MASK 0x0007FFFCL ++//BIF_RB_CNTL ++#define BIF_RB_CNTL__RB_ENABLE__MASK 0x00000001L ++#define BIF_RB_CNTL__RB_SIZE__MASK 0x0000003EL ++#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__MASK 0x00000100L ++#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__MASK 0x00003E00L ++#define BIF_RB_CNTL__BIF_RB_TRAN__MASK 0x00020000L ++#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__MASK 0x80000000L ++//BIF_RB_BASE ++#define BIF_RB_BASE__ADDR__MASK 0xFFFFFFFFL ++//BIF_RB_RPTR ++#define BIF_RB_RPTR__OFFSET__MASK 0x0003FFFCL ++//BIF_RB_WPTR ++#define BIF_RB_WPTR__BIF_RB_OVERFLOW__MASK 0x00000001L ++#define BIF_RB_WPTR__OFFSET__MASK 0x0003FFFCL ++//BIF_RB_WPTR_ADDR_HI ++#define BIF_RB_WPTR_ADDR_HI__ADDR__MASK 0x000000FFL ++//BIF_RB_WPTR_ADDR_LO ++#define BIF_RB_WPTR_ADDR_LO__ADDR__MASK 0xFFFFFFFCL ++//MAILBOX_INDEX ++#define MAILBOX_INDEX__MAILBOX_INDEX__MASK 0x0000001FL ++//BIF_GPUIOV_RESET_NOTIFICATION ++#define BIF_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION__MASK 0xFFFFFFFFL ++//BIF_UVD_GPUIOV_CFG_SIZE ++#define BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE__MASK 0x0000000FL ++//BIF_VCE_GPUIOV_CFG_SIZE ++#define BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE__MASK 0x0000000FL ++//BIF_GFX_SDMA_GPUIOV_CFG_SIZE ++#define BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__MASK 0x0000000FL ++//BIF_GMI_WRR_WEIGHT ++#define BIF_GMI_WRR_WEIGHT__GMI_REQ_REALTIME_WEIGHT__MASK 0x000000FFL ++#define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_P_WEIGHT__MASK 0x0000FF00L ++#define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_NP_WEIGHT__MASK 0x00FF0000L ++//NBIF_STRAP_WRITE_CTRL ++#define NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE__MASK 0x00000001L ++//BIF_PERSTB_PAD_CNTL ++#define BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__MASK 0x0000FFFFL ++//BIF_PX_EN_PAD_CNTL ++#define BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__MASK 0x000000FFL ++//BIF_REFPADKIN_PAD_CNTL ++#define BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__MASK 0x000000FFL ++//BIF_CLKREQB_PAD_CNTL ++#define BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__MASK 0x00FFFFFFL ++ ++ ++// addressBlock: rcc_pf_0_BIFDEC1 ++//RCC_BACO_CNTL_MISC ++#define RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__MASK 0x00000001L ++#define RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__MASK 0x00000002L ++//RCC_RESET_EN ++#define RCC_RESET_EN__DB_APER_RESET_EN__MASK 0x00008000L ++//RCC_VDM_SUPPORT ++#define RCC_VDM_SUPPORT__MCTP_SUPPORT__MASK 0x00000001L ++#define RCC_VDM_SUPPORT__AMPTP_SUPPORT__MASK 0x00000002L ++#define RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__MASK 0x00000004L ++#define RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__MASK 0x00000008L ++#define RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__MASK 0x00000010L ++//RCC_PEER_REG_RANGE0 ++#define RCC_PEER_REG_RANGE0__START_ADDR__MASK 0x0000FFFFL ++#define RCC_PEER_REG_RANGE0__END_ADDR__MASK 0xFFFF0000L ++//RCC_PEER_REG_RANGE1 ++#define RCC_PEER_REG_RANGE1__START_ADDR__MASK 0x0000FFFFL ++#define RCC_PEER_REG_RANGE1__END_ADDR__MASK 0xFFFF0000L ++//RCC_BUS_CNTL ++#define RCC_BUS_CNTL__PMI_IO_DIS__MASK 0x00000004L ++#define RCC_BUS_CNTL__PMI_MEM_DIS__MASK 0x00000008L ++#define RCC_BUS_CNTL__PMI_BM_DIS__MASK 0x00000010L ++#define RCC_BUS_CNTL__PMI_IO_DIS_DN__MASK 0x00000020L ++#define RCC_BUS_CNTL__PMI_MEM_DIS_DN__MASK 0x00000040L ++#define RCC_BUS_CNTL__PMI_IO_DIS_UP__MASK 0x00000080L ++#define RCC_BUS_CNTL__PMI_MEM_DIS_UP__MASK 0x00000100L ++#define RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__MASK 0x00001000L ++#define RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__MASK 0x00002000L ++#define RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__MASK 0x00010000L ++#define RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__MASK 0x00020000L ++#define RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__MASK 0x00040000L ++#define RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__MASK 0x00080000L ++#define RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__MASK 0x00100000L ++#define RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__MASK 0x00200000L ++#define RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__MASK 0x01000000L ++#define RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__MASK 0x0E000000L ++#define RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__MASK 0x10000000L ++#define RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__MASK 0xE0000000L ++//RCC_CONFIG_CNTL ++#define RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__MASK 0x00000001L ++#define RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__MASK 0x00000004L ++#define RCC_CONFIG_CNTL__GRPH_ADRSEL__MASK 0x00000018L ++//RCC_CONFIG_F0_BASE ++#define RCC_CONFIG_F0_BASE__F0_BASE__MASK 0xFFFFFFFFL ++//RCC_CONFIG_APER_SIZE ++#define RCC_CONFIG_APER_SIZE__APER_SIZE__MASK 0xFFFFFFFFL ++//RCC_CONFIG_REG_APER_SIZE ++#define RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__MASK 0x000FFFFFL ++//RCC_XDMA_LO ++#define RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__MASK 0x1FFFFFFFL ++#define RCC_XDMA_LO__BIF_XDMA_APER_EN__MASK 0x80000000L ++//RCC_XDMA_HI ++#define RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__MASK 0x1FFFFFFFL ++//RCC_FEATURES_CONTROL_MISC ++#define RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__MASK 0x00000010L ++#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__MASK 0x00000020L ++#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__MASK 0x00000040L ++#define RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__MASK 0x00000100L ++#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__MASK 0x00000200L ++#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__MASK 0x00000400L ++#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__MASK 0x00000800L ++#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__MASK 0x00001000L ++#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__MASK 0x00002000L ++#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__MASK 0x00004000L ++#define RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__MASK 0x00008000L ++#define RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__MASK 0x00010000L ++#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__MASK 0x00020000L ++#define RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__MASK 0x00040000L ++//RCC_BUSNUM_CNTL1 ++#define RCC_BUSNUM_CNTL1__ID_MASK__MASK 0x000000FFL ++//RCC_BUSNUM_LIST0 ++#define RCC_BUSNUM_LIST0__ID0__MASK 0x000000FFL ++#define RCC_BUSNUM_LIST0__ID1__MASK 0x0000FF00L ++#define RCC_BUSNUM_LIST0__ID2__MASK 0x00FF0000L ++#define RCC_BUSNUM_LIST0__ID3__MASK 0xFF000000L ++//RCC_BUSNUM_LIST1 ++#define RCC_BUSNUM_LIST1__ID4__MASK 0x000000FFL ++#define RCC_BUSNUM_LIST1__ID5__MASK 0x0000FF00L ++#define RCC_BUSNUM_LIST1__ID6__MASK 0x00FF0000L ++#define RCC_BUSNUM_LIST1__ID7__MASK 0xFF000000L ++//RCC_BUSNUM_CNTL2 ++#define RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__MASK 0x000000FFL ++#define RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__MASK 0x00000100L ++#define RCC_BUSNUM_CNTL2__HDPREG_CNTL__MASK 0x00010000L ++#define RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__MASK 0x00020000L ++//RCC_CAPTURE_HOST_BUSNUM ++#define RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__MASK 0x00000001L ++//RCC_HOST_BUSNUM ++#define RCC_HOST_BUSNUM__HOST_ID__MASK 0x0000FFFFL ++//RCC_PEER0_FB_OFFSET_HI ++#define RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__MASK 0x000FFFFFL ++//RCC_PEER0_FB_OFFSET_LO ++#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__MASK 0x000FFFFFL ++#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__MASK 0x80000000L ++//RCC_PEER1_FB_OFFSET_HI ++#define RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__MASK 0x000FFFFFL ++//RCC_PEER1_FB_OFFSET_LO ++#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__MASK 0x000FFFFFL ++#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__MASK 0x80000000L ++//RCC_PEER2_FB_OFFSET_HI ++#define RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__MASK 0x000FFFFFL ++//RCC_PEER2_FB_OFFSET_LO ++#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__MASK 0x000FFFFFL ++#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__MASK 0x80000000L ++//RCC_PEER3_FB_OFFSET_HI ++#define RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__MASK 0x000FFFFFL ++//RCC_PEER3_FB_OFFSET_LO ++#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__MASK 0x000FFFFFL ++#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__MASK 0x80000000L ++//RCC_DEVFUNCNUM_LIST0 ++#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__MASK 0x000000FFL ++#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__MASK 0x0000FF00L ++#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__MASK 0x00FF0000L ++#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__MASK 0xFF000000L ++//RCC_DEVFUNCNUM_LIST1 ++#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__MASK 0x000000FFL ++#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__MASK 0x0000FF00L ++#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__MASK 0x00FF0000L ++#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__MASK 0xFF000000L ++//RCC_DEV0_LINK_CNTL ++#define RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__MASK 0x00000001L ++#define RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__MASK 0x00000100L ++//RCC_CMN_LINK_CNTL ++#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__MASK 0x00000001L ++#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__MASK 0x00000002L ++#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__MASK 0x00000004L ++#define RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__MASK 0x00000008L ++//RCC_EP_REQUESTERID_RESTORE ++#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__MASK 0x000000FFL ++#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__MASK 0x00001F00L ++//RCC_LTR_LSWITCH_CNTL ++#define RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__MASK 0x000003FFL ++//RCC_MH_ARB_CNTL ++#define RCC_MH_ARB_CNTL__MH_ARB_MODE__MASK 0x00000001L ++#define RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__MASK 0x00007FFEL ++ ++ ++// addressBlock: rcc_pf_0_BIFDEC2 ++//GFXMSIX_VECT0_ADDR_LO ++#define GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL ++//GFXMSIX_VECT0_ADDR_HI ++#define GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL ++//GFXMSIX_VECT0_MSG_DATA ++#define GFXMSIX_VECT0_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL ++//GFXMSIX_VECT0_CONTROL ++#define GFXMSIX_VECT0_CONTROL__MASK_BIT__MASK 0x00000001L ++//GFXMSIX_VECT1_ADDR_LO ++#define GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL ++//GFXMSIX_VECT1_ADDR_HI ++#define GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL ++//GFXMSIX_VECT1_MSG_DATA ++#define GFXMSIX_VECT1_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL ++//GFXMSIX_VECT1_CONTROL ++#define GFXMSIX_VECT1_CONTROL__MASK_BIT__MASK 0x00000001L ++//GFXMSIX_VECT2_ADDR_LO ++#define GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL ++//GFXMSIX_VECT2_ADDR_HI ++#define GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL ++//GFXMSIX_VECT2_MSG_DATA ++#define GFXMSIX_VECT2_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL ++//GFXMSIX_VECT2_CONTROL ++#define GFXMSIX_VECT2_CONTROL__MASK_BIT__MASK 0x00000001L ++//GFXMSIX_PBA ++#define GFXMSIX_PBA__MSIX_PENDING_BITS_0__MASK 0x00000001L ++#define GFXMSIX_PBA__MSIX_PENDING_BITS_1__MASK 0x00000002L ++#define GFXMSIX_PBA__MSIX_PENDING_BITS_2__MASK 0x00000004L ++ ++ ++// addressBlock: rcc_strap_BIFDEC1 ++//RCC_DEV0_PORT_STRAP0 ++#define RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__MASK 0x00000002L ++#define RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__MASK 0x00000004L ++#define RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__MASK 0x00000008L ++#define RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__MASK 0x00000010L ++#define RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__MASK 0x001FFFE0L ++#define RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__MASK 0x00E00000L ++#define RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__MASK 0x01000000L ++#define RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__MASK 0x0E000000L ++#define RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__MASK 0x70000000L ++#define RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__MASK 0x80000000L ++//RCC_DEV0_PORT_STRAP1 ++#define RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__MASK 0x0000FFFFL ++#define RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__MASK 0xFFFF0000L ++//RCC_DEV0_PORT_STRAP2 ++#define RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__MASK 0x00000001L ++#define RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__MASK 0x00000002L ++#define RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__MASK 0x00000004L ++#define RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__MASK 0x00000008L ++#define RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__MASK 0x00000010L ++#define RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__MASK 0x00000020L ++#define RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__MASK 0x00000040L ++#define RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__MASK 0x00000080L ++#define RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__MASK 0x00000100L ++#define RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__MASK 0x00000E00L ++#define RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__MASK 0x00001000L ++#define RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__MASK 0x00002000L ++#define RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__MASK 0x00004000L ++#define RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__MASK 0x00008000L ++#define RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__MASK 0x00010000L ++#define RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__MASK 0x00060000L ++#define RCC_DEV0_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV0__MASK 0x00080000L ++#define RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__MASK 0x00700000L ++#define RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__MASK 0x03800000L ++#define RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__MASK 0x1C000000L ++#define RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__MASK 0xE0000000L ++//RCC_DEV0_PORT_STRAP3 ++#define RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__MASK 0x00000001L ++#define RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__MASK 0x00000002L ++#define RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__MASK 0x00000004L ++#define RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__MASK 0x00000038L ++#define RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__MASK 0x00000040L ++#define RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__MASK 0x00000080L ++#define RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__MASK 0x00000100L ++#define RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__MASK 0x00000600L ++#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__MASK 0x00003800L ++#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__MASK 0x0003C000L ++#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__MASK 0x001C0000L ++#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__MASK 0x01E00000L ++#define RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__MASK 0x06000000L ++#define RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__MASK 0x18000000L ++#define RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__MASK 0x20000000L ++#define RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0__MASK 0x40000000L ++#define RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__MASK 0x80000000L ++//RCC_DEV0_PORT_STRAP4 ++#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__MASK 0x000000FFL ++#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__MASK 0x0000FF00L ++#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__MASK 0x00FF0000L ++#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__MASK 0xFF000000L ++//RCC_DEV0_PORT_STRAP5 ++#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__MASK 0x000000FFL ++#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__MASK 0x0000FF00L ++#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__MASK 0x00010000L ++#define RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__MASK 0x00020000L ++#define RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__MASK 0x00040000L ++#define RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__MASK 0x00080000L ++#define RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__MASK 0x00100000L ++#define RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__MASK 0x00200000L ++#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__MASK 0x00800000L ++#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__MASK 0x01000000L ++#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__MASK 0x02000000L ++#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__MASK 0x04000000L ++#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__MASK 0x08000000L ++#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__MASK 0x10000000L ++#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__MASK 0x20000000L ++#define RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__MASK 0x40000000L ++#define RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__MASK 0x80000000L ++//RCC_DEV0_PORT_STRAP6 ++#define RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__MASK 0x00000001L ++#define RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__MASK 0x00000002L ++//RCC_DEV0_PORT_STRAP7 ++#define RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__MASK 0x000000FFL ++#define RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__MASK 0x00000F00L ++#define RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__MASK 0x0000F000L ++#define RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__MASK 0x00FF0000L ++#define RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__MASK 0x1F000000L ++#define RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__MASK 0xE0000000L ++//RCC_DEV0_EPF0_STRAP0 ++#define RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__MASK 0x0000FFFFL ++#define RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__MASK 0x000F0000L ++#define RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__MASK 0x00F00000L ++#define RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__MASK 0x0F000000L ++#define RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__MASK 0x10000000L ++#define RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__MASK 0x20000000L ++#define RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__MASK 0x40000000L ++#define RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__MASK 0x80000000L ++//RCC_DEV0_EPF0_STRAP1 ++#define RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__MASK 0x0000FFFFL ++#define RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__MASK 0xFFFF0000L ++//RCC_DEV0_EPF0_STRAP13 ++#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__MASK 0x000000FFL ++#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__MASK 0x0000FF00L ++#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__MASK 0x00FF0000L ++//RCC_DEV0_EPF0_STRAP2 ++#define RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__MASK 0x00000001L ++#define RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__MASK 0x0000003EL ++#define RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__MASK 0x00000040L ++#define RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__MASK 0x00000080L ++#define RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__MASK 0x00000100L ++#define RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__MASK 0x00003E00L ++#define RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__MASK 0x00004000L ++#define RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__MASK 0x00008000L ++#define RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__MASK 0x00010000L ++#define RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__MASK 0x00020000L ++#define RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__MASK 0x00040000L ++#define RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__MASK 0x00100000L ++#define RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__MASK 0x00200000L ++#define RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__MASK 0x00400000L ++#define RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__MASK 0x00800000L ++#define RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__MASK 0x07000000L ++#define RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__MASK 0x08000000L ++#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__MASK 0x10000000L ++#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__MASK 0x20000000L ++#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__MASK 0x40000000L ++#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__MASK 0x80000000L ++//RCC_DEV0_EPF0_STRAP3 ++#define RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__MASK 0x00000001L ++#define RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__MASK 0x00000002L ++#define RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__MASK 0x0003FFFCL ++#define RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__MASK 0x00040000L ++#define RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__MASK 0x00080000L ++#define RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__MASK 0x00100000L ++#define RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__MASK 0x00E00000L ++#define RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__MASK 0x01000000L ++#define RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0__MASK 0x02000000L ++#define RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__MASK 0x04000000L ++#define RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__MASK 0x08000000L ++//RCC_DEV0_EPF0_STRAP4 ++#define RCC_DEV0_EPF0_STRAP4__STRAP_MSIX_TABLE_OFFSET_DEV0_F0__MASK 0x000FFFFFL ++#define RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__MASK 0x00100000L ++#define RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__MASK 0x00200000L ++#define RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__MASK 0x00400000L ++#define RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__MASK 0x0F800000L ++#define RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__MASK 0x70000000L ++#define RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__MASK 0x80000000L ++//RCC_DEV0_EPF0_STRAP5 ++#define RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__MASK 0x0000FFFFL ++//RCC_DEV0_EPF0_STRAP8 ++#define RCC_DEV0_EPF0_STRAP8__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__MASK 0x00000001L ++#define RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__MASK 0x00000006L ++#define RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__MASK 0x00000008L ++#define RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0__MASK 0x00000010L ++#define RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__MASK 0x00000060L ++#define RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__MASK 0x00000080L ++#define RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__MASK 0x00000100L ++#define RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__MASK 0x00000E00L ++#define RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__MASK 0x00003000L ++#define RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__MASK 0x0000C000L ++#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__MASK 0x00070000L ++#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__MASK 0x00380000L ++#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__MASK 0x00C00000L ++#define RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__MASK 0x01000000L ++#define RCC_DEV0_EPF0_STRAP8__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__MASK 0x02000000L ++#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_PROT_DIS_DEV0_F0__MASK 0x04000000L ++#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__MASK 0x38000000L ++#define RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__MASK 0xC0000000L ++//RCC_DEV0_EPF0_STRAP9 ++//RCC_DEV0_EPF1_STRAP0 ++#define RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__MASK 0x0000FFFFL ++#define RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__MASK 0x000F0000L ++#define RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__MASK 0x00F00000L ++#define RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__MASK 0x10000000L ++#define RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__MASK 0x20000000L ++#define RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__MASK 0x40000000L ++#define RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__MASK 0x80000000L ++//RCC_DEV0_EPF1_STRAP10 ++#define RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1__MASK 0x00000001L ++#define RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1__MASK 0x001FFFFEL ++//RCC_DEV0_EPF1_STRAP11 ++#define RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1__MASK 0x00000001L ++#define RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1__MASK 0x001FFFFEL ++//RCC_DEV0_EPF1_STRAP12 ++#define RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1__MASK 0x00000001L ++#define RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1__MASK 0x001FFFFEL ++//RCC_DEV0_EPF1_STRAP13 ++#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__MASK 0x000000FFL ++#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__MASK 0x0000FF00L ++#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__MASK 0x00FF0000L ++//RCC_DEV0_EPF1_STRAP2 ++#define RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__MASK 0x00000080L ++#define RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__MASK 0x00000100L ++#define RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__MASK 0x00004000L ++#define RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__MASK 0x00010000L ++#define RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__MASK 0x00020000L ++#define RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__MASK 0x00040000L ++#define RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__MASK 0x00100000L ++#define RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__MASK 0x00200000L ++#define RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__MASK 0x00400000L ++#define RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__MASK 0x00800000L ++#define RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__MASK 0x07000000L ++//RCC_DEV0_EPF1_STRAP3 ++#define RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__MASK 0x00000001L ++#define RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__MASK 0x00000002L ++#define RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__MASK 0x0003FFFCL ++#define RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__MASK 0x00040000L ++#define RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__MASK 0x00080000L ++#define RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__MASK 0x00100000L ++#define RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__MASK 0x01000000L ++#define RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1__MASK 0x02000000L ++#define RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__MASK 0x04000000L ++#define RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__MASK 0x08000000L ++//RCC_DEV0_EPF1_STRAP4 ++#define RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__MASK 0x00100000L ++#define RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__MASK 0x00200000L ++#define RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__MASK 0x00400000L ++#define RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__MASK 0x0F800000L ++#define RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__MASK 0x70000000L ++#define RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__MASK 0x80000000L ++//RCC_DEV0_EPF1_STRAP5 ++#define RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__MASK 0x0000FFFFL ++//RCC_DEV0_EPF1_STRAP6 ++#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__MASK 0x00000001L ++#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__MASK 0x00000002L ++#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__MASK 0x00000004L ++#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1__MASK 0x00000070L ++#define RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__MASK 0x00000100L ++#define RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__MASK 0x00000200L ++#define RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__MASK 0x00010000L ++#define RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__MASK 0x00020000L ++#define RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__MASK 0x01000000L ++#define RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__MASK 0x02000000L ++//RCC_DEV0_EPF1_STRAP7 ++#define RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1__MASK 0x00000001L ++#define RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1__MASK 0x0000001EL ++ ++ ++// addressBlock: bif_bx_pf_BIFPFVFDEC1 ++//BIF_BME_STATUS ++#define BIF_BME_STATUS__DMA_ON_BME_LOW__MASK 0x00000001L ++#define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__MASK 0x00010000L ++//BIF_ATOMIC_ERR_LOG ++#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__MASK 0x00000001L ++#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__MASK 0x00000002L ++#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__MASK 0x00010000L ++#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__MASK 0x00020000L ++//DOORBELL_SELFRING_GPA_APER_BASE_HIGH ++#define DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__MASK 0xFFFFFFFFL ++//DOORBELL_SELFRING_GPA_APER_BASE_LOW ++#define DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__MASK 0xFFFFFFFFL ++//DOORBELL_SELFRING_GPA_APER_CNTL ++#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__MASK 0x00000001L ++#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__MASK 0x0000FF00L ++//HDP_REG_COHERENCY_FLUSH_CNTL ++#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__MASK 0x00000001L ++//HDP_MEM_COHERENCY_FLUSH_CNTL ++#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__MASK 0x00000001L ++//GPU_HDP_FLUSH_REQ ++#define GPU_HDP_FLUSH_REQ__CP0__MASK 0x00000001L ++#define GPU_HDP_FLUSH_REQ__CP1__MASK 0x00000002L ++#define GPU_HDP_FLUSH_REQ__CP2__MASK 0x00000004L ++#define GPU_HDP_FLUSH_REQ__CP3__MASK 0x00000008L ++#define GPU_HDP_FLUSH_REQ__CP4__MASK 0x00000010L ++#define GPU_HDP_FLUSH_REQ__CP5__MASK 0x00000020L ++#define GPU_HDP_FLUSH_REQ__CP6__MASK 0x00000040L ++#define GPU_HDP_FLUSH_REQ__CP7__MASK 0x00000080L ++#define GPU_HDP_FLUSH_REQ__CP8__MASK 0x00000100L ++#define GPU_HDP_FLUSH_REQ__CP9__MASK 0x00000200L ++#define GPU_HDP_FLUSH_REQ__SDMA0__MASK 0x00000400L ++#define GPU_HDP_FLUSH_REQ__SDMA1__MASK 0x00000800L ++//GPU_HDP_FLUSH_DONE ++#define GPU_HDP_FLUSH_DONE__CP0__MASK 0x00000001L ++#define GPU_HDP_FLUSH_DONE__CP1__MASK 0x00000002L ++#define GPU_HDP_FLUSH_DONE__CP2__MASK 0x00000004L ++#define GPU_HDP_FLUSH_DONE__CP3__MASK 0x00000008L ++#define GPU_HDP_FLUSH_DONE__CP4__MASK 0x00000010L ++#define GPU_HDP_FLUSH_DONE__CP5__MASK 0x00000020L ++#define GPU_HDP_FLUSH_DONE__CP6__MASK 0x00000040L ++#define GPU_HDP_FLUSH_DONE__CP7__MASK 0x00000080L ++#define GPU_HDP_FLUSH_DONE__CP8__MASK 0x00000100L ++#define GPU_HDP_FLUSH_DONE__CP9__MASK 0x00000200L ++#define GPU_HDP_FLUSH_DONE__SDMA0__MASK 0x00000400L ++#define GPU_HDP_FLUSH_DONE__SDMA1__MASK 0x00000800L ++//BIF_TRANS_PENDING ++#define BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__MASK 0x00000001L ++#define BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__MASK 0x00000002L ++//MAILBOX_MSGBUF_TRN_DW0 ++#define MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__MASK 0xFFFFFFFFL ++//MAILBOX_MSGBUF_TRN_DW1 ++#define MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__MASK 0xFFFFFFFFL ++//MAILBOX_MSGBUF_TRN_DW2 ++#define MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__MASK 0xFFFFFFFFL ++//MAILBOX_MSGBUF_TRN_DW3 ++#define MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__MASK 0xFFFFFFFFL ++//MAILBOX_MSGBUF_RCV_DW0 ++#define MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__MASK 0xFFFFFFFFL ++//MAILBOX_MSGBUF_RCV_DW1 ++#define MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__MASK 0xFFFFFFFFL ++//MAILBOX_MSGBUF_RCV_DW2 ++#define MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__MASK 0xFFFFFFFFL ++//MAILBOX_MSGBUF_RCV_DW3 ++#define MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__MASK 0xFFFFFFFFL ++//MAILBOX_CONTROL ++#define MAILBOX_CONTROL__TRN_MSG_VALID__MASK 0x00000001L ++#define MAILBOX_CONTROL__TRN_MSG_ACK__MASK 0x00000002L ++#define MAILBOX_CONTROL__RCV_MSG_VALID__MASK 0x00000100L ++#define MAILBOX_CONTROL__RCV_MSG_ACK__MASK 0x00000200L ++//MAILBOX_INT_CNTL ++#define MAILBOX_INT_CNTL__VALID_INT_EN__MASK 0x00000001L ++#define MAILBOX_INT_CNTL__ACK_INT_EN__MASK 0x00000002L ++//BIF_VMHV_MAILBOX ++#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__MASK 0x00000001L ++#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__MASK 0x00000002L ++#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__MASK 0x00000F00L ++#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__MASK 0x00008000L ++#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__MASK 0x000F0000L ++#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__MASK 0x00800000L ++#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__MASK 0x01000000L ++#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__MASK 0x02000000L ++ ++ ++// addressBlock: rcc_pf_0_BIFPFVFDEC1 ++//RCC_DOORBELL_APER_EN ++#define RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__MASK 0x00000001L ++//RCC_CONFIG_MEMSIZE ++#define RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__MASK 0xFFFFFFFFL ++//RCC_CONFIG_RESERVED ++#define RCC_CONFIG_RESERVED__CONFIG_RESERVED__MASK 0xFFFFFFFFL ++//RCC_IOV_FUNC_IDENTIFIER ++#define RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__MASK 0x00000001L ++#define RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__MASK 0x80000000L ++ ++ ++// addressBlock: syshub_mmreg_ind_syshubdec ++//SYSHUB_INDEX ++#define SYSHUB_INDEX__INDEX__MASK 0xFFFFFFFFL ++//SYSHUB_DATA ++#define SYSHUB_DATA__DATA__MASK 0xFFFFFFFFL ++ ++ ++// addressBlock: rcc_strap_rcc_strap_internal ++//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__MASK 0x00000002L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__MASK 0x00000004L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__MASK 0x00000008L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__MASK 0x00000010L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__MASK 0x001FFFE0L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__MASK 0x00E00000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__MASK 0x01000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__MASK 0x0E000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__MASK 0x70000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__MASK 0x80000000L ++//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__MASK 0x0000FFFFL ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__MASK 0xFFFF0000L ++//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__MASK 0x00000001L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__MASK 0x00000002L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__MASK 0x00000004L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__MASK 0x00000008L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__MASK 0x00000010L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__MASK 0x00000020L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__MASK 0x00000040L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__MASK 0x00000080L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__MASK 0x00000100L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__MASK 0x00000E00L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__MASK 0x00001000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__MASK 0x00002000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__MASK 0x00004000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__MASK 0x00008000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__MASK 0x00010000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__MASK 0x00060000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV0__MASK 0x00080000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__MASK 0x00700000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__MASK 0x03800000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__MASK 0x1C000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__MASK 0xE0000000L ++//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__MASK 0x00000001L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__MASK 0x00000002L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__MASK 0x00000004L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__MASK 0x00000038L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__MASK 0x00000040L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__MASK 0x00000080L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__MASK 0x00000100L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__MASK 0x00000600L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__MASK 0x00003800L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__MASK 0x0003C000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__MASK 0x001C0000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__MASK 0x01E00000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__MASK 0x06000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__MASK 0x18000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__MASK 0x20000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0__MASK 0x40000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__MASK 0x80000000L ++//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__MASK 0x000000FFL ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__MASK 0x0000FF00L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__MASK 0x00FF0000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__MASK 0xFF000000L ++//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__MASK 0x000000FFL ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__MASK 0x0000FF00L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__MASK 0x00010000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__MASK 0x00020000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__MASK 0x00040000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__MASK 0x00080000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__MASK 0x00100000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__MASK 0x00200000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__MASK 0x00800000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__MASK 0x01000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__MASK 0x02000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__MASK 0x04000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__MASK 0x08000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__MASK 0x10000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__MASK 0x20000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__MASK 0x40000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__MASK 0x80000000L ++//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__MASK 0x00000001L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__MASK 0x00000002L ++//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__MASK 0x000000FFL ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__MASK 0x00000F00L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__MASK 0x0000F000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__MASK 0x00FF0000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__MASK 0x1F000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__MASK 0xE0000000L ++//RCC_DEV1_PORT_STRAP0 ++#define RCC_DEV1_PORT_STRAP0__STRAP_ARI_EN_DN_DEV1__MASK 0x00000002L ++#define RCC_DEV1_PORT_STRAP0__STRAP_ACS_EN_DN_DEV1__MASK 0x00000004L ++#define RCC_DEV1_PORT_STRAP0__STRAP_AER_EN_DN_DEV1__MASK 0x00000008L ++#define RCC_DEV1_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV1__MASK 0x00000010L ++#define RCC_DEV1_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV1__MASK 0x001FFFE0L ++#define RCC_DEV1_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV1__MASK 0x00E00000L ++#define RCC_DEV1_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV1__MASK 0x01000000L ++#define RCC_DEV1_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV1__MASK 0x0E000000L ++#define RCC_DEV1_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV1__MASK 0x70000000L ++#define RCC_DEV1_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV1__MASK 0x80000000L ++//RCC_DEV1_PORT_STRAP1 ++#define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV1__MASK 0x0000FFFFL ++#define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV1__MASK 0xFFFF0000L ++//RCC_DEV1_PORT_STRAP2 ++#define RCC_DEV1_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV1__MASK 0x00000001L ++#define RCC_DEV1_PORT_STRAP2__STRAP_DSN_EN_DN_DEV1__MASK 0x00000002L ++#define RCC_DEV1_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV1__MASK 0x00000004L ++#define RCC_DEV1_PORT_STRAP2__STRAP_ECN1P1_EN_DEV1__MASK 0x00000008L ++#define RCC_DEV1_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV1__MASK 0x00000010L ++#define RCC_DEV1_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV1__MASK 0x00000020L ++#define RCC_DEV1_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV1__MASK 0x00000040L ++#define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV1__MASK 0x00000080L ++#define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV1__MASK 0x00000100L ++#define RCC_DEV1_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV1__MASK 0x00000E00L ++#define RCC_DEV1_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV1__MASK 0x00001000L ++#define RCC_DEV1_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV1__MASK 0x00002000L ++#define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV1__MASK 0x00004000L ++#define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_EN_DEV1__MASK 0x00008000L ++#define RCC_DEV1_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV1__MASK 0x00010000L ++#define RCC_DEV1_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV1__MASK 0x00060000L ++#define RCC_DEV1_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV1__MASK 0x00080000L ++#define RCC_DEV1_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV1__MASK 0x00700000L ++#define RCC_DEV1_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV1__MASK 0x03800000L ++#define RCC_DEV1_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV1__MASK 0x1C000000L ++#define RCC_DEV1_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV1__MASK 0xE0000000L ++//RCC_DEV1_PORT_STRAP3 ++#define RCC_DEV1_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV1__MASK 0x00000001L ++#define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DEV1__MASK 0x00000002L ++#define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DN_DEV1__MASK 0x00000004L ++#define RCC_DEV1_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV1__MASK 0x00000038L ++#define RCC_DEV1_PORT_STRAP3__STRAP_MSI_EN_DN_DEV1__MASK 0x00000040L ++#define RCC_DEV1_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV1__MASK 0x00000080L ++#define RCC_DEV1_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV1__MASK 0x00000100L ++#define RCC_DEV1_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV1__MASK 0x00000600L ++#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV1__MASK 0x00003800L ++#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV1__MASK 0x0003C000L ++#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV1__MASK 0x001C0000L ++#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV1__MASK 0x01E00000L ++#define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DEV1__MASK 0x06000000L ++#define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV1__MASK 0x18000000L ++#define RCC_DEV1_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV1__MASK 0x20000000L ++#define RCC_DEV1_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV1__MASK 0x40000000L ++#define RCC_DEV1_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV1__MASK 0x80000000L ++//RCC_DEV1_PORT_STRAP4 ++#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV1__MASK 0x000000FFL ++#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV1__MASK 0x0000FF00L ++#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV1__MASK 0x00FF0000L ++#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV1__MASK 0xFF000000L ++//RCC_DEV1_PORT_STRAP5 ++#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV1__MASK 0x000000FFL ++#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV1__MASK 0x0000FF00L ++#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV1__MASK 0x00010000L ++#define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV1__MASK 0x00020000L ++#define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV1__MASK 0x00040000L ++#define RCC_DEV1_PORT_STRAP5__STRAP_VC_EN_DN_DEV1__MASK 0x00080000L ++#define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DEV1__MASK 0x00100000L ++#define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV1__MASK 0x00200000L ++#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV1__MASK 0x00800000L ++#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV1__MASK 0x01000000L ++#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV1__MASK 0x02000000L ++#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV1__MASK 0x04000000L ++#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV1__MASK 0x08000000L ++#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV1__MASK 0x10000000L ++#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV1__MASK 0x20000000L ++#define RCC_DEV1_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV1__MASK 0x40000000L ++#define RCC_DEV1_PORT_STRAP5__STRAP_SSID_EN_DEV1__MASK 0x80000000L ++//RCC_DEV1_PORT_STRAP6 ++#define RCC_DEV1_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV1__MASK 0x00000001L ++#define RCC_DEV1_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV1__MASK 0x00000002L ++//RCC_DEV1_PORT_STRAP7 ++#define RCC_DEV1_PORT_STRAP7__STRAP_PORT_NUMBER_DEV1__MASK 0x000000FFL ++#define RCC_DEV1_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV1__MASK 0x00000F00L ++#define RCC_DEV1_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV1__MASK 0x0000F000L ++#define RCC_DEV1_PORT_STRAP7__STRAP_RP_BUSNUM_DEV1__MASK 0x00FF0000L ++#define RCC_DEV1_PORT_STRAP7__STRAP_DN_DEVNUM_DEV1__MASK 0x1F000000L ++#define RCC_DEV1_PORT_STRAP7__STRAP_DN_FUNCID_DEV1__MASK 0xE0000000L ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__MASK 0x0000FFFFL ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__MASK 0x000F0000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__MASK 0x00F00000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__MASK 0x0F000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__MASK 0x10000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__MASK 0x20000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__MASK 0x40000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__MASK 0x80000000L ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__MASK 0x0000FFFFL ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__MASK 0xFFFF0000L ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__MASK 0x00000001L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__MASK 0x0000003EL ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__MASK 0x00000040L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__MASK 0x00000080L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__MASK 0x00000100L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__MASK 0x00003E00L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__MASK 0x00004000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__MASK 0x00008000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__MASK 0x00010000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__MASK 0x00020000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__MASK 0x00040000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__MASK 0x00100000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__MASK 0x00200000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__MASK 0x00400000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__MASK 0x00800000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__MASK 0x07000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__MASK 0x08000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__MASK 0x10000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__MASK 0x20000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__MASK 0x40000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__MASK 0x80000000L ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__MASK 0x00000001L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__MASK 0x00000002L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__MASK 0x0003FFFCL ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__MASK 0x00040000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__MASK 0x00080000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__MASK 0x00100000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__MASK 0x00E00000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__MASK 0x01000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0__MASK 0x02000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__MASK 0x04000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__MASK 0x08000000L ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_MSIX_TABLE_OFFSET_DEV0_F0__MASK 0x000FFFFFL ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__MASK 0x00100000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__MASK 0x00200000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__MASK 0x00400000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__MASK 0x0F800000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__MASK 0x70000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__MASK 0x80000000L ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__MASK 0x0000FFFFL ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__MASK 0x00000001L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__MASK 0x00000006L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__MASK 0x00000008L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0__MASK 0x00000010L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__MASK 0x00000060L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__MASK 0x00000080L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__MASK 0x00000100L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__MASK 0x00000E00L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__MASK 0x00003000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__MASK 0x0000C000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__MASK 0x00070000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__MASK 0x00380000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__MASK 0x00C00000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__MASK 0x01000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__MASK 0x02000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_PROT_DIS_DEV0_F0__MASK 0x04000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__MASK 0x38000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__MASK 0xC0000000L ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP9 ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__MASK 0x000000FFL ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__MASK 0x0000FF00L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__MASK 0x00FF0000L ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__MASK 0x0000FFFFL ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__MASK 0x000F0000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__MASK 0x00F00000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__MASK 0x10000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__MASK 0x20000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__MASK 0x40000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__MASK 0x80000000L ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__MASK 0x00000080L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__MASK 0x00000100L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__MASK 0x00004000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__MASK 0x00010000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__MASK 0x00020000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__MASK 0x00040000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__MASK 0x00100000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__MASK 0x00200000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__MASK 0x00400000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__MASK 0x00800000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__MASK 0x07000000L ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__MASK 0x00000001L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__MASK 0x00000002L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__MASK 0x0003FFFCL ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__MASK 0x00040000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__MASK 0x00080000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__MASK 0x00100000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__MASK 0x01000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1__MASK 0x02000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__MASK 0x04000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__MASK 0x08000000L ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__MASK 0x00100000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__MASK 0x00200000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__MASK 0x00400000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__MASK 0x0F800000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__MASK 0x70000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__MASK 0x80000000L ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__MASK 0x0000FFFFL ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__MASK 0x00000001L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__MASK 0x00000002L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__MASK 0x00000004L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1__MASK 0x00000070L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__MASK 0x00000100L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__MASK 0x00000200L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__MASK 0x00010000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__MASK 0x00020000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__MASK 0x01000000L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__MASK 0x02000000L ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1__MASK 0x00000001L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1__MASK 0x0000001EL ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1__MASK 0x00000001L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1__MASK 0x001FFFFEL ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1__MASK 0x00000001L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1__MASK 0x001FFFFEL ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1__MASK 0x00000001L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1__MASK 0x001FFFFEL ++//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13 ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__MASK 0x000000FFL ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__MASK 0x0000FF00L ++#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__MASK 0x00FF0000L ++//RCC_DEV0_EPF2_STRAP0 ++#define RCC_DEV0_EPF2_STRAP0__STRAP_DEVICE_ID_DEV0_F2__MASK 0x0000FFFFL ++#define RCC_DEV0_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F2__MASK 0x000F0000L ++#define RCC_DEV0_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV0_F2__MASK 0x00F00000L ++#define RCC_DEV0_EPF2_STRAP0__STRAP_FUNC_EN_DEV0_F2__MASK 0x10000000L ++#define RCC_DEV0_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F2__MASK 0x20000000L ++#define RCC_DEV0_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV0_F2__MASK 0x40000000L ++#define RCC_DEV0_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV0_F2__MASK 0x80000000L ++//RCC_DEV0_EPF2_STRAP2 ++#define RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2__MASK 0x00000080L ++#define RCC_DEV0_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F2__MASK 0x00000100L ++#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2__MASK 0x00004000L ++#define RCC_DEV0_EPF2_STRAP2__STRAP_AER_EN_DEV0_F2__MASK 0x00010000L ++#define RCC_DEV0_EPF2_STRAP2__STRAP_ACS_EN_DEV0_F2__MASK 0x00020000L ++#define RCC_DEV0_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F2__MASK 0x00100000L ++#define RCC_DEV0_EPF2_STRAP2__STRAP_DPA_EN_DEV0_F2__MASK 0x00200000L ++#define RCC_DEV0_EPF2_STRAP2__STRAP_VC_EN_DEV0_F2__MASK 0x00800000L ++#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F2__MASK 0x07000000L ++//RCC_DEV0_EPF2_STRAP3 ++#define RCC_DEV0_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F2__MASK 0x00000001L ++#define RCC_DEV0_EPF2_STRAP3__STRAP_PWR_EN_DEV0_F2__MASK 0x00000002L ++#define RCC_DEV0_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV0_F2__MASK 0x0003FFFCL ++#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_EN_DEV0_F2__MASK 0x00040000L ++#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F2__MASK 0x00080000L ++#define RCC_DEV0_EPF2_STRAP3__STRAP_MSIX_EN_DEV0_F2__MASK 0x00100000L ++#define RCC_DEV0_EPF2_STRAP3__STRAP_PMC_DSI_DEV0_F2__MASK 0x01000000L ++#define RCC_DEV0_EPF2_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F2__MASK 0x02000000L ++#define RCC_DEV0_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F2__MASK 0x04000000L ++#define RCC_DEV0_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F2__MASK 0x08000000L ++//RCC_DEV0_EPF2_STRAP4 ++#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F2__MASK 0x00100000L ++#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV0_F2__MASK 0x00200000L ++#define RCC_DEV0_EPF2_STRAP4__STRAP_FLR_EN_DEV0_F2__MASK 0x00400000L ++#define RCC_DEV0_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV0_F2__MASK 0x0F800000L ++#define RCC_DEV0_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F2__MASK 0x70000000L ++#define RCC_DEV0_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F2__MASK 0x80000000L ++//RCC_DEV0_EPF2_STRAP5 ++#define RCC_DEV0_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F2__MASK 0x0000FFFFL ++#define RCC_DEV0_EPF2_STRAP5__STRAP_SATAIDP_EN_DEV0_F2__MASK 0x01000000L ++//RCC_DEV0_EPF2_STRAP6 ++#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_EN_DEV0_F2__MASK 0x00000001L ++#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F2__MASK 0x00000002L ++#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F2__MASK 0x00000070L ++#define RCC_DEV0_EPF2_STRAP6__STRAP_APER1_EN_DEV0_F2__MASK 0x00000100L ++#define RCC_DEV0_EPF2_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F2__MASK 0x00000200L ++//RCC_DEV0_EPF2_STRAP13 ++#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F2__MASK 0x000000FFL ++#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F2__MASK 0x0000FF00L ++#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F2__MASK 0x00FF0000L ++//RCC_DEV0_EPF3_STRAP0 ++#define RCC_DEV0_EPF3_STRAP0__STRAP_DEVICE_ID_DEV0_F3__MASK 0x0000FFFFL ++#define RCC_DEV0_EPF3_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F3__MASK 0x000F0000L ++#define RCC_DEV0_EPF3_STRAP0__STRAP_MINOR_REV_ID_DEV0_F3__MASK 0x00F00000L ++#define RCC_DEV0_EPF3_STRAP0__STRAP_FUNC_EN_DEV0_F3__MASK 0x10000000L ++#define RCC_DEV0_EPF3_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F3__MASK 0x20000000L ++#define RCC_DEV0_EPF3_STRAP0__STRAP_D1_SUPPORT_DEV0_F3__MASK 0x40000000L ++#define RCC_DEV0_EPF3_STRAP0__STRAP_D2_SUPPORT_DEV0_F3__MASK 0x80000000L ++//RCC_DEV0_EPF3_STRAP2 ++#define RCC_DEV0_EPF3_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F3__MASK 0x00000080L ++#define RCC_DEV0_EPF3_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F3__MASK 0x00000100L ++#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F3__MASK 0x00004000L ++#define RCC_DEV0_EPF3_STRAP2__STRAP_AER_EN_DEV0_F3__MASK 0x00010000L ++#define RCC_DEV0_EPF3_STRAP2__STRAP_ACS_EN_DEV0_F3__MASK 0x00020000L ++#define RCC_DEV0_EPF3_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F3__MASK 0x00100000L ++#define RCC_DEV0_EPF3_STRAP2__STRAP_DPA_EN_DEV0_F3__MASK 0x00200000L ++#define RCC_DEV0_EPF3_STRAP2__STRAP_VC_EN_DEV0_F3__MASK 0x00800000L ++#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F3__MASK 0x07000000L ++//RCC_DEV0_EPF3_STRAP3 ++#define RCC_DEV0_EPF3_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F3__MASK 0x00000001L ++#define RCC_DEV0_EPF3_STRAP3__STRAP_PWR_EN_DEV0_F3__MASK 0x00000002L ++#define RCC_DEV0_EPF3_STRAP3__STRAP_SUBSYS_ID_DEV0_F3__MASK 0x0003FFFCL ++#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_EN_DEV0_F3__MASK 0x00040000L ++#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F3__MASK 0x00080000L ++#define RCC_DEV0_EPF3_STRAP3__STRAP_MSIX_EN_DEV0_F3__MASK 0x00100000L ++#define RCC_DEV0_EPF3_STRAP3__STRAP_PMC_DSI_DEV0_F3__MASK 0x01000000L ++#define RCC_DEV0_EPF3_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F3__MASK 0x02000000L ++#define RCC_DEV0_EPF3_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F3__MASK 0x04000000L ++#define RCC_DEV0_EPF3_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F3__MASK 0x08000000L ++//RCC_DEV0_EPF3_STRAP4 ++#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F3__MASK 0x00100000L ++#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_EN_DEV0_F3__MASK 0x00200000L ++#define RCC_DEV0_EPF3_STRAP4__STRAP_FLR_EN_DEV0_F3__MASK 0x00400000L ++#define RCC_DEV0_EPF3_STRAP4__STRAP_PME_SUPPORT_DEV0_F3__MASK 0x0F800000L ++#define RCC_DEV0_EPF3_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F3__MASK 0x70000000L ++#define RCC_DEV0_EPF3_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F3__MASK 0x80000000L ++//RCC_DEV0_EPF3_STRAP5 ++#define RCC_DEV0_EPF3_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F3__MASK 0x0000FFFFL ++#define RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESEL_DEV0_F3__MASK 0x000F0000L ++#define RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESELD_DEV0_F3__MASK 0x00F00000L ++//RCC_DEV0_EPF3_STRAP6 ++#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_EN_DEV0_F3__MASK 0x00000001L ++#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F3__MASK 0x00000002L ++#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F3__MASK 0x00000070L ++//RCC_DEV0_EPF3_STRAP13 ++#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F3__MASK 0x000000FFL ++#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F3__MASK 0x0000FF00L ++#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F3__MASK 0x00FF0000L ++//RCC_DEV0_EPF4_STRAP0 ++#define RCC_DEV0_EPF4_STRAP0__STRAP_DEVICE_ID_DEV0_F4__MASK 0x0000FFFFL ++#define RCC_DEV0_EPF4_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F4__MASK 0x000F0000L ++#define RCC_DEV0_EPF4_STRAP0__STRAP_MINOR_REV_ID_DEV0_F4__MASK 0x00F00000L ++#define RCC_DEV0_EPF4_STRAP0__STRAP_FUNC_EN_DEV0_F4__MASK 0x10000000L ++#define RCC_DEV0_EPF4_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F4__MASK 0x20000000L ++#define RCC_DEV0_EPF4_STRAP0__STRAP_D1_SUPPORT_DEV0_F4__MASK 0x40000000L ++#define RCC_DEV0_EPF4_STRAP0__STRAP_D2_SUPPORT_DEV0_F4__MASK 0x80000000L ++//RCC_DEV0_EPF4_STRAP2 ++#define RCC_DEV0_EPF4_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F4__MASK 0x00000080L ++#define RCC_DEV0_EPF4_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F4__MASK 0x00000100L ++#define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F4__MASK 0x00004000L ++#define RCC_DEV0_EPF4_STRAP2__STRAP_AER_EN_DEV0_F4__MASK 0x00010000L ++#define RCC_DEV0_EPF4_STRAP2__STRAP_ACS_EN_DEV0_F4__MASK 0x00020000L ++#define RCC_DEV0_EPF4_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F4__MASK 0x00100000L ++#define RCC_DEV0_EPF4_STRAP2__STRAP_DPA_EN_DEV0_F4__MASK 0x00200000L ++#define RCC_DEV0_EPF4_STRAP2__STRAP_VC_EN_DEV0_F4__MASK 0x00800000L ++#define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F4__MASK 0x07000000L ++//RCC_DEV0_EPF4_STRAP3 ++#define RCC_DEV0_EPF4_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F4__MASK 0x00000001L ++#define RCC_DEV0_EPF4_STRAP3__STRAP_PWR_EN_DEV0_F4__MASK 0x00000002L ++#define RCC_DEV0_EPF4_STRAP3__STRAP_SUBSYS_ID_DEV0_F4__MASK 0x0003FFFCL ++#define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_EN_DEV0_F4__MASK 0x00040000L ++#define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F4__MASK 0x00080000L ++#define RCC_DEV0_EPF4_STRAP3__STRAP_MSIX_EN_DEV0_F4__MASK 0x00100000L ++#define RCC_DEV0_EPF4_STRAP3__STRAP_PMC_DSI_DEV0_F4__MASK 0x01000000L ++#define RCC_DEV0_EPF4_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F4__MASK 0x02000000L ++#define RCC_DEV0_EPF4_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F4__MASK 0x04000000L ++#define RCC_DEV0_EPF4_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F4__MASK 0x08000000L ++//RCC_DEV0_EPF4_STRAP4 ++#define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F4__MASK 0x00100000L ++#define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_EN_DEV0_F4__MASK 0x00200000L ++#define RCC_DEV0_EPF4_STRAP4__STRAP_FLR_EN_DEV0_F4__MASK 0x00400000L ++#define RCC_DEV0_EPF4_STRAP4__STRAP_PME_SUPPORT_DEV0_F4__MASK 0x0F800000L ++#define RCC_DEV0_EPF4_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F4__MASK 0x70000000L ++#define RCC_DEV0_EPF4_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F4__MASK 0x80000000L ++//RCC_DEV0_EPF4_STRAP5 ++#define RCC_DEV0_EPF4_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F4__MASK 0x0000FFFFL ++#define RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESEL_DEV0_F4__MASK 0x000F0000L ++#define RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESELD_DEV0_F4__MASK 0x00F00000L ++//RCC_DEV0_EPF4_STRAP6 ++#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_EN_DEV0_F4__MASK 0x00000001L ++#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F4__MASK 0x00000002L ++#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F4__MASK 0x00000070L ++#define RCC_DEV0_EPF4_STRAP6__STRAP_APER1_EN_DEV0_F4__MASK 0x00000100L ++#define RCC_DEV0_EPF4_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F4__MASK 0x00000200L ++#define RCC_DEV0_EPF4_STRAP6__STRAP_APER2_EN_DEV0_F4__MASK 0x00010000L ++#define RCC_DEV0_EPF4_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F4__MASK 0x00020000L ++//RCC_DEV0_EPF4_STRAP13 ++#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F4__MASK 0x000000FFL ++#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F4__MASK 0x0000FF00L ++#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F4__MASK 0x00FF0000L ++//RCC_DEV0_EPF5_STRAP0 ++#define RCC_DEV0_EPF5_STRAP0__STRAP_DEVICE_ID_DEV0_F5__MASK 0x0000FFFFL ++#define RCC_DEV0_EPF5_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F5__MASK 0x000F0000L ++#define RCC_DEV0_EPF5_STRAP0__STRAP_MINOR_REV_ID_DEV0_F5__MASK 0x00F00000L ++#define RCC_DEV0_EPF5_STRAP0__STRAP_FUNC_EN_DEV0_F5__MASK 0x10000000L ++#define RCC_DEV0_EPF5_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F5__MASK 0x20000000L ++#define RCC_DEV0_EPF5_STRAP0__STRAP_D1_SUPPORT_DEV0_F5__MASK 0x40000000L ++#define RCC_DEV0_EPF5_STRAP0__STRAP_D2_SUPPORT_DEV0_F5__MASK 0x80000000L ++//RCC_DEV0_EPF5_STRAP2 ++#define RCC_DEV0_EPF5_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F5__MASK 0x00000080L ++#define RCC_DEV0_EPF5_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F5__MASK 0x00000100L ++#define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F5__MASK 0x00004000L ++#define RCC_DEV0_EPF5_STRAP2__STRAP_AER_EN_DEV0_F5__MASK 0x00010000L ++#define RCC_DEV0_EPF5_STRAP2__STRAP_ACS_EN_DEV0_F5__MASK 0x00020000L ++#define RCC_DEV0_EPF5_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F5__MASK 0x00100000L ++#define RCC_DEV0_EPF5_STRAP2__STRAP_DPA_EN_DEV0_F5__MASK 0x00200000L ++#define RCC_DEV0_EPF5_STRAP2__STRAP_VC_EN_DEV0_F5__MASK 0x00800000L ++#define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F5__MASK 0x07000000L ++//RCC_DEV0_EPF5_STRAP3 ++#define RCC_DEV0_EPF5_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F5__MASK 0x00000001L ++#define RCC_DEV0_EPF5_STRAP3__STRAP_PWR_EN_DEV0_F5__MASK 0x00000002L ++#define RCC_DEV0_EPF5_STRAP3__STRAP_SUBSYS_ID_DEV0_F5__MASK 0x0003FFFCL ++#define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_EN_DEV0_F5__MASK 0x00040000L ++#define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F5__MASK 0x00080000L ++#define RCC_DEV0_EPF5_STRAP3__STRAP_MSIX_EN_DEV0_F5__MASK 0x00100000L ++#define RCC_DEV0_EPF5_STRAP3__STRAP_PMC_DSI_DEV0_F5__MASK 0x01000000L ++#define RCC_DEV0_EPF5_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F5__MASK 0x02000000L ++#define RCC_DEV0_EPF5_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F5__MASK 0x04000000L ++#define RCC_DEV0_EPF5_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F5__MASK 0x08000000L ++//RCC_DEV0_EPF5_STRAP4 ++#define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F5__MASK 0x00100000L ++#define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_EN_DEV0_F5__MASK 0x00200000L ++#define RCC_DEV0_EPF5_STRAP4__STRAP_FLR_EN_DEV0_F5__MASK 0x00400000L ++#define RCC_DEV0_EPF5_STRAP4__STRAP_PME_SUPPORT_DEV0_F5__MASK 0x0F800000L ++#define RCC_DEV0_EPF5_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F5__MASK 0x70000000L ++#define RCC_DEV0_EPF5_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F5__MASK 0x80000000L ++//RCC_DEV0_EPF5_STRAP5 ++#define RCC_DEV0_EPF5_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F5__MASK 0x0000FFFFL ++//RCC_DEV0_EPF5_STRAP6 ++#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_EN_DEV0_F5__MASK 0x00000001L ++#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F5__MASK 0x00000002L ++#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F5__MASK 0x00000070L ++#define RCC_DEV0_EPF5_STRAP6__STRAP_APER1_EN_DEV0_F5__MASK 0x00000100L ++#define RCC_DEV0_EPF5_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F5__MASK 0x00000200L ++#define RCC_DEV0_EPF5_STRAP6__STRAP_APER2_EN_DEV0_F5__MASK 0x00010000L ++#define RCC_DEV0_EPF5_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F5__MASK 0x00020000L ++//RCC_DEV0_EPF5_STRAP13 ++#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F5__MASK 0x000000FFL ++#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F5__MASK 0x0000FF00L ++#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F5__MASK 0x00FF0000L ++//RCC_DEV0_EPF6_STRAP0 ++#define RCC_DEV0_EPF6_STRAP0__STRAP_DEVICE_ID_DEV0_F6__MASK 0x0000FFFFL ++#define RCC_DEV0_EPF6_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F6__MASK 0x000F0000L ++#define RCC_DEV0_EPF6_STRAP0__STRAP_MINOR_REV_ID_DEV0_F6__MASK 0x00F00000L ++#define RCC_DEV0_EPF6_STRAP0__STRAP_FUNC_EN_DEV0_F6__MASK 0x10000000L ++#define RCC_DEV0_EPF6_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F6__MASK 0x20000000L ++#define RCC_DEV0_EPF6_STRAP0__STRAP_D1_SUPPORT_DEV0_F6__MASK 0x40000000L ++#define RCC_DEV0_EPF6_STRAP0__STRAP_D2_SUPPORT_DEV0_F6__MASK 0x80000000L ++//RCC_DEV0_EPF6_STRAP2 ++#define RCC_DEV0_EPF6_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F6__MASK 0x00000080L ++#define RCC_DEV0_EPF6_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F6__MASK 0x00000100L ++#define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F6__MASK 0x00004000L ++#define RCC_DEV0_EPF6_STRAP2__STRAP_AER_EN_DEV0_F6__MASK 0x00010000L ++#define RCC_DEV0_EPF6_STRAP2__STRAP_ACS_EN_DEV0_F6__MASK 0x00020000L ++#define RCC_DEV0_EPF6_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F6__MASK 0x00100000L ++#define RCC_DEV0_EPF6_STRAP2__STRAP_DPA_EN_DEV0_F6__MASK 0x00200000L ++#define RCC_DEV0_EPF6_STRAP2__STRAP_VC_EN_DEV0_F6__MASK 0x00800000L ++#define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F6__MASK 0x07000000L ++//RCC_DEV0_EPF6_STRAP3 ++#define RCC_DEV0_EPF6_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F6__MASK 0x00000001L ++#define RCC_DEV0_EPF6_STRAP3__STRAP_PWR_EN_DEV0_F6__MASK 0x00000002L ++#define RCC_DEV0_EPF6_STRAP3__STRAP_SUBSYS_ID_DEV0_F6__MASK 0x0003FFFCL ++#define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_EN_DEV0_F6__MASK 0x00040000L ++#define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F6__MASK 0x00080000L ++#define RCC_DEV0_EPF6_STRAP3__STRAP_MSIX_EN_DEV0_F6__MASK 0x00100000L ++#define RCC_DEV0_EPF6_STRAP3__STRAP_PMC_DSI_DEV0_F6__MASK 0x01000000L ++#define RCC_DEV0_EPF6_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F6__MASK 0x02000000L ++#define RCC_DEV0_EPF6_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F6__MASK 0x04000000L ++#define RCC_DEV0_EPF6_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F6__MASK 0x08000000L ++//RCC_DEV0_EPF6_STRAP4 ++#define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F6__MASK 0x00100000L ++#define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_EN_DEV0_F6__MASK 0x00200000L ++#define RCC_DEV0_EPF6_STRAP4__STRAP_FLR_EN_DEV0_F6__MASK 0x00400000L ++#define RCC_DEV0_EPF6_STRAP4__STRAP_PME_SUPPORT_DEV0_F6__MASK 0x0F800000L ++#define RCC_DEV0_EPF6_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F6__MASK 0x70000000L ++#define RCC_DEV0_EPF6_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F6__MASK 0x80000000L ++//RCC_DEV0_EPF6_STRAP5 ++#define RCC_DEV0_EPF6_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F6__MASK 0x0000FFFFL ++//RCC_DEV0_EPF6_STRAP6 ++#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_EN_DEV0_F6__MASK 0x00000001L ++#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F6__MASK 0x00000002L ++#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F6__MASK 0x00000070L ++#define RCC_DEV0_EPF6_STRAP6__STRAP_APER1_EN_DEV0_F6__MASK 0x00000100L ++#define RCC_DEV0_EPF6_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F6__MASK 0x00000200L ++#define RCC_DEV0_EPF6_STRAP6__STRAP_APER2_EN_DEV0_F6__MASK 0x00010000L ++#define RCC_DEV0_EPF6_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F6__MASK 0x00020000L ++//RCC_DEV0_EPF6_STRAP13 ++#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F6__MASK 0x000000FFL ++#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F6__MASK 0x0000FF00L ++#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F6__MASK 0x00FF0000L ++//RCC_DEV0_EPF7_STRAP0 ++#define RCC_DEV0_EPF7_STRAP0__STRAP_DEVICE_ID_DEV0_F7__MASK 0x0000FFFFL ++#define RCC_DEV0_EPF7_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F7__MASK 0x000F0000L ++#define RCC_DEV0_EPF7_STRAP0__STRAP_MINOR_REV_ID_DEV0_F7__MASK 0x00F00000L ++#define RCC_DEV0_EPF7_STRAP0__STRAP_FUNC_EN_DEV0_F7__MASK 0x10000000L ++#define RCC_DEV0_EPF7_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F7__MASK 0x20000000L ++#define RCC_DEV0_EPF7_STRAP0__STRAP_D1_SUPPORT_DEV0_F7__MASK 0x40000000L ++#define RCC_DEV0_EPF7_STRAP0__STRAP_D2_SUPPORT_DEV0_F7__MASK 0x80000000L ++//RCC_DEV0_EPF7_STRAP2 ++#define RCC_DEV0_EPF7_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F7__MASK 0x00000080L ++#define RCC_DEV0_EPF7_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F7__MASK 0x00000100L ++#define RCC_DEV0_EPF7_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F7__MASK 0x00004000L ++#define RCC_DEV0_EPF7_STRAP2__STRAP_AER_EN_DEV0_F7__MASK 0x00010000L ++#define RCC_DEV0_EPF7_STRAP2__STRAP_ACS_EN_DEV0_F7__MASK 0x00020000L ++#define RCC_DEV0_EPF7_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F7__MASK 0x00100000L ++#define RCC_DEV0_EPF7_STRAP2__STRAP_DPA_EN_DEV0_F7__MASK 0x00200000L ++#define RCC_DEV0_EPF7_STRAP2__STRAP_VC_EN_DEV0_F7__MASK 0x00800000L ++#define RCC_DEV0_EPF7_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F7__MASK 0x07000000L ++//RCC_DEV0_EPF7_STRAP3 ++#define RCC_DEV0_EPF7_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F7__MASK 0x00000001L ++#define RCC_DEV0_EPF7_STRAP3__STRAP_PWR_EN_DEV0_F7__MASK 0x00000002L ++#define RCC_DEV0_EPF7_STRAP3__STRAP_SUBSYS_ID_DEV0_F7__MASK 0x0003FFFCL ++#define RCC_DEV0_EPF7_STRAP3__STRAP_MSI_EN_DEV0_F7__MASK 0x00040000L ++#define RCC_DEV0_EPF7_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F7__MASK 0x00080000L ++#define RCC_DEV0_EPF7_STRAP3__STRAP_MSIX_EN_DEV0_F7__MASK 0x00100000L ++#define RCC_DEV0_EPF7_STRAP3__STRAP_PMC_DSI_DEV0_F7__MASK 0x01000000L ++#define RCC_DEV0_EPF7_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F7__MASK 0x02000000L ++#define RCC_DEV0_EPF7_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F7__MASK 0x04000000L ++#define RCC_DEV0_EPF7_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F7__MASK 0x08000000L ++//RCC_DEV0_EPF7_STRAP4 ++#define RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F7__MASK 0x00100000L ++#define RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_EN_DEV0_F7__MASK 0x00200000L ++#define RCC_DEV0_EPF7_STRAP4__STRAP_FLR_EN_DEV0_F7__MASK 0x00400000L ++#define RCC_DEV0_EPF7_STRAP4__STRAP_PME_SUPPORT_DEV0_F7__MASK 0x0F800000L ++#define RCC_DEV0_EPF7_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F7__MASK 0x70000000L ++#define RCC_DEV0_EPF7_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F7__MASK 0x80000000L ++//RCC_DEV0_EPF7_STRAP5 ++#define RCC_DEV0_EPF7_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F7__MASK 0x0000FFFFL ++//RCC_DEV0_EPF7_STRAP6 ++#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_EN_DEV0_F7__MASK 0x00000001L ++#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F7__MASK 0x00000002L ++#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F7__MASK 0x00000070L ++#define RCC_DEV0_EPF7_STRAP6__STRAP_APER1_EN_DEV0_F7__MASK 0x00000100L ++#define RCC_DEV0_EPF7_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F7__MASK 0x00000200L ++#define RCC_DEV0_EPF7_STRAP6__STRAP_APER2_EN_DEV0_F7__MASK 0x00010000L ++#define RCC_DEV0_EPF7_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F7__MASK 0x00020000L ++//RCC_DEV0_EPF7_STRAP13 ++#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F7__MASK 0x000000FFL ++#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F7__MASK 0x0000FF00L ++#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F7__MASK 0x00FF0000L ++//RCC_DEV1_EPF0_STRAP0 ++#define RCC_DEV1_EPF0_STRAP0__STRAP_DEVICE_ID_DEV1_F0__MASK 0x0000FFFFL ++#define RCC_DEV1_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F0__MASK 0x000F0000L ++#define RCC_DEV1_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV1_F0__MASK 0x00F00000L ++#define RCC_DEV1_EPF0_STRAP0__STRAP_FUNC_EN_DEV1_F0__MASK 0x10000000L ++#define RCC_DEV1_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F0__MASK 0x20000000L ++#define RCC_DEV1_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV1_F0__MASK 0x40000000L ++#define RCC_DEV1_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV1_F0__MASK 0x80000000L ++//RCC_DEV1_EPF0_STRAP2 ++#define RCC_DEV1_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F0__MASK 0x00000080L ++#define RCC_DEV1_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F0__MASK 0x00000100L ++#define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F0__MASK 0x00004000L ++#define RCC_DEV1_EPF0_STRAP2__STRAP_ARI_EN_DEV1_F0__MASK 0x00008000L ++#define RCC_DEV1_EPF0_STRAP2__STRAP_AER_EN_DEV1_F0__MASK 0x00010000L ++#define RCC_DEV1_EPF0_STRAP2__STRAP_ACS_EN_DEV1_F0__MASK 0x00020000L ++#define RCC_DEV1_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F0__MASK 0x00100000L ++#define RCC_DEV1_EPF0_STRAP2__STRAP_DPA_EN_DEV1_F0__MASK 0x00200000L ++#define RCC_DEV1_EPF0_STRAP2__STRAP_VC_EN_DEV1_F0__MASK 0x00800000L ++#define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F0__MASK 0x07000000L ++//RCC_DEV1_EPF0_STRAP3 ++#define RCC_DEV1_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F0__MASK 0x00000001L ++#define RCC_DEV1_EPF0_STRAP3__STRAP_PWR_EN_DEV1_F0__MASK 0x00000002L ++#define RCC_DEV1_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV1_F0__MASK 0x0003FFFCL ++#define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_EN_DEV1_F0__MASK 0x00040000L ++#define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F0__MASK 0x00080000L ++#define RCC_DEV1_EPF0_STRAP3__STRAP_MSIX_EN_DEV1_F0__MASK 0x00100000L ++#define RCC_DEV1_EPF0_STRAP3__STRAP_PMC_DSI_DEV1_F0__MASK 0x01000000L ++#define RCC_DEV1_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F0__MASK 0x02000000L ++#define RCC_DEV1_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F0__MASK 0x04000000L ++#define RCC_DEV1_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F0__MASK 0x08000000L ++//RCC_DEV1_EPF0_STRAP4 ++#define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F0__MASK 0x00100000L ++#define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV1_F0__MASK 0x00200000L ++#define RCC_DEV1_EPF0_STRAP4__STRAP_FLR_EN_DEV1_F0__MASK 0x00400000L ++#define RCC_DEV1_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV1_F0__MASK 0x0F800000L ++#define RCC_DEV1_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F0__MASK 0x70000000L ++#define RCC_DEV1_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F0__MASK 0x80000000L ++//RCC_DEV1_EPF0_STRAP5 ++#define RCC_DEV1_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F0__MASK 0x0000FFFFL ++#define RCC_DEV1_EPF0_STRAP5__STRAP_SATAIDP_EN_DEV1_F0__MASK 0x01000000L ++//RCC_DEV1_EPF0_STRAP6 ++#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_EN_DEV1_F0__MASK 0x00000001L ++#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F0__MASK 0x00000002L ++#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F0__MASK 0x00000070L ++//RCC_DEV1_EPF0_STRAP13 ++#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F0__MASK 0x000000FFL ++#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F0__MASK 0x0000FF00L ++#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F0__MASK 0x00FF0000L ++//RCC_DEV1_EPF1_STRAP0 ++#define RCC_DEV1_EPF1_STRAP0__STRAP_DEVICE_ID_DEV1_F1__MASK 0x0000FFFFL ++#define RCC_DEV1_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F1__MASK 0x000F0000L ++#define RCC_DEV1_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV1_F1__MASK 0x00F00000L ++#define RCC_DEV1_EPF1_STRAP0__STRAP_FUNC_EN_DEV1_F1__MASK 0x10000000L ++#define RCC_DEV1_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F1__MASK 0x20000000L ++#define RCC_DEV1_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV1_F1__MASK 0x40000000L ++#define RCC_DEV1_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV1_F1__MASK 0x80000000L ++//RCC_DEV1_EPF1_STRAP2 ++#define RCC_DEV1_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F1__MASK 0x00000080L ++#define RCC_DEV1_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F1__MASK 0x00000100L ++#define RCC_DEV1_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F1__MASK 0x00004000L ++#define RCC_DEV1_EPF1_STRAP2__STRAP_AER_EN_DEV1_F1__MASK 0x00010000L ++#define RCC_DEV1_EPF1_STRAP2__STRAP_ACS_EN_DEV1_F1__MASK 0x00020000L ++#define RCC_DEV1_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F1__MASK 0x00100000L ++#define RCC_DEV1_EPF1_STRAP2__STRAP_DPA_EN_DEV1_F1__MASK 0x00200000L ++#define RCC_DEV1_EPF1_STRAP2__STRAP_VC_EN_DEV1_F1__MASK 0x00800000L ++#define RCC_DEV1_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F1__MASK 0x07000000L ++//RCC_DEV1_EPF1_STRAP3 ++#define RCC_DEV1_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F1__MASK 0x00000001L ++#define RCC_DEV1_EPF1_STRAP3__STRAP_PWR_EN_DEV1_F1__MASK 0x00000002L ++#define RCC_DEV1_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV1_F1__MASK 0x0003FFFCL ++#define RCC_DEV1_EPF1_STRAP3__STRAP_MSI_EN_DEV1_F1__MASK 0x00040000L ++#define RCC_DEV1_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F1__MASK 0x00080000L ++#define RCC_DEV1_EPF1_STRAP3__STRAP_MSIX_EN_DEV1_F1__MASK 0x00100000L ++#define RCC_DEV1_EPF1_STRAP3__STRAP_PMC_DSI_DEV1_F1__MASK 0x01000000L ++#define RCC_DEV1_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F1__MASK 0x02000000L ++#define RCC_DEV1_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F1__MASK 0x04000000L ++#define RCC_DEV1_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F1__MASK 0x08000000L ++//RCC_DEV1_EPF1_STRAP4 ++#define RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F1__MASK 0x00100000L ++#define RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV1_F1__MASK 0x00200000L ++#define RCC_DEV1_EPF1_STRAP4__STRAP_FLR_EN_DEV1_F1__MASK 0x00400000L ++#define RCC_DEV1_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV1_F1__MASK 0x0F800000L ++#define RCC_DEV1_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F1__MASK 0x70000000L ++#define RCC_DEV1_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F1__MASK 0x80000000L ++//RCC_DEV1_EPF1_STRAP5 ++#define RCC_DEV1_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F1__MASK 0x0000FFFFL ++//RCC_DEV1_EPF1_STRAP6 ++#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_EN_DEV1_F1__MASK 0x00000001L ++#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F1__MASK 0x00000002L ++#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F1__MASK 0x00000070L ++#define RCC_DEV1_EPF1_STRAP6__STRAP_APER1_EN_DEV1_F1__MASK 0x00000100L ++#define RCC_DEV1_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV1_F1__MASK 0x00000200L ++#define RCC_DEV1_EPF1_STRAP6__STRAP_APER2_EN_DEV1_F1__MASK 0x00010000L ++#define RCC_DEV1_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV1_F1__MASK 0x00020000L ++#define RCC_DEV1_EPF1_STRAP6__STRAP_APER3_EN_DEV1_F1__MASK 0x01000000L ++#define RCC_DEV1_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV1_F1__MASK 0x02000000L ++//RCC_DEV1_EPF1_STRAP13 ++#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F1__MASK 0x000000FFL ++#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F1__MASK 0x0000FF00L ++#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F1__MASK 0x00FF0000L ++//RCC_DEV1_EPF2_STRAP0 ++#define RCC_DEV1_EPF2_STRAP0__STRAP_DEVICE_ID_DEV1_F2__MASK 0x0000FFFFL ++#define RCC_DEV1_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F2__MASK 0x000F0000L ++#define RCC_DEV1_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV1_F2__MASK 0x00F00000L ++#define RCC_DEV1_EPF2_STRAP0__STRAP_FUNC_EN_DEV1_F2__MASK 0x10000000L ++#define RCC_DEV1_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F2__MASK 0x20000000L ++#define RCC_DEV1_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV1_F2__MASK 0x40000000L ++#define RCC_DEV1_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV1_F2__MASK 0x80000000L ++//RCC_DEV1_EPF2_STRAP2 ++#define RCC_DEV1_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F2__MASK 0x00000080L ++#define RCC_DEV1_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F2__MASK 0x00000100L ++#define RCC_DEV1_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F2__MASK 0x00004000L ++#define RCC_DEV1_EPF2_STRAP2__STRAP_AER_EN_DEV1_F2__MASK 0x00010000L ++#define RCC_DEV1_EPF2_STRAP2__STRAP_ACS_EN_DEV1_F2__MASK 0x00020000L ++#define RCC_DEV1_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F2__MASK 0x00100000L ++#define RCC_DEV1_EPF2_STRAP2__STRAP_DPA_EN_DEV1_F2__MASK 0x00200000L ++#define RCC_DEV1_EPF2_STRAP2__STRAP_VC_EN_DEV1_F2__MASK 0x00800000L ++#define RCC_DEV1_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F2__MASK 0x07000000L ++//RCC_DEV1_EPF2_STRAP3 ++#define RCC_DEV1_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F2__MASK 0x00000001L ++#define RCC_DEV1_EPF2_STRAP3__STRAP_PWR_EN_DEV1_F2__MASK 0x00000002L ++#define RCC_DEV1_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV1_F2__MASK 0x0003FFFCL ++#define RCC_DEV1_EPF2_STRAP3__STRAP_MSI_EN_DEV1_F2__MASK 0x00040000L ++#define RCC_DEV1_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F2__MASK 0x00080000L ++#define RCC_DEV1_EPF2_STRAP3__STRAP_MSIX_EN_DEV1_F2__MASK 0x00100000L ++#define RCC_DEV1_EPF2_STRAP3__STRAP_PMC_DSI_DEV1_F2__MASK 0x01000000L ++#define RCC_DEV1_EPF2_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F2__MASK 0x02000000L ++#define RCC_DEV1_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F2__MASK 0x04000000L ++#define RCC_DEV1_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F2__MASK 0x08000000L ++//RCC_DEV1_EPF2_STRAP4 ++#define RCC_DEV1_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F2__MASK 0x00100000L ++#define RCC_DEV1_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV1_F2__MASK 0x00200000L ++#define RCC_DEV1_EPF2_STRAP4__STRAP_FLR_EN_DEV1_F2__MASK 0x00400000L ++#define RCC_DEV1_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV1_F2__MASK 0x0F800000L ++#define RCC_DEV1_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F2__MASK 0x70000000L ++#define RCC_DEV1_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F2__MASK 0x80000000L ++//RCC_DEV1_EPF2_STRAP5 ++#define RCC_DEV1_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F2__MASK 0x0000FFFFL ++//RCC_DEV1_EPF2_STRAP6 ++#define RCC_DEV1_EPF2_STRAP6__STRAP_APER0_EN_DEV1_F2__MASK 0x00000001L ++#define RCC_DEV1_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F2__MASK 0x00000002L ++#define RCC_DEV1_EPF2_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F2__MASK 0x00000070L ++#define RCC_DEV1_EPF2_STRAP6__STRAP_APER1_EN_DEV1_F2__MASK 0x00000100L ++#define RCC_DEV1_EPF2_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV1_F2__MASK 0x00000200L ++#define RCC_DEV1_EPF2_STRAP6__STRAP_APER2_EN_DEV1_F2__MASK 0x00010000L ++#define RCC_DEV1_EPF2_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV1_F2__MASK 0x00020000L ++#define RCC_DEV1_EPF2_STRAP6__STRAP_APER3_EN_DEV1_F2__MASK 0x01000000L ++#define RCC_DEV1_EPF2_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV1_F2__MASK 0x02000000L ++//RCC_DEV1_EPF2_STRAP13 ++#define RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F2__MASK 0x000000FFL ++#define RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F2__MASK 0x0000FF00L ++#define RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F2__MASK 0x00FF0000L ++ ++ ++// addressBlock: bif_rst_bif_rst_regblk ++//HARD_RST_CTRL ++#define HARD_RST_CTRL__DSPT_CFG_RST_EN__MASK 0x00000001L ++#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN__MASK 0x00000002L ++#define HARD_RST_CTRL__DSPT_PRV_RST_EN__MASK 0x00000004L ++#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN__MASK 0x00000008L ++#define HARD_RST_CTRL__EP_CFG_RST_EN__MASK 0x00000010L ++#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN__MASK 0x00000020L ++#define HARD_RST_CTRL__EP_PRV_RST_EN__MASK 0x00000040L ++#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN__MASK 0x00000080L ++#define HARD_RST_CTRL__SWUS_SHADOW_RST_EN__MASK 0x10000000L ++#define HARD_RST_CTRL__CORE_STICKY_RST_EN__MASK 0x20000000L ++#define HARD_RST_CTRL__RELOAD_STRAP_EN__MASK 0x40000000L ++#define HARD_RST_CTRL__CORE_RST_EN__MASK 0x80000000L ++//RSMU_SOFT_RST_CTRL ++#define RSMU_SOFT_RST_CTRL__DSPT_CFG_RST_EN__MASK 0x00000001L ++#define RSMU_SOFT_RST_CTRL__DSPT_CFG_STICKY_RST_EN__MASK 0x00000002L ++#define RSMU_SOFT_RST_CTRL__DSPT_PRV_RST_EN__MASK 0x00000004L ++#define RSMU_SOFT_RST_CTRL__DSPT_PRV_STICKY_RST_EN__MASK 0x00000008L ++#define RSMU_SOFT_RST_CTRL__EP_CFG_RST_EN__MASK 0x00000010L ++#define RSMU_SOFT_RST_CTRL__EP_CFG_STICKY_RST_EN__MASK 0x00000020L ++#define RSMU_SOFT_RST_CTRL__EP_PRV_RST_EN__MASK 0x00000040L ++#define RSMU_SOFT_RST_CTRL__EP_PRV_STICKY_RST_EN__MASK 0x00000080L ++#define RSMU_SOFT_RST_CTRL__SWUS_SHADOW_RST_EN__MASK 0x10000000L ++#define RSMU_SOFT_RST_CTRL__CORE_STICKY_RST_EN__MASK 0x20000000L ++#define RSMU_SOFT_RST_CTRL__RELOAD_STRAP_EN__MASK 0x40000000L ++#define RSMU_SOFT_RST_CTRL__CORE_RST_EN__MASK 0x80000000L ++//SELF_SOFT_RST ++#define SELF_SOFT_RST__DSPT0_CFG_RST__MASK 0x00000001L ++#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST__MASK 0x00000002L ++#define SELF_SOFT_RST__DSPT0_PRV_RST__MASK 0x00000004L ++#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST__MASK 0x00000008L ++#define SELF_SOFT_RST__EP0_CFG_RST__MASK 0x00000010L ++#define SELF_SOFT_RST__EP0_CFG_STICKY_RST__MASK 0x00000020L ++#define SELF_SOFT_RST__EP0_PRV_RST__MASK 0x00000040L ++#define SELF_SOFT_RST__EP0_PRV_STICKY_RST__MASK 0x00000080L ++#define SELF_SOFT_RST__SDP_PORT_RST__MASK 0x08000000L ++#define SELF_SOFT_RST__SWUS_SHADOW_RST__MASK 0x10000000L ++#define SELF_SOFT_RST__CORE_STICKY_RST__MASK 0x20000000L ++#define SELF_SOFT_RST__RELOAD_STRAP__MASK 0x40000000L ++#define SELF_SOFT_RST__CORE_RST__MASK 0x80000000L ++//GFX_DRV_MODE1_RST_CTRL ++#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_RST__MASK 0x00000001L ++#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_FLR_EXC_RST__MASK 0x00000002L ++#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_STICKY_RST__MASK 0x00000004L ++#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_PRV_RST__MASK 0x00000008L ++#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_PRV_STICKY_RST__MASK 0x00000010L ++#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_CFG_RST__MASK 0x00000020L ++#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_CFG_STICKY_RST__MASK 0x00000040L ++#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_PRV_RST__MASK 0x00000080L ++//BIF_RST_MISC_CTRL ++#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB__MASK 0x00000001L ++#define BIF_RST_MISC_CTRL__DRV_RST_MODE__MASK 0x0000000CL ++#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK__MASK 0x00000010L ++#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR__MASK 0x00000020L ++#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR__MASK 0x00000040L ++#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN__MASK 0x00000100L ++#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE__MASK 0x00000200L ++#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT__MASK 0x00001C00L ++#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL__MASK 0x00006000L ++#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL__MASK 0x00018000L ++#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__MASK 0x00060000L ++#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS__MASK 0x00800000L ++#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS__MASK 0x03000000L ++//BIF_RST_MISC_CTRL2 ++#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE__MASK 0x00010000L ++#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE__MASK 0x00020000L ++#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE__MASK 0x00040000L ++#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE__MASK 0x80000000L ++//BIF_RST_MISC_CTRL3 ++#define BIF_RST_MISC_CTRL3__TIMER_SCALE__MASK 0x0000000FL ++#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT__MASK 0x00000030L ++#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE__MASK 0x00000040L ++#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD__MASK 0x00000380L ++#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT__MASK 0x00001C00L ++#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF__MASK 0x0000E000L ++//BIF_RST_GFXVF_FLR_IDLE ++#define BIF_RST_GFXVF_FLR_IDLE__VF0_TRANS_IDLE__MASK 0x00000001L ++#define BIF_RST_GFXVF_FLR_IDLE__VF1_TRANS_IDLE__MASK 0x00000002L ++#define BIF_RST_GFXVF_FLR_IDLE__VF2_TRANS_IDLE__MASK 0x00000004L ++#define BIF_RST_GFXVF_FLR_IDLE__VF3_TRANS_IDLE__MASK 0x00000008L ++#define BIF_RST_GFXVF_FLR_IDLE__VF4_TRANS_IDLE__MASK 0x00000010L ++#define BIF_RST_GFXVF_FLR_IDLE__VF5_TRANS_IDLE__MASK 0x00000020L ++#define BIF_RST_GFXVF_FLR_IDLE__VF6_TRANS_IDLE__MASK 0x00000040L ++#define BIF_RST_GFXVF_FLR_IDLE__VF7_TRANS_IDLE__MASK 0x00000080L ++#define BIF_RST_GFXVF_FLR_IDLE__VF8_TRANS_IDLE__MASK 0x00000100L ++#define BIF_RST_GFXVF_FLR_IDLE__VF9_TRANS_IDLE__MASK 0x00000200L ++#define BIF_RST_GFXVF_FLR_IDLE__VF10_TRANS_IDLE__MASK 0x00000400L ++#define BIF_RST_GFXVF_FLR_IDLE__VF11_TRANS_IDLE__MASK 0x00000800L ++#define BIF_RST_GFXVF_FLR_IDLE__VF12_TRANS_IDLE__MASK 0x00001000L ++#define BIF_RST_GFXVF_FLR_IDLE__VF13_TRANS_IDLE__MASK 0x00002000L ++#define BIF_RST_GFXVF_FLR_IDLE__VF14_TRANS_IDLE__MASK 0x00004000L ++#define BIF_RST_GFXVF_FLR_IDLE__VF15_TRANS_IDLE__MASK 0x00008000L ++#define BIF_RST_GFXVF_FLR_IDLE__SOFTPF_TRANS_IDLE__MASK 0x80000000L ++//DEV0_PF0_FLR_RST_CTRL ++#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L ++#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L ++#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L ++#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L ++#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L ++#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN__MASK 0x00000020L ++#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN__MASK 0x00000040L ++#define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN__MASK 0x00000080L ++#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN__MASK 0x00000100L ++#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN__MASK 0x00000200L ++#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN__MASK 0x00000400L ++#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN__MASK 0x00000800L ++#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN__MASK 0x00001000L ++#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN__MASK 0x00002000L ++#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN__MASK 0x00004000L ++#define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN__MASK 0x00008000L ++#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN__MASK 0x00010000L ++#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L ++#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L ++#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L ++#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L ++//DEV0_PF1_FLR_RST_CTRL ++#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L ++#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L ++#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L ++#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L ++#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L ++#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L ++#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L ++#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L ++#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L ++//DEV0_PF2_FLR_RST_CTRL ++#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L ++#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L ++#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L ++#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L ++#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L ++#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L ++#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L ++#define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L ++#define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L ++//DEV0_PF3_FLR_RST_CTRL ++#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L ++#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L ++#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L ++#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L ++#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L ++#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L ++#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L ++#define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L ++#define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L ++//DEV0_PF4_FLR_RST_CTRL ++#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L ++#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L ++#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L ++#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L ++#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L ++#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L ++#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L ++#define DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L ++#define DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L ++//DEV0_PF5_FLR_RST_CTRL ++#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L ++#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L ++#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L ++#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L ++#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L ++#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L ++#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L ++#define DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L ++#define DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L ++//DEV0_PF6_FLR_RST_CTRL ++#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L ++#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L ++#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L ++#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L ++#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L ++#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L ++#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L ++#define DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L ++#define DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L ++//DEV0_PF7_FLR_RST_CTRL ++#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L ++#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L ++#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L ++#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L ++#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L ++#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L ++#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L ++#define DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L ++#define DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L ++//BIF_INST_RESET_INTR_STS ++#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS__MASK 0x00000001L ++#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS__MASK 0x00000002L ++#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS__MASK 0x00000004L ++#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS__MASK 0x00000008L ++#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS__MASK 0x00000010L ++//BIF_PF_FLR_INTR_STS ++#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS__MASK 0x00000001L ++#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS__MASK 0x00000002L ++#define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS__MASK 0x00000004L ++#define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS__MASK 0x00000008L ++#define BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS__MASK 0x00000010L ++#define BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS__MASK 0x00000020L ++#define BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS__MASK 0x00000040L ++#define BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS__MASK 0x00000080L ++//BIF_D3HOTD0_INTR_STS ++#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS__MASK 0x00000001L ++#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS__MASK 0x00000002L ++#define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS__MASK 0x00000004L ++#define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS__MASK 0x00000008L ++#define BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS__MASK 0x00000010L ++#define BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS__MASK 0x00000020L ++#define BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS__MASK 0x00000040L ++#define BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS__MASK 0x00000080L ++//BIF_POWER_INTR_STS ++#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS__MASK 0x00000001L ++#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS__MASK 0x00010000L ++//BIF_PF_DSTATE_INTR_STS ++#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS__MASK 0x00000001L ++#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS__MASK 0x00000002L ++#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS__MASK 0x00000004L ++#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS__MASK 0x00000008L ++#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS__MASK 0x00000010L ++#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS__MASK 0x00000020L ++#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS__MASK 0x00000040L ++#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS__MASK 0x00000080L ++//BIF_PF0_VF_FLR_INTR_STS ++#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF0_FLR_INTR_STS__MASK 0x00000001L ++#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF1_FLR_INTR_STS__MASK 0x00000002L ++#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF2_FLR_INTR_STS__MASK 0x00000004L ++#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF3_FLR_INTR_STS__MASK 0x00000008L ++#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF4_FLR_INTR_STS__MASK 0x00000010L ++#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF5_FLR_INTR_STS__MASK 0x00000020L ++#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF6_FLR_INTR_STS__MASK 0x00000040L ++#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF7_FLR_INTR_STS__MASK 0x00000080L ++#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF8_FLR_INTR_STS__MASK 0x00000100L ++#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF9_FLR_INTR_STS__MASK 0x00000200L ++#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF10_FLR_INTR_STS__MASK 0x00000400L ++#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF11_FLR_INTR_STS__MASK 0x00000800L ++#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF12_FLR_INTR_STS__MASK 0x00001000L ++#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF13_FLR_INTR_STS__MASK 0x00002000L ++#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF14_FLR_INTR_STS__MASK 0x00004000L ++#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF15_FLR_INTR_STS__MASK 0x00008000L ++#define BIF_PF0_VF_FLR_INTR_STS__PF0_SOFTPF_FLR_INTR_STS__MASK 0x80000000L ++//BIF_INST_RESET_INTR_MASK ++#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK__MASK 0x00000001L ++#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK__MASK 0x00000002L ++#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK__MASK 0x00000004L ++#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK__MASK 0x00000008L ++#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK__MASK 0x00000010L ++//BIF_PF_FLR_INTR_MASK ++#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK__MASK 0x00000001L ++#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK__MASK 0x00000002L ++#define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK__MASK 0x00000004L ++#define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK__MASK 0x00000008L ++#define BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK__MASK 0x00000010L ++#define BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK__MASK 0x00000020L ++#define BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK__MASK 0x00000040L ++#define BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK__MASK 0x00000080L ++//BIF_D3HOTD0_INTR_MASK ++#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK__MASK 0x00000001L ++#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK__MASK 0x00000002L ++#define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK__MASK 0x00000004L ++#define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK__MASK 0x00000008L ++#define BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK__MASK 0x00000010L ++#define BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK__MASK 0x00000020L ++#define BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK__MASK 0x00000040L ++#define BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK__MASK 0x00000080L ++//BIF_POWER_INTR_MASK ++#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK__MASK 0x00000001L ++#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__MASK 0x00010000L ++//BIF_PF_DSTATE_INTR_MASK ++#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK__MASK 0x00000001L ++#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK__MASK 0x00000002L ++#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK__MASK 0x00000004L ++#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK__MASK 0x00000008L ++#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK__MASK 0x00000010L ++#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK__MASK 0x00000020L ++#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK__MASK 0x00000040L ++#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK__MASK 0x00000080L ++//BIF_PF0_VF_FLR_INTR_MASK ++#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF0_FLR_INTR_MASK__MASK 0x00000001L ++#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF1_FLR_INTR_MASK__MASK 0x00000002L ++#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF2_FLR_INTR_MASK__MASK 0x00000004L ++#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF3_FLR_INTR_MASK__MASK 0x00000008L ++#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF4_FLR_INTR_MASK__MASK 0x00000010L ++#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF5_FLR_INTR_MASK__MASK 0x00000020L ++#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF6_FLR_INTR_MASK__MASK 0x00000040L ++#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF7_FLR_INTR_MASK__MASK 0x00000080L ++#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF8_FLR_INTR_MASK__MASK 0x00000100L ++#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF9_FLR_INTR_MASK__MASK 0x00000200L ++#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF10_FLR_INTR_MASK__MASK 0x00000400L ++#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF11_FLR_INTR_MASK__MASK 0x00000800L ++#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF12_FLR_INTR_MASK__MASK 0x00001000L ++#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF13_FLR_INTR_MASK__MASK 0x00002000L ++#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF14_FLR_INTR_MASK__MASK 0x00004000L ++#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF15_FLR_INTR_MASK__MASK 0x00008000L ++#define BIF_PF0_VF_FLR_INTR_MASK__PF0_SOFTPF_FLR_INTR_MASK__MASK 0x80000000L ++//BIF_PF_FLR_RST ++#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST__MASK 0x00000001L ++#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST__MASK 0x00000002L ++#define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST__MASK 0x00000004L ++#define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST__MASK 0x00000008L ++#define BIF_PF_FLR_RST__DEV0_PF4_FLR_RST__MASK 0x00000010L ++#define BIF_PF_FLR_RST__DEV0_PF5_FLR_RST__MASK 0x00000020L ++#define BIF_PF_FLR_RST__DEV0_PF6_FLR_RST__MASK 0x00000040L ++#define BIF_PF_FLR_RST__DEV0_PF7_FLR_RST__MASK 0x00000080L ++//BIF_PF0_VF_FLR_RST ++#define BIF_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__MASK 0x00000001L ++#define BIF_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__MASK 0x00000002L ++#define BIF_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__MASK 0x00000004L ++#define BIF_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__MASK 0x00000008L ++#define BIF_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__MASK 0x00000010L ++#define BIF_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__MASK 0x00000020L ++#define BIF_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__MASK 0x00000040L ++#define BIF_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__MASK 0x00000080L ++#define BIF_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__MASK 0x00000100L ++#define BIF_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__MASK 0x00000200L ++#define BIF_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__MASK 0x00000400L ++#define BIF_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__MASK 0x00000800L ++#define BIF_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__MASK 0x00001000L ++#define BIF_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__MASK 0x00002000L ++#define BIF_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__MASK 0x00004000L ++#define BIF_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__MASK 0x00008000L ++#define BIF_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__MASK 0x80000000L ++//BIF_DEV0_PF0_DSTATE_VALUE ++#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE__MASK 0x00000003L ++#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L ++#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE__MASK 0x00030000L ++//BIF_DEV0_PF1_DSTATE_VALUE ++#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE__MASK 0x00000003L ++#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L ++#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE__MASK 0x00030000L ++//BIF_DEV0_PF2_DSTATE_VALUE ++#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE__MASK 0x00000003L ++#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L ++#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE__MASK 0x00030000L ++//BIF_DEV0_PF3_DSTATE_VALUE ++#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE__MASK 0x00000003L ++#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L ++#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE__MASK 0x00030000L ++//BIF_DEV0_PF4_DSTATE_VALUE ++#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE__MASK 0x00000003L ++#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L ++#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE__MASK 0x00030000L ++//BIF_DEV0_PF5_DSTATE_VALUE ++#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE__MASK 0x00000003L ++#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L ++#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE__MASK 0x00030000L ++//BIF_DEV0_PF6_DSTATE_VALUE ++#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE__MASK 0x00000003L ++#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L ++#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE__MASK 0x00030000L ++//BIF_DEV0_PF7_DSTATE_VALUE ++#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE__MASK 0x00000003L ++#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L ++#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE__MASK 0x00030000L ++//DEV0_PF0_D3HOTD0_RST_CTRL ++#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L ++#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L ++#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L ++#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L ++#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L ++//DEV0_PF1_D3HOTD0_RST_CTRL ++#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L ++#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L ++#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L ++#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L ++#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L ++//DEV0_PF2_D3HOTD0_RST_CTRL ++#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L ++#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L ++#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L ++#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L ++#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L ++//DEV0_PF3_D3HOTD0_RST_CTRL ++#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L ++#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L ++#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L ++#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L ++#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L ++//DEV0_PF4_D3HOTD0_RST_CTRL ++#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L ++#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L ++#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L ++#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L ++#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L ++//DEV0_PF5_D3HOTD0_RST_CTRL ++#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L ++#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L ++#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L ++#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L ++#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L ++//DEV0_PF6_D3HOTD0_RST_CTRL ++#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L ++#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L ++#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L ++#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L ++#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L ++//DEV0_PF7_D3HOTD0_RST_CTRL ++#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L ++#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L ++#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L ++#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L ++#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L ++//BIF_PORT0_DSTATE_VALUE ++#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE__MASK 0x00000003L ++#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE__MASK 0x00030000L ++ ++ ++// addressBlock: bif_misc_bif_misc_regblk ++//MISC_SCRATCH ++#define MISC_SCRATCH__MISC_SCRATCH0__MASK 0xFFFFFFFFL ++//INTR_LINE_POLARITY ++#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0__MASK 0x000000FFL ++//INTR_LINE_ENABLE ++#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0__MASK 0x000000FFL ++//OUTSTANDING_VC_ALLOC ++#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC__MASK 0x00000003L ++#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC__MASK 0x0000000CL ++#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC__MASK 0x00000030L ++#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC__MASK 0x000000C0L ++#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC__MASK 0x00000300L ++#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC__MASK 0x00000C00L ++#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC__MASK 0x00003000L ++#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC__MASK 0x0000C000L ++#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD__MASK 0x000F0000L ++#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC__MASK 0x03000000L ++#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC__MASK 0x0C000000L ++#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD__MASK 0xF0000000L ++//BIFC_MISC_CTRL0 ++#define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN__MASK 0x00000001L ++#define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN__MASK 0x00000006L ++#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE__MASK 0x00000100L ++#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK__MASK 0x00000200L ++#define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK__MASK 0x00000400L ++#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS__MASK 0x00010000L ++#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL__MASK 0x00020000L ++#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS__MASK 0x01000000L ++#define BIFC_MISC_CTRL0__VC7_DMA_IOCFG_DIS__MASK 0x02000000L ++#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS__MASK 0x04000000L ++#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE__MASK 0x08000000L ++#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE__MASK 0x10000000L ++#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION__MASK 0x80000000L ++//BIFC_MISC_CTRL1 ++#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT__MASK 0x00000001L ++#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT__MASK 0x00000002L ++#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT__MASK 0x00000004L ++#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT__MASK 0x00000008L ++#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS__MASK 0x00000010L ++#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR__MASK 0x00000020L ++#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS__MASK 0x00000040L ++#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL__MASK 0x00000080L ++#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS__MASK 0x00000300L ++#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS__MASK 0x00000C00L ++#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ__MASK 0x00001000L ++#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE__MASK 0x00002000L ++#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE__MASK 0x00004000L ++#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1__MASK 0x00008000L ++#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS__MASK 0x00010000L ++#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS__MASK 0x00020000L ++#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS__MASK 0x00040000L ++#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS__MASK 0x00080000L ++//BIFC_BME_ERR_LOG ++#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F0__MASK 0x00000001L ++#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F1__MASK 0x00000002L ++#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F2__MASK 0x00000004L ++#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F3__MASK 0x00000008L ++#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F4__MASK 0x00000010L ++#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F5__MASK 0x00000020L ++#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F6__MASK 0x00000040L ++#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F7__MASK 0x00000080L ++#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F0__MASK 0x00010000L ++#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F1__MASK 0x00020000L ++#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F2__MASK 0x00040000L ++#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F3__MASK 0x00080000L ++#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F4__MASK 0x00100000L ++#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F5__MASK 0x00200000L ++#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F6__MASK 0x00400000L ++#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F7__MASK 0x00800000L ++//BIFC_RCCBIH_BME_ERR_LOG ++#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F0__MASK 0x00000001L ++#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F1__MASK 0x00000002L ++#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F2__MASK 0x00000004L ++#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F3__MASK 0x00000008L ++#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F4__MASK 0x00000010L ++#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F5__MASK 0x00000020L ++#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F6__MASK 0x00000040L ++#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F7__MASK 0x00000080L ++#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__MASK 0x00010000L ++#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__MASK 0x00020000L ++#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2__MASK 0x00040000L ++#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3__MASK 0x00080000L ++#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4__MASK 0x00100000L ++#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5__MASK 0x00200000L ++#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6__MASK 0x00400000L ++#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7__MASK 0x00800000L ++//BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0__MASK 0x00000003L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0__MASK 0x0000000CL ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0__MASK 0x000000C0L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0__MASK 0x00000300L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0__MASK 0x00000C00L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0__MASK 0x00003000L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1__MASK 0x00030000L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1__MASK 0x000C0000L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1__MASK 0x00C00000L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1__MASK 0x03000000L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1__MASK 0x0C000000L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1__MASK 0x30000000L ++//BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2__MASK 0x00000003L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2__MASK 0x0000000CL ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2__MASK 0x000000C0L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2__MASK 0x00000300L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2__MASK 0x00000C00L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2__MASK 0x00003000L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3__MASK 0x00030000L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3__MASK 0x000C0000L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3__MASK 0x00C00000L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3__MASK 0x03000000L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3__MASK 0x0C000000L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3__MASK 0x30000000L ++//BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4__MASK 0x00000003L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4__MASK 0x0000000CL ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4__MASK 0x000000C0L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4__MASK 0x00000300L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4__MASK 0x00000C00L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4__MASK 0x00003000L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5__MASK 0x00030000L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5__MASK 0x000C0000L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5__MASK 0x00C00000L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5__MASK 0x03000000L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5__MASK 0x0C000000L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5__MASK 0x30000000L ++//BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6__MASK 0x00000003L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6__MASK 0x0000000CL ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6__MASK 0x000000C0L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6__MASK 0x00000300L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6__MASK 0x00000C00L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6__MASK 0x00003000L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7__MASK 0x00030000L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7__MASK 0x000C0000L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7__MASK 0x00C00000L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7__MASK 0x03000000L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7__MASK 0x0C000000L ++#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7__MASK 0x30000000L ++//NBIF_VWIRE_CTRL ++#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT__MASK 0x000000F0L ++#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED__MASK 0x00000100L ++#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT__MASK 0x00F00000L ++#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL__MASK 0x0C000000L ++//NBIF_SMN_VWR_VCHG_DIS_CTRL ++#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS__MASK 0x00000001L ++#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS__MASK 0x00000002L ++#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS__MASK 0x00000004L ++#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS__MASK 0x00000008L ++#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS__MASK 0x00000010L ++#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS__MASK 0x00000020L ++#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS__MASK 0x00000040L ++//NBIF_SMN_VWR_VCHG_RST_CTRL0 ++#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV__MASK 0x00000001L ++#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV__MASK 0x00000002L ++#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV__MASK 0x00000004L ++#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV__MASK 0x00000008L ++#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV__MASK 0x00000010L ++#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV__MASK 0x00000020L ++#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV__MASK 0x00000040L ++//NBIF_SMN_VWR_VCHG_TRIG ++#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG__MASK 0x00000001L ++#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG__MASK 0x00000002L ++#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG__MASK 0x00000004L ++#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG__MASK 0x00000008L ++#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG__MASK 0x00000010L ++#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG__MASK 0x00000020L ++#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG__MASK 0x00000040L ++//NBIF_SMN_VWR_WTRIG_CNTL ++#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS__MASK 0x00000001L ++#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS__MASK 0x00000002L ++#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS__MASK 0x00000004L ++#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS__MASK 0x00000008L ++#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS__MASK 0x00000010L ++#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS__MASK 0x00000020L ++#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS__MASK 0x00000040L ++//NBIF_SMN_VWR_VCHG_DIS_CTRL_1 ++#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV__MASK 0x00000001L ++#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV__MASK 0x00000002L ++#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV__MASK 0x00000004L ++#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV__MASK 0x00000008L ++#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV__MASK 0x00000010L ++#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV__MASK 0x00000020L ++#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV__MASK 0x00000040L ++//NBIF_MGCG_CTRL ++#define NBIF_MGCG_CTRL__NBIF_MGCG_EN__MASK 0x00000001L ++#define NBIF_MGCG_CTRL__NBIF_MGCG_MODE__MASK 0x00000002L ++#define NBIF_MGCG_CTRL__NBIF_MGCG_HYSTERESIS__MASK 0x000003FCL ++//NBIF_DS_CTRL_LCLK ++#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN__MASK 0x00000001L ++#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER__MASK 0xFFFF0000L ++//SMN_MST_CNTL0 ++#define SMN_MST_CNTL0__SMN_ARB_MODE__MASK 0x00000003L ++#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS__MASK 0x00000100L ++#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS__MASK 0x00000200L ++#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS__MASK 0x00000400L ++#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS__MASK 0x00000800L ++#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0__MASK 0x00010000L ++#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0__MASK 0x00100000L ++#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0__MASK 0x01000000L ++#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0__MASK 0x10000000L ++//SMN_MST_EP_CNTL1 ++#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0__MASK 0x00000001L ++#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1__MASK 0x00000002L ++#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2__MASK 0x00000004L ++#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3__MASK 0x00000008L ++#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4__MASK 0x00000010L ++#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5__MASK 0x00000020L ++#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6__MASK 0x00000040L ++#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7__MASK 0x00000080L ++//SMN_MST_EP_CNTL2 ++#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0__MASK 0x00000001L ++#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1__MASK 0x00000002L ++#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2__MASK 0x00000004L ++#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3__MASK 0x00000008L ++#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4__MASK 0x00000010L ++#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5__MASK 0x00000020L ++#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6__MASK 0x00000040L ++#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7__MASK 0x00000080L ++//NBIF_SDP_VWR_VCHG_DIS_CTRL ++#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS__MASK 0x00000001L ++#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS__MASK 0x00000002L ++#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS__MASK 0x00000004L ++#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS__MASK 0x00000008L ++#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS__MASK 0x00000010L ++#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS__MASK 0x00000020L ++#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS__MASK 0x00000040L ++#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS__MASK 0x00000080L ++#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS__MASK 0x01000000L ++//NBIF_SDP_VWR_VCHG_RST_CTRL0 ++#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN__MASK 0x00000001L ++#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN__MASK 0x00000002L ++#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN__MASK 0x00000004L ++#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN__MASK 0x00000008L ++#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN__MASK 0x00000010L ++#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN__MASK 0x00000020L ++#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN__MASK 0x00000040L ++#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN__MASK 0x00000080L ++#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN__MASK 0x01000000L ++//NBIF_SDP_VWR_VCHG_RST_CTRL1 ++#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL__MASK 0x00000001L ++#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL__MASK 0x00000002L ++#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL__MASK 0x00000004L ++#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL__MASK 0x00000008L ++#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL__MASK 0x00000010L ++#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL__MASK 0x00000020L ++#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL__MASK 0x00000040L ++#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL__MASK 0x00000080L ++#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL__MASK 0x01000000L ++//NBIF_SDP_VWR_VCHG_TRIG ++#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG__MASK 0x00000001L ++#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG__MASK 0x00000002L ++#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG__MASK 0x00000004L ++#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG__MASK 0x00000008L ++#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG__MASK 0x00000010L ++#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG__MASK 0x00000020L ++#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG__MASK 0x00000040L ++#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG__MASK 0x00000080L ++#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG__MASK 0x01000000L ++//BME_DUMMY_CNTL_0 ++#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0__MASK 0x00000003L ++#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1__MASK 0x0000000CL ++#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2__MASK 0x00000030L ++#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3__MASK 0x000000C0L ++#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4__MASK 0x00000300L ++#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5__MASK 0x00000C00L ++#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6__MASK 0x00003000L ++#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7__MASK 0x0000C000L ++//BIFC_THT_CNTL ++#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0__MASK 0x0000000FL ++#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0__MASK 0x000000F0L ++#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1__MASK 0x00000F00L ++//BIFC_HSTARB_CNTL ++#define BIFC_HSTARB_CNTL__SLVARB_MODE__MASK 0x00000003L ++//BIFC_GSI_CNTL ++#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE__MASK 0x00000003L ++#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE__MASK 0x0000001CL ++#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN__MASK 0x00000020L ++#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN__MASK 0x00000040L ++#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN__MASK 0x00000080L ++#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN__MASK 0x00000100L ++#define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN__MASK 0x00000200L ++#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE__MASK 0x00000C00L ++#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE__MASK 0x00003000L ++//BIFC_PCIEFUNC_CNTL ++#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC__MASK 0x0000FFFFL ++#define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC__MASK 0x00010000L ++//BIFC_SDP_CNTL_0 ++#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS__MASK 0x0000003FL ++#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS__MASK 0x00000FC0L ++#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS__MASK 0x0003F000L ++#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS__MASK 0x00FC0000L ++//BIFC_PERF_CNTL_0 ++#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN__MASK 0x00000001L ++#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN__MASK 0x00000002L ++#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET__MASK 0x00000100L ++#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET__MASK 0x00000200L ++#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL__MASK 0x001F0000L ++#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL__MASK 0x1F000000L ++//BIFC_PERF_CNTL_1 ++#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN__MASK 0x00000001L ++#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN__MASK 0x00000002L ++#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET__MASK 0x00000100L ++#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET__MASK 0x00000200L ++#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL__MASK 0x003F0000L ++#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL__MASK 0x7F000000L ++//BIFC_PERF_CNT_MMIO_RD ++#define BIFC_PERF_CNT_MMIO_RD__PERF_CNT_MMIO_RD_VALUE__MASK 0xFFFFFFFFL ++//BIFC_PERF_CNT_MMIO_WR ++#define BIFC_PERF_CNT_MMIO_WR__PERF_CNT_MMIO_WR_VALUE__MASK 0xFFFFFFFFL ++//BIFC_PERF_CNT_DMA_RD ++#define BIFC_PERF_CNT_DMA_RD__PERF_CNT_DMA_RD_VALUE__MASK 0xFFFFFFFFL ++//BIFC_PERF_CNT_DMA_WR ++#define BIFC_PERF_CNT_DMA_WR__PERF_CNT_DMA_WR_VALUE__MASK 0xFFFFFFFFL ++//NBIF_REGIF_ERRSET_CTRL ++#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS__MASK 0x00000001L ++//SMN_MST_EP_CNTL3 ++#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0__MASK 0x00000001L ++#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1__MASK 0x00000002L ++#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2__MASK 0x00000004L ++#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3__MASK 0x00000008L ++#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4__MASK 0x00000010L ++#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5__MASK 0x00000020L ++#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6__MASK 0x00000040L ++#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7__MASK 0x00000080L ++//SMN_MST_EP_CNTL4 ++#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0__MASK 0x00000001L ++#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1__MASK 0x00000002L ++#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2__MASK 0x00000004L ++#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3__MASK 0x00000008L ++#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4__MASK 0x00000010L ++#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5__MASK 0x00000020L ++#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6__MASK 0x00000040L ++#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7__MASK 0x00000080L ++//BIF_SELFRING_BUFFER_VID ++#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID__MASK 0x000000FFL ++#define BIF_SELFRING_BUFFER_VID__IOHUB_RAS_INTR_CID__MASK 0x0000FF00L ++//BIF_SELFRING_VECTOR_CNTL ++#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS__MASK 0x00000001L ++ ++ ++// addressBlock: bif_ras_bif_ras_regblk ++//BIF_RAS_LEAF0_CTRL ++#define BIF_RAS_LEAF0_CTRL__POISON_DET_EN__MASK 0x00000001L ++#define BIF_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L ++#define BIF_RAS_LEAF0_CTRL__POISON_STALL_EN__MASK 0x00000004L ++#define BIF_RAS_LEAF0_CTRL__PARITY_DET_EN__MASK 0x00000010L ++#define BIF_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L ++#define BIF_RAS_LEAF0_CTRL__PARITY_STALL_EN__MASK 0x00000040L ++#define BIF_RAS_LEAF0_CTRL__ERR_EVENT_RECV__MASK 0x00010000L ++#define BIF_RAS_LEAF0_CTRL__LINK_DIS_RECV__MASK 0x00020000L ++#define BIF_RAS_LEAF0_CTRL__POISON_ERR_DET__MASK 0x00040000L ++#define BIF_RAS_LEAF0_CTRL__PARITY_ERR_DET__MASK 0x00080000L ++#define BIF_RAS_LEAF0_CTRL__ERR_EVENT_SENT__MASK 0x00100000L ++#define BIF_RAS_LEAF0_CTRL__EGRESS_STALLED__MASK 0x00200000L ++//BIF_RAS_LEAF1_CTRL ++#define BIF_RAS_LEAF1_CTRL__POISON_DET_EN__MASK 0x00000001L ++#define BIF_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L ++#define BIF_RAS_LEAF1_CTRL__POISON_STALL_EN__MASK 0x00000004L ++#define BIF_RAS_LEAF1_CTRL__PARITY_DET_EN__MASK 0x00000010L ++#define BIF_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L ++#define BIF_RAS_LEAF1_CTRL__PARITY_STALL_EN__MASK 0x00000040L ++#define BIF_RAS_LEAF1_CTRL__ERR_EVENT_RECV__MASK 0x00010000L ++#define BIF_RAS_LEAF1_CTRL__LINK_DIS_RECV__MASK 0x00020000L ++#define BIF_RAS_LEAF1_CTRL__POISON_ERR_DET__MASK 0x00040000L ++#define BIF_RAS_LEAF1_CTRL__PARITY_ERR_DET__MASK 0x00080000L ++#define BIF_RAS_LEAF1_CTRL__ERR_EVENT_SENT__MASK 0x00100000L ++#define BIF_RAS_LEAF1_CTRL__EGRESS_STALLED__MASK 0x00200000L ++//BIF_RAS_LEAF2_CTRL ++#define BIF_RAS_LEAF2_CTRL__POISON_DET_EN__MASK 0x00000001L ++#define BIF_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L ++#define BIF_RAS_LEAF2_CTRL__POISON_STALL_EN__MASK 0x00000004L ++#define BIF_RAS_LEAF2_CTRL__PARITY_DET_EN__MASK 0x00000010L ++#define BIF_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L ++#define BIF_RAS_LEAF2_CTRL__PARITY_STALL_EN__MASK 0x00000040L ++#define BIF_RAS_LEAF2_CTRL__ERR_EVENT_RECV__MASK 0x00010000L ++#define BIF_RAS_LEAF2_CTRL__LINK_DIS_RECV__MASK 0x00020000L ++#define BIF_RAS_LEAF2_CTRL__POISON_ERR_DET__MASK 0x00040000L ++#define BIF_RAS_LEAF2_CTRL__PARITY_ERR_DET__MASK 0x00080000L ++#define BIF_RAS_LEAF2_CTRL__ERR_EVENT_SENT__MASK 0x00100000L ++#define BIF_RAS_LEAF2_CTRL__EGRESS_STALLED__MASK 0x00200000L ++//BIF_RAS_MISC_CTRL ++#define BIF_RAS_MISC_CTRL__LINKDIS_TRIG_ERREVENT_EN__MASK 0x00000001L ++//BIF_IOHUB_RAS_IH_CNTL ++#define BIF_IOHUB_RAS_IH_CNTL__RAS_IH_INTR_EN__MASK 0x00000001L ++//BIF_RAS_VWR_FROM_IOHUB ++#define BIF_RAS_VWR_FROM_IOHUB__RAS_IH_INTR_TRIG__MASK 0x00000001L ++ ++ ++// addressBlock: rcc_pfc_amdgfx_RCCPFCDEC ++//RCC_PFC_LTR_CNTL ++#define RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__MASK 0x000003FFL ++#define RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__MASK 0x00001C00L ++#define RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__MASK 0x00008000L ++#define RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__MASK 0x03FF0000L ++#define RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__MASK 0x1C000000L ++#define RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__MASK 0x80000000L ++//RCC_PFC_PME_RESTORE ++#define RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__MASK 0x00000001L ++#define RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__MASK 0x00000100L ++//RCC_PFC_STICKY_RESTORE_0 ++#define RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__MASK 0x00000001L ++#define RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__MASK 0x00000002L ++#define RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__MASK 0x00000004L ++#define RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__MASK 0x00000008L ++#define RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__MASK 0x00000010L ++#define RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__MASK 0x00000020L ++#define RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__MASK 0x00000040L ++#define RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__MASK 0x00000080L ++//RCC_PFC_STICKY_RESTORE_1 ++#define RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__MASK 0xFFFFFFFFL ++//RCC_PFC_STICKY_RESTORE_2 ++#define RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__MASK 0xFFFFFFFFL ++//RCC_PFC_STICKY_RESTORE_3 ++#define RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__MASK 0xFFFFFFFFL ++//RCC_PFC_STICKY_RESTORE_4 ++#define RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__MASK 0xFFFFFFFFL ++//RCC_PFC_STICKY_RESTORE_5 ++#define RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__MASK 0xFFFFFFFFL ++//RCC_PFC_AUXPWR_CNTL ++#define RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__MASK 0x00000007L ++#define RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__MASK 0x00000008L ++ ++ ++// addressBlock: rcc_pfc_amdgfxaz_RCCPFCDEC ++//RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL ++#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__MASK 0x000003FFL ++#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__MASK 0x00001C00L ++#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__MASK 0x00008000L ++#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__MASK 0x03FF0000L ++#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__MASK 0x1C000000L ++#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__MASK 0x80000000L ++//RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE ++#define RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__MASK 0x00000001L ++#define RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__MASK 0x00000100L ++//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0 ++#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__MASK 0x00000001L ++#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__MASK 0x00000002L ++#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__MASK 0x00000004L ++#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__MASK 0x00000008L ++#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__MASK 0x00000010L ++#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__MASK 0x00000020L ++#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__MASK 0x00000040L ++#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__MASK 0x00000080L ++//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1 ++#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__MASK 0xFFFFFFFFL ++//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2 ++#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__MASK 0xFFFFFFFFL ++//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3 ++#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__MASK 0xFFFFFFFFL ++//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4 ++#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__MASK 0xFFFFFFFFL ++//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5 ++#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__MASK 0xFFFFFFFFL ++//RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL ++#define RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__MASK 0x00000007L ++#define RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__MASK 0x00000008L ++ ++ ++// addressBlock: pciemsix_amdgfx_MSIXTDEC ++//PCIEMSIX_VECT0_ADDR_LO ++#define PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL ++//PCIEMSIX_VECT0_ADDR_HI ++#define PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT0_MSG_DATA ++#define PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT0_CONTROL ++#define PCIEMSIX_VECT0_CONTROL__MASK_BIT__MASK 0x00000001L ++//PCIEMSIX_VECT1_ADDR_LO ++#define PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL ++//PCIEMSIX_VECT1_ADDR_HI ++#define PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT1_MSG_DATA ++#define PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT1_CONTROL ++#define PCIEMSIX_VECT1_CONTROL__MASK_BIT__MASK 0x00000001L ++//PCIEMSIX_VECT2_ADDR_LO ++#define PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL ++//PCIEMSIX_VECT2_ADDR_HI ++#define PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT2_MSG_DATA ++#define PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT2_CONTROL ++#define PCIEMSIX_VECT2_CONTROL__MASK_BIT__MASK 0x00000001L ++//PCIEMSIX_VECT3_ADDR_LO ++#define PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL ++//PCIEMSIX_VECT3_ADDR_HI ++#define PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT3_MSG_DATA ++#define PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT3_CONTROL ++#define PCIEMSIX_VECT3_CONTROL__MASK_BIT__MASK 0x00000001L ++//PCIEMSIX_VECT4_ADDR_LO ++#define PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL ++//PCIEMSIX_VECT4_ADDR_HI ++#define PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT4_MSG_DATA ++#define PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT4_CONTROL ++#define PCIEMSIX_VECT4_CONTROL__MASK_BIT__MASK 0x00000001L ++//PCIEMSIX_VECT5_ADDR_LO ++#define PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL ++//PCIEMSIX_VECT5_ADDR_HI ++#define PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT5_MSG_DATA ++#define PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT5_CONTROL ++#define PCIEMSIX_VECT5_CONTROL__MASK_BIT__MASK 0x00000001L ++//PCIEMSIX_VECT6_ADDR_LO ++#define PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL ++//PCIEMSIX_VECT6_ADDR_HI ++#define PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT6_MSG_DATA ++#define PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT6_CONTROL ++#define PCIEMSIX_VECT6_CONTROL__MASK_BIT__MASK 0x00000001L ++//PCIEMSIX_VECT7_ADDR_LO ++#define PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL ++//PCIEMSIX_VECT7_ADDR_HI ++#define PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT7_MSG_DATA ++#define PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT7_CONTROL ++#define PCIEMSIX_VECT7_CONTROL__MASK_BIT__MASK 0x00000001L ++//PCIEMSIX_VECT8_ADDR_LO ++#define PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL ++//PCIEMSIX_VECT8_ADDR_HI ++#define PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT8_MSG_DATA ++#define PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT8_CONTROL ++#define PCIEMSIX_VECT8_CONTROL__MASK_BIT__MASK 0x00000001L ++//PCIEMSIX_VECT9_ADDR_LO ++#define PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL ++//PCIEMSIX_VECT9_ADDR_HI ++#define PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT9_MSG_DATA ++#define PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT9_CONTROL ++#define PCIEMSIX_VECT9_CONTROL__MASK_BIT__MASK 0x00000001L ++//PCIEMSIX_VECT10_ADDR_LO ++#define PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL ++//PCIEMSIX_VECT10_ADDR_HI ++#define PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT10_MSG_DATA ++#define PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT10_CONTROL ++#define PCIEMSIX_VECT10_CONTROL__MASK_BIT__MASK 0x00000001L ++//PCIEMSIX_VECT11_ADDR_LO ++#define PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL ++//PCIEMSIX_VECT11_ADDR_HI ++#define PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT11_MSG_DATA ++#define PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT11_CONTROL ++#define PCIEMSIX_VECT11_CONTROL__MASK_BIT__MASK 0x00000001L ++//PCIEMSIX_VECT12_ADDR_LO ++#define PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL ++//PCIEMSIX_VECT12_ADDR_HI ++#define PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT12_MSG_DATA ++#define PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT12_CONTROL ++#define PCIEMSIX_VECT12_CONTROL__MASK_BIT__MASK 0x00000001L ++//PCIEMSIX_VECT13_ADDR_LO ++#define PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL ++//PCIEMSIX_VECT13_ADDR_HI ++#define PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT13_MSG_DATA ++#define PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT13_CONTROL ++#define PCIEMSIX_VECT13_CONTROL__MASK_BIT__MASK 0x00000001L ++//PCIEMSIX_VECT14_ADDR_LO ++#define PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL ++//PCIEMSIX_VECT14_ADDR_HI ++#define PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT14_MSG_DATA ++#define PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT14_CONTROL ++#define PCIEMSIX_VECT14_CONTROL__MASK_BIT__MASK 0x00000001L ++//PCIEMSIX_VECT15_ADDR_LO ++#define PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL ++//PCIEMSIX_VECT15_ADDR_HI ++#define PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT15_MSG_DATA ++#define PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT15_CONTROL ++#define PCIEMSIX_VECT15_CONTROL__MASK_BIT__MASK 0x00000001L ++//PCIEMSIX_VECT16_ADDR_LO ++#define PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL ++//PCIEMSIX_VECT16_ADDR_HI ++#define PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT16_MSG_DATA ++#define PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT16_CONTROL ++#define PCIEMSIX_VECT16_CONTROL__MASK_BIT__MASK 0x00000001L ++//PCIEMSIX_VECT17_ADDR_LO ++#define PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL ++//PCIEMSIX_VECT17_ADDR_HI ++#define PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT17_MSG_DATA ++#define PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT17_CONTROL ++#define PCIEMSIX_VECT17_CONTROL__MASK_BIT__MASK 0x00000001L ++//PCIEMSIX_VECT18_ADDR_LO ++#define PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL ++//PCIEMSIX_VECT18_ADDR_HI ++#define PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT18_MSG_DATA ++#define PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT18_CONTROL ++#define PCIEMSIX_VECT18_CONTROL__MASK_BIT__MASK 0x00000001L ++//PCIEMSIX_VECT19_ADDR_LO ++#define PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL ++//PCIEMSIX_VECT19_ADDR_HI ++#define PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT19_MSG_DATA ++#define PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT19_CONTROL ++#define PCIEMSIX_VECT19_CONTROL__MASK_BIT__MASK 0x00000001L ++//PCIEMSIX_VECT20_ADDR_LO ++#define PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL ++//PCIEMSIX_VECT20_ADDR_HI ++#define PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT20_MSG_DATA ++#define PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT20_CONTROL ++#define PCIEMSIX_VECT20_CONTROL__MASK_BIT__MASK 0x00000001L ++//PCIEMSIX_VECT21_ADDR_LO ++#define PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL ++//PCIEMSIX_VECT21_ADDR_HI ++#define PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT21_MSG_DATA ++#define PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT21_CONTROL ++#define PCIEMSIX_VECT21_CONTROL__MASK_BIT__MASK 0x00000001L ++//PCIEMSIX_VECT22_ADDR_LO ++#define PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL ++//PCIEMSIX_VECT22_ADDR_HI ++#define PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT22_MSG_DATA ++#define PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT22_CONTROL ++#define PCIEMSIX_VECT22_CONTROL__MASK_BIT__MASK 0x00000001L ++//PCIEMSIX_VECT23_ADDR_LO ++#define PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL ++//PCIEMSIX_VECT23_ADDR_HI ++#define PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT23_MSG_DATA ++#define PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT23_CONTROL ++#define PCIEMSIX_VECT23_CONTROL__MASK_BIT__MASK 0x00000001L ++//PCIEMSIX_VECT24_ADDR_LO ++#define PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL ++//PCIEMSIX_VECT24_ADDR_HI ++#define PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT24_MSG_DATA ++#define PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT24_CONTROL ++#define PCIEMSIX_VECT24_CONTROL__MASK_BIT__MASK 0x00000001L ++//PCIEMSIX_VECT25_ADDR_LO ++#define PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL ++//PCIEMSIX_VECT25_ADDR_HI ++#define PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT25_MSG_DATA ++#define PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT25_CONTROL ++#define PCIEMSIX_VECT25_CONTROL__MASK_BIT__MASK 0x00000001L ++//PCIEMSIX_VECT26_ADDR_LO ++#define PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL ++//PCIEMSIX_VECT26_ADDR_HI ++#define PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT26_MSG_DATA ++#define PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT26_CONTROL ++#define PCIEMSIX_VECT26_CONTROL__MASK_BIT__MASK 0x00000001L ++//PCIEMSIX_VECT27_ADDR_LO ++#define PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL ++//PCIEMSIX_VECT27_ADDR_HI ++#define PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT27_MSG_DATA ++#define PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT27_CONTROL ++#define PCIEMSIX_VECT27_CONTROL__MASK_BIT__MASK 0x00000001L ++//PCIEMSIX_VECT28_ADDR_LO ++#define PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL ++//PCIEMSIX_VECT28_ADDR_HI ++#define PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT28_MSG_DATA ++#define PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT28_CONTROL ++#define PCIEMSIX_VECT28_CONTROL__MASK_BIT__MASK 0x00000001L ++//PCIEMSIX_VECT29_ADDR_LO ++#define PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL ++//PCIEMSIX_VECT29_ADDR_HI ++#define PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT29_MSG_DATA ++#define PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT29_CONTROL ++#define PCIEMSIX_VECT29_CONTROL__MASK_BIT__MASK 0x00000001L ++//PCIEMSIX_VECT30_ADDR_LO ++#define PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL ++//PCIEMSIX_VECT30_ADDR_HI ++#define PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT30_MSG_DATA ++#define PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT30_CONTROL ++#define PCIEMSIX_VECT30_CONTROL__MASK_BIT__MASK 0x00000001L ++//PCIEMSIX_VECT31_ADDR_LO ++#define PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL ++//PCIEMSIX_VECT31_ADDR_HI ++#define PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT31_MSG_DATA ++#define PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL ++//PCIEMSIX_VECT31_CONTROL ++#define PCIEMSIX_VECT31_CONTROL__MASK_BIT__MASK 0x00000001L ++ ++ ++// addressBlock: pciemsix_amdgfx_MSIXPDEC ++//PCIEMSIX_PBA ++#define PCIEMSIX_PBA__MSIX_PENDING_BITS__MASK 0xFFFFFFFFL ++ ++ ++// addressBlock: syshub_mmreg_ind_syshubind ++//SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000001L ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000002L ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000004L ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000008L ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000010L ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000020L ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000040L ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000080L ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00010000L ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00020000L ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00040000L ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00080000L ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00100000L ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00200000L ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00400000L ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00800000L ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x10000000L ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__MASK 0x80000000L ++//SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__MASK 0x0000FFFFL ++//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK ++#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en__MASK 0x00000001L ++#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en__MASK 0x00000002L ++#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__MASK 0x00008000L ++#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en__MASK 0x00010000L ++#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en__MASK 0x00020000L ++//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK ++#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en__MASK 0x00000001L ++#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en__MASK 0x00000002L ++#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__MASK 0x00008000L ++#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en__MASK 0x00010000L ++#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en__MASK 0x00020000L ++//SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L ++//SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL ++#define SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L ++#define SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL ++#define SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L ++//SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L ++//SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L ++//SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L ++//SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L ++//SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L ++//SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L ++#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L ++//SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL ++#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L ++#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L ++#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L ++#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L ++#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L ++#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L ++//SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL ++#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L ++#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L ++#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L ++#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L ++#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L ++#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L ++//SYSHUBMMREGIND_SYSHUB_CG_CNTL ++#define SYSHUBMMREGIND_SYSHUB_CG_CNTL__SYSHUB_CG_EN__MASK 0x00000001L ++#define SYSHUBMMREGIND_SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER__MASK 0x0000FF00L ++#define SYSHUBMMREGIND_SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER__MASK 0x00FF0000L ++//SYSHUBMMREGIND_SYSHUB_TRANS_IDLE ++#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0__MASK 0x00000001L ++#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1__MASK 0x00000002L ++#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2__MASK 0x00000004L ++#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3__MASK 0x00000008L ++#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4__MASK 0x00000010L ++#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5__MASK 0x00000020L ++#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6__MASK 0x00000040L ++#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7__MASK 0x00000080L ++#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8__MASK 0x00000100L ++#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9__MASK 0x00000200L ++#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10__MASK 0x00000400L ++#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11__MASK 0x00000800L ++#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12__MASK 0x00001000L ++#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13__MASK 0x00002000L ++#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14__MASK 0x00004000L ++#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15__MASK 0x00008000L ++#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF__MASK 0x00010000L ++//SYSHUBMMREGIND_SYSHUB_HP_TIMER ++#define SYSHUBMMREGIND_SYSHUB_HP_TIMER__SYSHUB_HP_TIMER__MASK 0xFFFFFFFFL ++//SYSHUBMMREGIND_SYSHUB_SCRATCH ++#define SYSHUBMMREGIND_SYSHUB_SCRATCH__SCRATCH__MASK 0xFFFFFFFFL ++//SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000001L ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000002L ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000004L ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000008L ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000010L ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000020L ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000040L ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000080L ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00010000L ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00020000L ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00040000L ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00080000L ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00100000L ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00200000L ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00400000L ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00800000L ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x10000000L ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN__MASK 0x80000000L ++//SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK ++#define SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER__MASK 0x0000FFFFL ++//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK ++#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en__MASK 0x00008000L ++#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en__MASK 0x00010000L ++//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK ++#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en__MASK 0x00008000L ++#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en__MASK 0x00010000L ++//SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L ++//SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L ++//SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L ++//SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L ++//SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L ++//SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L ++//SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L ++#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L ++//SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L ++//SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L ++//SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L ++//SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L ++//SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L ++#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L ++ ++#endif +diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_default.h +deleted file mode 100644 +index daa7eae..0000000 +--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_default.h ++++ /dev/null +@@ -1,1271 +0,0 @@ +-/* +- * Copyright (C) 2017 Advanced Micro Devices, Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included +- * in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- */ +-#ifndef _nbif_6_1_DEFAULT_HEADER +-#define _nbif_6_1_DEFAULT_HEADER +- +- +-// addressBlock: bif_cfg_dev0_epf0_bifcfgdecp +-// base address: 0x0 +-#define cfgVENDOR_ID_DEFAULT 0x00000000 +-#define cfgDEVICE_ID_DEFAULT 0x00000000 +-#define cfgCOMMAND_DEFAULT 0x00000000 +-#define cfgSTATUS_DEFAULT 0x00000000 +-#define cfgREVISION_ID_DEFAULT 0x00000000 +-#define cfgPROG_INTERFACE_DEFAULT 0x00000000 +-#define cfgSUB_CLASS_DEFAULT 0x00000000 +-#define cfgBASE_CLASS_DEFAULT 0x00000000 +-#define cfgCACHE_LINE_DEFAULT 0x00000000 +-#define cfgLATENCY_DEFAULT 0x00000000 +-#define cfgHEADER_DEFAULT 0x00000000 +-#define cfgBIST_DEFAULT 0x00000000 +-#define cfgBASE_ADDR_1_DEFAULT 0x00000000 +-#define cfgBASE_ADDR_2_DEFAULT 0x00000000 +-#define cfgBASE_ADDR_3_DEFAULT 0x00000000 +-#define cfgBASE_ADDR_4_DEFAULT 0x00000000 +-#define cfgBASE_ADDR_5_DEFAULT 0x00000000 +-#define cfgBASE_ADDR_6_DEFAULT 0x00000000 +-#define cfgADAPTER_ID_DEFAULT 0x00000000 +-#define cfgROM_BASE_ADDR_DEFAULT 0x00000000 +-#define cfgCAP_PTR_DEFAULT 0x00000000 +-#define cfgINTERRUPT_LINE_DEFAULT 0x000000ff +-#define cfgINTERRUPT_PIN_DEFAULT 0x00000000 +-#define cfgMIN_GRANT_DEFAULT 0x00000000 +-#define cfgMAX_LATENCY_DEFAULT 0x00000000 +-#define cfgVENDOR_CAP_LIST_DEFAULT 0x00000000 +-#define cfgADAPTER_ID_W_DEFAULT 0x00000000 +-#define cfgPMI_CAP_LIST_DEFAULT 0x00000000 +-#define cfgPMI_CAP_DEFAULT 0x00000000 +-#define cfgPMI_STATUS_CNTL_DEFAULT 0x00000000 +-#define cfgPCIE_CAP_LIST_DEFAULT 0x0000a000 +-#define cfgPCIE_CAP_DEFAULT 0x00000002 +-#define cfgDEVICE_CAP_DEFAULT 0x10000000 +-#define cfgDEVICE_CNTL_DEFAULT 0x00002810 +-#define cfgDEVICE_STATUS_DEFAULT 0x00000000 +-#define cfgLINK_CAP_DEFAULT 0x00011c03 +-#define cfgLINK_CNTL_DEFAULT 0x00000000 +-#define cfgLINK_STATUS_DEFAULT 0x00000001 +-#define cfgDEVICE_CAP2_DEFAULT 0x00000000 +-#define cfgDEVICE_CNTL2_DEFAULT 0x00000000 +-#define cfgDEVICE_STATUS2_DEFAULT 0x00000000 +-#define cfgLINK_CAP2_DEFAULT 0x0000000e +-#define cfgLINK_CNTL2_DEFAULT 0x00000003 +-#define cfgLINK_STATUS2_DEFAULT 0x00000000 +-#define cfgSLOT_CAP2_DEFAULT 0x00000000 +-#define cfgSLOT_CNTL2_DEFAULT 0x00000000 +-#define cfgSLOT_STATUS2_DEFAULT 0x00000000 +-#define cfgMSI_CAP_LIST_DEFAULT 0x0000c000 +-#define cfgMSI_MSG_CNTL_DEFAULT 0x00000080 +-#define cfgMSI_MSG_ADDR_LO_DEFAULT 0x00000000 +-#define cfgMSI_MSG_ADDR_HI_DEFAULT 0x00000000 +-#define cfgMSI_MSG_DATA_DEFAULT 0x00000000 +-#define cfgMSI_MSG_DATA_64_DEFAULT 0x00000000 +-#define cfgMSI_MASK_DEFAULT 0x00000000 +-#define cfgMSI_PENDING_DEFAULT 0x00000000 +-#define cfgMSI_MASK_64_DEFAULT 0x00000000 +-#define cfgMSI_PENDING_64_DEFAULT 0x00000000 +-#define cfgMSIX_CAP_LIST_DEFAULT 0x00000000 +-#define cfgMSIX_MSG_CNTL_DEFAULT 0x00000000 +-#define cfgMSIX_TABLE_DEFAULT 0x00000000 +-#define cfgMSIX_PBA_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_DEFAULT 0x11000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC1_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC2_DEFAULT 0x00000000 +-#define cfgPCIE_VC_ENH_CAP_LIST_DEFAULT 0x14000000 +-#define cfgPCIE_PORT_VC_CAP_REG1_DEFAULT 0x00000000 +-#define cfgPCIE_PORT_VC_CAP_REG2_DEFAULT 0x00000000 +-#define cfgPCIE_PORT_VC_CNTL_DEFAULT 0x00000000 +-#define cfgPCIE_PORT_VC_STATUS_DEFAULT 0x00000000 +-#define cfgPCIE_VC0_RESOURCE_CAP_DEFAULT 0x00000000 +-#define cfgPCIE_VC0_RESOURCE_CNTL_DEFAULT 0x000000fe +-#define cfgPCIE_VC0_RESOURCE_STATUS_DEFAULT 0x00000002 +-#define cfgPCIE_VC1_RESOURCE_CAP_DEFAULT 0x00000000 +-#define cfgPCIE_VC1_RESOURCE_CNTL_DEFAULT 0x00000000 +-#define cfgPCIE_VC1_RESOURCE_STATUS_DEFAULT 0x00000002 +-#define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_DEFAULT 0x15000000 +-#define cfgPCIE_DEV_SERIAL_NUM_DW1_DEFAULT 0x00000000 +-#define cfgPCIE_DEV_SERIAL_NUM_DW2_DEFAULT 0x00000000 +-#define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST_DEFAULT 0x20020000 +-#define cfgPCIE_UNCORR_ERR_STATUS_DEFAULT 0x00000000 +-#define cfgPCIE_UNCORR_ERR_MASK_DEFAULT 0x00000000 +-#define cfgPCIE_UNCORR_ERR_SEVERITY_DEFAULT 0x00440010 +-#define cfgPCIE_CORR_ERR_STATUS_DEFAULT 0x00000000 +-#define cfgPCIE_CORR_ERR_MASK_DEFAULT 0x00002000 +-#define cfgPCIE_ADV_ERR_CAP_CNTL_DEFAULT 0x00000000 +-#define cfgPCIE_HDR_LOG0_DEFAULT 0x00000000 +-#define cfgPCIE_HDR_LOG1_DEFAULT 0x00000000 +-#define cfgPCIE_HDR_LOG2_DEFAULT 0x00000000 +-#define cfgPCIE_HDR_LOG3_DEFAULT 0x00000000 +-#define cfgPCIE_ROOT_ERR_CMD_DEFAULT 0x00000000 +-#define cfgPCIE_ROOT_ERR_STATUS_DEFAULT 0x00000000 +-#define cfgPCIE_ERR_SRC_ID_DEFAULT 0x00000000 +-#define cfgPCIE_TLP_PREFIX_LOG0_DEFAULT 0x00000000 +-#define cfgPCIE_TLP_PREFIX_LOG1_DEFAULT 0x00000000 +-#define cfgPCIE_TLP_PREFIX_LOG2_DEFAULT 0x00000000 +-#define cfgPCIE_TLP_PREFIX_LOG3_DEFAULT 0x00000000 +-#define cfgPCIE_BAR_ENH_CAP_LIST_DEFAULT 0x24000000 +-#define cfgPCIE_BAR1_CAP_DEFAULT 0x00000000 +-#define cfgPCIE_BAR1_CNTL_DEFAULT 0x00000020 +-#define cfgPCIE_BAR2_CAP_DEFAULT 0x00000000 +-#define cfgPCIE_BAR2_CNTL_DEFAULT 0x00000000 +-#define cfgPCIE_BAR3_CAP_DEFAULT 0x00000000 +-#define cfgPCIE_BAR3_CNTL_DEFAULT 0x00000000 +-#define cfgPCIE_BAR4_CAP_DEFAULT 0x00000000 +-#define cfgPCIE_BAR4_CNTL_DEFAULT 0x00000000 +-#define cfgPCIE_BAR5_CAP_DEFAULT 0x00000000 +-#define cfgPCIE_BAR5_CNTL_DEFAULT 0x00000000 +-#define cfgPCIE_BAR6_CAP_DEFAULT 0x00000000 +-#define cfgPCIE_BAR6_CNTL_DEFAULT 0x00000000 +-#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST_DEFAULT 0x25000000 +-#define cfgPCIE_PWR_BUDGET_DATA_SELECT_DEFAULT 0x00000000 +-#define cfgPCIE_PWR_BUDGET_DATA_DEFAULT 0x00000000 +-#define cfgPCIE_PWR_BUDGET_CAP_DEFAULT 0x00000000 +-#define cfgPCIE_DPA_ENH_CAP_LIST_DEFAULT 0x27000000 +-#define cfgPCIE_DPA_CAP_DEFAULT 0x00000000 +-#define cfgPCIE_DPA_LATENCY_INDICATOR_DEFAULT 0x00000000 +-#define cfgPCIE_DPA_STATUS_DEFAULT 0x00000100 +-#define cfgPCIE_DPA_CNTL_DEFAULT 0x00000000 +-#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x00000000 +-#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x00000000 +-#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000000 +-#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000000 +-#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x00000000 +-#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000000 +-#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000000 +-#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x00000000 +-#define cfgPCIE_SECONDARY_ENH_CAP_LIST_DEFAULT 0x2a010019 +-#define cfgPCIE_LINK_CNTL3_DEFAULT 0x00000000 +-#define cfgPCIE_LANE_ERROR_STATUS_DEFAULT 0x00000000 +-#define cfgPCIE_LANE_0_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +-#define cfgPCIE_LANE_1_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +-#define cfgPCIE_LANE_2_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +-#define cfgPCIE_LANE_3_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +-#define cfgPCIE_LANE_4_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +-#define cfgPCIE_LANE_5_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +-#define cfgPCIE_LANE_6_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +-#define cfgPCIE_LANE_7_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +-#define cfgPCIE_LANE_8_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +-#define cfgPCIE_LANE_9_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +-#define cfgPCIE_LANE_10_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +-#define cfgPCIE_LANE_11_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +-#define cfgPCIE_LANE_12_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +-#define cfgPCIE_LANE_13_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +-#define cfgPCIE_LANE_14_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +-#define cfgPCIE_LANE_15_EQUALIZATION_CNTL_DEFAULT 0x00007f00 +-#define cfgPCIE_ACS_ENH_CAP_LIST_DEFAULT 0x2b000000 +-#define cfgPCIE_ACS_CAP_DEFAULT 0x00000000 +-#define cfgPCIE_ACS_CNTL_DEFAULT 0x00000000 +-#define cfgPCIE_ATS_ENH_CAP_LIST_DEFAULT 0x2c000000 +-#define cfgPCIE_ATS_CAP_DEFAULT 0x00000000 +-#define cfgPCIE_ATS_CNTL_DEFAULT 0x00000000 +-#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST_DEFAULT 0x2d000000 +-#define cfgPCIE_PAGE_REQ_CNTL_DEFAULT 0x00000000 +-#define cfgPCIE_PAGE_REQ_STATUS_DEFAULT 0x00000000 +-#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY_DEFAULT 0x00000000 +-#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC_DEFAULT 0x00000000 +-#define cfgPCIE_PASID_ENH_CAP_LIST_DEFAULT 0x2e000000 +-#define cfgPCIE_PASID_CAP_DEFAULT 0x00000000 +-#define cfgPCIE_PASID_CNTL_DEFAULT 0x00000000 +-#define cfgPCIE_TPH_REQR_ENH_CAP_LIST_DEFAULT 0x2f000000 +-#define cfgPCIE_TPH_REQR_CAP_DEFAULT 0x00000000 +-#define cfgPCIE_TPH_REQR_CNTL_DEFAULT 0x00000000 +-#define cfgPCIE_MC_ENH_CAP_LIST_DEFAULT 0x32000000 +-#define cfgPCIE_MC_CAP_DEFAULT 0x00000000 +-#define cfgPCIE_MC_CNTL_DEFAULT 0x00000000 +-#define cfgPCIE_MC_ADDR0_DEFAULT 0x00000000 +-#define cfgPCIE_MC_ADDR1_DEFAULT 0x00000000 +-#define cfgPCIE_MC_RCV0_DEFAULT 0x00000000 +-#define cfgPCIE_MC_RCV1_DEFAULT 0x00000000 +-#define cfgPCIE_MC_BLOCK_ALL0_DEFAULT 0x00000000 +-#define cfgPCIE_MC_BLOCK_ALL1_DEFAULT 0x00000000 +-#define cfgPCIE_MC_BLOCK_UNTRANSLATED_0_DEFAULT 0x00000000 +-#define cfgPCIE_MC_BLOCK_UNTRANSLATED_1_DEFAULT 0x00000000 +-#define cfgPCIE_LTR_ENH_CAP_LIST_DEFAULT 0x32800000 +-#define cfgPCIE_LTR_CAP_DEFAULT 0x00000000 +-#define cfgPCIE_ARI_ENH_CAP_LIST_DEFAULT 0x33000000 +-#define cfgPCIE_ARI_CAP_DEFAULT 0x00000000 +-#define cfgPCIE_ARI_CNTL_DEFAULT 0x00000000 +-#define cfgPCIE_SRIOV_ENH_CAP_LIST_DEFAULT 0x00000000 +-#define cfgPCIE_SRIOV_CAP_DEFAULT 0x00000000 +-#define cfgPCIE_SRIOV_CONTROL_DEFAULT 0x00000000 +-#define cfgPCIE_SRIOV_STATUS_DEFAULT 0x00000000 +-#define cfgPCIE_SRIOV_INITIAL_VFS_DEFAULT 0x00000000 +-#define cfgPCIE_SRIOV_TOTAL_VFS_DEFAULT 0x00000000 +-#define cfgPCIE_SRIOV_NUM_VFS_DEFAULT 0x00000000 +-#define cfgPCIE_SRIOV_FUNC_DEP_LINK_DEFAULT 0x00000000 +-#define cfgPCIE_SRIOV_FIRST_VF_OFFSET_DEFAULT 0x00000000 +-#define cfgPCIE_SRIOV_VF_STRIDE_DEFAULT 0x00000000 +-#define cfgPCIE_SRIOV_VF_DEVICE_ID_DEFAULT 0x00000000 +-#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE_DEFAULT 0x00000000 +-#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE_DEFAULT 0x00000001 +-#define cfgPCIE_SRIOV_VF_BASE_ADDR_0_DEFAULT 0x00000000 +-#define cfgPCIE_SRIOV_VF_BASE_ADDR_1_DEFAULT 0x00000000 +-#define cfgPCIE_SRIOV_VF_BASE_ADDR_2_DEFAULT 0x00000000 +-#define cfgPCIE_SRIOV_VF_BASE_ADDR_3_DEFAULT 0x00000000 +-#define cfgPCIE_SRIOV_VF_BASE_ADDR_4_DEFAULT 0x00000000 +-#define cfgPCIE_SRIOV_VF_BASE_ADDR_5_DEFAULT 0x00000000 +-#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6_DEFAULT 0x00000000 +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7_DEFAULT 0x00000000 +- +- +-// addressBlock: bif_cfg_dev0_swds_bifcfgdecp +-// base address: 0x0 +-#define mmSUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +-#define mmIO_BASE_LIMIT_DEFAULT 0x00000000 +-#define mmSECONDARY_STATUS_DEFAULT 0x00000000 +-#define mmMEM_BASE_LIMIT_DEFAULT 0x00000000 +-#define mmPREF_BASE_LIMIT_DEFAULT 0x00000000 +-#define mmPREF_BASE_UPPER_DEFAULT 0x00000000 +-#define mmPREF_LIMIT_UPPER_DEFAULT 0x00000000 +-#define mmIO_BASE_LIMIT_HI_DEFAULT 0x00000000 +-#define mmIRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +-#define mmSLOT_CAP_DEFAULT 0x00000000 +-#define mmSLOT_CNTL_DEFAULT 0x00000000 +-#define mmSLOT_STATUS_DEFAULT 0x00000000 +-#define mmSSID_CAP_LIST_DEFAULT 0x00000000 +-#define mmSSID_CAP_DEFAULT 0x00000000 +- +- +-// addressBlock: rcc_shadow_reg_shadowdec +-// base address: 0x0 +-#define ixSHADOW_COMMAND_DEFAULT 0x00000000 +-#define ixSHADOW_BASE_ADDR_1_DEFAULT 0x00000000 +-#define ixSHADOW_BASE_ADDR_2_DEFAULT 0x00000000 +-#define ixSHADOW_SUB_BUS_NUMBER_LATENCY_DEFAULT 0x00000000 +-#define ixSHADOW_IO_BASE_LIMIT_DEFAULT 0x00000000 +-#define ixSHADOW_MEM_BASE_LIMIT_DEFAULT 0x00000000 +-#define ixSHADOW_PREF_BASE_LIMIT_DEFAULT 0x00000000 +-#define ixSHADOW_PREF_BASE_UPPER_DEFAULT 0x00000000 +-#define ixSHADOW_PREF_LIMIT_UPPER_DEFAULT 0x00000000 +-#define ixSHADOW_IO_BASE_LIMIT_HI_DEFAULT 0x00000000 +-#define ixSHADOW_IRQ_BRIDGE_CNTL_DEFAULT 0x00000000 +-#define ixSUC_INDEX_DEFAULT 0x00000000 +-#define ixSUC_DATA_DEFAULT 0x00000000 +- +- +-// addressBlock: bif_bx_pf_SUMDEC +-// base address: 0x0 +-#define ixSUM_INDEX_DEFAULT 0x00000000 +-#define ixSUM_DATA_DEFAULT 0x00000000 +- +- +-// addressBlock: gdc_GDCDEC +-// base address: 0x1400000 +-#define mmA2S_CNTL_CL0_DEFAULT 0x00280540 +-#define mmA2S_CNTL_CL1_DEFAULT 0x00282540 +-#define mmA2S_CNTL_CL2_DEFAULT 0x002825a0 +-#define mmA2S_CNTL_CL3_DEFAULT 0x00282550 +-#define mmA2S_CNTL_CL4_DEFAULT 0x00282550 +-#define mmA2S_CNTL_SW0_DEFAULT 0x08080005 +-#define mmA2S_CNTL_SW1_DEFAULT 0x08080205 +-#define mmA2S_CNTL_SW2_DEFAULT 0x08080200 +-#define mmNGDC_MGCG_CTRL_DEFAULT 0x00000080 +-#define mmA2S_MISC_CNTL_DEFAULT 0x00000003 +-#define mmNGDC_SDP_PORT_CTRL_DEFAULT 0x0000000f +-#define mmNGDC_RESERVED_0_DEFAULT 0x00000000 +-#define mmNGDC_RESERVED_1_DEFAULT 0x00000000 +-#define mmBIF_SDMA0_DOORBELL_RANGE_DEFAULT 0x00000000 +-#define mmBIF_SDMA1_DOORBELL_RANGE_DEFAULT 0x00000000 +-#define mmBIF_IH_DOORBELL_RANGE_DEFAULT 0x00000000 +-#define mmBIF_MMSCH0_DOORBELL_RANGE_DEFAULT 0x00000000 +-#define mmBIF_DOORBELL_FENCE_CNTL_DEFAULT 0x00000000 +-#define mmS2A_MISC_CNTL_DEFAULT 0x00000000 +-#define mmA2S_CNTL2_SEC_CL0_DEFAULT 0x00000006 +-#define mmA2S_CNTL2_SEC_CL1_DEFAULT 0x00000006 +-#define mmA2S_CNTL2_SEC_CL2_DEFAULT 0x00000006 +-#define mmA2S_CNTL2_SEC_CL3_DEFAULT 0x00000006 +-#define mmA2S_CNTL2_SEC_CL4_DEFAULT 0x00000006 +- +- +-// addressBlock: nbif_sion_SIONDEC +-// base address: 0x1400000 +-#define ixSION_CL0_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 +-#define ixSION_CL0_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 +-#define ixSION_CL0_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 +-#define ixSION_CL0_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 +-#define ixSION_CL0_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 +-#define ixSION_CL0_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 +-#define ixSION_CL0_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 +-#define ixSION_CL0_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 +-#define ixSION_CL0_Req_BurstTarget_REG0_DEFAULT 0x00000000 +-#define ixSION_CL0_Req_BurstTarget_REG1_DEFAULT 0x00000000 +-#define ixSION_CL0_Req_TimeSlot_REG0_DEFAULT 0x00000000 +-#define ixSION_CL0_Req_TimeSlot_REG1_DEFAULT 0x00000000 +-#define ixSION_CL0_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +-#define ixSION_CL0_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +-#define ixSION_CL0_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +-#define ixSION_CL0_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +-#define ixSION_CL0_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +-#define ixSION_CL0_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +-#define ixSION_CL0_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +-#define ixSION_CL0_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +-#define ixSION_CL1_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 +-#define ixSION_CL1_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 +-#define ixSION_CL1_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 +-#define ixSION_CL1_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 +-#define ixSION_CL1_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 +-#define ixSION_CL1_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 +-#define ixSION_CL1_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 +-#define ixSION_CL1_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 +-#define ixSION_CL1_Req_BurstTarget_REG0_DEFAULT 0x00000000 +-#define ixSION_CL1_Req_BurstTarget_REG1_DEFAULT 0x00000000 +-#define ixSION_CL1_Req_TimeSlot_REG0_DEFAULT 0x00000000 +-#define ixSION_CL1_Req_TimeSlot_REG1_DEFAULT 0x00000000 +-#define ixSION_CL1_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +-#define ixSION_CL1_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +-#define ixSION_CL1_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +-#define ixSION_CL1_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +-#define ixSION_CL1_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +-#define ixSION_CL1_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +-#define ixSION_CL1_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +-#define ixSION_CL1_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +-#define ixSION_CL2_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 +-#define ixSION_CL2_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 +-#define ixSION_CL2_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 +-#define ixSION_CL2_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 +-#define ixSION_CL2_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 +-#define ixSION_CL2_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 +-#define ixSION_CL2_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 +-#define ixSION_CL2_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 +-#define ixSION_CL2_Req_BurstTarget_REG0_DEFAULT 0x00000000 +-#define ixSION_CL2_Req_BurstTarget_REG1_DEFAULT 0x00000000 +-#define ixSION_CL2_Req_TimeSlot_REG0_DEFAULT 0x00000000 +-#define ixSION_CL2_Req_TimeSlot_REG1_DEFAULT 0x00000000 +-#define ixSION_CL2_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +-#define ixSION_CL2_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +-#define ixSION_CL2_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +-#define ixSION_CL2_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +-#define ixSION_CL2_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +-#define ixSION_CL2_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +-#define ixSION_CL2_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +-#define ixSION_CL2_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +-#define ixSION_CL3_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 +-#define ixSION_CL3_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 +-#define ixSION_CL3_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 +-#define ixSION_CL3_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 +-#define ixSION_CL3_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 +-#define ixSION_CL3_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 +-#define ixSION_CL3_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 +-#define ixSION_CL3_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 +-#define ixSION_CL3_Req_BurstTarget_REG0_DEFAULT 0x00000000 +-#define ixSION_CL3_Req_BurstTarget_REG1_DEFAULT 0x00000000 +-#define ixSION_CL3_Req_TimeSlot_REG0_DEFAULT 0x00000000 +-#define ixSION_CL3_Req_TimeSlot_REG1_DEFAULT 0x00000000 +-#define ixSION_CL3_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +-#define ixSION_CL3_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +-#define ixSION_CL3_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +-#define ixSION_CL3_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +-#define ixSION_CL3_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +-#define ixSION_CL3_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +-#define ixSION_CL3_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +-#define ixSION_CL3_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +-#define ixSION_CL4_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 +-#define ixSION_CL4_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 +-#define ixSION_CL4_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 +-#define ixSION_CL4_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 +-#define ixSION_CL4_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 +-#define ixSION_CL4_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 +-#define ixSION_CL4_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 +-#define ixSION_CL4_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 +-#define ixSION_CL4_Req_BurstTarget_REG0_DEFAULT 0x00000000 +-#define ixSION_CL4_Req_BurstTarget_REG1_DEFAULT 0x00000000 +-#define ixSION_CL4_Req_TimeSlot_REG0_DEFAULT 0x00000000 +-#define ixSION_CL4_Req_TimeSlot_REG1_DEFAULT 0x00000000 +-#define ixSION_CL4_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +-#define ixSION_CL4_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +-#define ixSION_CL4_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +-#define ixSION_CL4_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +-#define ixSION_CL4_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +-#define ixSION_CL4_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +-#define ixSION_CL4_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +-#define ixSION_CL4_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +-#define ixSION_CL5_RdRsp_BurstTarget_REG0_DEFAULT 0x00000000 +-#define ixSION_CL5_RdRsp_BurstTarget_REG1_DEFAULT 0x00000000 +-#define ixSION_CL5_RdRsp_TimeSlot_REG0_DEFAULT 0x00000000 +-#define ixSION_CL5_RdRsp_TimeSlot_REG1_DEFAULT 0x00000000 +-#define ixSION_CL5_WrRsp_BurstTarget_REG0_DEFAULT 0x00000000 +-#define ixSION_CL5_WrRsp_BurstTarget_REG1_DEFAULT 0x00000000 +-#define ixSION_CL5_WrRsp_TimeSlot_REG0_DEFAULT 0x00000000 +-#define ixSION_CL5_WrRsp_TimeSlot_REG1_DEFAULT 0x00000000 +-#define ixSION_CL5_Req_BurstTarget_REG0_DEFAULT 0x00000000 +-#define ixSION_CL5_Req_BurstTarget_REG1_DEFAULT 0x00000000 +-#define ixSION_CL5_Req_TimeSlot_REG0_DEFAULT 0x00000000 +-#define ixSION_CL5_Req_TimeSlot_REG1_DEFAULT 0x00000000 +-#define ixSION_CL5_ReqPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +-#define ixSION_CL5_ReqPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +-#define ixSION_CL5_DataPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +-#define ixSION_CL5_DataPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +-#define ixSION_CL5_RdRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +-#define ixSION_CL5_RdRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +-#define ixSION_CL5_WrRspPoolCredit_Alloc_REG0_DEFAULT 0x00000000 +-#define ixSION_CL5_WrRspPoolCredit_Alloc_REG1_DEFAULT 0x00000000 +-#define ixSION_CNTL_REG0_DEFAULT 0x00000000 +-#define ixSION_CNTL_REG1_DEFAULT 0x00000000 +- +- +-// addressBlock: syshub_mmreg_direct_syshubdirect +-// base address: 0x1400000 +-#define ixSYSHUB_DS_CTRL_SOCCLK_DEFAULT 0x00000000 +-#define ixSYSHUB_DS_CTRL2_SOCCLK_DEFAULT 0x00000100 +-#define ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK_DEFAULT 0x00000000 +-#define ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK_DEFAULT 0x00000000 +-#define ixDMA_CLK0_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e +-#define ixDMA_CLK0_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e +-#define ixDMA_CLK0_SW0_CL0_CNTL_DEFAULT 0x20200000 +-#define ixDMA_CLK0_SW0_CL1_CNTL_DEFAULT 0x20200000 +-#define ixDMA_CLK0_SW0_CL2_CNTL_DEFAULT 0x20200000 +-#define ixDMA_CLK0_SW0_CL3_CNTL_DEFAULT 0x20200000 +-#define ixDMA_CLK0_SW0_CL4_CNTL_DEFAULT 0x20200000 +-#define ixDMA_CLK0_SW0_CL5_CNTL_DEFAULT 0x20200000 +-#define ixDMA_CLK0_SW1_CL0_CNTL_DEFAULT 0x20200000 +-#define ixDMA_CLK0_SW2_CL0_CNTL_DEFAULT 0x20200000 +-#define ixSYSHUB_CG_CNTL_DEFAULT 0x00082000 +-#define ixSYSHUB_TRANS_IDLE_DEFAULT 0x00000000 +-#define ixSYSHUB_HP_TIMER_DEFAULT 0x00000100 +-#define ixSYSHUB_SCRATCH_DEFAULT 0x00000040 +-#define ixSYSHUB_DS_CTRL_SHUBCLK_DEFAULT 0x00000000 +-#define ixSYSHUB_DS_CTRL2_SHUBCLK_DEFAULT 0x00000100 +-#define ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK_DEFAULT 0x00000000 +-#define ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK_DEFAULT 0x00000000 +-#define ixDMA_CLK1_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e +-#define ixDMA_CLK1_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e +-#define ixDMA_CLK1_SW0_CL0_CNTL_DEFAULT 0x20200000 +-#define ixDMA_CLK1_SW0_CL1_CNTL_DEFAULT 0x20200000 +-#define ixDMA_CLK1_SW0_CL2_CNTL_DEFAULT 0x20200000 +-#define ixDMA_CLK1_SW0_CL3_CNTL_DEFAULT 0x20200000 +-#define ixDMA_CLK1_SW0_CL4_CNTL_DEFAULT 0x20200000 +-#define ixDMA_CLK1_SW1_CL0_CNTL_DEFAULT 0x20200000 +-#define ixDMA_CLK1_SW1_CL1_CNTL_DEFAULT 0x20200000 +-#define ixDMA_CLK1_SW1_CL2_CNTL_DEFAULT 0x20200000 +-#define ixDMA_CLK1_SW1_CL3_CNTL_DEFAULT 0x20200000 +-#define ixDMA_CLK1_SW1_CL4_CNTL_DEFAULT 0x20200000 +- +- +-// addressBlock: gdc_ras_gdc_ras_regblk +-// base address: 0x1400000 +-#define ixGDC_RAS_LEAF0_CTRL_DEFAULT 0x00000000 +-#define ixGDC_RAS_LEAF1_CTRL_DEFAULT 0x00000000 +-#define ixGDC_RAS_LEAF2_CTRL_DEFAULT 0x00000000 +-#define ixGDC_RAS_LEAF3_CTRL_DEFAULT 0x00000000 +-#define ixGDC_RAS_LEAF4_CTRL_DEFAULT 0x00000000 +-#define ixGDC_RAS_LEAF5_CTRL_DEFAULT 0x00000000 +- +- +-// addressBlock: gdc_rst_GDCRST_DEC +-// base address: 0x1400000 +-#define ixSHUB_PF_FLR_RST_DEFAULT 0x00000000 +-#define ixSHUB_GFX_DRV_MODE1_RST_DEFAULT 0x00000000 +-#define ixSHUB_LINK_RESET_DEFAULT 0x00000000 +-#define ixSHUB_PF0_VF_FLR_RST_DEFAULT 0x00000000 +-#define ixSHUB_HARD_RST_CTRL_DEFAULT 0x0000001b +-#define ixSHUB_SOFT_RST_CTRL_DEFAULT 0x00000009 +-#define ixSHUB_SDP_PORT_RST_DEFAULT 0x00000000 +- +- +-// addressBlock: bif_bx_pf_SYSDEC +-// base address: 0x0 +-#define mmSBIOS_SCRATCH_0_DEFAULT 0x00000000 +-#define mmSBIOS_SCRATCH_1_DEFAULT 0x00000000 +-#define mmSBIOS_SCRATCH_2_DEFAULT 0x00000000 +-#define mmSBIOS_SCRATCH_3_DEFAULT 0x00000000 +-#define mmBIOS_SCRATCH_0_DEFAULT 0x00000000 +-#define mmBIOS_SCRATCH_1_DEFAULT 0x00000000 +-#define mmBIOS_SCRATCH_2_DEFAULT 0x00000000 +-#define mmBIOS_SCRATCH_3_DEFAULT 0x00000000 +-#define mmBIOS_SCRATCH_4_DEFAULT 0x00000000 +-#define mmBIOS_SCRATCH_5_DEFAULT 0x00000000 +-#define mmBIOS_SCRATCH_6_DEFAULT 0x00000000 +-#define mmBIOS_SCRATCH_7_DEFAULT 0x00000000 +-#define mmBIOS_SCRATCH_8_DEFAULT 0x00000000 +-#define mmBIOS_SCRATCH_9_DEFAULT 0x00000000 +-#define mmBIOS_SCRATCH_10_DEFAULT 0x00000000 +-#define mmBIOS_SCRATCH_11_DEFAULT 0x00000000 +-#define mmBIOS_SCRATCH_12_DEFAULT 0x00000000 +-#define mmBIOS_SCRATCH_13_DEFAULT 0x00000000 +-#define mmBIOS_SCRATCH_14_DEFAULT 0x00000000 +-#define mmBIOS_SCRATCH_15_DEFAULT 0x00000000 +-#define mmBIF_RLC_INTR_CNTL_DEFAULT 0x00000000 +-#define mmBIF_VCE_INTR_CNTL_DEFAULT 0x00000000 +-#define mmBIF_UVD_INTR_CNTL_DEFAULT 0x00000000 +-#define mmGFX_MMIOREG_CAM_ADDR0_DEFAULT 0x00000000 +-#define mmGFX_MMIOREG_CAM_REMAP_ADDR0_DEFAULT 0x00000000 +-#define mmGFX_MMIOREG_CAM_ADDR1_DEFAULT 0x00000000 +-#define mmGFX_MMIOREG_CAM_REMAP_ADDR1_DEFAULT 0x00000000 +-#define mmGFX_MMIOREG_CAM_ADDR2_DEFAULT 0x00000000 +-#define mmGFX_MMIOREG_CAM_REMAP_ADDR2_DEFAULT 0x00000000 +-#define mmGFX_MMIOREG_CAM_ADDR3_DEFAULT 0x00000000 +-#define mmGFX_MMIOREG_CAM_REMAP_ADDR3_DEFAULT 0x00000000 +-#define mmGFX_MMIOREG_CAM_ADDR4_DEFAULT 0x00000000 +-#define mmGFX_MMIOREG_CAM_REMAP_ADDR4_DEFAULT 0x00000000 +-#define mmGFX_MMIOREG_CAM_ADDR5_DEFAULT 0x00000000 +-#define mmGFX_MMIOREG_CAM_REMAP_ADDR5_DEFAULT 0x00000000 +-#define mmGFX_MMIOREG_CAM_ADDR6_DEFAULT 0x00000000 +-#define mmGFX_MMIOREG_CAM_REMAP_ADDR6_DEFAULT 0x00000000 +-#define mmGFX_MMIOREG_CAM_ADDR7_DEFAULT 0x00000000 +-#define mmGFX_MMIOREG_CAM_REMAP_ADDR7_DEFAULT 0x00000000 +-#define mmGFX_MMIOREG_CAM_CNTL_DEFAULT 0x00000000 +-#define mmGFX_MMIOREG_CAM_ZERO_CPL_DEFAULT 0x00000000 +-#define mmGFX_MMIOREG_CAM_ONE_CPL_DEFAULT 0x00000000 +-#define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_DEFAULT 0x00000000 +- +- +-// addressBlock: bif_bx_pf_SYSPFVFDEC +-// base address: 0x0 +-#define mmMM_INDEX_DEFAULT 0x00000000 +-#define mmMM_DATA_DEFAULT 0x00000000 +-#define mmMM_INDEX_HI_DEFAULT 0x00000000 +-#define mmSYSHUB_INDEX_OVLP_DEFAULT 0x00000000 +-#define mmSYSHUB_DATA_OVLP_DEFAULT 0x00000000 +-#define mmPCIE_INDEX_DEFAULT 0x00000000 +-#define mmPCIE_DATA_DEFAULT 0x00000000 +-#define mmPCIE_INDEX2_DEFAULT 0x00000000 +-#define mmPCIE_DATA2_DEFAULT 0x00000000 +- +- +-// addressBlock: rcc_dwn_BIFDEC1 +-// base address: 0x0 +-#define mmDN_PCIE_RESERVED_DEFAULT 0x00000000 +-#define mmDN_PCIE_SCRATCH_DEFAULT 0x00000000 +-#define mmDN_PCIE_CNTL_DEFAULT 0x00000000 +-#define mmDN_PCIE_CONFIG_CNTL_DEFAULT 0x00000000 +-#define mmDN_PCIE_RX_CNTL2_DEFAULT 0x00000000 +-#define mmDN_PCIE_BUS_CNTL_DEFAULT 0x00000080 +-#define mmDN_PCIE_CFG_CNTL_DEFAULT 0x00000000 +-#define mmDN_PCIE_STRAP_F0_DEFAULT 0x00000001 +-#define mmDN_PCIE_STRAP_MISC_DEFAULT 0x00000000 +-#define mmDN_PCIE_STRAP_MISC2_DEFAULT 0x00000000 +- +- +-// addressBlock: rcc_dwnp_BIFDEC1 +-// base address: 0x0 +-#define mmPCIEP_RESERVED_DEFAULT 0x00000000 +-#define mmPCIEP_SCRATCH_DEFAULT 0x00000000 +-#define mmPCIE_ERR_CNTL_DEFAULT 0x00000500 +-#define mmPCIE_RX_CNTL_DEFAULT 0x00000000 +-#define mmPCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 +-#define mmPCIE_LC_CNTL2_DEFAULT 0x00000000 +-#define mmPCIEP_STRAP_MISC_DEFAULT 0x00000000 +-#define mmLTR_MSG_INFO_FROM_EP_DEFAULT 0x00000000 +- +- +-// addressBlock: rcc_ep_BIFDEC1 +-// base address: 0x0 +-#define mmEP_PCIE_SCRATCH_DEFAULT 0x00000000 +-#define mmEP_PCIE_CNTL_DEFAULT 0x00000100 +-#define mmEP_PCIE_INT_CNTL_DEFAULT 0x00000000 +-#define mmEP_PCIE_INT_STATUS_DEFAULT 0x00000000 +-#define mmEP_PCIE_RX_CNTL2_DEFAULT 0x00000000 +-#define mmEP_PCIE_BUS_CNTL_DEFAULT 0x00000080 +-#define mmEP_PCIE_CFG_CNTL_DEFAULT 0x00000000 +-#define mmEP_PCIE_OBFF_CNTL_DEFAULT 0x00012774 +-#define mmEP_PCIE_TX_LTR_CNTL_DEFAULT 0x00003468 +-#define mmEP_PCIE_STRAP_MISC_DEFAULT 0x00000000 +-#define mmEP_PCIE_STRAP_MISC2_DEFAULT 0x00000000 +-#define mmEP_PCIE_STRAP_PI_DEFAULT 0x00000000 +-#define mmEP_PCIE_F0_DPA_CAP_DEFAULT 0x190a1000 +-#define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR_DEFAULT 0x000000f0 +-#define mmEP_PCIE_F0_DPA_CNTL_DEFAULT 0x00000100 +-#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_DEFAULT 0x000000fa +-#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_DEFAULT 0x000000c8 +-#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_DEFAULT 0x00000096 +-#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_DEFAULT 0x00000064 +-#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_DEFAULT 0x0000004b +-#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_DEFAULT 0x00000032 +-#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_DEFAULT 0x00000019 +-#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_DEFAULT 0x0000000a +-#define mmEP_PCIE_PME_CONTROL_DEFAULT 0x00000000 +-#define mmEP_PCIEP_RESERVED_DEFAULT 0x00000000 +-#define mmEP_PCIE_TX_CNTL_DEFAULT 0x00000000 +-#define mmEP_PCIE_TX_REQUESTER_ID_DEFAULT 0x00000000 +-#define mmEP_PCIE_ERR_CNTL_DEFAULT 0x00000500 +-#define mmEP_PCIE_RX_CNTL_DEFAULT 0x01000000 +-#define mmEP_PCIE_LC_SPEED_CNTL_DEFAULT 0x00000000 +- +- +-// addressBlock: bif_bx_pf_BIFDEC1 +-// base address: 0x0 +-#define mmBIF_MM_INDACCESS_CNTL_DEFAULT 0x00000000 +-#define mmBUS_CNTL_DEFAULT 0x00000000 +-#define mmBIF_SCRATCH0_DEFAULT 0x00000000 +-#define mmBIF_SCRATCH1_DEFAULT 0x00000000 +-#define mmBX_RESET_EN_DEFAULT 0x00010003 +-#define mmMM_CFGREGS_CNTL_DEFAULT 0x00000000 +-#define mmBX_RESET_CNTL_DEFAULT 0x00000000 +-#define mmINTERRUPT_CNTL_DEFAULT 0x00000010 +-#define mmINTERRUPT_CNTL2_DEFAULT 0x00000000 +-#define mmCLKREQB_PAD_CNTL_DEFAULT 0x000008e0 +-#define mmCLKREQB_PERF_COUNTER_DEFAULT 0x00000000 +-#define mmBIF_CLK_CTRL_DEFAULT 0x00000000 +-#define mmBIF_FEATURES_CONTROL_MISC_DEFAULT 0x00000000 +-#define mmBIF_DOORBELL_CNTL_DEFAULT 0x00000000 +-#define mmBIF_DOORBELL_INT_CNTL_DEFAULT 0x00000000 +-#define mmBIF_SLVARB_MODE_DEFAULT 0x00000000 +-#define mmBIF_FB_EN_DEFAULT 0x00000000 +-#define mmBIF_BUSY_DELAY_CNTR_DEFAULT 0x0000003f +-#define mmBIF_PERFMON_CNTL_DEFAULT 0x00000000 +-#define mmBIF_PERFCOUNTER0_RESULT_DEFAULT 0x00000000 +-#define mmBIF_PERFCOUNTER1_RESULT_DEFAULT 0x00000000 +-#define mmBIF_MST_TRANS_PENDING_VF_DEFAULT 0x00000000 +-#define mmBIF_SLV_TRANS_PENDING_VF_DEFAULT 0x00000000 +-#define mmBACO_CNTL_DEFAULT 0x00000000 +-#define mmBIF_BACO_EXIT_TIME0_DEFAULT 0x00000100 +-#define mmBIF_BACO_EXIT_TIMER1_DEFAULT 0x00000100 +-#define mmBIF_BACO_EXIT_TIMER2_DEFAULT 0x00000300 +-#define mmBIF_BACO_EXIT_TIMER3_DEFAULT 0x00000400 +-#define mmBIF_BACO_EXIT_TIMER4_DEFAULT 0x00000100 +-#define mmMEM_TYPE_CNTL_DEFAULT 0x00000000 +-#define mmSMU_BIF_VDDGFX_PWR_STATUS_DEFAULT 0x00000000 +-#define mmBIF_VDDGFX_GFX0_LOWER_DEFAULT 0xc0008000 +-#define mmBIF_VDDGFX_GFX0_UPPER_DEFAULT 0x0000cffc +-#define mmBIF_VDDGFX_GFX1_LOWER_DEFAULT 0xc0028000 +-#define mmBIF_VDDGFX_GFX1_UPPER_DEFAULT 0x00031ffc +-#define mmBIF_VDDGFX_GFX2_LOWER_DEFAULT 0xc0034000 +-#define mmBIF_VDDGFX_GFX2_UPPER_DEFAULT 0x00037ffc +-#define mmBIF_VDDGFX_GFX3_LOWER_DEFAULT 0xc003c000 +-#define mmBIF_VDDGFX_GFX3_UPPER_DEFAULT 0x0003e1fc +-#define mmBIF_VDDGFX_GFX4_LOWER_DEFAULT 0xc003ec00 +-#define mmBIF_VDDGFX_GFX4_UPPER_DEFAULT 0x0003f1fc +-#define mmBIF_VDDGFX_GFX5_LOWER_DEFAULT 0xc003fc00 +-#define mmBIF_VDDGFX_GFX5_UPPER_DEFAULT 0x0003fffc +-#define mmBIF_VDDGFX_RSV1_LOWER_DEFAULT 0x00000000 +-#define mmBIF_VDDGFX_RSV1_UPPER_DEFAULT 0x00000000 +-#define mmBIF_VDDGFX_RSV2_LOWER_DEFAULT 0x00000000 +-#define mmBIF_VDDGFX_RSV2_UPPER_DEFAULT 0x00000000 +-#define mmBIF_VDDGFX_RSV3_LOWER_DEFAULT 0x00000000 +-#define mmBIF_VDDGFX_RSV3_UPPER_DEFAULT 0x00000000 +-#define mmBIF_VDDGFX_RSV4_LOWER_DEFAULT 0x00000000 +-#define mmBIF_VDDGFX_RSV4_UPPER_DEFAULT 0x00000000 +-#define mmBIF_VDDGFX_FB_CMP_DEFAULT 0x00000000 +-#define mmBIF_DOORBELL_GBLAPER1_LOWER_DEFAULT 0x80000780 +-#define mmBIF_DOORBELL_GBLAPER1_UPPER_DEFAULT 0x000007fc +-#define mmBIF_DOORBELL_GBLAPER2_LOWER_DEFAULT 0x80000800 +-#define mmBIF_DOORBELL_GBLAPER2_UPPER_DEFAULT 0x0000087c +-#define mmREMAP_HDP_MEM_FLUSH_CNTL_DEFAULT 0x0000385c +-#define mmREMAP_HDP_REG_FLUSH_CNTL_DEFAULT 0x00003858 +-#define mmBIF_RB_CNTL_DEFAULT 0x00000000 +-#define mmBIF_RB_BASE_DEFAULT 0x00000000 +-#define mmBIF_RB_RPTR_DEFAULT 0x00000000 +-#define mmBIF_RB_WPTR_DEFAULT 0x00000000 +-#define mmBIF_RB_WPTR_ADDR_HI_DEFAULT 0x00000000 +-#define mmBIF_RB_WPTR_ADDR_LO_DEFAULT 0x00000000 +-#define mmMAILBOX_INDEX_DEFAULT 0x00000000 +-#define mmBIF_GPUIOV_RESET_NOTIFICATION_DEFAULT 0x00000000 +-#define mmBIF_UVD_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 +-#define mmBIF_VCE_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 +-#define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE_DEFAULT 0x00000008 +-#define mmBIF_GMI_WRR_WEIGHT_DEFAULT 0x00202020 +-#define mmNBIF_STRAP_WRITE_CTRL_DEFAULT 0x00000000 +-#define mmBIF_PERSTB_PAD_CNTL_DEFAULT 0x000000c0 +-#define mmBIF_PX_EN_PAD_CNTL_DEFAULT 0x00000031 +-#define mmBIF_REFPADKIN_PAD_CNTL_DEFAULT 0x00000007 +-#define mmBIF_CLKREQB_PAD_CNTL_DEFAULT 0x00600100 +- +- +-// addressBlock: rcc_pf_0_BIFDEC1 +-// base address: 0x0 +-#define mmRCC_BACO_CNTL_MISC_DEFAULT 0x00000000 +-#define mmRCC_RESET_EN_DEFAULT 0x00008000 +-#define mmRCC_VDM_SUPPORT_DEFAULT 0x00000000 +-#define mmRCC_PEER_REG_RANGE0_DEFAULT 0xffff0000 +-#define mmRCC_PEER_REG_RANGE1_DEFAULT 0xffff0000 +-#define mmRCC_BUS_CNTL_DEFAULT 0x00000000 +-#define mmRCC_CONFIG_CNTL_DEFAULT 0x00000000 +-#define mmRCC_CONFIG_F0_BASE_DEFAULT 0x00000000 +-#define mmRCC_CONFIG_APER_SIZE_DEFAULT 0x00000000 +-#define mmRCC_CONFIG_REG_APER_SIZE_DEFAULT 0x00000000 +-#define mmRCC_XDMA_LO_DEFAULT 0x00000000 +-#define mmRCC_XDMA_HI_DEFAULT 0x00000000 +-#define mmRCC_FEATURES_CONTROL_MISC_DEFAULT 0x00000000 +-#define mmRCC_BUSNUM_CNTL1_DEFAULT 0x00000000 +-#define mmRCC_BUSNUM_LIST0_DEFAULT 0x00000000 +-#define mmRCC_BUSNUM_LIST1_DEFAULT 0x00000000 +-#define mmRCC_BUSNUM_CNTL2_DEFAULT 0x00000000 +-#define mmRCC_CAPTURE_HOST_BUSNUM_DEFAULT 0x00000000 +-#define mmRCC_HOST_BUSNUM_DEFAULT 0x00000000 +-#define mmRCC_PEER0_FB_OFFSET_HI_DEFAULT 0x00000000 +-#define mmRCC_PEER0_FB_OFFSET_LO_DEFAULT 0x00000000 +-#define mmRCC_PEER1_FB_OFFSET_HI_DEFAULT 0x00000000 +-#define mmRCC_PEER1_FB_OFFSET_LO_DEFAULT 0x00000000 +-#define mmRCC_PEER2_FB_OFFSET_HI_DEFAULT 0x00000000 +-#define mmRCC_PEER2_FB_OFFSET_LO_DEFAULT 0x00000000 +-#define mmRCC_PEER3_FB_OFFSET_HI_DEFAULT 0x00000000 +-#define mmRCC_PEER3_FB_OFFSET_LO_DEFAULT 0x00000000 +-#define mmRCC_DEVFUNCNUM_LIST0_DEFAULT 0x00000000 +-#define mmRCC_DEVFUNCNUM_LIST1_DEFAULT 0x00000000 +-#define mmRCC_DEV0_LINK_CNTL_DEFAULT 0x00000000 +-#define mmRCC_CMN_LINK_CNTL_DEFAULT 0x00000000 +-#define mmRCC_EP_REQUESTERID_RESTORE_DEFAULT 0x00000000 +-#define mmRCC_LTR_LSWITCH_CNTL_DEFAULT 0x00000000 +-#define mmRCC_MH_ARB_CNTL_DEFAULT 0x00000000 +- +- +-// addressBlock: rcc_pf_0_BIFDEC2 +-// base address: 0x0 +-#define mmGFXMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 +-#define mmGFXMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 +-#define mmGFXMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 +-#define mmGFXMSIX_VECT0_CONTROL_DEFAULT 0x00000001 +-#define mmGFXMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 +-#define mmGFXMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 +-#define mmGFXMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 +-#define mmGFXMSIX_VECT1_CONTROL_DEFAULT 0x00000001 +-#define mmGFXMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 +-#define mmGFXMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 +-#define mmGFXMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 +-#define mmGFXMSIX_VECT2_CONTROL_DEFAULT 0x00000001 +-#define mmGFXMSIX_PBA_DEFAULT 0x00000000 +- +- +-// addressBlock: rcc_strap_BIFDEC1 +-// base address: 0x0 +-#define mmRCC_DEV0_PORT_STRAP0_DEFAULT 0x54228bc0 +-#define mmRCC_DEV0_PORT_STRAP1_DEFAULT 0x1022145e +-#define mmRCC_DEV0_PORT_STRAP2_DEFAULT 0x1c65e009 +-#define mmRCC_DEV0_PORT_STRAP3_DEFAULT 0x5ffff849 +-#define mmRCC_DEV0_PORT_STRAP4_DEFAULT 0x00000000 +-#define mmRCC_DEV0_PORT_STRAP5_DEFAULT 0xaf800000 +-#define mmRCC_DEV0_PORT_STRAP6_DEFAULT 0x00000002 +-#define mmRCC_DEV0_PORT_STRAP7_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF0_STRAP0_DEFAULT 0x30000000 +-#define mmRCC_DEV0_EPF0_STRAP1_DEFAULT 0x05530000 +-#define mmRCC_DEV0_EPF0_STRAP13_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF0_STRAP2_DEFAULT 0x02000000 +-#define mmRCC_DEV0_EPF0_STRAP3_DEFAULT 0x08b40001 +-#define mmRCC_DEV0_EPF0_STRAP4_DEFAULT 0x1f000042 +-#define mmRCC_DEV0_EPF0_STRAP5_DEFAULT 0x00001022 +-#define mmRCC_DEV0_EPF0_STRAP8_DEFAULT 0xc8c73002 +-#define mmRCC_DEV0_EPF0_STRAP9_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF1_STRAP0_DEFAULT 0x30000000 +-#define mmRCC_DEV0_EPF1_STRAP10_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF1_STRAP11_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF1_STRAP12_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF1_STRAP13_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF1_STRAP2_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF1_STRAP3_DEFAULT 0x08040001 +-#define mmRCC_DEV0_EPF1_STRAP4_DEFAULT 0x2f000000 +-#define mmRCC_DEV0_EPF1_STRAP5_DEFAULT 0x00001022 +-#define mmRCC_DEV0_EPF1_STRAP6_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF1_STRAP7_DEFAULT 0x00000000 +- +- +-// addressBlock: bif_bx_pf_BIFPFVFDEC1 +-// base address: 0x0 +-#define mmBIF_BME_STATUS_DEFAULT 0x00000000 +-#define mmBIF_ATOMIC_ERR_LOG_DEFAULT 0x00000000 +-#define mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH_DEFAULT 0x00000000 +-#define mmDOORBELL_SELFRING_GPA_APER_BASE_LOW_DEFAULT 0x00000000 +-#define mmDOORBELL_SELFRING_GPA_APER_CNTL_DEFAULT 0x00000000 +-#define mmHDP_REG_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 +-#define mmHDP_MEM_COHERENCY_FLUSH_CNTL_DEFAULT 0x00000000 +-#define mmGPU_HDP_FLUSH_REQ_DEFAULT 0x00000000 +-#define mmGPU_HDP_FLUSH_DONE_DEFAULT 0x00000000 +-#define mmBIF_TRANS_PENDING_DEFAULT 0x00000000 +-#define mmMAILBOX_MSGBUF_TRN_DW0_DEFAULT 0x00000000 +-#define mmMAILBOX_MSGBUF_TRN_DW1_DEFAULT 0x00000000 +-#define mmMAILBOX_MSGBUF_TRN_DW2_DEFAULT 0x00000000 +-#define mmMAILBOX_MSGBUF_TRN_DW3_DEFAULT 0x00000000 +-#define mmMAILBOX_MSGBUF_RCV_DW0_DEFAULT 0x00000000 +-#define mmMAILBOX_MSGBUF_RCV_DW1_DEFAULT 0x00000000 +-#define mmMAILBOX_MSGBUF_RCV_DW2_DEFAULT 0x00000000 +-#define mmMAILBOX_MSGBUF_RCV_DW3_DEFAULT 0x00000000 +-#define mmMAILBOX_CONTROL_DEFAULT 0x00000000 +-#define mmMAILBOX_INT_CNTL_DEFAULT 0x00000000 +-#define mmBIF_VMHV_MAILBOX_DEFAULT 0x00000000 +- +- +-// addressBlock: rcc_pf_0_BIFPFVFDEC1 +-// base address: 0x0 +-#define mmRCC_DOORBELL_APER_EN_DEFAULT 0x00000000 +-#define mmRCC_CONFIG_MEMSIZE_DEFAULT 0x00000000 +-#define mmRCC_CONFIG_RESERVED_DEFAULT 0x00000000 +-#define mmRCC_IOV_FUNC_IDENTIFIER_DEFAULT 0x00000000 +- +- +-// addressBlock: syshub_mmreg_ind_syshubdec +-// base address: 0x0 +-#define mmSYSHUB_INDEX_DEFAULT 0x00000000 +-#define mmSYSHUB_DATA_DEFAULT 0x00000000 +- +- +-// addressBlock: rcc_strap_rcc_strap_internal +-// base address: 0x10100000 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0_DEFAULT 0x54228bc0 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1_DEFAULT 0x1022145e +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2_DEFAULT 0x1c65e009 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3_DEFAULT 0x5ffff849 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4_DEFAULT 0x00000000 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5_DEFAULT 0xaf800000 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6_DEFAULT 0x00000002 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7_DEFAULT 0x00000000 +-#define mmRCC_DEV1_PORT_STRAP0_DEFAULT 0x00000000 +-#define mmRCC_DEV1_PORT_STRAP1_DEFAULT 0x00000000 +-#define mmRCC_DEV1_PORT_STRAP2_DEFAULT 0x00000000 +-#define mmRCC_DEV1_PORT_STRAP3_DEFAULT 0x00000000 +-#define mmRCC_DEV1_PORT_STRAP4_DEFAULT 0x00000000 +-#define mmRCC_DEV1_PORT_STRAP5_DEFAULT 0x00000000 +-#define mmRCC_DEV1_PORT_STRAP6_DEFAULT 0x00000000 +-#define mmRCC_DEV1_PORT_STRAP7_DEFAULT 0x00000000 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0_DEFAULT 0x30000000 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1_DEFAULT 0x05530000 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2_DEFAULT 0x02000000 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3_DEFAULT 0x08b40001 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4_DEFAULT 0x1f000042 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5_DEFAULT 0x00001022 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8_DEFAULT 0xc8c73002 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP9_DEFAULT 0x00000000 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13_DEFAULT 0x00000000 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0_DEFAULT 0x30000000 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2_DEFAULT 0x00000000 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3_DEFAULT 0x08040001 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4_DEFAULT 0x2f000000 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5_DEFAULT 0x00001022 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6_DEFAULT 0x00000000 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7_DEFAULT 0x00000000 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10_DEFAULT 0x00000000 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11_DEFAULT 0x00000000 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12_DEFAULT 0x00000000 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF2_STRAP0_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF2_STRAP2_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF2_STRAP3_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF2_STRAP4_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF2_STRAP5_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF2_STRAP6_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF2_STRAP13_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF3_STRAP0_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF3_STRAP2_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF3_STRAP3_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF3_STRAP4_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF3_STRAP5_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF3_STRAP6_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF3_STRAP13_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF4_STRAP0_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF4_STRAP2_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF4_STRAP3_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF4_STRAP4_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF4_STRAP5_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF4_STRAP6_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF4_STRAP13_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF5_STRAP0_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF5_STRAP2_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF5_STRAP3_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF5_STRAP4_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF5_STRAP5_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF5_STRAP6_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF5_STRAP13_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF6_STRAP0_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF6_STRAP2_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF6_STRAP3_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF6_STRAP4_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF6_STRAP5_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF6_STRAP6_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF6_STRAP13_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF7_STRAP0_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF7_STRAP2_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF7_STRAP3_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF7_STRAP4_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF7_STRAP5_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF7_STRAP6_DEFAULT 0x00000000 +-#define mmRCC_DEV0_EPF7_STRAP13_DEFAULT 0x00000000 +-#define mmRCC_DEV1_EPF0_STRAP0_DEFAULT 0x00000000 +-#define mmRCC_DEV1_EPF0_STRAP2_DEFAULT 0x00000000 +-#define mmRCC_DEV1_EPF0_STRAP3_DEFAULT 0x00000000 +-#define mmRCC_DEV1_EPF0_STRAP4_DEFAULT 0x00000000 +-#define mmRCC_DEV1_EPF0_STRAP5_DEFAULT 0x00000000 +-#define mmRCC_DEV1_EPF0_STRAP6_DEFAULT 0x00000000 +-#define mmRCC_DEV1_EPF0_STRAP13_DEFAULT 0x00000000 +-#define mmRCC_DEV1_EPF1_STRAP0_DEFAULT 0x00000000 +-#define mmRCC_DEV1_EPF1_STRAP2_DEFAULT 0x00000000 +-#define mmRCC_DEV1_EPF1_STRAP3_DEFAULT 0x00000000 +-#define mmRCC_DEV1_EPF1_STRAP4_DEFAULT 0x00000000 +-#define mmRCC_DEV1_EPF1_STRAP5_DEFAULT 0x00000000 +-#define mmRCC_DEV1_EPF1_STRAP6_DEFAULT 0x00000000 +-#define mmRCC_DEV1_EPF1_STRAP13_DEFAULT 0x00000000 +-#define mmRCC_DEV1_EPF2_STRAP0_DEFAULT 0x00000000 +-#define mmRCC_DEV1_EPF2_STRAP2_DEFAULT 0x00000000 +-#define mmRCC_DEV1_EPF2_STRAP3_DEFAULT 0x00000000 +-#define mmRCC_DEV1_EPF2_STRAP4_DEFAULT 0x00000000 +-#define mmRCC_DEV1_EPF2_STRAP5_DEFAULT 0x00000000 +-#define mmRCC_DEV1_EPF2_STRAP6_DEFAULT 0x00000000 +-#define mmRCC_DEV1_EPF2_STRAP13_DEFAULT 0x00000000 +- +- +-// addressBlock: bif_rst_bif_rst_regblk +-// base address: 0x10100000 +-#define ixHARD_RST_CTRL_DEFAULT 0xb0000055 +-#define ixRSMU_SOFT_RST_CTRL_DEFAULT 0x90000000 +-#define ixSELF_SOFT_RST_DEFAULT 0x00000000 +-#define ixGFX_DRV_MODE1_RST_CTRL_DEFAULT 0x000000a9 +-#define ixBIF_RST_MISC_CTRL_DEFAULT 0x00000644 +-#define ixBIF_RST_MISC_CTRL2_DEFAULT 0x00000000 +-#define ixBIF_RST_MISC_CTRL3_DEFAULT 0x00004900 +-#define ixBIF_RST_GFXVF_FLR_IDLE_DEFAULT 0x00000000 +-#define ixDEV0_PF0_FLR_RST_CTRL_DEFAULT 0x0206a9a9 +-#define ixDEV0_PF1_FLR_RST_CTRL_DEFAULT 0x02060009 +-#define ixDEV0_PF2_FLR_RST_CTRL_DEFAULT 0x02060009 +-#define ixDEV0_PF3_FLR_RST_CTRL_DEFAULT 0x02060009 +-#define ixDEV0_PF4_FLR_RST_CTRL_DEFAULT 0x02060009 +-#define ixDEV0_PF5_FLR_RST_CTRL_DEFAULT 0x02060009 +-#define ixDEV0_PF6_FLR_RST_CTRL_DEFAULT 0x02060009 +-#define ixDEV0_PF7_FLR_RST_CTRL_DEFAULT 0x02060009 +-#define ixBIF_INST_RESET_INTR_STS_DEFAULT 0x00000000 +-#define ixBIF_PF_FLR_INTR_STS_DEFAULT 0x00000000 +-#define ixBIF_D3HOTD0_INTR_STS_DEFAULT 0x00000000 +-#define ixBIF_POWER_INTR_STS_DEFAULT 0x00000000 +-#define ixBIF_PF_DSTATE_INTR_STS_DEFAULT 0x00000000 +-#define ixBIF_PF0_VF_FLR_INTR_STS_DEFAULT 0x00000000 +-#define ixBIF_INST_RESET_INTR_MASK_DEFAULT 0x00000000 +-#define ixBIF_PF_FLR_INTR_MASK_DEFAULT 0x00000000 +-#define ixBIF_D3HOTD0_INTR_MASK_DEFAULT 0x000000ff +-#define ixBIF_POWER_INTR_MASK_DEFAULT 0x00000000 +-#define ixBIF_PF_DSTATE_INTR_MASK_DEFAULT 0x00000000 +-#define ixBIF_PF0_VF_FLR_INTR_MASK_DEFAULT 0x00000000 +-#define ixBIF_PF_FLR_RST_DEFAULT 0x00000000 +-#define ixBIF_PF0_VF_FLR_RST_DEFAULT 0x00000000 +-#define ixBIF_DEV0_PF0_DSTATE_VALUE_DEFAULT 0x00000000 +-#define ixBIF_DEV0_PF1_DSTATE_VALUE_DEFAULT 0x00000000 +-#define ixBIF_DEV0_PF2_DSTATE_VALUE_DEFAULT 0x00000000 +-#define ixBIF_DEV0_PF3_DSTATE_VALUE_DEFAULT 0x00000000 +-#define ixBIF_DEV0_PF4_DSTATE_VALUE_DEFAULT 0x00000000 +-#define ixBIF_DEV0_PF5_DSTATE_VALUE_DEFAULT 0x00000000 +-#define ixBIF_DEV0_PF6_DSTATE_VALUE_DEFAULT 0x00000000 +-#define ixBIF_DEV0_PF7_DSTATE_VALUE_DEFAULT 0x00000000 +-#define ixDEV0_PF0_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b +-#define ixDEV0_PF1_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b +-#define ixDEV0_PF2_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b +-#define ixDEV0_PF3_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b +-#define ixDEV0_PF4_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b +-#define ixDEV0_PF5_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b +-#define ixDEV0_PF6_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b +-#define ixDEV0_PF7_D3HOTD0_RST_CTRL_DEFAULT 0x0000001b +-#define ixBIF_PORT0_DSTATE_VALUE_DEFAULT 0x00000000 +- +- +-// addressBlock: bif_misc_bif_misc_regblk +-// base address: 0x10100000 +-#define ixMISC_SCRATCH_DEFAULT 0x00000000 +-#define ixINTR_LINE_POLARITY_DEFAULT 0x00000000 +-#define ixINTR_LINE_ENABLE_DEFAULT 0x00000000 +-#define ixOUTSTANDING_VC_ALLOC_DEFAULT 0x6f06c0cf +-#define ixBIFC_MISC_CTRL0_DEFAULT 0x08000004 +-#define ixBIFC_MISC_CTRL1_DEFAULT 0x00008004 +-#define ixBIFC_BME_ERR_LOG_DEFAULT 0x00000000 +-#define ixBIFC_RCCBIH_BME_ERR_LOG_DEFAULT 0x00000000 +-#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1_DEFAULT 0x00000000 +-#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3_DEFAULT 0x00000000 +-#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5_DEFAULT 0x00000000 +-#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7_DEFAULT 0x00000000 +-#define ixNBIF_VWIRE_CTRL_DEFAULT 0x00000000 +-#define ixNBIF_SMN_VWR_VCHG_DIS_CTRL_DEFAULT 0x00000000 +-#define ixNBIF_SMN_VWR_VCHG_RST_CTRL0_DEFAULT 0x00000000 +-#define ixNBIF_SMN_VWR_VCHG_TRIG_DEFAULT 0x00000000 +-#define ixNBIF_SMN_VWR_WTRIG_CNTL_DEFAULT 0x00000000 +-#define ixNBIF_SMN_VWR_VCHG_DIS_CTRL_1_DEFAULT 0x00000000 +-#define ixNBIF_MGCG_CTRL_DEFAULT 0x00000080 +-#define ixNBIF_DS_CTRL_LCLK_DEFAULT 0x01000000 +-#define ixSMN_MST_CNTL0_DEFAULT 0x00000001 +-#define ixSMN_MST_EP_CNTL1_DEFAULT 0x00000000 +-#define ixSMN_MST_EP_CNTL2_DEFAULT 0x00000000 +-#define ixNBIF_SDP_VWR_VCHG_DIS_CTRL_DEFAULT 0x00000000 +-#define ixNBIF_SDP_VWR_VCHG_RST_CTRL0_DEFAULT 0x00000000 +-#define ixNBIF_SDP_VWR_VCHG_RST_CTRL1_DEFAULT 0x00000000 +-#define ixNBIF_SDP_VWR_VCHG_TRIG_DEFAULT 0x00000000 +-#define ixBME_DUMMY_CNTL_0_DEFAULT 0x0000aaaa +-#define ixBIFC_THT_CNTL_DEFAULT 0x00000222 +-#define ixBIFC_HSTARB_CNTL_DEFAULT 0x00000000 +-#define ixBIFC_GSI_CNTL_DEFAULT 0x000017c0 +-#define ixBIFC_PCIEFUNC_CNTL_DEFAULT 0x00000000 +-#define ixBIFC_SDP_CNTL_0_DEFAULT 0x003cf3cf +-#define ixBIFC_PERF_CNTL_0_DEFAULT 0x00000000 +-#define ixBIFC_PERF_CNTL_1_DEFAULT 0x00000000 +-#define ixBIFC_PERF_CNT_MMIO_RD_DEFAULT 0x00000000 +-#define ixBIFC_PERF_CNT_MMIO_WR_DEFAULT 0x00000000 +-#define ixBIFC_PERF_CNT_DMA_RD_DEFAULT 0x00000000 +-#define ixBIFC_PERF_CNT_DMA_WR_DEFAULT 0x00000000 +-#define ixNBIF_REGIF_ERRSET_CTRL_DEFAULT 0x00000000 +-#define ixSMN_MST_EP_CNTL3_DEFAULT 0x00000000 +-#define ixSMN_MST_EP_CNTL4_DEFAULT 0x00000000 +-#define ixBIF_SELFRING_BUFFER_VID_DEFAULT 0x0000605f +-#define ixBIF_SELFRING_VECTOR_CNTL_DEFAULT 0x00000000 +- +- +-// addressBlock: bif_ras_bif_ras_regblk +-// base address: 0x10100000 +-#define ixBIF_RAS_LEAF0_CTRL_DEFAULT 0x00000000 +-#define ixBIF_RAS_LEAF1_CTRL_DEFAULT 0x00000000 +-#define ixBIF_RAS_LEAF2_CTRL_DEFAULT 0x00000000 +-#define ixBIF_RAS_MISC_CTRL_DEFAULT 0x00000000 +-#define ixBIF_IOHUB_RAS_IH_CNTL_DEFAULT 0x00000000 +-#define ixBIF_RAS_VWR_FROM_IOHUB_DEFAULT 0x00000000 +- +- +-// addressBlock: rcc_pfc_amdgfx_RCCPFCDEC +-// base address: 0x10134000 +-#define ixRCC_PFC_LTR_CNTL_DEFAULT 0x00000000 +-#define ixRCC_PFC_PME_RESTORE_DEFAULT 0x00000000 +-#define ixRCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000 +-#define ixRCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000 +-#define ixRCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000 +-#define ixRCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000 +-#define ixRCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000 +-#define ixRCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000 +-#define ixRCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000 +- +- +-// addressBlock: rcc_pfc_amdgfxaz_RCCPFCDEC +-// base address: 0x10134200 +-#define ixRCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL_DEFAULT 0x00000000 +-#define ixRCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE_DEFAULT 0x00000000 +-#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0_DEFAULT 0x00000000 +-#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1_DEFAULT 0x00000000 +-#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2_DEFAULT 0x00000000 +-#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3_DEFAULT 0x00000000 +-#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4_DEFAULT 0x00000000 +-#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5_DEFAULT 0x00000000 +-#define ixRCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL_DEFAULT 0x00000000 +- +- +-// addressBlock: pciemsix_amdgfx_MSIXTDEC +-// base address: 0x10170000 +-#define ixPCIEMSIX_VECT0_ADDR_LO_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT0_ADDR_HI_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT0_MSG_DATA_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT0_CONTROL_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT1_ADDR_LO_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT1_ADDR_HI_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT1_MSG_DATA_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT1_CONTROL_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT2_ADDR_LO_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT2_ADDR_HI_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT2_MSG_DATA_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT2_CONTROL_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT3_ADDR_LO_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT3_ADDR_HI_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT3_MSG_DATA_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT3_CONTROL_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT4_ADDR_LO_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT4_ADDR_HI_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT4_MSG_DATA_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT4_CONTROL_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT5_ADDR_LO_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT5_ADDR_HI_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT5_MSG_DATA_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT5_CONTROL_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT6_ADDR_LO_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT6_ADDR_HI_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT6_MSG_DATA_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT6_CONTROL_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT7_ADDR_LO_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT7_ADDR_HI_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT7_MSG_DATA_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT7_CONTROL_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT8_ADDR_LO_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT8_ADDR_HI_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT8_MSG_DATA_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT8_CONTROL_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT9_ADDR_LO_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT9_ADDR_HI_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT9_MSG_DATA_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT9_CONTROL_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT10_ADDR_LO_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT10_ADDR_HI_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT10_MSG_DATA_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT10_CONTROL_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT11_ADDR_LO_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT11_ADDR_HI_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT11_MSG_DATA_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT11_CONTROL_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT12_ADDR_LO_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT12_ADDR_HI_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT12_MSG_DATA_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT12_CONTROL_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT13_ADDR_LO_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT13_ADDR_HI_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT13_MSG_DATA_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT13_CONTROL_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT14_ADDR_LO_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT14_ADDR_HI_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT14_MSG_DATA_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT14_CONTROL_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT15_ADDR_LO_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT15_ADDR_HI_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT15_MSG_DATA_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT15_CONTROL_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT16_ADDR_LO_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT16_ADDR_HI_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT16_MSG_DATA_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT16_CONTROL_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT17_ADDR_LO_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT17_ADDR_HI_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT17_MSG_DATA_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT17_CONTROL_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT18_ADDR_LO_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT18_ADDR_HI_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT18_MSG_DATA_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT18_CONTROL_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT19_ADDR_LO_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT19_ADDR_HI_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT19_MSG_DATA_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT19_CONTROL_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT20_ADDR_LO_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT20_ADDR_HI_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT20_MSG_DATA_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT20_CONTROL_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT21_ADDR_LO_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT21_ADDR_HI_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT21_MSG_DATA_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT21_CONTROL_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT22_ADDR_LO_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT22_ADDR_HI_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT22_MSG_DATA_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT22_CONTROL_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT23_ADDR_LO_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT23_ADDR_HI_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT23_MSG_DATA_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT23_CONTROL_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT24_ADDR_LO_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT24_ADDR_HI_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT24_MSG_DATA_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT24_CONTROL_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT25_ADDR_LO_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT25_ADDR_HI_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT25_MSG_DATA_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT25_CONTROL_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT26_ADDR_LO_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT26_ADDR_HI_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT26_MSG_DATA_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT26_CONTROL_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT27_ADDR_LO_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT27_ADDR_HI_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT27_MSG_DATA_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT27_CONTROL_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT28_ADDR_LO_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT28_ADDR_HI_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT28_MSG_DATA_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT28_CONTROL_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT29_ADDR_LO_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT29_ADDR_HI_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT29_MSG_DATA_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT29_CONTROL_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT30_ADDR_LO_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT30_ADDR_HI_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT30_MSG_DATA_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT30_CONTROL_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT31_ADDR_LO_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT31_ADDR_HI_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT31_MSG_DATA_DEFAULT 0x00000000 +-#define ixPCIEMSIX_VECT31_CONTROL_DEFAULT 0x00000000 +- +- +-// addressBlock: pciemsix_amdgfx_MSIXPDEC +-// base address: 0x10171000 +-#define ixPCIEMSIX_PBA_DEFAULT 0x00000000 +- +- +-// addressBlock: syshub_mmreg_ind_syshubind +-// base address: 0x0 +-#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK_DEFAULT 0x00000000 +-#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK_DEFAULT 0x00000100 +-#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK_DEFAULT 0x00000000 +-#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK_DEFAULT 0x00000000 +-#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e +-#define ixSYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e +-#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL_DEFAULT 0x20200000 +-#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL_DEFAULT 0x20200000 +-#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL_DEFAULT 0x20200000 +-#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL_DEFAULT 0x20200000 +-#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL_DEFAULT 0x20200000 +-#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL_DEFAULT 0x20200000 +-#define ixSYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL_DEFAULT 0x20200000 +-#define ixSYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL_DEFAULT 0x20200000 +-#define ixSYSHUBMMREGIND_SYSHUB_CG_CNTL_DEFAULT 0x00082000 +-#define ixSYSHUBMMREGIND_SYSHUB_TRANS_IDLE_DEFAULT 0x00000000 +-#define ixSYSHUBMMREGIND_SYSHUB_HP_TIMER_DEFAULT 0x00000100 +-#define ixSYSHUBMMREGIND_SYSHUB_SCRATCH_DEFAULT 0x00000040 +-#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK_DEFAULT 0x00000000 +-#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK_DEFAULT 0x00000100 +-#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK_DEFAULT 0x00000000 +-#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK_DEFAULT 0x00000000 +-#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e +-#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL_DEFAULT 0x0000001e +-#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL_DEFAULT 0x20200000 +-#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL_DEFAULT 0x20200000 +-#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL_DEFAULT 0x20200000 +-#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL_DEFAULT 0x20200000 +-#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL_DEFAULT 0x20200000 +-#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL_DEFAULT 0x20200000 +-#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL_DEFAULT 0x20200000 +-#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL_DEFAULT 0x20200000 +-#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL_DEFAULT 0x20200000 +-#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL_DEFAULT 0x20200000 +- +-#endif +diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_offset.h +deleted file mode 100644 +index 68d0ffa..0000000 +--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_offset.h ++++ /dev/null +@@ -1,1688 +0,0 @@ +-/* +- * Copyright (C) 2017 Advanced Micro Devices, Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included +- * in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- */ +-#ifndef _nbif_6_1_OFFSET_HEADER +-#define _nbif_6_1_OFFSET_HEADER +- +- +-// addressBlock: bif_cfg_dev0_epf0_bifcfgdecp +-// base address: 0x0 +-#define cfgVENDOR_ID 0x0000 // duplicate +-#define cfgDEVICE_ID 0x0002 // duplicate +-#define cfgCOMMAND 0x0004 // duplicate +-#define cfgSTATUS 0x0006 // duplicate +-#define cfgREVISION_ID 0x0008 // duplicate +-#define cfgPROG_INTERFACE 0x0009 // duplicate +-#define cfgSUB_CLASS 0x000a // duplicate +-#define cfgBASE_CLASS 0x000b // duplicate +-#define cfgCACHE_LINE 0x000c // duplicate +-#define cfgLATENCY 0x000d // duplicate +-#define cfgHEADER 0x000e // duplicate +-#define cfgBIST 0x000f // duplicate +-#define cfgBASE_ADDR_1 0x0010 // duplicate +-#define cfgBASE_ADDR_2 0x0014 // duplicate +-#define cfgBASE_ADDR_3 0x0018 // duplicate +-#define cfgBASE_ADDR_4 0x001c // duplicate +-#define cfgBASE_ADDR_5 0x0020 // duplicate +-#define cfgBASE_ADDR_6 0x0024 // duplicate +-#define cfgADAPTER_ID 0x002c // duplicate +-#define cfgROM_BASE_ADDR 0x0030 // duplicate +-#define cfgCAP_PTR 0x0034 // duplicate +-#define cfgINTERRUPT_LINE 0x003c // duplicate +-#define cfgINTERRUPT_PIN 0x003d // duplicate +-#define cfgMIN_GRANT 0x003e // duplicate +-#define cfgMAX_LATENCY 0x003f // duplicate +-#define cfgVENDOR_CAP_LIST 0x0048 // duplicate +-#define cfgADAPTER_ID_W 0x004c // duplicate +-#define cfgPMI_CAP_LIST 0x0050 // duplicate +-#define cfgPMI_CAP 0x0052 // duplicate +-#define cfgPMI_STATUS_CNTL 0x0054 // duplicate +-#define cfgPCIE_CAP_LIST 0x0064 // duplicate +-#define cfgPCIE_CAP 0x0066 // duplicate +-#define cfgDEVICE_CAP 0x0068 // duplicate +-#define cfgDEVICE_CNTL 0x006c // duplicate +-#define cfgDEVICE_STATUS 0x006e // duplicate +-#define cfgLINK_CAP 0x0070 // duplicate +-#define cfgLINK_CNTL 0x0074 // duplicate +-#define cfgLINK_STATUS 0x0076 // duplicate +-#define cfgDEVICE_CAP2 0x0088 // duplicate +-#define cfgDEVICE_CNTL2 0x008c // duplicate +-#define cfgDEVICE_STATUS2 0x008e // duplicate +-#define cfgLINK_CAP2 0x0090 // duplicate +-#define cfgLINK_CNTL2 0x0094 // duplicate +-#define cfgLINK_STATUS2 0x0096 // duplicate +-#define cfgSLOT_CAP2 0x0098 // duplicate +-#define cfgSLOT_CNTL2 0x009c // duplicate +-#define cfgSLOT_STATUS2 0x009e // duplicate +-#define cfgMSI_CAP_LIST 0x00a0 // duplicate +-#define cfgMSI_MSG_CNTL 0x00a2 // duplicate +-#define cfgMSI_MSG_ADDR_LO 0x00a4 // duplicate +-#define cfgMSI_MSG_ADDR_HI 0x00a8 // duplicate +-#define cfgMSI_MSG_DATA 0x00a8 // duplicate +-#define cfgMSI_MSG_DATA_64 0x00ac // duplicate +-#define cfgMSI_MASK 0x00ac // duplicate +-#define cfgMSI_PENDING 0x00b0 // duplicate +-#define cfgMSI_MASK_64 0x00b0 // duplicate +-#define cfgMSI_PENDING_64 0x00b4 // duplicate +-#define cfgMSIX_CAP_LIST 0x00c0 // duplicate +-#define cfgMSIX_MSG_CNTL 0x00c2 // duplicate +-#define cfgMSIX_TABLE 0x00c4 // duplicate +-#define cfgMSIX_PBA 0x00c8 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR 0x0104 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC1 0x0108 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC2 0x010c // duplicate +-#define cfgPCIE_VC_ENH_CAP_LIST 0x0110 // duplicate +-#define cfgPCIE_PORT_VC_CAP_REG1 0x0114 // duplicate +-#define cfgPCIE_PORT_VC_CAP_REG2 0x0118 // duplicate +-#define cfgPCIE_PORT_VC_CNTL 0x011c // duplicate +-#define cfgPCIE_PORT_VC_STATUS 0x011e // duplicate +-#define cfgPCIE_VC0_RESOURCE_CAP 0x0120 // duplicate +-#define cfgPCIE_VC0_RESOURCE_CNTL 0x0124 // duplicate +-#define cfgPCIE_VC0_RESOURCE_STATUS 0x012a // duplicate +-#define cfgPCIE_VC1_RESOURCE_CAP 0x012c // duplicate +-#define cfgPCIE_VC1_RESOURCE_CNTL 0x0130 // duplicate +-#define cfgPCIE_VC1_RESOURCE_STATUS 0x0136 // duplicate +-#define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 // duplicate +-#define cfgPCIE_DEV_SERIAL_NUM_DW1 0x0144 // duplicate +-#define cfgPCIE_DEV_SERIAL_NUM_DW2 0x0148 // duplicate +-#define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 // duplicate +-#define cfgPCIE_UNCORR_ERR_STATUS 0x0154 // duplicate +-#define cfgPCIE_UNCORR_ERR_MASK 0x0158 // duplicate +-#define cfgPCIE_UNCORR_ERR_SEVERITY 0x015c // duplicate +-#define cfgPCIE_CORR_ERR_STATUS 0x0160 // duplicate +-#define cfgPCIE_CORR_ERR_MASK 0x0164 // duplicate +-#define cfgPCIE_ADV_ERR_CAP_CNTL 0x0168 // duplicate +-#define cfgPCIE_HDR_LOG0 0x016c // duplicate +-#define cfgPCIE_HDR_LOG1 0x0170 // duplicate +-#define cfgPCIE_HDR_LOG2 0x0174 // duplicate +-#define cfgPCIE_HDR_LOG3 0x0178 // duplicate +-#define cfgPCIE_ROOT_ERR_CMD 0x017c // duplicate +-#define cfgPCIE_ROOT_ERR_STATUS 0x0180 // duplicate +-#define cfgPCIE_ERR_SRC_ID 0x0184 // duplicate +-#define cfgPCIE_TLP_PREFIX_LOG0 0x0188 // duplicate +-#define cfgPCIE_TLP_PREFIX_LOG1 0x018c // duplicate +-#define cfgPCIE_TLP_PREFIX_LOG2 0x0190 // duplicate +-#define cfgPCIE_TLP_PREFIX_LOG3 0x0194 // duplicate +-#define cfgPCIE_BAR_ENH_CAP_LIST 0x0200 // duplicate +-#define cfgPCIE_BAR1_CAP 0x0204 // duplicate +-#define cfgPCIE_BAR1_CNTL 0x0208 // duplicate +-#define cfgPCIE_BAR2_CAP 0x020c // duplicate +-#define cfgPCIE_BAR2_CNTL 0x0210 // duplicate +-#define cfgPCIE_BAR3_CAP 0x0214 // duplicate +-#define cfgPCIE_BAR3_CNTL 0x0218 // duplicate +-#define cfgPCIE_BAR4_CAP 0x021c // duplicate +-#define cfgPCIE_BAR4_CNTL 0x0220 // duplicate +-#define cfgPCIE_BAR5_CAP 0x0224 // duplicate +-#define cfgPCIE_BAR5_CNTL 0x0228 // duplicate +-#define cfgPCIE_BAR6_CAP 0x022c // duplicate +-#define cfgPCIE_BAR6_CNTL 0x0230 // duplicate +-#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 // duplicate +-#define cfgPCIE_PWR_BUDGET_DATA_SELECT 0x0244 // duplicate +-#define cfgPCIE_PWR_BUDGET_DATA 0x0248 // duplicate +-#define cfgPCIE_PWR_BUDGET_CAP 0x024c // duplicate +-#define cfgPCIE_DPA_ENH_CAP_LIST 0x0250 // duplicate +-#define cfgPCIE_DPA_CAP 0x0254 // duplicate +-#define cfgPCIE_DPA_LATENCY_INDICATOR 0x0258 // duplicate +-#define cfgPCIE_DPA_STATUS 0x025c // duplicate +-#define cfgPCIE_DPA_CNTL 0x025e // duplicate +-#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 // duplicate +-#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 // duplicate +-#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 // duplicate +-#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 // duplicate +-#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 // duplicate +-#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 // duplicate +-#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 // duplicate +-#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 // duplicate +-#define cfgPCIE_SECONDARY_ENH_CAP_LIST 0x0270 // duplicate +-#define cfgPCIE_LINK_CNTL3 0x0274 // duplicate +-#define cfgPCIE_LANE_ERROR_STATUS 0x0278 // duplicate +-#define cfgPCIE_LANE_0_EQUALIZATION_CNTL 0x027c // duplicate +-#define cfgPCIE_LANE_1_EQUALIZATION_CNTL 0x027e // duplicate +-#define cfgPCIE_LANE_2_EQUALIZATION_CNTL 0x0280 // duplicate +-#define cfgPCIE_LANE_3_EQUALIZATION_CNTL 0x0282 // duplicate +-#define cfgPCIE_LANE_4_EQUALIZATION_CNTL 0x0284 // duplicate +-#define cfgPCIE_LANE_5_EQUALIZATION_CNTL 0x0286 // duplicate +-#define cfgPCIE_LANE_6_EQUALIZATION_CNTL 0x0288 // duplicate +-#define cfgPCIE_LANE_7_EQUALIZATION_CNTL 0x028a // duplicate +-#define cfgPCIE_LANE_8_EQUALIZATION_CNTL 0x028c // duplicate +-#define cfgPCIE_LANE_9_EQUALIZATION_CNTL 0x028e // duplicate +-#define cfgPCIE_LANE_10_EQUALIZATION_CNTL 0x0290 // duplicate +-#define cfgPCIE_LANE_11_EQUALIZATION_CNTL 0x0292 // duplicate +-#define cfgPCIE_LANE_12_EQUALIZATION_CNTL 0x0294 // duplicate +-#define cfgPCIE_LANE_13_EQUALIZATION_CNTL 0x0296 // duplicate +-#define cfgPCIE_LANE_14_EQUALIZATION_CNTL 0x0298 // duplicate +-#define cfgPCIE_LANE_15_EQUALIZATION_CNTL 0x029a // duplicate +-#define cfgPCIE_ACS_ENH_CAP_LIST 0x02a0 // duplicate +-#define cfgPCIE_ACS_CAP 0x02a4 // duplicate +-#define cfgPCIE_ACS_CNTL 0x02a6 // duplicate +-#define cfgPCIE_ATS_ENH_CAP_LIST 0x02b0 // duplicate +-#define cfgPCIE_ATS_CAP 0x02b4 // duplicate +-#define cfgPCIE_ATS_CNTL 0x02b6 // duplicate +-#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0 // duplicate +-#define cfgPCIE_PAGE_REQ_CNTL 0x02c4 // duplicate +-#define cfgPCIE_PAGE_REQ_STATUS 0x02c6 // duplicate +-#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8 // duplicate +-#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc // duplicate +-#define cfgPCIE_PASID_ENH_CAP_LIST 0x02d0 // duplicate +-#define cfgPCIE_PASID_CAP 0x02d4 // duplicate +-#define cfgPCIE_PASID_CNTL 0x02d6 // duplicate +-#define cfgPCIE_TPH_REQR_ENH_CAP_LIST 0x02e0 // duplicate +-#define cfgPCIE_TPH_REQR_CAP 0x02e4 // duplicate +-#define cfgPCIE_TPH_REQR_CNTL 0x02e8 // duplicate +-#define cfgPCIE_MC_ENH_CAP_LIST 0x02f0 // duplicate +-#define cfgPCIE_MC_CAP 0x02f4 // duplicate +-#define cfgPCIE_MC_CNTL 0x02f6 // duplicate +-#define cfgPCIE_MC_ADDR0 0x02f8 // duplicate +-#define cfgPCIE_MC_ADDR1 0x02fc // duplicate +-#define cfgPCIE_MC_RCV0 0x0300 // duplicate +-#define cfgPCIE_MC_RCV1 0x0304 // duplicate +-#define cfgPCIE_MC_BLOCK_ALL0 0x0308 // duplicate +-#define cfgPCIE_MC_BLOCK_ALL1 0x030c // duplicate +-#define cfgPCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 // duplicate +-#define cfgPCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 // duplicate +-#define cfgPCIE_LTR_ENH_CAP_LIST 0x0320 // duplicate +-#define cfgPCIE_LTR_CAP 0x0324 // duplicate +-#define cfgPCIE_ARI_ENH_CAP_LIST 0x0328 // duplicate +-#define cfgPCIE_ARI_CAP 0x032c // duplicate +-#define cfgPCIE_ARI_CNTL 0x032e // duplicate +-#define cfgPCIE_SRIOV_ENH_CAP_LIST 0x0330 // duplicate +-#define cfgPCIE_SRIOV_CAP 0x0334 // duplicate +-#define cfgPCIE_SRIOV_CONTROL 0x0338 // duplicate +-#define cfgPCIE_SRIOV_STATUS 0x033a // duplicate +-#define cfgPCIE_SRIOV_INITIAL_VFS 0x033c // duplicate +-#define cfgPCIE_SRIOV_TOTAL_VFS 0x033e // duplicate +-#define cfgPCIE_SRIOV_NUM_VFS 0x0340 // duplicate +-#define cfgPCIE_SRIOV_FUNC_DEP_LINK 0x0342 // duplicate +-#define cfgPCIE_SRIOV_FIRST_VF_OFFSET 0x0344 // duplicate +-#define cfgPCIE_SRIOV_VF_STRIDE 0x0346 // duplicate +-#define cfgPCIE_SRIOV_VF_DEVICE_ID 0x034a // duplicate +-#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c // duplicate +-#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 // duplicate +-#define cfgPCIE_SRIOV_VF_BASE_ADDR_0 0x0354 // duplicate +-#define cfgPCIE_SRIOV_VF_BASE_ADDR_1 0x0358 // duplicate +-#define cfgPCIE_SRIOV_VF_BASE_ADDR_2 0x035c // duplicate +-#define cfgPCIE_SRIOV_VF_BASE_ADDR_3 0x0360 // duplicate +-#define cfgPCIE_SRIOV_VF_BASE_ADDR_4 0x0364 // duplicate +-#define cfgPCIE_SRIOV_VF_BASE_ADDR_5 0x0368 // duplicate +-#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0400 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0404 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0408 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x040c // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0410 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0414 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0418 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x041c // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x0420 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0424 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0428 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x042c // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0430 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x0434 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x0438 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x043c // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0440 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x0444 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x0448 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x044c // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0450 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x0454 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x0458 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x045c // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0460 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x0464 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x0468 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x046c // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0x0470 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0x0474 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0x0478 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0x047c // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0x0480 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0x0484 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0x0488 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0x048c // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0x0490 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0x0494 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0x0498 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0x049c // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0x04a0 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0x04a4 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0x04a8 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0x04ac // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0x04b0 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0x04b4 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0x04b8 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0x04bc // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0x04c0 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0x04c4 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0x04c8 // duplicate +-#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0x04cc // duplicate +- +- +-// addressBlock: bif_cfg_dev0_swds_bifcfgdecp +-// base address: 0x0 +-#define mmSUB_BUS_NUMBER_LATENCY 0x0006 // duplicate +-#define mmSUB_BUS_NUMBER_LATENCY_BASE_IDX 0 +-#define mmIO_BASE_LIMIT 0x0007 // duplicate +-#define mmIO_BASE_LIMIT_BASE_IDX 0 +-#define mmSECONDARY_STATUS 0x0007 // duplicate +-#define mmSECONDARY_STATUS_BASE_IDX 0 +-#define mmMEM_BASE_LIMIT 0x0008 // duplicate +-#define mmMEM_BASE_LIMIT_BASE_IDX 0 +-#define mmPREF_BASE_LIMIT 0x0009 // duplicate +-#define mmPREF_BASE_LIMIT_BASE_IDX 0 +-#define mmPREF_BASE_UPPER 0x000a // duplicate +-#define mmPREF_BASE_UPPER_BASE_IDX 0 +-#define mmPREF_LIMIT_UPPER 0x000b // duplicate +-#define mmPREF_LIMIT_UPPER_BASE_IDX 0 +-#define mmIO_BASE_LIMIT_HI 0x000c // duplicate +-#define mmIO_BASE_LIMIT_HI_BASE_IDX 0 +-#define mmIRQ_BRIDGE_CNTL 0x000f // duplicate +-#define mmIRQ_BRIDGE_CNTL_BASE_IDX 0 +-#define mmSLOT_CAP 0x001b // duplicate +-#define mmSLOT_CAP_BASE_IDX 0 +-#define mmSLOT_CNTL 0x001c // duplicate +-#define mmSLOT_CNTL_BASE_IDX 0 +-#define mmSLOT_STATUS 0x001c // duplicate +-#define mmSLOT_STATUS_BASE_IDX 0 +-#define mmSSID_CAP_LIST 0x0030 // duplicate +-#define mmSSID_CAP_LIST_BASE_IDX 0 +-#define mmSSID_CAP 0x0031 // duplicate +-#define mmSSID_CAP_BASE_IDX 0 +- +- +-// addressBlock: rcc_shadow_reg_shadowdec +-// base address: 0x0 +-#define ixSHADOW_COMMAND 0x0004 // duplicate +-#define ixSHADOW_BASE_ADDR_1 0x0010 // duplicate +-#define ixSHADOW_BASE_ADDR_2 0x0014 // duplicate +-#define ixSHADOW_SUB_BUS_NUMBER_LATENCY 0x0018 // duplicate +-#define ixSHADOW_IO_BASE_LIMIT 0x001c // duplicate +-#define ixSHADOW_MEM_BASE_LIMIT 0x0020 // duplicate +-#define ixSHADOW_PREF_BASE_LIMIT 0x0024 // duplicate +-#define ixSHADOW_PREF_BASE_UPPER 0x0028 // duplicate +-#define ixSHADOW_PREF_LIMIT_UPPER 0x002c // duplicate +-#define ixSHADOW_IO_BASE_LIMIT_HI 0x0030 // duplicate +-#define ixSHADOW_IRQ_BRIDGE_CNTL 0x003e // duplicate +-#define ixSUC_INDEX 0x00e0 // duplicate +-#define ixSUC_DATA 0x00e4 // duplicate +- +- +-// addressBlock: bif_bx_pf_SUMDEC +-// base address: 0x0 +-#define ixSUM_INDEX 0x00e0 // duplicate +-#define ixSUM_DATA 0x00e4 // duplicate +- +- +-// addressBlock: gdc_GDCDEC +-// base address: 0x1400000 +-#define mmA2S_CNTL_CL0 0x4f0ab0 // duplicate +-#define mmA2S_CNTL_CL0_BASE_IDX 3 +-#define mmA2S_CNTL_CL1 0x4f0ab1 // duplicate +-#define mmA2S_CNTL_CL1_BASE_IDX 3 +-#define mmA2S_CNTL_CL2 0x4f0ab2 // duplicate +-#define mmA2S_CNTL_CL2_BASE_IDX 3 +-#define mmA2S_CNTL_CL3 0x4f0ab3 // duplicate +-#define mmA2S_CNTL_CL3_BASE_IDX 3 +-#define mmA2S_CNTL_CL4 0x4f0ab4 // duplicate +-#define mmA2S_CNTL_CL4_BASE_IDX 3 +-#define mmA2S_CNTL_SW0 0x4f0ad0 // duplicate +-#define mmA2S_CNTL_SW0_BASE_IDX 3 +-#define mmA2S_CNTL_SW1 0x4f0ad1 // duplicate +-#define mmA2S_CNTL_SW1_BASE_IDX 3 +-#define mmA2S_CNTL_SW2 0x4f0ad2 // duplicate +-#define mmA2S_CNTL_SW2_BASE_IDX 3 +-#define mmNGDC_MGCG_CTRL 0x4f0ae0 // duplicate +-#define mmNGDC_MGCG_CTRL_BASE_IDX 3 +-#define mmA2S_MISC_CNTL 0x4f0ae1 // duplicate +-#define mmA2S_MISC_CNTL_BASE_IDX 3 +-#define mmNGDC_SDP_PORT_CTRL 0x4f0ae2 // duplicate +-#define mmNGDC_SDP_PORT_CTRL_BASE_IDX 3 +-#define mmNGDC_RESERVED_0 0x4f0aeb // duplicate +-#define mmNGDC_RESERVED_0_BASE_IDX 3 +-#define mmNGDC_RESERVED_1 0x4f0aec // duplicate +-#define mmNGDC_RESERVED_1_BASE_IDX 3 +-#define mmBIF_SDMA0_DOORBELL_RANGE 0x4f0af0 // duplicate +-#define mmBIF_SDMA0_DOORBELL_RANGE_BASE_IDX 3 +-#define mmBIF_SDMA1_DOORBELL_RANGE 0x4f0af1 // duplicate +-#define mmBIF_SDMA1_DOORBELL_RANGE_BASE_IDX 3 +-#define mmBIF_IH_DOORBELL_RANGE 0x4f0af2 // duplicate +-#define mmBIF_IH_DOORBELL_RANGE_BASE_IDX 3 +-#define mmBIF_MMSCH0_DOORBELL_RANGE 0x4f0af3 // duplicate +-#define mmBIF_MMSCH0_DOORBELL_RANGE_BASE_IDX 3 +-#define mmBIF_DOORBELL_FENCE_CNTL 0x4f0afe // duplicate +-#define mmBIF_DOORBELL_FENCE_CNTL_BASE_IDX 3 +-#define mmS2A_MISC_CNTL 0x4f0aff // duplicate +-#define mmS2A_MISC_CNTL_BASE_IDX 3 +-#define mmA2S_CNTL2_SEC_CL0 0x4f0b00 // duplicate +-#define mmA2S_CNTL2_SEC_CL0_BASE_IDX 3 +-#define mmA2S_CNTL2_SEC_CL1 0x4f0b01 // duplicate +-#define mmA2S_CNTL2_SEC_CL1_BASE_IDX 3 +-#define mmA2S_CNTL2_SEC_CL2 0x4f0b02 // duplicate +-#define mmA2S_CNTL2_SEC_CL2_BASE_IDX 3 +-#define mmA2S_CNTL2_SEC_CL3 0x4f0b03 // duplicate +-#define mmA2S_CNTL2_SEC_CL3_BASE_IDX 3 +-#define mmA2S_CNTL2_SEC_CL4 0x4f0b04 // duplicate +-#define mmA2S_CNTL2_SEC_CL4_BASE_IDX 3 +- +- +-// addressBlock: nbif_sion_SIONDEC +-// base address: 0x1400000 +-#define ixSION_CL0_RdRsp_BurstTarget_REG0 0x1e000 +-#define ixSION_CL0_RdRsp_BurstTarget_REG1 0x1e004 +-#define ixSION_CL0_RdRsp_TimeSlot_REG0 0x1e008 +-#define ixSION_CL0_RdRsp_TimeSlot_REG1 0x1e00c +-#define ixSION_CL0_WrRsp_BurstTarget_REG0 0x1e010 +-#define ixSION_CL0_WrRsp_BurstTarget_REG1 0x1e014 +-#define ixSION_CL0_WrRsp_TimeSlot_REG0 0x1e018 +-#define ixSION_CL0_WrRsp_TimeSlot_REG1 0x1e01c +-#define ixSION_CL0_Req_BurstTarget_REG0 0x1e020 +-#define ixSION_CL0_Req_BurstTarget_REG1 0x1e024 +-#define ixSION_CL0_Req_TimeSlot_REG0 0x1e028 +-#define ixSION_CL0_Req_TimeSlot_REG1 0x1e02c +-#define ixSION_CL0_ReqPoolCredit_Alloc_REG0 0x1e030 +-#define ixSION_CL0_ReqPoolCredit_Alloc_REG1 0x1e034 +-#define ixSION_CL0_DataPoolCredit_Alloc_REG0 0x1e038 +-#define ixSION_CL0_DataPoolCredit_Alloc_REG1 0x1e03c +-#define ixSION_CL0_RdRspPoolCredit_Alloc_REG0 0x1e040 +-#define ixSION_CL0_RdRspPoolCredit_Alloc_REG1 0x1e044 +-#define ixSION_CL0_WrRspPoolCredit_Alloc_REG0 0x1e048 +-#define ixSION_CL0_WrRspPoolCredit_Alloc_REG1 0x1e04c +-#define ixSION_CL1_RdRsp_BurstTarget_REG0 0x1e050 +-#define ixSION_CL1_RdRsp_BurstTarget_REG1 0x1e054 +-#define ixSION_CL1_RdRsp_TimeSlot_REG0 0x1e058 +-#define ixSION_CL1_RdRsp_TimeSlot_REG1 0x1e05c +-#define ixSION_CL1_WrRsp_BurstTarget_REG0 0x1e060 +-#define ixSION_CL1_WrRsp_BurstTarget_REG1 0x1e064 +-#define ixSION_CL1_WrRsp_TimeSlot_REG0 0x1e068 +-#define ixSION_CL1_WrRsp_TimeSlot_REG1 0x1e06c +-#define ixSION_CL1_Req_BurstTarget_REG0 0x1e070 +-#define ixSION_CL1_Req_BurstTarget_REG1 0x1e074 +-#define ixSION_CL1_Req_TimeSlot_REG0 0x1e078 +-#define ixSION_CL1_Req_TimeSlot_REG1 0x1e07c +-#define ixSION_CL1_ReqPoolCredit_Alloc_REG0 0x1e080 +-#define ixSION_CL1_ReqPoolCredit_Alloc_REG1 0x1e084 +-#define ixSION_CL1_DataPoolCredit_Alloc_REG0 0x1e088 +-#define ixSION_CL1_DataPoolCredit_Alloc_REG1 0x1e08c +-#define ixSION_CL1_RdRspPoolCredit_Alloc_REG0 0x1e090 +-#define ixSION_CL1_RdRspPoolCredit_Alloc_REG1 0x1e094 +-#define ixSION_CL1_WrRspPoolCredit_Alloc_REG0 0x1e098 +-#define ixSION_CL1_WrRspPoolCredit_Alloc_REG1 0x1e09c +-#define ixSION_CL2_RdRsp_BurstTarget_REG0 0x1e0a0 +-#define ixSION_CL2_RdRsp_BurstTarget_REG1 0x1e0a4 +-#define ixSION_CL2_RdRsp_TimeSlot_REG0 0x1e0a8 +-#define ixSION_CL2_RdRsp_TimeSlot_REG1 0x1e0ac +-#define ixSION_CL2_WrRsp_BurstTarget_REG0 0x1e0b0 +-#define ixSION_CL2_WrRsp_BurstTarget_REG1 0x1e0b4 +-#define ixSION_CL2_WrRsp_TimeSlot_REG0 0x1e0b8 +-#define ixSION_CL2_WrRsp_TimeSlot_REG1 0x1e0bc +-#define ixSION_CL2_Req_BurstTarget_REG0 0x1e0c0 +-#define ixSION_CL2_Req_BurstTarget_REG1 0x1e0c4 +-#define ixSION_CL2_Req_TimeSlot_REG0 0x1e0c8 +-#define ixSION_CL2_Req_TimeSlot_REG1 0x1e0cc +-#define ixSION_CL2_ReqPoolCredit_Alloc_REG0 0x1e0d0 +-#define ixSION_CL2_ReqPoolCredit_Alloc_REG1 0x1e0d4 +-#define ixSION_CL2_DataPoolCredit_Alloc_REG0 0x1e0d8 +-#define ixSION_CL2_DataPoolCredit_Alloc_REG1 0x1e0dc +-#define ixSION_CL2_RdRspPoolCredit_Alloc_REG0 0x1e0e0 +-#define ixSION_CL2_RdRspPoolCredit_Alloc_REG1 0x1e0e4 +-#define ixSION_CL2_WrRspPoolCredit_Alloc_REG0 0x1e0e8 +-#define ixSION_CL2_WrRspPoolCredit_Alloc_REG1 0x1e0ec +-#define ixSION_CL3_RdRsp_BurstTarget_REG0 0x1e0f0 +-#define ixSION_CL3_RdRsp_BurstTarget_REG1 0x1e0f4 +-#define ixSION_CL3_RdRsp_TimeSlot_REG0 0x1e0f8 +-#define ixSION_CL3_RdRsp_TimeSlot_REG1 0x1e0fc +-#define ixSION_CL3_WrRsp_BurstTarget_REG0 0x1e100 +-#define ixSION_CL3_WrRsp_BurstTarget_REG1 0x1e104 +-#define ixSION_CL3_WrRsp_TimeSlot_REG0 0x1e108 +-#define ixSION_CL3_WrRsp_TimeSlot_REG1 0x1e10c +-#define ixSION_CL3_Req_BurstTarget_REG0 0x1e110 +-#define ixSION_CL3_Req_BurstTarget_REG1 0x1e114 +-#define ixSION_CL3_Req_TimeSlot_REG0 0x1e118 +-#define ixSION_CL3_Req_TimeSlot_REG1 0x1e11c +-#define ixSION_CL3_ReqPoolCredit_Alloc_REG0 0x1e120 +-#define ixSION_CL3_ReqPoolCredit_Alloc_REG1 0x1e124 +-#define ixSION_CL3_DataPoolCredit_Alloc_REG0 0x1e128 +-#define ixSION_CL3_DataPoolCredit_Alloc_REG1 0x1e12c +-#define ixSION_CL3_RdRspPoolCredit_Alloc_REG0 0x1e130 +-#define ixSION_CL3_RdRspPoolCredit_Alloc_REG1 0x1e134 +-#define ixSION_CL3_WrRspPoolCredit_Alloc_REG0 0x1e138 +-#define ixSION_CL3_WrRspPoolCredit_Alloc_REG1 0x1e13c +-#define ixSION_CL4_RdRsp_BurstTarget_REG0 0x1e140 +-#define ixSION_CL4_RdRsp_BurstTarget_REG1 0x1e144 +-#define ixSION_CL4_RdRsp_TimeSlot_REG0 0x1e148 +-#define ixSION_CL4_RdRsp_TimeSlot_REG1 0x1e14c +-#define ixSION_CL4_WrRsp_BurstTarget_REG0 0x1e150 +-#define ixSION_CL4_WrRsp_BurstTarget_REG1 0x1e154 +-#define ixSION_CL4_WrRsp_TimeSlot_REG0 0x1e158 +-#define ixSION_CL4_WrRsp_TimeSlot_REG1 0x1e15c +-#define ixSION_CL4_Req_BurstTarget_REG0 0x1e160 +-#define ixSION_CL4_Req_BurstTarget_REG1 0x1e164 +-#define ixSION_CL4_Req_TimeSlot_REG0 0x1e168 +-#define ixSION_CL4_Req_TimeSlot_REG1 0x1e16c +-#define ixSION_CL4_ReqPoolCredit_Alloc_REG0 0x1e170 +-#define ixSION_CL4_ReqPoolCredit_Alloc_REG1 0x1e174 +-#define ixSION_CL4_DataPoolCredit_Alloc_REG0 0x1e178 +-#define ixSION_CL4_DataPoolCredit_Alloc_REG1 0x1e17c +-#define ixSION_CL4_RdRspPoolCredit_Alloc_REG0 0x1e180 +-#define ixSION_CL4_RdRspPoolCredit_Alloc_REG1 0x1e184 +-#define ixSION_CL4_WrRspPoolCredit_Alloc_REG0 0x1e188 +-#define ixSION_CL4_WrRspPoolCredit_Alloc_REG1 0x1e18c +-#define ixSION_CL5_RdRsp_BurstTarget_REG0 0x1e190 +-#define ixSION_CL5_RdRsp_BurstTarget_REG1 0x1e194 +-#define ixSION_CL5_RdRsp_TimeSlot_REG0 0x1e198 +-#define ixSION_CL5_RdRsp_TimeSlot_REG1 0x1e19c +-#define ixSION_CL5_WrRsp_BurstTarget_REG0 0x1e1a0 +-#define ixSION_CL5_WrRsp_BurstTarget_REG1 0x1e1a4 +-#define ixSION_CL5_WrRsp_TimeSlot_REG0 0x1e1a8 +-#define ixSION_CL5_WrRsp_TimeSlot_REG1 0x1e1ac +-#define ixSION_CL5_Req_BurstTarget_REG0 0x1e1b0 +-#define ixSION_CL5_Req_BurstTarget_REG1 0x1e1b4 +-#define ixSION_CL5_Req_TimeSlot_REG0 0x1e1b8 +-#define ixSION_CL5_Req_TimeSlot_REG1 0x1e1bc +-#define ixSION_CL5_ReqPoolCredit_Alloc_REG0 0x1e1c0 +-#define ixSION_CL5_ReqPoolCredit_Alloc_REG1 0x1e1c4 +-#define ixSION_CL5_DataPoolCredit_Alloc_REG0 0x1e1c8 +-#define ixSION_CL5_DataPoolCredit_Alloc_REG1 0x1e1cc +-#define ixSION_CL5_RdRspPoolCredit_Alloc_REG0 0x1e1d0 +-#define ixSION_CL5_RdRspPoolCredit_Alloc_REG1 0x1e1d4 +-#define ixSION_CL5_WrRspPoolCredit_Alloc_REG0 0x1e1d8 +-#define ixSION_CL5_WrRspPoolCredit_Alloc_REG1 0x1e1dc +-#define ixSION_CNTL_REG0 0x1e1e0 +-#define ixSION_CNTL_REG1 0x1e1e4 +- +- +-// addressBlock: syshub_mmreg_direct_syshubdirect +-// base address: 0x1400000 +-#define ixSYSHUB_DS_CTRL_SOCCLK 0x10000 // duplicate +-#define ixSYSHUB_DS_CTRL2_SOCCLK 0x10004 // duplicate +-#define ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK 0x10008 // duplicate +-#define ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK 0x1000c // duplicate +-#define ixDMA_CLK0_SW0_SYSHUB_QOS_CNTL 0x10010 // duplicate +-#define ixDMA_CLK0_SW1_SYSHUB_QOS_CNTL 0x10014 // duplicate +-#define ixDMA_CLK0_SW0_CL0_CNTL 0x10018 // duplicate +-#define ixDMA_CLK0_SW0_CL1_CNTL 0x1001c // duplicate +-#define ixDMA_CLK0_SW0_CL2_CNTL 0x10020 // duplicate +-#define ixDMA_CLK0_SW0_CL3_CNTL 0x10024 // duplicate +-#define ixDMA_CLK0_SW0_CL4_CNTL 0x10028 // duplicate +-#define ixDMA_CLK0_SW0_CL5_CNTL 0x1002c // duplicate +-#define ixDMA_CLK0_SW1_CL0_CNTL 0x10030 // duplicate +-#define ixDMA_CLK0_SW2_CL0_CNTL 0x10034 // duplicate +-#define ixSYSHUB_CG_CNTL 0x10300 // duplicate +-#define ixSYSHUB_TRANS_IDLE 0x10308 // duplicate +-#define ixSYSHUB_HP_TIMER 0x1030c // duplicate +-#define ixSYSHUB_SCRATCH 0x10f00 // duplicate +-#define ixSYSHUB_DS_CTRL_SHUBCLK 0x11000 // duplicate +-#define ixSYSHUB_DS_CTRL2_SHUBCLK 0x11004 // duplicate +-#define ixSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK 0x11008 // duplicate +-#define ixSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK 0x1100c // duplicate +-#define ixDMA_CLK1_SW0_SYSHUB_QOS_CNTL 0x11010 // duplicate +-#define ixDMA_CLK1_SW1_SYSHUB_QOS_CNTL 0x11014 // duplicate +-#define ixDMA_CLK1_SW0_CL0_CNTL 0x11018 // duplicate +-#define ixDMA_CLK1_SW0_CL1_CNTL 0x1101c // duplicate +-#define ixDMA_CLK1_SW0_CL2_CNTL 0x11020 // duplicate +-#define ixDMA_CLK1_SW0_CL3_CNTL 0x11024 // duplicate +-#define ixDMA_CLK1_SW0_CL4_CNTL 0x11028 // duplicate +-#define ixDMA_CLK1_SW1_CL0_CNTL 0x1102c // duplicate +-#define ixDMA_CLK1_SW1_CL1_CNTL 0x11030 // duplicate +-#define ixDMA_CLK1_SW1_CL2_CNTL 0x11034 // duplicate +-#define ixDMA_CLK1_SW1_CL3_CNTL 0x11038 // duplicate +-#define ixDMA_CLK1_SW1_CL4_CNTL 0x1103c // duplicate +- +- +-// addressBlock: gdc_ras_gdc_ras_regblk +-// base address: 0x1400000 +-#define ixGDC_RAS_LEAF0_CTRL 0x1f800 +-#define ixGDC_RAS_LEAF1_CTRL 0x1f804 +-#define ixGDC_RAS_LEAF2_CTRL 0x1f808 +-#define ixGDC_RAS_LEAF3_CTRL 0x1f80c +-#define ixGDC_RAS_LEAF4_CTRL 0x1f810 +-#define ixGDC_RAS_LEAF5_CTRL 0x1f814 +- +- +-// addressBlock: gdc_rst_GDCRST_DEC +-// base address: 0x1400000 +-#define ixSHUB_PF_FLR_RST 0x1f000 +-#define ixSHUB_GFX_DRV_MODE1_RST 0x1f004 +-#define ixSHUB_LINK_RESET 0x1f008 +-#define ixSHUB_PF0_VF_FLR_RST 0x1f020 +-#define ixSHUB_HARD_RST_CTRL 0x1f040 +-#define ixSHUB_SOFT_RST_CTRL 0x1f044 +-#define ixSHUB_SDP_PORT_RST 0x1f048 +- +- +-// memoryMap:EP0F0Reg +- +- +-// addressBlock: bif_bx_pf_SYSDEC +-// base address: 0x0 +-#define mmSBIOS_SCRATCH_0 0x0048 // duplicate +-#define mmSBIOS_SCRATCH_0_BASE_IDX 0 +-#define mmSBIOS_SCRATCH_1 0x0049 // duplicate +-#define mmSBIOS_SCRATCH_1_BASE_IDX 0 +-#define mmSBIOS_SCRATCH_2 0x004a // duplicate +-#define mmSBIOS_SCRATCH_2_BASE_IDX 0 +-#define mmSBIOS_SCRATCH_3 0x004b // duplicate +-#define mmSBIOS_SCRATCH_3_BASE_IDX 0 +-#define mmBIOS_SCRATCH_0 0x004c // duplicate +-#define mmBIOS_SCRATCH_0_BASE_IDX 0 +-#define mmBIOS_SCRATCH_1 0x004d // duplicate +-#define mmBIOS_SCRATCH_1_BASE_IDX 0 +-#define mmBIOS_SCRATCH_2 0x004e // duplicate +-#define mmBIOS_SCRATCH_2_BASE_IDX 0 +-#define mmBIOS_SCRATCH_3 0x004f // duplicate +-#define mmBIOS_SCRATCH_3_BASE_IDX 0 +-#define mmBIOS_SCRATCH_4 0x0050 // duplicate +-#define mmBIOS_SCRATCH_4_BASE_IDX 0 +-#define mmBIOS_SCRATCH_5 0x0051 // duplicate +-#define mmBIOS_SCRATCH_5_BASE_IDX 0 +-#define mmBIOS_SCRATCH_6 0x0052 // duplicate +-#define mmBIOS_SCRATCH_6_BASE_IDX 0 +-#define mmBIOS_SCRATCH_7 0x0053 // duplicate +-#define mmBIOS_SCRATCH_7_BASE_IDX 0 +-#define mmBIOS_SCRATCH_8 0x0054 // duplicate +-#define mmBIOS_SCRATCH_8_BASE_IDX 0 +-#define mmBIOS_SCRATCH_9 0x0055 // duplicate +-#define mmBIOS_SCRATCH_9_BASE_IDX 0 +-#define mmBIOS_SCRATCH_10 0x0056 // duplicate +-#define mmBIOS_SCRATCH_10_BASE_IDX 0 +-#define mmBIOS_SCRATCH_11 0x0057 // duplicate +-#define mmBIOS_SCRATCH_11_BASE_IDX 0 +-#define mmBIOS_SCRATCH_12 0x0058 // duplicate +-#define mmBIOS_SCRATCH_12_BASE_IDX 0 +-#define mmBIOS_SCRATCH_13 0x0059 // duplicate +-#define mmBIOS_SCRATCH_13_BASE_IDX 0 +-#define mmBIOS_SCRATCH_14 0x005a // duplicate +-#define mmBIOS_SCRATCH_14_BASE_IDX 0 +-#define mmBIOS_SCRATCH_15 0x005b // duplicate +-#define mmBIOS_SCRATCH_15_BASE_IDX 0 +-#define mmBIF_RLC_INTR_CNTL 0x0060 // duplicate +-#define mmBIF_RLC_INTR_CNTL_BASE_IDX 0 +-#define mmBIF_VCE_INTR_CNTL 0x0061 // duplicate +-#define mmBIF_VCE_INTR_CNTL_BASE_IDX 0 +-#define mmBIF_UVD_INTR_CNTL 0x0062 // duplicate +-#define mmBIF_UVD_INTR_CNTL_BASE_IDX 0 +-#define mmGFX_MMIOREG_CAM_ADDR0 0x0080 // duplicate +-#define mmGFX_MMIOREG_CAM_ADDR0_BASE_IDX 0 +-#define mmGFX_MMIOREG_CAM_REMAP_ADDR0 0x0081 // duplicate +-#define mmGFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 0 +-#define mmGFX_MMIOREG_CAM_ADDR1 0x0082 // duplicate +-#define mmGFX_MMIOREG_CAM_ADDR1_BASE_IDX 0 +-#define mmGFX_MMIOREG_CAM_REMAP_ADDR1 0x0083 // duplicate +-#define mmGFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 0 +-#define mmGFX_MMIOREG_CAM_ADDR2 0x0084 // duplicate +-#define mmGFX_MMIOREG_CAM_ADDR2_BASE_IDX 0 +-#define mmGFX_MMIOREG_CAM_REMAP_ADDR2 0x0085 // duplicate +-#define mmGFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 0 +-#define mmGFX_MMIOREG_CAM_ADDR3 0x0086 // duplicate +-#define mmGFX_MMIOREG_CAM_ADDR3_BASE_IDX 0 +-#define mmGFX_MMIOREG_CAM_REMAP_ADDR3 0x0087 // duplicate +-#define mmGFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 0 +-#define mmGFX_MMIOREG_CAM_ADDR4 0x0088 // duplicate +-#define mmGFX_MMIOREG_CAM_ADDR4_BASE_IDX 0 +-#define mmGFX_MMIOREG_CAM_REMAP_ADDR4 0x0089 // duplicate +-#define mmGFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 0 +-#define mmGFX_MMIOREG_CAM_ADDR5 0x008a // duplicate +-#define mmGFX_MMIOREG_CAM_ADDR5_BASE_IDX 0 +-#define mmGFX_MMIOREG_CAM_REMAP_ADDR5 0x008b // duplicate +-#define mmGFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 0 +-#define mmGFX_MMIOREG_CAM_ADDR6 0x008c // duplicate +-#define mmGFX_MMIOREG_CAM_ADDR6_BASE_IDX 0 +-#define mmGFX_MMIOREG_CAM_REMAP_ADDR6 0x008d // duplicate +-#define mmGFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 0 +-#define mmGFX_MMIOREG_CAM_ADDR7 0x008e // duplicate +-#define mmGFX_MMIOREG_CAM_ADDR7_BASE_IDX 0 +-#define mmGFX_MMIOREG_CAM_REMAP_ADDR7 0x008f // duplicate +-#define mmGFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 0 +-#define mmGFX_MMIOREG_CAM_CNTL 0x0090 // duplicate +-#define mmGFX_MMIOREG_CAM_CNTL_BASE_IDX 0 +-#define mmGFX_MMIOREG_CAM_ZERO_CPL 0x0091 // duplicate +-#define mmGFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 0 +-#define mmGFX_MMIOREG_CAM_ONE_CPL 0x0092 // duplicate +-#define mmGFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 0 +-#define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x0093 // duplicate +-#define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 0 +- +- +-// addressBlock: bif_bx_pf_SYSPFVFDEC +-// base address: 0x0 +-#define mmMM_INDEX 0x0000 // duplicate +-#define mmMM_INDEX_BASE_IDX 0 +-#define mmMM_DATA 0x0001 // duplicate +-#define mmMM_DATA_BASE_IDX 0 +-#define mmMM_INDEX_HI 0x0006 // duplicate +-#define mmMM_INDEX_HI_BASE_IDX 0 +-#define mmSYSHUB_INDEX_OVLP 0x0008 // duplicate +-#define mmSYSHUB_INDEX_OVLP_BASE_IDX 0 +-#define mmSYSHUB_DATA_OVLP 0x0009 // duplicate +-#define mmSYSHUB_DATA_OVLP_BASE_IDX 0 +-#define mmPCIE_INDEX 0x000c // duplicate +-#define mmPCIE_INDEX_BASE_IDX 0 +-#define mmPCIE_DATA 0x000d // duplicate +-#define mmPCIE_DATA_BASE_IDX 0 +-#define mmPCIE_INDEX2 0x000e // duplicate +-#define mmPCIE_INDEX2_BASE_IDX 0 +-#define mmPCIE_DATA2 0x000f // duplicate +-#define mmPCIE_DATA2_BASE_IDX 0 +- +- +-// addressBlock: rcc_dwn_BIFDEC1 +-// base address: 0x0 +-#define mmDN_PCIE_RESERVED 0x0d60 // duplicate +-#define mmDN_PCIE_RESERVED_BASE_IDX 0 +-#define mmDN_PCIE_SCRATCH 0x0d61 // duplicate +-#define mmDN_PCIE_SCRATCH_BASE_IDX 0 +-#define mmDN_PCIE_CNTL 0x0d63 // duplicate +-#define mmDN_PCIE_CNTL_BASE_IDX 0 +-#define mmDN_PCIE_CONFIG_CNTL 0x0d64 // duplicate +-#define mmDN_PCIE_CONFIG_CNTL_BASE_IDX 0 +-#define mmDN_PCIE_RX_CNTL2 0x0d65 // duplicate +-#define mmDN_PCIE_RX_CNTL2_BASE_IDX 0 +-#define mmDN_PCIE_BUS_CNTL 0x0d66 // duplicate +-#define mmDN_PCIE_BUS_CNTL_BASE_IDX 0 +-#define mmDN_PCIE_CFG_CNTL 0x0d67 // duplicate +-#define mmDN_PCIE_CFG_CNTL_BASE_IDX 0 +-#define mmDN_PCIE_STRAP_F0 0x0d68 // duplicate +-#define mmDN_PCIE_STRAP_F0_BASE_IDX 0 +-#define mmDN_PCIE_STRAP_MISC 0x0d69 // duplicate +-#define mmDN_PCIE_STRAP_MISC_BASE_IDX 0 +-#define mmDN_PCIE_STRAP_MISC2 0x0d6a // duplicate +-#define mmDN_PCIE_STRAP_MISC2_BASE_IDX 0 +- +- +-// addressBlock: rcc_dwnp_BIFDEC1 +-// base address: 0x0 +-#define mmPCIEP_RESERVED 0x0d6c // duplicate +-#define mmPCIEP_RESERVED_BASE_IDX 0 +-#define mmPCIEP_SCRATCH 0x0d6d // duplicate +-#define mmPCIEP_SCRATCH_BASE_IDX 0 +-#define mmPCIE_ERR_CNTL 0x0d6f // duplicate +-#define mmPCIE_ERR_CNTL_BASE_IDX 0 +-#define mmPCIE_RX_CNTL 0x0d70 // duplicate +-#define mmPCIE_RX_CNTL_BASE_IDX 0 +-#define mmPCIE_LC_SPEED_CNTL 0x0d71 // duplicate +-#define mmPCIE_LC_SPEED_CNTL_BASE_IDX 0 +-#define mmPCIE_LC_CNTL2 0x0d72 // duplicate +-#define mmPCIE_LC_CNTL2_BASE_IDX 0 +-#define mmPCIEP_STRAP_MISC 0x0d73 // duplicate +-#define mmPCIEP_STRAP_MISC_BASE_IDX 0 +-#define mmLTR_MSG_INFO_FROM_EP 0x0d74 // duplicate +-#define mmLTR_MSG_INFO_FROM_EP_BASE_IDX 0 +- +- +-// addressBlock: rcc_ep_BIFDEC1 +-// base address: 0x0 +-#define mmEP_PCIE_SCRATCH 0x0d43 // duplicate +-#define mmEP_PCIE_SCRATCH_BASE_IDX 0 +-#define mmEP_PCIE_CNTL 0x0d45 // duplicate +-#define mmEP_PCIE_CNTL_BASE_IDX 0 +-#define mmEP_PCIE_INT_CNTL 0x0d46 // duplicate +-#define mmEP_PCIE_INT_CNTL_BASE_IDX 0 +-#define mmEP_PCIE_INT_STATUS 0x0d47 // duplicate +-#define mmEP_PCIE_INT_STATUS_BASE_IDX 0 +-#define mmEP_PCIE_RX_CNTL2 0x0d48 // duplicate +-#define mmEP_PCIE_RX_CNTL2_BASE_IDX 0 +-#define mmEP_PCIE_BUS_CNTL 0x0d49 // duplicate +-#define mmEP_PCIE_BUS_CNTL_BASE_IDX 0 +-#define mmEP_PCIE_CFG_CNTL 0x0d4a // duplicate +-#define mmEP_PCIE_CFG_CNTL_BASE_IDX 0 +-#define mmEP_PCIE_OBFF_CNTL 0x0d4b // duplicate +-#define mmEP_PCIE_OBFF_CNTL_BASE_IDX 0 +-#define mmEP_PCIE_TX_LTR_CNTL 0x0d4c // duplicate +-#define mmEP_PCIE_TX_LTR_CNTL_BASE_IDX 0 +-#define mmEP_PCIE_STRAP_MISC 0x0d4f // duplicate +-#define mmEP_PCIE_STRAP_MISC_BASE_IDX 0 +-#define mmEP_PCIE_STRAP_MISC2 0x0d50 // duplicate +-#define mmEP_PCIE_STRAP_MISC2_BASE_IDX 0 +-#define mmEP_PCIE_STRAP_PI 0x0d51 // duplicate +-#define mmEP_PCIE_STRAP_PI_BASE_IDX 0 +-#define mmEP_PCIE_F0_DPA_CAP 0x0d52 // duplicate +-#define mmEP_PCIE_F0_DPA_CAP_BASE_IDX 0 +-#define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR 0x0d53 // duplicate +-#define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 0 +-#define mmEP_PCIE_F0_DPA_CNTL 0x0d53 // duplicate +-#define mmEP_PCIE_F0_DPA_CNTL_BASE_IDX 0 +-#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x0d53 // duplicate +-#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 0 +-#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x0d54 // duplicate +-#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 0 +-#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x0d54 // duplicate +-#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 0 +-#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x0d54 // duplicate +-#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 0 +-#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x0d54 // duplicate +-#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 0 +-#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x0d55 // duplicate +-#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 0 +-#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x0d55 // duplicate +-#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 0 +-#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x0d55 // duplicate +-#define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 0 +-#define mmEP_PCIE_PME_CONTROL 0x0d55 // duplicate +-#define mmEP_PCIE_PME_CONTROL_BASE_IDX 0 +-#define mmEP_PCIEP_RESERVED 0x0d56 // duplicate +-#define mmEP_PCIEP_RESERVED_BASE_IDX 0 +-#define mmEP_PCIE_TX_CNTL 0x0d58 // duplicate +-#define mmEP_PCIE_TX_CNTL_BASE_IDX 0 +-#define mmEP_PCIE_TX_REQUESTER_ID 0x0d59 // duplicate +-#define mmEP_PCIE_TX_REQUESTER_ID_BASE_IDX 0 +-#define mmEP_PCIE_ERR_CNTL 0x0d5a // duplicate +-#define mmEP_PCIE_ERR_CNTL_BASE_IDX 0 +-#define mmEP_PCIE_RX_CNTL 0x0d5b // duplicate +-#define mmEP_PCIE_RX_CNTL_BASE_IDX 0 +-#define mmEP_PCIE_LC_SPEED_CNTL 0x0d5c // duplicate +-#define mmEP_PCIE_LC_SPEED_CNTL_BASE_IDX 0 +- +- +-// addressBlock: bif_bx_pf_BIFDEC1 +-// base address: 0x0 +-#define mmBIF_MM_INDACCESS_CNTL 0x0e06 // duplicate +-#define mmBIF_MM_INDACCESS_CNTL_BASE_IDX 0 +-#define mmBUS_CNTL 0x0e07 // duplicate +-#define mmBUS_CNTL_BASE_IDX 0 +-#define mmBIF_SCRATCH0 0x0e08 // duplicate +-#define mmBIF_SCRATCH0_BASE_IDX 0 +-#define mmBIF_SCRATCH1 0x0e09 // duplicate +-#define mmBIF_SCRATCH1_BASE_IDX 0 +-#define mmBX_RESET_EN 0x0e0d // duplicate +-#define mmBX_RESET_EN_BASE_IDX 0 +-#define mmMM_CFGREGS_CNTL 0x0e0e // duplicate +-#define mmMM_CFGREGS_CNTL_BASE_IDX 0 +-#define mmBX_RESET_CNTL 0x0e10 // duplicate +-#define mmBX_RESET_CNTL_BASE_IDX 0 +-#define mmINTERRUPT_CNTL 0x0e11 // duplicate +-#define mmINTERRUPT_CNTL_BASE_IDX 0 +-#define mmINTERRUPT_CNTL2 0x0e12 // duplicate +-#define mmINTERRUPT_CNTL2_BASE_IDX 0 +-#define mmCLKREQB_PAD_CNTL 0x0e18 // duplicate +-#define mmCLKREQB_PAD_CNTL_BASE_IDX 0 +-#define mmCLKREQB_PERF_COUNTER 0x0e19 // duplicate +-#define mmCLKREQB_PERF_COUNTER_BASE_IDX 0 +-#define mmBIF_CLK_CTRL 0x0e1a // duplicate +-#define mmBIF_CLK_CTRL_BASE_IDX 0 +-#define mmBIF_FEATURES_CONTROL_MISC 0x0e1b // duplicate +-#define mmBIF_FEATURES_CONTROL_MISC_BASE_IDX 0 +-#define mmBIF_DOORBELL_CNTL 0x0e1c // duplicate +-#define mmBIF_DOORBELL_CNTL_BASE_IDX 0 +-#define mmBIF_DOORBELL_INT_CNTL 0x0e1d // duplicate +-#define mmBIF_DOORBELL_INT_CNTL_BASE_IDX 0 +-#define mmBIF_SLVARB_MODE 0x0e1e // duplicate +-#define mmBIF_SLVARB_MODE_BASE_IDX 0 +-#define mmBIF_FB_EN 0x0e1f // duplicate +-#define mmBIF_FB_EN_BASE_IDX 0 +-#define mmBIF_BUSY_DELAY_CNTR 0x0e20 // duplicate +-#define mmBIF_BUSY_DELAY_CNTR_BASE_IDX 0 +-#define mmBIF_PERFMON_CNTL 0x0e21 // duplicate +-#define mmBIF_PERFMON_CNTL_BASE_IDX 0 +-#define mmBIF_PERFCOUNTER0_RESULT 0x0e22 // duplicate +-#define mmBIF_PERFCOUNTER0_RESULT_BASE_IDX 0 +-#define mmBIF_PERFCOUNTER1_RESULT 0x0e23 // duplicate +-#define mmBIF_PERFCOUNTER1_RESULT_BASE_IDX 0 +-#define mmBIF_MST_TRANS_PENDING_VF 0x0e29 // duplicate +-#define mmBIF_MST_TRANS_PENDING_VF_BASE_IDX 0 +-#define mmBIF_SLV_TRANS_PENDING_VF 0x0e2a // duplicate +-#define mmBIF_SLV_TRANS_PENDING_VF_BASE_IDX 0 +-#define mmBACO_CNTL 0x0e2b // duplicate +-#define mmBACO_CNTL_BASE_IDX 0 +-#define mmBIF_BACO_EXIT_TIME0 0x0e2c // duplicate +-#define mmBIF_BACO_EXIT_TIME0_BASE_IDX 0 +-#define mmBIF_BACO_EXIT_TIMER1 0x0e2d // duplicate +-#define mmBIF_BACO_EXIT_TIMER1_BASE_IDX 0 +-#define mmBIF_BACO_EXIT_TIMER2 0x0e2e // duplicate +-#define mmBIF_BACO_EXIT_TIMER2_BASE_IDX 0 +-#define mmBIF_BACO_EXIT_TIMER3 0x0e2f // duplicate +-#define mmBIF_BACO_EXIT_TIMER3_BASE_IDX 0 +-#define mmBIF_BACO_EXIT_TIMER4 0x0e30 // duplicate +-#define mmBIF_BACO_EXIT_TIMER4_BASE_IDX 0 +-#define mmMEM_TYPE_CNTL 0x0e31 // duplicate +-#define mmMEM_TYPE_CNTL_BASE_IDX 0 +-#define mmSMU_BIF_VDDGFX_PWR_STATUS 0x0e33 // duplicate +-#define mmSMU_BIF_VDDGFX_PWR_STATUS_BASE_IDX 0 +-#define mmBIF_VDDGFX_GFX0_LOWER 0x0e34 // duplicate +-#define mmBIF_VDDGFX_GFX0_LOWER_BASE_IDX 0 +-#define mmBIF_VDDGFX_GFX0_UPPER 0x0e35 // duplicate +-#define mmBIF_VDDGFX_GFX0_UPPER_BASE_IDX 0 +-#define mmBIF_VDDGFX_GFX1_LOWER 0x0e36 // duplicate +-#define mmBIF_VDDGFX_GFX1_LOWER_BASE_IDX 0 +-#define mmBIF_VDDGFX_GFX1_UPPER 0x0e37 // duplicate +-#define mmBIF_VDDGFX_GFX1_UPPER_BASE_IDX 0 +-#define mmBIF_VDDGFX_GFX2_LOWER 0x0e38 // duplicate +-#define mmBIF_VDDGFX_GFX2_LOWER_BASE_IDX 0 +-#define mmBIF_VDDGFX_GFX2_UPPER 0x0e39 // duplicate +-#define mmBIF_VDDGFX_GFX2_UPPER_BASE_IDX 0 +-#define mmBIF_VDDGFX_GFX3_LOWER 0x0e3a // duplicate +-#define mmBIF_VDDGFX_GFX3_LOWER_BASE_IDX 0 +-#define mmBIF_VDDGFX_GFX3_UPPER 0x0e3b // duplicate +-#define mmBIF_VDDGFX_GFX3_UPPER_BASE_IDX 0 +-#define mmBIF_VDDGFX_GFX4_LOWER 0x0e3c // duplicate +-#define mmBIF_VDDGFX_GFX4_LOWER_BASE_IDX 0 +-#define mmBIF_VDDGFX_GFX4_UPPER 0x0e3d // duplicate +-#define mmBIF_VDDGFX_GFX4_UPPER_BASE_IDX 0 +-#define mmBIF_VDDGFX_GFX5_LOWER 0x0e3e // duplicate +-#define mmBIF_VDDGFX_GFX5_LOWER_BASE_IDX 0 +-#define mmBIF_VDDGFX_GFX5_UPPER 0x0e3f // duplicate +-#define mmBIF_VDDGFX_GFX5_UPPER_BASE_IDX 0 +-#define mmBIF_VDDGFX_RSV1_LOWER 0x0e40 // duplicate +-#define mmBIF_VDDGFX_RSV1_LOWER_BASE_IDX 0 +-#define mmBIF_VDDGFX_RSV1_UPPER 0x0e41 // duplicate +-#define mmBIF_VDDGFX_RSV1_UPPER_BASE_IDX 0 +-#define mmBIF_VDDGFX_RSV2_LOWER 0x0e42 // duplicate +-#define mmBIF_VDDGFX_RSV2_LOWER_BASE_IDX 0 +-#define mmBIF_VDDGFX_RSV2_UPPER 0x0e43 // duplicate +-#define mmBIF_VDDGFX_RSV2_UPPER_BASE_IDX 0 +-#define mmBIF_VDDGFX_RSV3_LOWER 0x0e44 // duplicate +-#define mmBIF_VDDGFX_RSV3_LOWER_BASE_IDX 0 +-#define mmBIF_VDDGFX_RSV3_UPPER 0x0e45 // duplicate +-#define mmBIF_VDDGFX_RSV3_UPPER_BASE_IDX 0 +-#define mmBIF_VDDGFX_RSV4_LOWER 0x0e46 // duplicate +-#define mmBIF_VDDGFX_RSV4_LOWER_BASE_IDX 0 +-#define mmBIF_VDDGFX_RSV4_UPPER 0x0e47 // duplicate +-#define mmBIF_VDDGFX_RSV4_UPPER_BASE_IDX 0 +-#define mmBIF_VDDGFX_FB_CMP 0x0e48 // duplicate +-#define mmBIF_VDDGFX_FB_CMP_BASE_IDX 0 +-#define mmBIF_DOORBELL_GBLAPER1_LOWER 0x0e49 // duplicate +-#define mmBIF_DOORBELL_GBLAPER1_LOWER_BASE_IDX 0 +-#define mmBIF_DOORBELL_GBLAPER1_UPPER 0x0e4a // duplicate +-#define mmBIF_DOORBELL_GBLAPER1_UPPER_BASE_IDX 0 +-#define mmBIF_DOORBELL_GBLAPER2_LOWER 0x0e4b // duplicate +-#define mmBIF_DOORBELL_GBLAPER2_LOWER_BASE_IDX 0 +-#define mmBIF_DOORBELL_GBLAPER2_UPPER 0x0e4c // duplicate +-#define mmBIF_DOORBELL_GBLAPER2_UPPER_BASE_IDX 0 +-#define mmREMAP_HDP_MEM_FLUSH_CNTL 0x0e4d // duplicate +-#define mmREMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 0 +-#define mmREMAP_HDP_REG_FLUSH_CNTL 0x0e4e // duplicate +-#define mmREMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 0 +-#define mmBIF_RB_CNTL 0x0e4f // duplicate +-#define mmBIF_RB_CNTL_BASE_IDX 0 +-#define mmBIF_RB_BASE 0x0e50 // duplicate +-#define mmBIF_RB_BASE_BASE_IDX 0 +-#define mmBIF_RB_RPTR 0x0e51 // duplicate +-#define mmBIF_RB_RPTR_BASE_IDX 0 +-#define mmBIF_RB_WPTR 0x0e52 // duplicate +-#define mmBIF_RB_WPTR_BASE_IDX 0 +-#define mmBIF_RB_WPTR_ADDR_HI 0x0e53 // duplicate +-#define mmBIF_RB_WPTR_ADDR_HI_BASE_IDX 0 +-#define mmBIF_RB_WPTR_ADDR_LO 0x0e54 // duplicate +-#define mmBIF_RB_WPTR_ADDR_LO_BASE_IDX 0 +-#define mmMAILBOX_INDEX 0x0e55 // duplicate +-#define mmMAILBOX_INDEX_BASE_IDX 0 +-#define mmBIF_GPUIOV_RESET_NOTIFICATION 0x0e62 // duplicate +-#define mmBIF_GPUIOV_RESET_NOTIFICATION_BASE_IDX 0 +-#define mmBIF_UVD_GPUIOV_CFG_SIZE 0x0e63 // duplicate +-#define mmBIF_UVD_GPUIOV_CFG_SIZE_BASE_IDX 0 +-#define mmBIF_VCE_GPUIOV_CFG_SIZE 0x0e64 // duplicate +-#define mmBIF_VCE_GPUIOV_CFG_SIZE_BASE_IDX 0 +-#define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE 0x0e65 // duplicate +-#define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE_BASE_IDX 0 +-#define mmBIF_GMI_WRR_WEIGHT 0x0e66 // duplicate +-#define mmBIF_GMI_WRR_WEIGHT_BASE_IDX 0 +-#define mmNBIF_STRAP_WRITE_CTRL 0x0e67 // duplicate +-#define mmNBIF_STRAP_WRITE_CTRL_BASE_IDX 0 +-#define mmBIF_PERSTB_PAD_CNTL 0x0e68 // duplicate +-#define mmBIF_PERSTB_PAD_CNTL_BASE_IDX 0 +-#define mmBIF_PX_EN_PAD_CNTL 0x0e69 // duplicate +-#define mmBIF_PX_EN_PAD_CNTL_BASE_IDX 0 +-#define mmBIF_REFPADKIN_PAD_CNTL 0x0e6a // duplicate +-#define mmBIF_REFPADKIN_PAD_CNTL_BASE_IDX 0 +-#define mmBIF_CLKREQB_PAD_CNTL 0x0e6b // duplicate +-#define mmBIF_CLKREQB_PAD_CNTL_BASE_IDX 0 +- +- +-// addressBlock: rcc_pf_0_BIFDEC1 +-// base address: 0x0 +-#define mmRCC_BACO_CNTL_MISC 0x0da7 // duplicate +-#define mmRCC_BACO_CNTL_MISC_BASE_IDX 0 +-#define mmRCC_RESET_EN 0x0da8 // duplicate +-#define mmRCC_RESET_EN_BASE_IDX 0 +-#define mmRCC_VDM_SUPPORT 0x0da9 // duplicate +-#define mmRCC_VDM_SUPPORT_BASE_IDX 0 +-#define mmRCC_PEER_REG_RANGE0 0x0dde // duplicate +-#define mmRCC_PEER_REG_RANGE0_BASE_IDX 0 +-#define mmRCC_PEER_REG_RANGE1 0x0ddf // duplicate +-#define mmRCC_PEER_REG_RANGE1_BASE_IDX 0 +-#define mmRCC_BUS_CNTL 0x0de1 // duplicate +-#define mmRCC_BUS_CNTL_BASE_IDX 0 +-#define mmRCC_CONFIG_CNTL 0x0de2 // duplicate +-#define mmRCC_CONFIG_CNTL_BASE_IDX 0 +-#define mmRCC_CONFIG_F0_BASE 0x0de6 // duplicate +-#define mmRCC_CONFIG_F0_BASE_BASE_IDX 0 +-#define mmRCC_CONFIG_APER_SIZE 0x0de7 // duplicate +-#define mmRCC_CONFIG_APER_SIZE_BASE_IDX 0 +-#define mmRCC_CONFIG_REG_APER_SIZE 0x0de8 // duplicate +-#define mmRCC_CONFIG_REG_APER_SIZE_BASE_IDX 0 +-#define mmRCC_XDMA_LO 0x0de9 // duplicate +-#define mmRCC_XDMA_LO_BASE_IDX 0 +-#define mmRCC_XDMA_HI 0x0dea // duplicate +-#define mmRCC_XDMA_HI_BASE_IDX 0 +-#define mmRCC_FEATURES_CONTROL_MISC 0x0deb // duplicate +-#define mmRCC_FEATURES_CONTROL_MISC_BASE_IDX 0 +-#define mmRCC_BUSNUM_CNTL1 0x0dec // duplicate +-#define mmRCC_BUSNUM_CNTL1_BASE_IDX 0 +-#define mmRCC_BUSNUM_LIST0 0x0ded // duplicate +-#define mmRCC_BUSNUM_LIST0_BASE_IDX 0 +-#define mmRCC_BUSNUM_LIST1 0x0dee // duplicate +-#define mmRCC_BUSNUM_LIST1_BASE_IDX 0 +-#define mmRCC_BUSNUM_CNTL2 0x0def // duplicate +-#define mmRCC_BUSNUM_CNTL2_BASE_IDX 0 +-#define mmRCC_CAPTURE_HOST_BUSNUM 0x0df0 // duplicate +-#define mmRCC_CAPTURE_HOST_BUSNUM_BASE_IDX 0 +-#define mmRCC_HOST_BUSNUM 0x0df1 // duplicate +-#define mmRCC_HOST_BUSNUM_BASE_IDX 0 +-#define mmRCC_PEER0_FB_OFFSET_HI 0x0df2 // duplicate +-#define mmRCC_PEER0_FB_OFFSET_HI_BASE_IDX 0 +-#define mmRCC_PEER0_FB_OFFSET_LO 0x0df3 // duplicate +-#define mmRCC_PEER0_FB_OFFSET_LO_BASE_IDX 0 +-#define mmRCC_PEER1_FB_OFFSET_HI 0x0df4 // duplicate +-#define mmRCC_PEER1_FB_OFFSET_HI_BASE_IDX 0 +-#define mmRCC_PEER1_FB_OFFSET_LO 0x0df5 // duplicate +-#define mmRCC_PEER1_FB_OFFSET_LO_BASE_IDX 0 +-#define mmRCC_PEER2_FB_OFFSET_HI 0x0df6 // duplicate +-#define mmRCC_PEER2_FB_OFFSET_HI_BASE_IDX 0 +-#define mmRCC_PEER2_FB_OFFSET_LO 0x0df7 // duplicate +-#define mmRCC_PEER2_FB_OFFSET_LO_BASE_IDX 0 +-#define mmRCC_PEER3_FB_OFFSET_HI 0x0df8 // duplicate +-#define mmRCC_PEER3_FB_OFFSET_HI_BASE_IDX 0 +-#define mmRCC_PEER3_FB_OFFSET_LO 0x0df9 // duplicate +-#define mmRCC_PEER3_FB_OFFSET_LO_BASE_IDX 0 +-#define mmRCC_DEVFUNCNUM_LIST0 0x0dfa // duplicate +-#define mmRCC_DEVFUNCNUM_LIST0_BASE_IDX 0 +-#define mmRCC_DEVFUNCNUM_LIST1 0x0dfb // duplicate +-#define mmRCC_DEVFUNCNUM_LIST1_BASE_IDX 0 +-#define mmRCC_DEV0_LINK_CNTL 0x0dfd // duplicate +-#define mmRCC_DEV0_LINK_CNTL_BASE_IDX 0 +-#define mmRCC_CMN_LINK_CNTL 0x0dfe // duplicate +-#define mmRCC_CMN_LINK_CNTL_BASE_IDX 0 +-#define mmRCC_EP_REQUESTERID_RESTORE 0x0dff // duplicate +-#define mmRCC_EP_REQUESTERID_RESTORE_BASE_IDX 0 +-#define mmRCC_LTR_LSWITCH_CNTL 0x0e00 // duplicate +-#define mmRCC_LTR_LSWITCH_CNTL_BASE_IDX 0 +-#define mmRCC_MH_ARB_CNTL 0x0e01 // duplicate +-#define mmRCC_MH_ARB_CNTL_BASE_IDX 0 +- +- +-// addressBlock: rcc_pf_0_BIFDEC2 +-// base address: 0x0 +-#define mmGFXMSIX_VECT0_ADDR_LO 0x10800 // duplicate +-#define mmGFXMSIX_VECT0_ADDR_LO_BASE_IDX 0 +-#define mmGFXMSIX_VECT0_ADDR_HI 0x10801 // duplicate +-#define mmGFXMSIX_VECT0_ADDR_HI_BASE_IDX 0 +-#define mmGFXMSIX_VECT0_MSG_DATA 0x10802 // duplicate +-#define mmGFXMSIX_VECT0_MSG_DATA_BASE_IDX 0 +-#define mmGFXMSIX_VECT0_CONTROL 0x10803 // duplicate +-#define mmGFXMSIX_VECT0_CONTROL_BASE_IDX 0 +-#define mmGFXMSIX_VECT1_ADDR_LO 0x10804 // duplicate +-#define mmGFXMSIX_VECT1_ADDR_LO_BASE_IDX 0 +-#define mmGFXMSIX_VECT1_ADDR_HI 0x10805 // duplicate +-#define mmGFXMSIX_VECT1_ADDR_HI_BASE_IDX 0 +-#define mmGFXMSIX_VECT1_MSG_DATA 0x10806 // duplicate +-#define mmGFXMSIX_VECT1_MSG_DATA_BASE_IDX 0 +-#define mmGFXMSIX_VECT1_CONTROL 0x10807 // duplicate +-#define mmGFXMSIX_VECT1_CONTROL_BASE_IDX 0 +-#define mmGFXMSIX_VECT2_ADDR_LO 0x10808 // duplicate +-#define mmGFXMSIX_VECT2_ADDR_LO_BASE_IDX 0 +-#define mmGFXMSIX_VECT2_ADDR_HI 0x10809 // duplicate +-#define mmGFXMSIX_VECT2_ADDR_HI_BASE_IDX 0 +-#define mmGFXMSIX_VECT2_MSG_DATA 0x1080a // duplicate +-#define mmGFXMSIX_VECT2_MSG_DATA_BASE_IDX 0 +-#define mmGFXMSIX_VECT2_CONTROL 0x1080b // duplicate +-#define mmGFXMSIX_VECT2_CONTROL_BASE_IDX 0 +-#define mmGFXMSIX_PBA 0x10c00 // duplicate +-#define mmGFXMSIX_PBA_BASE_IDX 0 +- +- +-// addressBlock: rcc_strap_BIFDEC1 +-// base address: 0x0 +-#define mmRCC_DEV0_PORT_STRAP0 0x0d27 // duplicate +-#define mmRCC_DEV0_PORT_STRAP0_BASE_IDX 0 +-#define mmRCC_DEV0_PORT_STRAP1 0x0d28 // duplicate +-#define mmRCC_DEV0_PORT_STRAP1_BASE_IDX 0 +-#define mmRCC_DEV0_PORT_STRAP2 0x0d29 // duplicate +-#define mmRCC_DEV0_PORT_STRAP2_BASE_IDX 0 +-#define mmRCC_DEV0_PORT_STRAP3 0x0d2a // duplicate +-#define mmRCC_DEV0_PORT_STRAP3_BASE_IDX 0 +-#define mmRCC_DEV0_PORT_STRAP4 0x0d2b // duplicate +-#define mmRCC_DEV0_PORT_STRAP4_BASE_IDX 0 +-#define mmRCC_DEV0_PORT_STRAP5 0x0d2c // duplicate +-#define mmRCC_DEV0_PORT_STRAP5_BASE_IDX 0 +-#define mmRCC_DEV0_PORT_STRAP6 0x0d2d // duplicate +-#define mmRCC_DEV0_PORT_STRAP6_BASE_IDX 0 +-#define mmRCC_DEV0_PORT_STRAP7 0x0d2e // duplicate +-#define mmRCC_DEV0_PORT_STRAP7_BASE_IDX 0 +-#define mmRCC_DEV0_EPF0_STRAP0 0x0d2f // duplicate +-#define mmRCC_DEV0_EPF0_STRAP0_BASE_IDX 0 +-#define mmRCC_DEV0_EPF0_STRAP1 0x0d30 // duplicate +-#define mmRCC_DEV0_EPF0_STRAP1_BASE_IDX 0 +-#define mmRCC_DEV0_EPF0_STRAP13 0x0d31 // duplicate +-#define mmRCC_DEV0_EPF0_STRAP13_BASE_IDX 0 +-#define mmRCC_DEV0_EPF0_STRAP2 0x0d32 // duplicate +-#define mmRCC_DEV0_EPF0_STRAP2_BASE_IDX 0 +-#define mmRCC_DEV0_EPF0_STRAP3 0x0d33 // duplicate +-#define mmRCC_DEV0_EPF0_STRAP3_BASE_IDX 0 +-#define mmRCC_DEV0_EPF0_STRAP4 0x0d34 // duplicate +-#define mmRCC_DEV0_EPF0_STRAP4_BASE_IDX 0 +-#define mmRCC_DEV0_EPF0_STRAP5 0x0d35 // duplicate +-#define mmRCC_DEV0_EPF0_STRAP5_BASE_IDX 0 +-#define mmRCC_DEV0_EPF0_STRAP8 0x0d36 // duplicate +-#define mmRCC_DEV0_EPF0_STRAP8_BASE_IDX 0 +-#define mmRCC_DEV0_EPF0_STRAP9 0x0d37 // duplicate +-#define mmRCC_DEV0_EPF0_STRAP9_BASE_IDX 0 +-#define mmRCC_DEV0_EPF1_STRAP0 0x0d38 // duplicate +-#define mmRCC_DEV0_EPF1_STRAP0_BASE_IDX 0 +-#define mmRCC_DEV0_EPF1_STRAP10 0x0d39 // duplicate +-#define mmRCC_DEV0_EPF1_STRAP10_BASE_IDX 0 +-#define mmRCC_DEV0_EPF1_STRAP11 0x0d3a // duplicate +-#define mmRCC_DEV0_EPF1_STRAP11_BASE_IDX 0 +-#define mmRCC_DEV0_EPF1_STRAP12 0x0d3b // duplicate +-#define mmRCC_DEV0_EPF1_STRAP12_BASE_IDX 0 +-#define mmRCC_DEV0_EPF1_STRAP13 0x0d3c // duplicate +-#define mmRCC_DEV0_EPF1_STRAP13_BASE_IDX 0 +-#define mmRCC_DEV0_EPF1_STRAP2 0x0d3d // duplicate +-#define mmRCC_DEV0_EPF1_STRAP2_BASE_IDX 0 +-#define mmRCC_DEV0_EPF1_STRAP3 0x0d3e // duplicate +-#define mmRCC_DEV0_EPF1_STRAP3_BASE_IDX 0 +-#define mmRCC_DEV0_EPF1_STRAP4 0x0d3f // duplicate +-#define mmRCC_DEV0_EPF1_STRAP4_BASE_IDX 0 +-#define mmRCC_DEV0_EPF1_STRAP5 0x0d40 // duplicate +-#define mmRCC_DEV0_EPF1_STRAP5_BASE_IDX 0 +-#define mmRCC_DEV0_EPF1_STRAP6 0x0d41 // duplicate +-#define mmRCC_DEV0_EPF1_STRAP6_BASE_IDX 0 +-#define mmRCC_DEV0_EPF1_STRAP7 0x0d42 // duplicate +-#define mmRCC_DEV0_EPF1_STRAP7_BASE_IDX 0 +- +- +-// addressBlock: bif_bx_pf_BIFPFVFDEC1 +-// base address: 0x0 +-#define mmBIF_BME_STATUS 0x0e0b // duplicate +-#define mmBIF_BME_STATUS_BASE_IDX 0 +-#define mmBIF_ATOMIC_ERR_LOG 0x0e0c // duplicate +-#define mmBIF_ATOMIC_ERR_LOG_BASE_IDX 0 +-#define mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x0e13 // duplicate +-#define mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 0 +-#define mmDOORBELL_SELFRING_GPA_APER_BASE_LOW 0x0e14 // duplicate +-#define mmDOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 0 +-#define mmDOORBELL_SELFRING_GPA_APER_CNTL 0x0e15 // duplicate +-#define mmDOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 0 +-#define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x0e16 // duplicate +-#define mmHDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 0 +-#define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x0e17 // duplicate +-#define mmHDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 0 +-#define mmGPU_HDP_FLUSH_REQ 0x0e26 // duplicate +-#define mmGPU_HDP_FLUSH_REQ_BASE_IDX 0 +-#define mmGPU_HDP_FLUSH_DONE 0x0e27 // duplicate +-#define mmGPU_HDP_FLUSH_DONE_BASE_IDX 0 +-#define mmBIF_TRANS_PENDING 0x0e28 // duplicate +-#define mmBIF_TRANS_PENDING_BASE_IDX 0 +-#define mmMAILBOX_MSGBUF_TRN_DW0 0x0e56 // duplicate +-#define mmMAILBOX_MSGBUF_TRN_DW0_BASE_IDX 0 +-#define mmMAILBOX_MSGBUF_TRN_DW1 0x0e57 // duplicate +-#define mmMAILBOX_MSGBUF_TRN_DW1_BASE_IDX 0 +-#define mmMAILBOX_MSGBUF_TRN_DW2 0x0e58 // duplicate +-#define mmMAILBOX_MSGBUF_TRN_DW2_BASE_IDX 0 +-#define mmMAILBOX_MSGBUF_TRN_DW3 0x0e59 // duplicate +-#define mmMAILBOX_MSGBUF_TRN_DW3_BASE_IDX 0 +-#define mmMAILBOX_MSGBUF_RCV_DW0 0x0e5a // duplicate +-#define mmMAILBOX_MSGBUF_RCV_DW0_BASE_IDX 0 +-#define mmMAILBOX_MSGBUF_RCV_DW1 0x0e5b // duplicate +-#define mmMAILBOX_MSGBUF_RCV_DW1_BASE_IDX 0 +-#define mmMAILBOX_MSGBUF_RCV_DW2 0x0e5c // duplicate +-#define mmMAILBOX_MSGBUF_RCV_DW2_BASE_IDX 0 +-#define mmMAILBOX_MSGBUF_RCV_DW3 0x0e5d // duplicate +-#define mmMAILBOX_MSGBUF_RCV_DW3_BASE_IDX 0 +-#define mmMAILBOX_CONTROL 0x0e5e // duplicate +-#define mmMAILBOX_CONTROL_BASE_IDX 0 +-#define mmMAILBOX_INT_CNTL 0x0e5f // duplicate +-#define mmMAILBOX_INT_CNTL_BASE_IDX 0 +-#define mmBIF_VMHV_MAILBOX 0x0e60 // duplicate +-#define mmBIF_VMHV_MAILBOX_BASE_IDX 0 +- +- +-// addressBlock: rcc_pf_0_BIFPFVFDEC1 +-// base address: 0x0 +-#define mmRCC_DOORBELL_APER_EN 0x0de0 // duplicate +-#define mmRCC_DOORBELL_APER_EN_BASE_IDX 0 +-#define mmRCC_CONFIG_MEMSIZE 0x0de3 // duplicate +-#define mmRCC_CONFIG_MEMSIZE_BASE_IDX 0 +-#define mmRCC_CONFIG_RESERVED 0x0de4 // duplicate +-#define mmRCC_CONFIG_RESERVED_BASE_IDX 0 +-#define mmRCC_IOV_FUNC_IDENTIFIER 0x0de5 // duplicate +-#define mmRCC_IOV_FUNC_IDENTIFIER_BASE_IDX 0 +- +- +-// addressBlock: syshub_mmreg_ind_syshubdec +-// base address: 0x0 +-#define mmSYSHUB_INDEX 0x0008 +-#define mmSYSHUB_INDEX_BASE_IDX 0 +-#define mmSYSHUB_DATA 0x0009 +-#define mmSYSHUB_DATA_BASE_IDX 0 +- +- +-// addressBlock: rcc_strap_rcc_strap_internal +-// base address: 0x10100000 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0 0x403c000 // duplicate +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0_BASE_IDX 3 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1 0x403c001 // duplicate +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1_BASE_IDX 3 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2 0x403c002 // duplicate +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2_BASE_IDX 3 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3 0x403c003 // duplicate +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3_BASE_IDX 3 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4 0x403c004 // duplicate +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4_BASE_IDX 3 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5 0x403c005 // duplicate +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5_BASE_IDX 3 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6 0x403c006 // duplicate +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6_BASE_IDX 3 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7 0x403c007 // duplicate +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7_BASE_IDX 3 +-#define mmRCC_DEV1_PORT_STRAP0 0x403c080 +-#define mmRCC_DEV1_PORT_STRAP0_BASE_IDX 3 +-#define mmRCC_DEV1_PORT_STRAP1 0x403c081 +-#define mmRCC_DEV1_PORT_STRAP1_BASE_IDX 3 +-#define mmRCC_DEV1_PORT_STRAP2 0x403c082 +-#define mmRCC_DEV1_PORT_STRAP2_BASE_IDX 3 +-#define mmRCC_DEV1_PORT_STRAP3 0x403c083 +-#define mmRCC_DEV1_PORT_STRAP3_BASE_IDX 3 +-#define mmRCC_DEV1_PORT_STRAP4 0x403c084 +-#define mmRCC_DEV1_PORT_STRAP4_BASE_IDX 3 +-#define mmRCC_DEV1_PORT_STRAP5 0x403c085 +-#define mmRCC_DEV1_PORT_STRAP5_BASE_IDX 3 +-#define mmRCC_DEV1_PORT_STRAP6 0x403c086 +-#define mmRCC_DEV1_PORT_STRAP6_BASE_IDX 3 +-#define mmRCC_DEV1_PORT_STRAP7 0x403c087 +-#define mmRCC_DEV1_PORT_STRAP7_BASE_IDX 3 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0 0x403cc00 // duplicate +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0_BASE_IDX 3 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1 0x403cc01 // duplicate +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1_BASE_IDX 3 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2 0x403cc02 // duplicate +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2_BASE_IDX 3 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3 0x403cc03 // duplicate +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3_BASE_IDX 3 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4 0x403cc04 // duplicate +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4_BASE_IDX 3 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5 0x403cc05 // duplicate +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5_BASE_IDX 3 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8 0x403cc08 // duplicate +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8_BASE_IDX 3 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP9 0x403cc09 // duplicate +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP9_BASE_IDX 3 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13 0x403cc0d // duplicate +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13_BASE_IDX 3 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0 0x403cc80 // duplicate +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0_BASE_IDX 3 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2 0x403cc82 // duplicate +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2_BASE_IDX 3 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3 0x403cc83 // duplicate +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3_BASE_IDX 3 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4 0x403cc84 // duplicate +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4_BASE_IDX 3 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5 0x403cc85 // duplicate +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5_BASE_IDX 3 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6 0x403cc86 // duplicate +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6_BASE_IDX 3 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7 0x403cc87 // duplicate +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7_BASE_IDX 3 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10 0x403cc8a // duplicate +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10_BASE_IDX 3 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11 0x403cc8b // duplicate +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11_BASE_IDX 3 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12 0x403cc8c // duplicate +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12_BASE_IDX 3 +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13 0x403cc8d // duplicate +-#define mmRCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13_BASE_IDX 3 +-#define mmRCC_DEV0_EPF2_STRAP0 0x403cd00 +-#define mmRCC_DEV0_EPF2_STRAP0_BASE_IDX 3 +-#define mmRCC_DEV0_EPF2_STRAP2 0x403cd02 +-#define mmRCC_DEV0_EPF2_STRAP2_BASE_IDX 3 +-#define mmRCC_DEV0_EPF2_STRAP3 0x403cd03 +-#define mmRCC_DEV0_EPF2_STRAP3_BASE_IDX 3 +-#define mmRCC_DEV0_EPF2_STRAP4 0x403cd04 +-#define mmRCC_DEV0_EPF2_STRAP4_BASE_IDX 3 +-#define mmRCC_DEV0_EPF2_STRAP5 0x403cd05 +-#define mmRCC_DEV0_EPF2_STRAP5_BASE_IDX 3 +-#define mmRCC_DEV0_EPF2_STRAP6 0x403cd06 +-#define mmRCC_DEV0_EPF2_STRAP6_BASE_IDX 3 +-#define mmRCC_DEV0_EPF2_STRAP13 0x403cd0d +-#define mmRCC_DEV0_EPF2_STRAP13_BASE_IDX 3 +-#define mmRCC_DEV0_EPF3_STRAP0 0x403cd80 +-#define mmRCC_DEV0_EPF3_STRAP0_BASE_IDX 3 +-#define mmRCC_DEV0_EPF3_STRAP2 0x403cd82 +-#define mmRCC_DEV0_EPF3_STRAP2_BASE_IDX 3 +-#define mmRCC_DEV0_EPF3_STRAP3 0x403cd83 +-#define mmRCC_DEV0_EPF3_STRAP3_BASE_IDX 3 +-#define mmRCC_DEV0_EPF3_STRAP4 0x403cd84 +-#define mmRCC_DEV0_EPF3_STRAP4_BASE_IDX 3 +-#define mmRCC_DEV0_EPF3_STRAP5 0x403cd85 +-#define mmRCC_DEV0_EPF3_STRAP5_BASE_IDX 3 +-#define mmRCC_DEV0_EPF3_STRAP6 0x403cd86 +-#define mmRCC_DEV0_EPF3_STRAP6_BASE_IDX 3 +-#define mmRCC_DEV0_EPF3_STRAP13 0x403cd8d +-#define mmRCC_DEV0_EPF3_STRAP13_BASE_IDX 3 +-#define mmRCC_DEV0_EPF4_STRAP0 0x403ce00 +-#define mmRCC_DEV0_EPF4_STRAP0_BASE_IDX 3 +-#define mmRCC_DEV0_EPF4_STRAP2 0x403ce02 +-#define mmRCC_DEV0_EPF4_STRAP2_BASE_IDX 3 +-#define mmRCC_DEV0_EPF4_STRAP3 0x403ce03 +-#define mmRCC_DEV0_EPF4_STRAP3_BASE_IDX 3 +-#define mmRCC_DEV0_EPF4_STRAP4 0x403ce04 +-#define mmRCC_DEV0_EPF4_STRAP4_BASE_IDX 3 +-#define mmRCC_DEV0_EPF4_STRAP5 0x403ce05 +-#define mmRCC_DEV0_EPF4_STRAP5_BASE_IDX 3 +-#define mmRCC_DEV0_EPF4_STRAP6 0x403ce06 +-#define mmRCC_DEV0_EPF4_STRAP6_BASE_IDX 3 +-#define mmRCC_DEV0_EPF4_STRAP13 0x403ce0d +-#define mmRCC_DEV0_EPF4_STRAP13_BASE_IDX 3 +-#define mmRCC_DEV0_EPF5_STRAP0 0x403ce80 +-#define mmRCC_DEV0_EPF5_STRAP0_BASE_IDX 3 +-#define mmRCC_DEV0_EPF5_STRAP2 0x403ce82 +-#define mmRCC_DEV0_EPF5_STRAP2_BASE_IDX 3 +-#define mmRCC_DEV0_EPF5_STRAP3 0x403ce83 +-#define mmRCC_DEV0_EPF5_STRAP3_BASE_IDX 3 +-#define mmRCC_DEV0_EPF5_STRAP4 0x403ce84 +-#define mmRCC_DEV0_EPF5_STRAP4_BASE_IDX 3 +-#define mmRCC_DEV0_EPF5_STRAP5 0x403ce85 +-#define mmRCC_DEV0_EPF5_STRAP5_BASE_IDX 3 +-#define mmRCC_DEV0_EPF5_STRAP6 0x403ce86 +-#define mmRCC_DEV0_EPF5_STRAP6_BASE_IDX 3 +-#define mmRCC_DEV0_EPF5_STRAP13 0x403ce8d +-#define mmRCC_DEV0_EPF5_STRAP13_BASE_IDX 3 +-#define mmRCC_DEV0_EPF6_STRAP0 0x403cf00 +-#define mmRCC_DEV0_EPF6_STRAP0_BASE_IDX 3 +-#define mmRCC_DEV0_EPF6_STRAP2 0x403cf02 +-#define mmRCC_DEV0_EPF6_STRAP2_BASE_IDX 3 +-#define mmRCC_DEV0_EPF6_STRAP3 0x403cf03 +-#define mmRCC_DEV0_EPF6_STRAP3_BASE_IDX 3 +-#define mmRCC_DEV0_EPF6_STRAP4 0x403cf04 +-#define mmRCC_DEV0_EPF6_STRAP4_BASE_IDX 3 +-#define mmRCC_DEV0_EPF6_STRAP5 0x403cf05 +-#define mmRCC_DEV0_EPF6_STRAP5_BASE_IDX 3 +-#define mmRCC_DEV0_EPF6_STRAP6 0x403cf06 +-#define mmRCC_DEV0_EPF6_STRAP6_BASE_IDX 3 +-#define mmRCC_DEV0_EPF6_STRAP13 0x403cf0d +-#define mmRCC_DEV0_EPF6_STRAP13_BASE_IDX 3 +-#define mmRCC_DEV0_EPF7_STRAP0 0x403cf80 +-#define mmRCC_DEV0_EPF7_STRAP0_BASE_IDX 3 +-#define mmRCC_DEV0_EPF7_STRAP2 0x403cf82 +-#define mmRCC_DEV0_EPF7_STRAP2_BASE_IDX 3 +-#define mmRCC_DEV0_EPF7_STRAP3 0x403cf83 +-#define mmRCC_DEV0_EPF7_STRAP3_BASE_IDX 3 +-#define mmRCC_DEV0_EPF7_STRAP4 0x403cf84 +-#define mmRCC_DEV0_EPF7_STRAP4_BASE_IDX 3 +-#define mmRCC_DEV0_EPF7_STRAP5 0x403cf85 +-#define mmRCC_DEV0_EPF7_STRAP5_BASE_IDX 3 +-#define mmRCC_DEV0_EPF7_STRAP6 0x403cf86 +-#define mmRCC_DEV0_EPF7_STRAP6_BASE_IDX 3 +-#define mmRCC_DEV0_EPF7_STRAP13 0x403cf8d +-#define mmRCC_DEV0_EPF7_STRAP13_BASE_IDX 3 +-#define mmRCC_DEV1_EPF0_STRAP0 0x403d000 +-#define mmRCC_DEV1_EPF0_STRAP0_BASE_IDX 3 +-#define mmRCC_DEV1_EPF0_STRAP2 0x403d002 +-#define mmRCC_DEV1_EPF0_STRAP2_BASE_IDX 3 +-#define mmRCC_DEV1_EPF0_STRAP3 0x403d003 +-#define mmRCC_DEV1_EPF0_STRAP3_BASE_IDX 3 +-#define mmRCC_DEV1_EPF0_STRAP4 0x403d004 +-#define mmRCC_DEV1_EPF0_STRAP4_BASE_IDX 3 +-#define mmRCC_DEV1_EPF0_STRAP5 0x403d005 +-#define mmRCC_DEV1_EPF0_STRAP5_BASE_IDX 3 +-#define mmRCC_DEV1_EPF0_STRAP6 0x403d006 +-#define mmRCC_DEV1_EPF0_STRAP6_BASE_IDX 3 +-#define mmRCC_DEV1_EPF0_STRAP13 0x403d00d +-#define mmRCC_DEV1_EPF0_STRAP13_BASE_IDX 3 +-#define mmRCC_DEV1_EPF1_STRAP0 0x403d080 +-#define mmRCC_DEV1_EPF1_STRAP0_BASE_IDX 3 +-#define mmRCC_DEV1_EPF1_STRAP2 0x403d082 +-#define mmRCC_DEV1_EPF1_STRAP2_BASE_IDX 3 +-#define mmRCC_DEV1_EPF1_STRAP3 0x403d083 +-#define mmRCC_DEV1_EPF1_STRAP3_BASE_IDX 3 +-#define mmRCC_DEV1_EPF1_STRAP4 0x403d084 +-#define mmRCC_DEV1_EPF1_STRAP4_BASE_IDX 3 +-#define mmRCC_DEV1_EPF1_STRAP5 0x403d085 +-#define mmRCC_DEV1_EPF1_STRAP5_BASE_IDX 3 +-#define mmRCC_DEV1_EPF1_STRAP6 0x403d086 +-#define mmRCC_DEV1_EPF1_STRAP6_BASE_IDX 3 +-#define mmRCC_DEV1_EPF1_STRAP13 0x403d08d +-#define mmRCC_DEV1_EPF1_STRAP13_BASE_IDX 3 +-#define mmRCC_DEV1_EPF2_STRAP0 0x403d100 +-#define mmRCC_DEV1_EPF2_STRAP0_BASE_IDX 3 +-#define mmRCC_DEV1_EPF2_STRAP2 0x403d102 +-#define mmRCC_DEV1_EPF2_STRAP2_BASE_IDX 3 +-#define mmRCC_DEV1_EPF2_STRAP3 0x403d103 +-#define mmRCC_DEV1_EPF2_STRAP3_BASE_IDX 3 +-#define mmRCC_DEV1_EPF2_STRAP4 0x403d104 +-#define mmRCC_DEV1_EPF2_STRAP4_BASE_IDX 3 +-#define mmRCC_DEV1_EPF2_STRAP5 0x403d105 +-#define mmRCC_DEV1_EPF2_STRAP5_BASE_IDX 3 +-#define mmRCC_DEV1_EPF2_STRAP6 0x403d106 +-#define mmRCC_DEV1_EPF2_STRAP6_BASE_IDX 3 +-#define mmRCC_DEV1_EPF2_STRAP13 0x403d10d +-#define mmRCC_DEV1_EPF2_STRAP13_BASE_IDX 3 +- +- +-// addressBlock: bif_rst_bif_rst_regblk +-// base address: 0x10100000 +-#define ixHARD_RST_CTRL 0x38000 +-#define ixRSMU_SOFT_RST_CTRL 0x38004 +-#define ixSELF_SOFT_RST 0x38008 +-#define ixGFX_DRV_MODE1_RST_CTRL 0x3800c +-#define ixBIF_RST_MISC_CTRL 0x38010 +-#define ixBIF_RST_MISC_CTRL2 0x38014 +-#define ixBIF_RST_MISC_CTRL3 0x38018 +-#define ixBIF_RST_GFXVF_FLR_IDLE 0x3801c +-#define ixDEV0_PF0_FLR_RST_CTRL 0x38020 +-#define ixDEV0_PF1_FLR_RST_CTRL 0x38024 +-#define ixDEV0_PF2_FLR_RST_CTRL 0x38028 +-#define ixDEV0_PF3_FLR_RST_CTRL 0x3802c +-#define ixDEV0_PF4_FLR_RST_CTRL 0x38030 +-#define ixDEV0_PF5_FLR_RST_CTRL 0x38034 +-#define ixDEV0_PF6_FLR_RST_CTRL 0x38038 +-#define ixDEV0_PF7_FLR_RST_CTRL 0x3803c +-#define ixBIF_INST_RESET_INTR_STS 0x38040 +-#define ixBIF_PF_FLR_INTR_STS 0x38044 +-#define ixBIF_D3HOTD0_INTR_STS 0x38048 +-#define ixBIF_POWER_INTR_STS 0x38050 +-#define ixBIF_PF_DSTATE_INTR_STS 0x38054 +-#define ixBIF_PF0_VF_FLR_INTR_STS 0x38060 +-#define ixBIF_INST_RESET_INTR_MASK 0x38080 +-#define ixBIF_PF_FLR_INTR_MASK 0x38084 +-#define ixBIF_D3HOTD0_INTR_MASK 0x38088 +-#define ixBIF_POWER_INTR_MASK 0x38090 +-#define ixBIF_PF_DSTATE_INTR_MASK 0x38094 +-#define ixBIF_PF0_VF_FLR_INTR_MASK 0x380a0 +-#define ixBIF_PF_FLR_RST 0x38100 +-#define ixBIF_PF0_VF_FLR_RST 0x38120 +-#define ixBIF_DEV0_PF0_DSTATE_VALUE 0x38140 +-#define ixBIF_DEV0_PF1_DSTATE_VALUE 0x38144 +-#define ixBIF_DEV0_PF2_DSTATE_VALUE 0x38148 +-#define ixBIF_DEV0_PF3_DSTATE_VALUE 0x3814c +-#define ixBIF_DEV0_PF4_DSTATE_VALUE 0x38150 +-#define ixBIF_DEV0_PF5_DSTATE_VALUE 0x38154 +-#define ixBIF_DEV0_PF6_DSTATE_VALUE 0x38158 +-#define ixBIF_DEV0_PF7_DSTATE_VALUE 0x3815c +-#define ixDEV0_PF0_D3HOTD0_RST_CTRL 0x381e0 +-#define ixDEV0_PF1_D3HOTD0_RST_CTRL 0x381e4 +-#define ixDEV0_PF2_D3HOTD0_RST_CTRL 0x381e8 +-#define ixDEV0_PF3_D3HOTD0_RST_CTRL 0x381ec +-#define ixDEV0_PF4_D3HOTD0_RST_CTRL 0x381f0 +-#define ixDEV0_PF5_D3HOTD0_RST_CTRL 0x381f4 +-#define ixDEV0_PF6_D3HOTD0_RST_CTRL 0x381f8 +-#define ixDEV0_PF7_D3HOTD0_RST_CTRL 0x381fc +-#define ixBIF_PORT0_DSTATE_VALUE 0x388c0 +- +- +-// addressBlock: bif_misc_bif_misc_regblk +-// base address: 0x10100000 +-#define ixMISC_SCRATCH 0x3a000 +-#define ixINTR_LINE_POLARITY 0x3a004 +-#define ixINTR_LINE_ENABLE 0x3a008 +-#define ixOUTSTANDING_VC_ALLOC 0x3a00c +-#define ixBIFC_MISC_CTRL0 0x3a010 +-#define ixBIFC_MISC_CTRL1 0x3a014 +-#define ixBIFC_BME_ERR_LOG 0x3a018 +-#define ixBIFC_RCCBIH_BME_ERR_LOG 0x3a01c +-#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 0x3a020 +-#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 0x3a024 +-#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 0x3a028 +-#define ixBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 0x3a02c +-#define ixNBIF_VWIRE_CTRL 0x3a040 +-#define ixNBIF_SMN_VWR_VCHG_DIS_CTRL 0x3a044 +-#define ixNBIF_SMN_VWR_VCHG_RST_CTRL0 0x3a048 +-#define ixNBIF_SMN_VWR_VCHG_TRIG 0x3a050 +-#define ixNBIF_SMN_VWR_WTRIG_CNTL 0x3a054 +-#define ixNBIF_SMN_VWR_VCHG_DIS_CTRL_1 0x3a058 +-#define ixNBIF_MGCG_CTRL 0x3a05c +-#define ixNBIF_DS_CTRL_LCLK 0x3a060 +-#define ixSMN_MST_CNTL0 0x3a064 +-#define ixSMN_MST_EP_CNTL1 0x3a068 +-#define ixSMN_MST_EP_CNTL2 0x3a06c +-#define ixNBIF_SDP_VWR_VCHG_DIS_CTRL 0x3a070 +-#define ixNBIF_SDP_VWR_VCHG_RST_CTRL0 0x3a074 +-#define ixNBIF_SDP_VWR_VCHG_RST_CTRL1 0x3a078 +-#define ixNBIF_SDP_VWR_VCHG_TRIG 0x3a07c +-#define ixBME_DUMMY_CNTL_0 0x3a098 +-#define ixBIFC_THT_CNTL 0x3a09c +-#define ixBIFC_HSTARB_CNTL 0x3a0a0 +-#define ixBIFC_GSI_CNTL 0x3a0a4 +-#define ixBIFC_PCIEFUNC_CNTL 0x3a0a8 +-#define ixBIFC_SDP_CNTL_0 0x3a0b0 +-#define ixBIFC_PERF_CNTL_0 0x3a0c0 +-#define ixBIFC_PERF_CNTL_1 0x3a0c4 +-#define ixBIFC_PERF_CNT_MMIO_RD 0x3a0c8 +-#define ixBIFC_PERF_CNT_MMIO_WR 0x3a0cc +-#define ixBIFC_PERF_CNT_DMA_RD 0x3a0d0 +-#define ixBIFC_PERF_CNT_DMA_WR 0x3a0d4 +-#define ixNBIF_REGIF_ERRSET_CTRL 0x3a0d8 +-#define ixSMN_MST_EP_CNTL3 0x3a0f0 +-#define ixSMN_MST_EP_CNTL4 0x3a0f4 +-#define ixBIF_SELFRING_BUFFER_VID 0x3a100 +-#define ixBIF_SELFRING_VECTOR_CNTL 0x3a104 +- +- +-// addressBlock: bif_ras_bif_ras_regblk +-// base address: 0x10100000 +-#define ixBIF_RAS_LEAF0_CTRL 0x39000 +-#define ixBIF_RAS_LEAF1_CTRL 0x39004 +-#define ixBIF_RAS_LEAF2_CTRL 0x39008 +-#define ixBIF_RAS_MISC_CTRL 0x39100 +-#define ixBIF_IOHUB_RAS_IH_CNTL 0x39ff8 +-#define ixBIF_RAS_VWR_FROM_IOHUB 0x39ffc +- +- +-// addressBlock: rcc_pfc_amdgfx_RCCPFCDEC +-// base address: 0x10134000 +-#define ixRCC_PFC_LTR_CNTL 0x0100 // duplicate +-#define ixRCC_PFC_PME_RESTORE 0x0104 // duplicate +-#define ixRCC_PFC_STICKY_RESTORE_0 0x0108 // duplicate +-#define ixRCC_PFC_STICKY_RESTORE_1 0x010c // duplicate +-#define ixRCC_PFC_STICKY_RESTORE_2 0x0110 // duplicate +-#define ixRCC_PFC_STICKY_RESTORE_3 0x0114 // duplicate +-#define ixRCC_PFC_STICKY_RESTORE_4 0x0118 // duplicate +-#define ixRCC_PFC_STICKY_RESTORE_5 0x011c // duplicate +-#define ixRCC_PFC_AUXPWR_CNTL 0x0120 // duplicate +- +- +-// addressBlock: rcc_pfc_amdgfxaz_RCCPFCDEC +-// base address: 0x10134200 +-#define ixRCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL 0x0100 // duplicate +-#define ixRCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE 0x0104 // duplicate +-#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0 0x0108 // duplicate +-#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1 0x010c // duplicate +-#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2 0x0110 // duplicate +-#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3 0x0114 // duplicate +-#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4 0x0118 // duplicate +-#define ixRCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5 0x011c // duplicate +-#define ixRCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL 0x0120 // duplicate +- +- +-// addressBlock: pciemsix_amdgfx_MSIXTDEC +-// base address: 0x10170000 +-#define ixPCIEMSIX_VECT0_ADDR_LO 0x0000 +-#define ixPCIEMSIX_VECT0_ADDR_HI 0x0004 +-#define ixPCIEMSIX_VECT0_MSG_DATA 0x0008 +-#define ixPCIEMSIX_VECT0_CONTROL 0x000c +-#define ixPCIEMSIX_VECT1_ADDR_LO 0x0010 +-#define ixPCIEMSIX_VECT1_ADDR_HI 0x0014 +-#define ixPCIEMSIX_VECT1_MSG_DATA 0x0018 +-#define ixPCIEMSIX_VECT1_CONTROL 0x001c +-#define ixPCIEMSIX_VECT2_ADDR_LO 0x0020 +-#define ixPCIEMSIX_VECT2_ADDR_HI 0x0024 +-#define ixPCIEMSIX_VECT2_MSG_DATA 0x0028 +-#define ixPCIEMSIX_VECT2_CONTROL 0x002c +-#define ixPCIEMSIX_VECT3_ADDR_LO 0x0030 +-#define ixPCIEMSIX_VECT3_ADDR_HI 0x0034 +-#define ixPCIEMSIX_VECT3_MSG_DATA 0x0038 +-#define ixPCIEMSIX_VECT3_CONTROL 0x003c +-#define ixPCIEMSIX_VECT4_ADDR_LO 0x0040 +-#define ixPCIEMSIX_VECT4_ADDR_HI 0x0044 +-#define ixPCIEMSIX_VECT4_MSG_DATA 0x0048 +-#define ixPCIEMSIX_VECT4_CONTROL 0x004c +-#define ixPCIEMSIX_VECT5_ADDR_LO 0x0050 +-#define ixPCIEMSIX_VECT5_ADDR_HI 0x0054 +-#define ixPCIEMSIX_VECT5_MSG_DATA 0x0058 +-#define ixPCIEMSIX_VECT5_CONTROL 0x005c +-#define ixPCIEMSIX_VECT6_ADDR_LO 0x0060 +-#define ixPCIEMSIX_VECT6_ADDR_HI 0x0064 +-#define ixPCIEMSIX_VECT6_MSG_DATA 0x0068 +-#define ixPCIEMSIX_VECT6_CONTROL 0x006c +-#define ixPCIEMSIX_VECT7_ADDR_LO 0x0070 +-#define ixPCIEMSIX_VECT7_ADDR_HI 0x0074 +-#define ixPCIEMSIX_VECT7_MSG_DATA 0x0078 +-#define ixPCIEMSIX_VECT7_CONTROL 0x007c +-#define ixPCIEMSIX_VECT8_ADDR_LO 0x0080 +-#define ixPCIEMSIX_VECT8_ADDR_HI 0x0084 +-#define ixPCIEMSIX_VECT8_MSG_DATA 0x0088 +-#define ixPCIEMSIX_VECT8_CONTROL 0x008c +-#define ixPCIEMSIX_VECT9_ADDR_LO 0x0090 +-#define ixPCIEMSIX_VECT9_ADDR_HI 0x0094 +-#define ixPCIEMSIX_VECT9_MSG_DATA 0x0098 +-#define ixPCIEMSIX_VECT9_CONTROL 0x009c +-#define ixPCIEMSIX_VECT10_ADDR_LO 0x00a0 +-#define ixPCIEMSIX_VECT10_ADDR_HI 0x00a4 +-#define ixPCIEMSIX_VECT10_MSG_DATA 0x00a8 +-#define ixPCIEMSIX_VECT10_CONTROL 0x00ac +-#define ixPCIEMSIX_VECT11_ADDR_LO 0x00b0 +-#define ixPCIEMSIX_VECT11_ADDR_HI 0x00b4 +-#define ixPCIEMSIX_VECT11_MSG_DATA 0x00b8 +-#define ixPCIEMSIX_VECT11_CONTROL 0x00bc +-#define ixPCIEMSIX_VECT12_ADDR_LO 0x00c0 +-#define ixPCIEMSIX_VECT12_ADDR_HI 0x00c4 +-#define ixPCIEMSIX_VECT12_MSG_DATA 0x00c8 +-#define ixPCIEMSIX_VECT12_CONTROL 0x00cc +-#define ixPCIEMSIX_VECT13_ADDR_LO 0x00d0 +-#define ixPCIEMSIX_VECT13_ADDR_HI 0x00d4 +-#define ixPCIEMSIX_VECT13_MSG_DATA 0x00d8 +-#define ixPCIEMSIX_VECT13_CONTROL 0x00dc +-#define ixPCIEMSIX_VECT14_ADDR_LO 0x00e0 +-#define ixPCIEMSIX_VECT14_ADDR_HI 0x00e4 +-#define ixPCIEMSIX_VECT14_MSG_DATA 0x00e8 +-#define ixPCIEMSIX_VECT14_CONTROL 0x00ec +-#define ixPCIEMSIX_VECT15_ADDR_LO 0x00f0 +-#define ixPCIEMSIX_VECT15_ADDR_HI 0x00f4 +-#define ixPCIEMSIX_VECT15_MSG_DATA 0x00f8 +-#define ixPCIEMSIX_VECT15_CONTROL 0x00fc +-#define ixPCIEMSIX_VECT16_ADDR_LO 0x0100 +-#define ixPCIEMSIX_VECT16_ADDR_HI 0x0104 +-#define ixPCIEMSIX_VECT16_MSG_DATA 0x0108 +-#define ixPCIEMSIX_VECT16_CONTROL 0x010c +-#define ixPCIEMSIX_VECT17_ADDR_LO 0x0110 +-#define ixPCIEMSIX_VECT17_ADDR_HI 0x0114 +-#define ixPCIEMSIX_VECT17_MSG_DATA 0x0118 +-#define ixPCIEMSIX_VECT17_CONTROL 0x011c +-#define ixPCIEMSIX_VECT18_ADDR_LO 0x0120 +-#define ixPCIEMSIX_VECT18_ADDR_HI 0x0124 +-#define ixPCIEMSIX_VECT18_MSG_DATA 0x0128 +-#define ixPCIEMSIX_VECT18_CONTROL 0x012c +-#define ixPCIEMSIX_VECT19_ADDR_LO 0x0130 +-#define ixPCIEMSIX_VECT19_ADDR_HI 0x0134 +-#define ixPCIEMSIX_VECT19_MSG_DATA 0x0138 +-#define ixPCIEMSIX_VECT19_CONTROL 0x013c +-#define ixPCIEMSIX_VECT20_ADDR_LO 0x0140 +-#define ixPCIEMSIX_VECT20_ADDR_HI 0x0144 +-#define ixPCIEMSIX_VECT20_MSG_DATA 0x0148 +-#define ixPCIEMSIX_VECT20_CONTROL 0x014c +-#define ixPCIEMSIX_VECT21_ADDR_LO 0x0150 +-#define ixPCIEMSIX_VECT21_ADDR_HI 0x0154 +-#define ixPCIEMSIX_VECT21_MSG_DATA 0x0158 +-#define ixPCIEMSIX_VECT21_CONTROL 0x015c +-#define ixPCIEMSIX_VECT22_ADDR_LO 0x0160 +-#define ixPCIEMSIX_VECT22_ADDR_HI 0x0164 +-#define ixPCIEMSIX_VECT22_MSG_DATA 0x0168 +-#define ixPCIEMSIX_VECT22_CONTROL 0x016c +-#define ixPCIEMSIX_VECT23_ADDR_LO 0x0170 +-#define ixPCIEMSIX_VECT23_ADDR_HI 0x0174 +-#define ixPCIEMSIX_VECT23_MSG_DATA 0x0178 +-#define ixPCIEMSIX_VECT23_CONTROL 0x017c +-#define ixPCIEMSIX_VECT24_ADDR_LO 0x0180 +-#define ixPCIEMSIX_VECT24_ADDR_HI 0x0184 +-#define ixPCIEMSIX_VECT24_MSG_DATA 0x0188 +-#define ixPCIEMSIX_VECT24_CONTROL 0x018c +-#define ixPCIEMSIX_VECT25_ADDR_LO 0x0190 +-#define ixPCIEMSIX_VECT25_ADDR_HI 0x0194 +-#define ixPCIEMSIX_VECT25_MSG_DATA 0x0198 +-#define ixPCIEMSIX_VECT25_CONTROL 0x019c +-#define ixPCIEMSIX_VECT26_ADDR_LO 0x01a0 +-#define ixPCIEMSIX_VECT26_ADDR_HI 0x01a4 +-#define ixPCIEMSIX_VECT26_MSG_DATA 0x01a8 +-#define ixPCIEMSIX_VECT26_CONTROL 0x01ac +-#define ixPCIEMSIX_VECT27_ADDR_LO 0x01b0 +-#define ixPCIEMSIX_VECT27_ADDR_HI 0x01b4 +-#define ixPCIEMSIX_VECT27_MSG_DATA 0x01b8 +-#define ixPCIEMSIX_VECT27_CONTROL 0x01bc +-#define ixPCIEMSIX_VECT28_ADDR_LO 0x01c0 +-#define ixPCIEMSIX_VECT28_ADDR_HI 0x01c4 +-#define ixPCIEMSIX_VECT28_MSG_DATA 0x01c8 +-#define ixPCIEMSIX_VECT28_CONTROL 0x01cc +-#define ixPCIEMSIX_VECT29_ADDR_LO 0x01d0 +-#define ixPCIEMSIX_VECT29_ADDR_HI 0x01d4 +-#define ixPCIEMSIX_VECT29_MSG_DATA 0x01d8 +-#define ixPCIEMSIX_VECT29_CONTROL 0x01dc +-#define ixPCIEMSIX_VECT30_ADDR_LO 0x01e0 +-#define ixPCIEMSIX_VECT30_ADDR_HI 0x01e4 +-#define ixPCIEMSIX_VECT30_MSG_DATA 0x01e8 +-#define ixPCIEMSIX_VECT30_CONTROL 0x01ec +-#define ixPCIEMSIX_VECT31_ADDR_LO 0x01f0 +-#define ixPCIEMSIX_VECT31_ADDR_HI 0x01f4 +-#define ixPCIEMSIX_VECT31_MSG_DATA 0x01f8 +-#define ixPCIEMSIX_VECT31_CONTROL 0x01fc +- +- +-// addressBlock: pciemsix_amdgfx_MSIXPDEC +-// base address: 0x10171000 +-#define ixPCIEMSIX_PBA 0x0000 +- +- +-// addressBlock: syshub_mmreg_ind_syshubind +-// base address: 0x0 +-#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK 0x10000 // duplicate +-#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK 0x10004 // duplicate +-#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK 0x10008 // duplicate +-#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK 0x1000c // duplicate +-#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL 0x10010 // duplicate +-#define ixSYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL 0x10014 // duplicate +-#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL 0x10018 // duplicate +-#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL 0x1001c // duplicate +-#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL 0x10020 // duplicate +-#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL 0x10024 // duplicate +-#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL 0x10028 // duplicate +-#define ixSYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL 0x1002c // duplicate +-#define ixSYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL 0x10030 // duplicate +-#define ixSYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL 0x10034 // duplicate +-#define ixSYSHUBMMREGIND_SYSHUB_CG_CNTL 0x10300 // duplicate +-#define ixSYSHUBMMREGIND_SYSHUB_TRANS_IDLE 0x10308 // duplicate +-#define ixSYSHUBMMREGIND_SYSHUB_HP_TIMER 0x1030c // duplicate +-#define ixSYSHUBMMREGIND_SYSHUB_SCRATCH 0x10f00 // duplicate +-#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK 0x11000 // duplicate +-#define ixSYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK 0x11004 // duplicate +-#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK 0x11008 // duplicate +-#define ixSYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK 0x1100c // duplicate +-#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL 0x11010 // duplicate +-#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL 0x11014 // duplicate +-#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL 0x11018 // duplicate +-#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL 0x1101c // duplicate +-#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL 0x11020 // duplicate +-#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL 0x11024 // duplicate +-#define ixSYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL 0x11028 // duplicate +-#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL 0x1102c // duplicate +-#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL 0x11030 // duplicate +-#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL 0x11034 // duplicate +-#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL 0x11038 // duplicate +-#define ixSYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL 0x1103c // duplicate +- +-#endif +diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_sh_mask.h +deleted file mode 100644 +index c7518b8..0000000 +--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_sh_mask.h ++++ /dev/null +@@ -1,10281 +0,0 @@ +-/* +- * Copyright (C) 2017 Advanced Micro Devices, Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included +- * in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- */ +-#ifndef _nbif_6_1_SH_MASK_HEADER +-#define _nbif_6_1_SH_MASK_HEADER +- +- +-// addressBlock: bif_cfg_dev0_epf0_bifcfgdecp +-//VENDOR_ID +-#define VENDOR_ID__VENDOR_ID__SHIFT 0x0 +-//DEVICE_ID +-#define DEVICE_ID__DEVICE_ID__SHIFT 0x0 +-//COMMAND +-#define COMMAND__IO_ACCESS_EN__SHIFT 0x0 +-#define COMMAND__MEM_ACCESS_EN__SHIFT 0x1 +-#define COMMAND__BUS_MASTER_EN__SHIFT 0x2 +-#define COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 +-#define COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 +-#define COMMAND__PAL_SNOOP_EN__SHIFT 0x5 +-#define COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 +-#define COMMAND__AD_STEPPING__SHIFT 0x7 +-#define COMMAND__SERR_EN__SHIFT 0x8 +-#define COMMAND__FAST_B2B_EN__SHIFT 0x9 +-#define COMMAND__INT_DIS__SHIFT 0xa +-//STATUS +-#define STATUS__INT_STATUS__SHIFT 0x3 +-#define STATUS__CAP_LIST__SHIFT 0x4 +-#define STATUS__PCI_66_EN__SHIFT 0x5 +-#define STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +-#define STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +-#define STATUS__DEVSEL_TIMING__SHIFT 0x9 +-#define STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +-#define STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +-#define STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +-#define STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe +-#define STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +-//REVISION_ID +-#define REVISION_ID__MINOR_REV_ID__SHIFT 0x0 +-#define REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 +-//PROG_INTERFACE +-#define PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 +-//SUB_CLASS +-#define SUB_CLASS__SUB_CLASS__SHIFT 0x0 +-//BASE_CLASS +-#define BASE_CLASS__BASE_CLASS__SHIFT 0x0 +-//CACHE_LINE +-#define CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 +-//LATENCY +-#define LATENCY__LATENCY_TIMER__SHIFT 0x0 +-//HEADER +-#define HEADER__HEADER_TYPE__SHIFT 0x0 +-#define HEADER__DEVICE_TYPE__SHIFT 0x7 +-//BIST +-#define BIST__BIST_COMP__SHIFT 0x0 +-#define BIST__BIST_STRT__SHIFT 0x6 +-#define BIST__BIST_CAP__SHIFT 0x7 +-//BASE_ADDR_1 +-#define BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 +-//BASE_ADDR_2 +-#define BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 +-//BASE_ADDR_3 +-#define BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 +-//BASE_ADDR_4 +-#define BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 +-//BASE_ADDR_5 +-#define BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 +-//BASE_ADDR_6 +-#define BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 +-//ADAPTER_ID +-#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +-#define ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 +-//ROM_BASE_ADDR +-#define ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +-//CAP_PTR +-#define CAP_PTR__CAP_PTR__SHIFT 0x0 +-//INTERRUPT_LINE +-#define INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 +-//INTERRUPT_PIN +-#define INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 +-//MIN_GRANT +-#define MIN_GRANT__MIN_GNT__SHIFT 0x0 +-//MAX_LATENCY +-#define MAX_LATENCY__MAX_LAT__SHIFT 0x0 +-//VENDOR_CAP_LIST +-#define VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 +-#define VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 +-#define VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 +-//ADAPTER_ID_W +-#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +-#define ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 +-//PMI_CAP_LIST +-#define PMI_CAP_LIST__CAP_ID__SHIFT 0x0 +-#define PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +-//PMI_CAP +-#define PMI_CAP__VERSION__SHIFT 0x0 +-#define PMI_CAP__PME_CLOCK__SHIFT 0x3 +-#define PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 +-#define PMI_CAP__AUX_CURRENT__SHIFT 0x6 +-#define PMI_CAP__D1_SUPPORT__SHIFT 0x9 +-#define PMI_CAP__D2_SUPPORT__SHIFT 0xa +-#define PMI_CAP__PME_SUPPORT__SHIFT 0xb +-//PMI_STATUS_CNTL +-#define PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 +-#define PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 +-#define PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 +-#define PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 +-#define PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd +-#define PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf +-#define PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 +-#define PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 +-#define PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 +-//PCIE_CAP_LIST +-#define PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 +-#define PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 +-//PCIE_CAP +-#define PCIE_CAP__VERSION__SHIFT 0x0 +-#define PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 +-#define PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 +-#define PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 +-//DEVICE_CAP +-#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 +-#define DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 +-#define DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 +-#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 +-#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 +-#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf +-#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 +-#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a +-#define DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c +-//DEVICE_CNTL +-#define DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 +-#define DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 +-#define DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 +-#define DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 +-#define DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 +-#define DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 +-#define DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 +-#define DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 +-#define DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa +-#define DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb +-#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc +-#define DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf +-//DEVICE_STATUS +-#define DEVICE_STATUS__CORR_ERR__SHIFT 0x0 +-#define DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 +-#define DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 +-#define DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 +-#define DEVICE_STATUS__AUX_PWR__SHIFT 0x4 +-#define DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 +-//LINK_CAP +-#define LINK_CAP__LINK_SPEED__SHIFT 0x0 +-#define LINK_CAP__LINK_WIDTH__SHIFT 0x4 +-#define LINK_CAP__PM_SUPPORT__SHIFT 0xa +-#define LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc +-#define LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf +-#define LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 +-#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 +-#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 +-#define LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 +-#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 +-#define LINK_CAP__PORT_NUMBER__SHIFT 0x18 +-//LINK_CNTL +-#define LINK_CNTL__PM_CONTROL__SHIFT 0x0 +-#define LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 +-#define LINK_CNTL__LINK_DIS__SHIFT 0x4 +-#define LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 +-#define LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 +-#define LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 +-#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 +-#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 +-#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa +-#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb +-//LINK_STATUS +-#define LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 +-#define LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 +-#define LINK_STATUS__LINK_TRAINING__SHIFT 0xb +-#define LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc +-#define LINK_STATUS__DL_ACTIVE__SHIFT 0xd +-#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe +-#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf +-//DEVICE_CAP2 +-#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 +-#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 +-#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 +-#define DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 +-#define DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 +-#define DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 +-#define DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 +-#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa +-#define DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb +-#define DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc +-#define DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 +-#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 +-#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 +-#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 +-//DEVICE_CNTL2 +-#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 +-#define DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 +-#define DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 +-#define DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 +-#define DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 +-#define DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 +-#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 +-#define DEVICE_CNTL2__LTR_EN__SHIFT 0xa +-#define DEVICE_CNTL2__OBFF_EN__SHIFT 0xd +-#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf +-//DEVICE_STATUS2 +-#define DEVICE_STATUS2__RESERVED__SHIFT 0x0 +-//LINK_CAP2 +-#define LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 +-#define LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 +-#define LINK_CAP2__RESERVED__SHIFT 0x9 +-//LINK_CNTL2 +-#define LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 +-#define LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 +-#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 +-#define LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 +-#define LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 +-#define LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa +-#define LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb +-#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc +-//LINK_STATUS2 +-#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 +-#define LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 +-#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 +-#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 +-#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 +-#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 +-//SLOT_CAP2 +-#define SLOT_CAP2__RESERVED__SHIFT 0x0 +-//SLOT_CNTL2 +-#define SLOT_CNTL2__RESERVED__SHIFT 0x0 +-//SLOT_STATUS2 +-#define SLOT_STATUS2__RESERVED__SHIFT 0x0 +-//MSI_CAP_LIST +-#define MSI_CAP_LIST__CAP_ID__SHIFT 0x0 +-#define MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 +-//MSI_MSG_CNTL +-#define MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 +-#define MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 +-#define MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 +-#define MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 +-#define MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 +-//MSI_MSG_ADDR_LO +-#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 +-//MSI_MSG_ADDR_HI +-#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 +-//MSI_MSG_DATA +-#define MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 +-//MSI_MSG_DATA_64 +-#define MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 +-//MSI_MASK +-#define MSI_MASK__MSI_MASK__SHIFT 0x0 +-//MSI_PENDING +-#define MSI_PENDING__MSI_PENDING__SHIFT 0x0 +-//MSI_MASK_64 +-#define MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 +-//MSI_PENDING_64 +-#define MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 +-//MSIX_CAP_LIST +-#define MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 +-#define MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 +-//MSIX_MSG_CNTL +-#define MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 +-#define MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe +-#define MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf +-//MSIX_TABLE +-#define MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 +-#define MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 +-//MSIX_PBA +-#define MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 +-#define MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 +-//PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +-#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +-#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +-#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +-//PCIE_VENDOR_SPECIFIC_HDR +-#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 +-#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 +-#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 +-//PCIE_VENDOR_SPECIFIC1 +-#define PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 +-//PCIE_VENDOR_SPECIFIC2 +-#define PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 +-//PCIE_VC_ENH_CAP_LIST +-#define PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +-#define PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +-#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +-//PCIE_PORT_VC_CAP_REG1 +-#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 +-#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 +-#define PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 +-#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa +-//PCIE_PORT_VC_CAP_REG2 +-#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 +-#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 +-//PCIE_PORT_VC_CNTL +-#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 +-#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 +-//PCIE_PORT_VC_STATUS +-#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 +-//PCIE_VC0_RESOURCE_CAP +-#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +-#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +-#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +-#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +-//PCIE_VC0_RESOURCE_CNTL +-#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +-#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +-#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +-#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +-#define PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +-#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +-//PCIE_VC0_RESOURCE_STATUS +-#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +-#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +-//PCIE_VC1_RESOURCE_CAP +-#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 +-#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf +-#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 +-#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 +-//PCIE_VC1_RESOURCE_CNTL +-#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 +-#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 +-#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 +-#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 +-#define PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 +-#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f +-//PCIE_VC1_RESOURCE_STATUS +-#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 +-#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 +-//PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +-#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +-#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +-#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +-//PCIE_DEV_SERIAL_NUM_DW1 +-#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 +-//PCIE_DEV_SERIAL_NUM_DW2 +-#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 +-//PCIE_ADV_ERR_RPT_ENH_CAP_LIST +-#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +-#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +-#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +-//PCIE_UNCORR_ERR_STATUS +-#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 +-#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 +-#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc +-#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd +-#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe +-#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf +-#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 +-#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 +-#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 +-#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 +-#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 +-#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 +-#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 +-#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 +-#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 +-#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 +-//PCIE_UNCORR_ERR_MASK +-#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 +-#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 +-#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc +-#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd +-#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe +-#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf +-#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 +-#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 +-#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 +-#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 +-#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 +-#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 +-#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 +-#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 +-#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 +-#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 +-//PCIE_UNCORR_ERR_SEVERITY +-#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 +-#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 +-#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc +-#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd +-#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe +-#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf +-#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 +-#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 +-#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 +-#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 +-#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 +-#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 +-#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 +-#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 +-#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 +-#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 +-//PCIE_CORR_ERR_STATUS +-#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 +-#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 +-#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 +-#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 +-#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc +-#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd +-#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe +-#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf +-//PCIE_CORR_ERR_MASK +-#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 +-#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 +-#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 +-#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 +-#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc +-#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd +-#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe +-#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf +-//PCIE_ADV_ERR_CAP_CNTL +-#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 +-#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 +-#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 +-#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 +-#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 +-#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 +-#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa +-#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb +-//PCIE_HDR_LOG0 +-#define PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 +-//PCIE_HDR_LOG1 +-#define PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 +-//PCIE_HDR_LOG2 +-#define PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 +-//PCIE_HDR_LOG3 +-#define PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 +-//PCIE_ROOT_ERR_CMD +-#define PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 +-#define PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 +-#define PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 +-//PCIE_ROOT_ERR_STATUS +-#define PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 +-#define PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 +-#define PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 +-#define PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 +-#define PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 +-#define PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 +-#define PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 +-#define PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b +-//PCIE_ERR_SRC_ID +-#define PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 +-#define PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 +-//PCIE_TLP_PREFIX_LOG0 +-#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 +-//PCIE_TLP_PREFIX_LOG1 +-#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 +-//PCIE_TLP_PREFIX_LOG2 +-#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 +-//PCIE_TLP_PREFIX_LOG3 +-#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 +-//PCIE_BAR_ENH_CAP_LIST +-#define PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +-#define PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +-#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +-//PCIE_BAR1_CAP +-#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +-//PCIE_BAR1_CNTL +-#define PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 +-#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +-#define PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 +-//PCIE_BAR2_CAP +-#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +-//PCIE_BAR2_CNTL +-#define PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 +-#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +-#define PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 +-//PCIE_BAR3_CAP +-#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +-//PCIE_BAR3_CNTL +-#define PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 +-#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +-#define PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 +-//PCIE_BAR4_CAP +-#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +-//PCIE_BAR4_CNTL +-#define PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 +-#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +-#define PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 +-//PCIE_BAR5_CAP +-#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +-//PCIE_BAR5_CNTL +-#define PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 +-#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +-#define PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 +-//PCIE_BAR6_CAP +-#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 +-//PCIE_BAR6_CNTL +-#define PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 +-#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 +-#define PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 +-//PCIE_PWR_BUDGET_ENH_CAP_LIST +-#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +-#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +-#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +-//PCIE_PWR_BUDGET_DATA_SELECT +-#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 +-//PCIE_PWR_BUDGET_DATA +-#define PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 +-#define PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 +-#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa +-#define PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd +-#define PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf +-#define PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 +-//PCIE_PWR_BUDGET_CAP +-#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 +-//PCIE_DPA_ENH_CAP_LIST +-#define PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +-#define PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +-#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +-//PCIE_DPA_CAP +-#define PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 +-#define PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +-#define PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +-#define PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +-#define PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +-//PCIE_DPA_LATENCY_INDICATOR +-#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +-//PCIE_DPA_STATUS +-#define PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 +-#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 +-//PCIE_DPA_CNTL +-#define PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 +-//PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +-#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +-//PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +-#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +-//PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +-#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +-//PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +-#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +-//PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +-#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +-//PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +-#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +-//PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +-#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +-//PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +-#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +-//PCIE_SECONDARY_ENH_CAP_LIST +-#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +-#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +-#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +-//PCIE_LINK_CNTL3 +-#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 +-#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 +-#define PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 +-//PCIE_LANE_ERROR_STATUS +-#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 +-#define PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 +-//PCIE_LANE_0_EQUALIZATION_CNTL +-#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +-#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +-#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +-#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +-#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +-//PCIE_LANE_1_EQUALIZATION_CNTL +-#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +-#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +-#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +-#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +-#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +-//PCIE_LANE_2_EQUALIZATION_CNTL +-#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +-#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +-#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +-#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +-#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +-//PCIE_LANE_3_EQUALIZATION_CNTL +-#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +-#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +-#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +-#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +-#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +-//PCIE_LANE_4_EQUALIZATION_CNTL +-#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +-#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +-#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +-#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +-#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +-//PCIE_LANE_5_EQUALIZATION_CNTL +-#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +-#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +-#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +-#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +-#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +-//PCIE_LANE_6_EQUALIZATION_CNTL +-#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +-#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +-#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +-#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +-#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +-//PCIE_LANE_7_EQUALIZATION_CNTL +-#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +-#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +-#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +-#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +-#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +-//PCIE_LANE_8_EQUALIZATION_CNTL +-#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +-#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +-#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +-#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +-#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +-//PCIE_LANE_9_EQUALIZATION_CNTL +-#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +-#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +-#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +-#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +-#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +-//PCIE_LANE_10_EQUALIZATION_CNTL +-#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +-#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +-#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +-#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +-#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +-//PCIE_LANE_11_EQUALIZATION_CNTL +-#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +-#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +-#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +-#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +-#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +-//PCIE_LANE_12_EQUALIZATION_CNTL +-#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +-#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +-#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +-#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +-#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +-//PCIE_LANE_13_EQUALIZATION_CNTL +-#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +-#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +-#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +-#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +-#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +-//PCIE_LANE_14_EQUALIZATION_CNTL +-#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +-#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +-#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +-#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +-#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +-//PCIE_LANE_15_EQUALIZATION_CNTL +-#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 +-#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 +-#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 +-#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc +-#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf +-//PCIE_ACS_ENH_CAP_LIST +-#define PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +-#define PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +-#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +-//PCIE_ACS_CAP +-#define PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 +-#define PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 +-#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 +-#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 +-#define PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 +-#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 +-#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 +-#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 +-//PCIE_ACS_CNTL +-#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 +-#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 +-#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 +-#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 +-#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 +-#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 +-#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 +-//PCIE_ATS_ENH_CAP_LIST +-#define PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +-#define PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +-#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +-//PCIE_ATS_CAP +-#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 +-#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 +-#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 +-//PCIE_ATS_CNTL +-#define PCIE_ATS_CNTL__STU__SHIFT 0x0 +-#define PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf +-//PCIE_PAGE_REQ_ENH_CAP_LIST +-#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +-#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +-#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +-//PCIE_PAGE_REQ_CNTL +-#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 +-#define PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 +-//PCIE_PAGE_REQ_STATUS +-#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 +-#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 +-#define PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 +-#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf +-//PCIE_OUTSTAND_PAGE_REQ_CAPACITY +-#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 +-//PCIE_OUTSTAND_PAGE_REQ_ALLOC +-#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 +-//PCIE_PASID_ENH_CAP_LIST +-#define PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +-#define PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +-#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +-//PCIE_PASID_CAP +-#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 +-#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 +-#define PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 +-//PCIE_PASID_CNTL +-#define PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 +-#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 +-#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 +-//PCIE_TPH_REQR_ENH_CAP_LIST +-#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +-#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +-#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +-//PCIE_TPH_REQR_CAP +-#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0 +-#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1 +-#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2 +-#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8 +-#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9 +-#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10 +-//PCIE_TPH_REQR_CNTL +-#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0 +-#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8 +-//PCIE_MC_ENH_CAP_LIST +-#define PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +-#define PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +-#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +-//PCIE_MC_CAP +-#define PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 +-#define PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 +-#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf +-//PCIE_MC_CNTL +-#define PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 +-#define PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf +-//PCIE_MC_ADDR0 +-#define PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 +-#define PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc +-//PCIE_MC_ADDR1 +-#define PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 +-//PCIE_MC_RCV0 +-#define PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 +-//PCIE_MC_RCV1 +-#define PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 +-//PCIE_MC_BLOCK_ALL0 +-#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 +-//PCIE_MC_BLOCK_ALL1 +-#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 +-//PCIE_MC_BLOCK_UNTRANSLATED_0 +-#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 +-//PCIE_MC_BLOCK_UNTRANSLATED_1 +-#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 +-//PCIE_LTR_ENH_CAP_LIST +-#define PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +-#define PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +-#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +-//PCIE_LTR_CAP +-#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 +-#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa +-#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 +-#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a +-//PCIE_ARI_ENH_CAP_LIST +-#define PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +-#define PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +-#define PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +-//PCIE_ARI_CAP +-#define PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 +-#define PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 +-#define PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 +-//PCIE_ARI_CNTL +-#define PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 +-#define PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 +-#define PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 +-//PCIE_SRIOV_ENH_CAP_LIST +-#define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 +-#define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 +-#define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 +-//PCIE_SRIOV_CAP +-#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 +-#define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 +-#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 +-//PCIE_SRIOV_CONTROL +-#define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 +-#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 +-#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 +-#define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 +-#define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 +-//PCIE_SRIOV_STATUS +-#define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 +-//PCIE_SRIOV_INITIAL_VFS +-#define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 +-//PCIE_SRIOV_TOTAL_VFS +-#define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 +-//PCIE_SRIOV_NUM_VFS +-#define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 +-//PCIE_SRIOV_FUNC_DEP_LINK +-#define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 +-//PCIE_SRIOV_FIRST_VF_OFFSET +-#define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 +-//PCIE_SRIOV_VF_STRIDE +-#define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 +-//PCIE_SRIOV_VF_DEVICE_ID +-#define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 +-//PCIE_SRIOV_SUPPORTED_PAGE_SIZE +-#define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 +-//PCIE_SRIOV_SYSTEM_PAGE_SIZE +-#define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 +-//PCIE_SRIOV_VF_BASE_ADDR_0 +-#define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 +-//PCIE_SRIOV_VF_BASE_ADDR_1 +-#define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 +-//PCIE_SRIOV_VF_BASE_ADDR_2 +-#define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 +-//PCIE_SRIOV_VF_BASE_ADDR_3 +-#define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 +-//PCIE_SRIOV_VF_BASE_ADDR_4 +-#define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 +-//PCIE_SRIOV_VF_BASE_ADDR_5 +-#define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 +-//PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET +-#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT 0x0 +-#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 +-//PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV +-#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0 +-#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10 +-#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x0 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0 +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0 +- +- +-// addressBlock: bif_cfg_dev0_swds_bifcfgdecp +-//SUB_BUS_NUMBER_LATENCY +-#define SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 +-#define SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 +-#define SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 +-#define SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 +-//IO_BASE_LIMIT +-#define IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 +-#define IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 +-#define IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 +-#define IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc +-//SECONDARY_STATUS +-#define SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 +-#define SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 +-#define SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 +-#define SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 +-#define SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 +-#define SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb +-#define SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc +-#define SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd +-#define SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe +-#define SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf +-//MEM_BASE_LIMIT +-#define MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +-#define MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 +-#define MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +-#define MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 +-//PREF_BASE_LIMIT +-#define PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +-#define PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 +-#define PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +-#define PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 +-//PREF_BASE_UPPER +-#define PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 +-//PREF_LIMIT_UPPER +-#define PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 +-//IO_BASE_LIMIT_HI +-#define IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 +-#define IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 +-//IRQ_BRIDGE_CNTL +-#define IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 +-#define IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 +-#define IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 +-#define IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 +-#define IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 +-#define IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 +-#define IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 +-#define IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 +-//SLOT_CAP +-#define SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 +-#define SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 +-#define SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 +-#define SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 +-#define SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 +-#define SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 +-#define SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 +-#define SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 +-#define SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf +-#define SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 +-#define SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 +-#define SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 +-//SLOT_CNTL +-#define SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 +-#define SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 +-#define SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 +-#define SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 +-#define SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 +-#define SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 +-#define SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 +-#define SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 +-#define SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa +-#define SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb +-#define SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc +-//SLOT_STATUS +-#define SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 +-#define SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 +-#define SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 +-#define SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 +-#define SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 +-#define SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 +-#define SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 +-#define SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 +-#define SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 +-//SSID_CAP_LIST +-#define SSID_CAP_LIST__CAP_ID__SHIFT 0x0 +-#define SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 +-//SSID_CAP +-#define SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 +-#define SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 +- +- +-// addressBlock: rcc_shadow_reg_shadowdec +-//SHADOW_COMMAND +-#define SHADOW_COMMAND__IOEN_UP__SHIFT 0x0 +-#define SHADOW_COMMAND__MEMEN_UP__SHIFT 0x1 +-//SHADOW_BASE_ADDR_1 +-#define SHADOW_BASE_ADDR_1__BAR1_UP__SHIFT 0x0 +-//SHADOW_BASE_ADDR_2 +-#define SHADOW_BASE_ADDR_2__BAR2_UP__SHIFT 0x0 +-//SHADOW_SUB_BUS_NUMBER_LATENCY +-#define SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP__SHIFT 0x8 +-#define SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP__SHIFT 0x10 +-//SHADOW_IO_BASE_LIMIT +-#define SHADOW_IO_BASE_LIMIT__IO_BASE_UP__SHIFT 0x4 +-#define SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP__SHIFT 0xc +-//SHADOW_MEM_BASE_LIMIT +-#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 +-#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP__SHIFT 0x4 +-#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 +-#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP__SHIFT 0x14 +-//SHADOW_PREF_BASE_LIMIT +-#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 +-#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP__SHIFT 0x4 +-#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 +-#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP__SHIFT 0x14 +-//SHADOW_PREF_BASE_UPPER +-#define SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP__SHIFT 0x0 +-//SHADOW_PREF_LIMIT_UPPER +-#define SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP__SHIFT 0x0 +-//SHADOW_IO_BASE_LIMIT_HI +-#define SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP__SHIFT 0x0 +-#define SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP__SHIFT 0x10 +-//SHADOW_IRQ_BRIDGE_CNTL +-#define SHADOW_IRQ_BRIDGE_CNTL__ISA_EN_UP__SHIFT 0x2 +-#define SHADOW_IRQ_BRIDGE_CNTL__VGA_EN_UP__SHIFT 0x3 +-#define SHADOW_IRQ_BRIDGE_CNTL__VGA_DEC_UP__SHIFT 0x4 +-#define SHADOW_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_UP__SHIFT 0x6 +-//SUC_INDEX +-#define SUC_INDEX__SUC_INDEX__SHIFT 0x0 +-//SUC_DATA +-#define SUC_DATA__SUC_DATA__SHIFT 0x0 +- +- +-// addressBlock: bif_bx_pf_SUMDEC +-//SUM_INDEX +-#define SUM_INDEX__SUM_INDEX__SHIFT 0x0 +-//SUM_DATA +-#define SUM_DATA__SUM_DATA__SHIFT 0x0 +- +- +-// addressBlock: gdc_GDCDEC +-//A2S_CNTL_CL0 +-#define A2S_CNTL_CL0__NSNOOP_MAP__SHIFT 0x0 +-#define A2S_CNTL_CL0__REQPASSPW_VC0_MAP__SHIFT 0x2 +-#define A2S_CNTL_CL0__REQPASSPW_NVC0_MAP__SHIFT 0x4 +-#define A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP__SHIFT 0x6 +-#define A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8 +-#define A2S_CNTL_CL0__BLKLVL_MAP__SHIFT 0xa +-#define A2S_CNTL_CL0__DATERR_MAP__SHIFT 0xc +-#define A2S_CNTL_CL0__EXOKAY_WR_MAP__SHIFT 0xe +-#define A2S_CNTL_CL0__EXOKAY_RD_MAP__SHIFT 0x10 +-#define A2S_CNTL_CL0__RESP_WR_MAP__SHIFT 0x12 +-#define A2S_CNTL_CL0__RESP_RD_MAP__SHIFT 0x14 +-//A2S_CNTL_CL1 +-#define A2S_CNTL_CL1__NSNOOP_MAP__SHIFT 0x0 +-#define A2S_CNTL_CL1__REQPASSPW_VC0_MAP__SHIFT 0x2 +-#define A2S_CNTL_CL1__REQPASSPW_NVC0_MAP__SHIFT 0x4 +-#define A2S_CNTL_CL1__REQRSPPASSPW_VC0_MAP__SHIFT 0x6 +-#define A2S_CNTL_CL1__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8 +-#define A2S_CNTL_CL1__BLKLVL_MAP__SHIFT 0xa +-#define A2S_CNTL_CL1__DATERR_MAP__SHIFT 0xc +-#define A2S_CNTL_CL1__EXOKAY_WR_MAP__SHIFT 0xe +-#define A2S_CNTL_CL1__EXOKAY_RD_MAP__SHIFT 0x10 +-#define A2S_CNTL_CL1__RESP_WR_MAP__SHIFT 0x12 +-#define A2S_CNTL_CL1__RESP_RD_MAP__SHIFT 0x14 +-//A2S_CNTL_CL2 +-#define A2S_CNTL_CL2__NSNOOP_MAP__SHIFT 0x0 +-#define A2S_CNTL_CL2__REQPASSPW_VC0_MAP__SHIFT 0x2 +-#define A2S_CNTL_CL2__REQPASSPW_NVC0_MAP__SHIFT 0x4 +-#define A2S_CNTL_CL2__REQRSPPASSPW_VC0_MAP__SHIFT 0x6 +-#define A2S_CNTL_CL2__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8 +-#define A2S_CNTL_CL2__BLKLVL_MAP__SHIFT 0xa +-#define A2S_CNTL_CL2__DATERR_MAP__SHIFT 0xc +-#define A2S_CNTL_CL2__EXOKAY_WR_MAP__SHIFT 0xe +-#define A2S_CNTL_CL2__EXOKAY_RD_MAP__SHIFT 0x10 +-#define A2S_CNTL_CL2__RESP_WR_MAP__SHIFT 0x12 +-#define A2S_CNTL_CL2__RESP_RD_MAP__SHIFT 0x14 +-//A2S_CNTL_CL3 +-#define A2S_CNTL_CL3__NSNOOP_MAP__SHIFT 0x0 +-#define A2S_CNTL_CL3__REQPASSPW_VC0_MAP__SHIFT 0x2 +-#define A2S_CNTL_CL3__REQPASSPW_NVC0_MAP__SHIFT 0x4 +-#define A2S_CNTL_CL3__REQRSPPASSPW_VC0_MAP__SHIFT 0x6 +-#define A2S_CNTL_CL3__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8 +-#define A2S_CNTL_CL3__BLKLVL_MAP__SHIFT 0xa +-#define A2S_CNTL_CL3__DATERR_MAP__SHIFT 0xc +-#define A2S_CNTL_CL3__EXOKAY_WR_MAP__SHIFT 0xe +-#define A2S_CNTL_CL3__EXOKAY_RD_MAP__SHIFT 0x10 +-#define A2S_CNTL_CL3__RESP_WR_MAP__SHIFT 0x12 +-#define A2S_CNTL_CL3__RESP_RD_MAP__SHIFT 0x14 +-//A2S_CNTL_CL4 +-#define A2S_CNTL_CL4__NSNOOP_MAP__SHIFT 0x0 +-#define A2S_CNTL_CL4__REQPASSPW_VC0_MAP__SHIFT 0x2 +-#define A2S_CNTL_CL4__REQPASSPW_NVC0_MAP__SHIFT 0x4 +-#define A2S_CNTL_CL4__REQRSPPASSPW_VC0_MAP__SHIFT 0x6 +-#define A2S_CNTL_CL4__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8 +-#define A2S_CNTL_CL4__BLKLVL_MAP__SHIFT 0xa +-#define A2S_CNTL_CL4__DATERR_MAP__SHIFT 0xc +-#define A2S_CNTL_CL4__EXOKAY_WR_MAP__SHIFT 0xe +-#define A2S_CNTL_CL4__EXOKAY_RD_MAP__SHIFT 0x10 +-#define A2S_CNTL_CL4__RESP_WR_MAP__SHIFT 0x12 +-#define A2S_CNTL_CL4__RESP_RD_MAP__SHIFT 0x14 +-//A2S_CNTL_SW0 +-#define A2S_CNTL_SW0__WR_TAG_SET_MIN__SHIFT 0x0 +-#define A2S_CNTL_SW0__RD_TAG_SET_MIN__SHIFT 0x3 +-#define A2S_CNTL_SW0__FORCE_RSP_REORDER_EN__SHIFT 0x6 +-#define A2S_CNTL_SW0__RSP_REORDER_DIS__SHIFT 0x7 +-#define A2S_CNTL_SW0__WRRSP_ACCUM_SEL__SHIFT 0x8 +-#define A2S_CNTL_SW0__SDP_WR_CHAIN_DIS__SHIFT 0x9 +-#define A2S_CNTL_SW0__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0xa +-#define A2S_CNTL_SW0__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0xb +-#define A2S_CNTL_SW0__RDRSP_STS_DATSTS_PRIORITY__SHIFT 0xc +-#define A2S_CNTL_SW0__WRR_RD_WEIGHT__SHIFT 0x10 +-#define A2S_CNTL_SW0__WRR_WR_WEIGHT__SHIFT 0x18 +-//A2S_CNTL_SW1 +-#define A2S_CNTL_SW1__WR_TAG_SET_MIN__SHIFT 0x0 +-#define A2S_CNTL_SW1__RD_TAG_SET_MIN__SHIFT 0x3 +-#define A2S_CNTL_SW1__FORCE_RSP_REORDER_EN__SHIFT 0x6 +-#define A2S_CNTL_SW1__RSP_REORDER_DIS__SHIFT 0x7 +-#define A2S_CNTL_SW1__WRRSP_ACCUM_SEL__SHIFT 0x8 +-#define A2S_CNTL_SW1__SDP_WR_CHAIN_DIS__SHIFT 0x9 +-#define A2S_CNTL_SW1__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0xa +-#define A2S_CNTL_SW1__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0xb +-#define A2S_CNTL_SW1__RDRSP_STS_DATSTS_PRIORITY__SHIFT 0xc +-#define A2S_CNTL_SW1__WRR_RD_WEIGHT__SHIFT 0x10 +-#define A2S_CNTL_SW1__WRR_WR_WEIGHT__SHIFT 0x18 +-//A2S_CNTL_SW2 +-#define A2S_CNTL_SW2__WR_TAG_SET_MIN__SHIFT 0x0 +-#define A2S_CNTL_SW2__RD_TAG_SET_MIN__SHIFT 0x3 +-#define A2S_CNTL_SW2__FORCE_RSP_REORDER_EN__SHIFT 0x6 +-#define A2S_CNTL_SW2__RSP_REORDER_DIS__SHIFT 0x7 +-#define A2S_CNTL_SW2__WRRSP_ACCUM_SEL__SHIFT 0x8 +-#define A2S_CNTL_SW2__SDP_WR_CHAIN_DIS__SHIFT 0x9 +-#define A2S_CNTL_SW2__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0xa +-#define A2S_CNTL_SW2__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0xb +-#define A2S_CNTL_SW2__RDRSP_STS_DATSTS_PRIORITY__SHIFT 0xc +-#define A2S_CNTL_SW2__WRR_RD_WEIGHT__SHIFT 0x10 +-#define A2S_CNTL_SW2__WRR_WR_WEIGHT__SHIFT 0x18 +-//NGDC_MGCG_CTRL +-#define NGDC_MGCG_CTRL__NGDC_MGCG_EN__SHIFT 0x0 +-#define NGDC_MGCG_CTRL__NGDC_MGCG_MODE__SHIFT 0x1 +-#define NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__SHIFT 0x2 +-//A2S_MISC_CNTL +-#define A2S_MISC_CNTL__BLKLVL_FOR_MSG__SHIFT 0x0 +-#define A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS__SHIFT 0x2 +-//NGDC_SDP_PORT_CTRL +-#define NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT 0x0 +-//NGDC_RESERVED_0 +-#define NGDC_RESERVED_0__RESERVED__SHIFT 0x0 +-//NGDC_RESERVED_1 +-#define NGDC_RESERVED_1__RESERVED__SHIFT 0x0 +-//BIF_SDMA0_DOORBELL_RANGE +-#define BIF_SDMA0_DOORBELL_RANGE__OFFSET__SHIFT 0x2 +-#define BIF_SDMA0_DOORBELL_RANGE__SIZE__SHIFT 0x10 +-//BIF_SDMA1_DOORBELL_RANGE +-#define BIF_SDMA1_DOORBELL_RANGE__OFFSET__SHIFT 0x2 +-#define BIF_SDMA1_DOORBELL_RANGE__SIZE__SHIFT 0x10 +-//BIF_IH_DOORBELL_RANGE +-#define BIF_IH_DOORBELL_RANGE__OFFSET__SHIFT 0x2 +-#define BIF_IH_DOORBELL_RANGE__SIZE__SHIFT 0x10 +-//BIF_MMSCH0_DOORBELL_RANGE +-#define BIF_MMSCH0_DOORBELL_RANGE__OFFSET__SHIFT 0x2 +-#define BIF_MMSCH0_DOORBELL_RANGE__SIZE__SHIFT 0x10 +-//BIF_DOORBELL_FENCE_CNTL +-#define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE__SHIFT 0x0 +-//S2A_MISC_CNTL +-#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__SHIFT 0x0 +-#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__SHIFT 0x1 +-#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__SHIFT 0x2 +-//A2S_CNTL2_SEC_CL0 +-#define A2S_CNTL2_SEC_CL0__SECLVL_MAP__SHIFT 0x0 +-//A2S_CNTL2_SEC_CL1 +-#define A2S_CNTL2_SEC_CL1__SECLVL_MAP__SHIFT 0x0 +-//A2S_CNTL2_SEC_CL2 +-#define A2S_CNTL2_SEC_CL2__SECLVL_MAP__SHIFT 0x0 +-//A2S_CNTL2_SEC_CL3 +-#define A2S_CNTL2_SEC_CL3__SECLVL_MAP__SHIFT 0x0 +-//A2S_CNTL2_SEC_CL4 +-#define A2S_CNTL2_SEC_CL4__SECLVL_MAP__SHIFT 0x0 +- +- +-// addressBlock: nbif_sion_SIONDEC +-//SION_CL0_RdRsp_BurstTarget_REG0 +-#define SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 +-//SION_CL0_RdRsp_BurstTarget_REG1 +-#define SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 +-//SION_CL0_RdRsp_TimeSlot_REG0 +-#define SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 +-//SION_CL0_RdRsp_TimeSlot_REG1 +-#define SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 +-//SION_CL0_WrRsp_BurstTarget_REG0 +-#define SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 +-//SION_CL0_WrRsp_BurstTarget_REG1 +-#define SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 +-//SION_CL0_WrRsp_TimeSlot_REG0 +-#define SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 +-//SION_CL0_WrRsp_TimeSlot_REG1 +-#define SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 +-//SION_CL0_Req_BurstTarget_REG0 +-#define SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 +-//SION_CL0_Req_BurstTarget_REG1 +-#define SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 +-//SION_CL0_Req_TimeSlot_REG0 +-#define SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 +-//SION_CL0_Req_TimeSlot_REG1 +-#define SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 +-//SION_CL0_ReqPoolCredit_Alloc_REG0 +-#define SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 +-//SION_CL0_ReqPoolCredit_Alloc_REG1 +-#define SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 +-//SION_CL0_DataPoolCredit_Alloc_REG0 +-#define SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 +-//SION_CL0_DataPoolCredit_Alloc_REG1 +-#define SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 +-//SION_CL0_RdRspPoolCredit_Alloc_REG0 +-#define SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 +-//SION_CL0_RdRspPoolCredit_Alloc_REG1 +-#define SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 +-//SION_CL0_WrRspPoolCredit_Alloc_REG0 +-#define SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 +-//SION_CL0_WrRspPoolCredit_Alloc_REG1 +-#define SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 +-//SION_CL1_RdRsp_BurstTarget_REG0 +-#define SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 +-//SION_CL1_RdRsp_BurstTarget_REG1 +-#define SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 +-//SION_CL1_RdRsp_TimeSlot_REG0 +-#define SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 +-//SION_CL1_RdRsp_TimeSlot_REG1 +-#define SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 +-//SION_CL1_WrRsp_BurstTarget_REG0 +-#define SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 +-//SION_CL1_WrRsp_BurstTarget_REG1 +-#define SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 +-//SION_CL1_WrRsp_TimeSlot_REG0 +-#define SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 +-//SION_CL1_WrRsp_TimeSlot_REG1 +-#define SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 +-//SION_CL1_Req_BurstTarget_REG0 +-#define SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 +-//SION_CL1_Req_BurstTarget_REG1 +-#define SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 +-//SION_CL1_Req_TimeSlot_REG0 +-#define SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 +-//SION_CL1_Req_TimeSlot_REG1 +-#define SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 +-//SION_CL1_ReqPoolCredit_Alloc_REG0 +-#define SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 +-//SION_CL1_ReqPoolCredit_Alloc_REG1 +-#define SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 +-//SION_CL1_DataPoolCredit_Alloc_REG0 +-#define SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 +-//SION_CL1_DataPoolCredit_Alloc_REG1 +-#define SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 +-//SION_CL1_RdRspPoolCredit_Alloc_REG0 +-#define SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 +-//SION_CL1_RdRspPoolCredit_Alloc_REG1 +-#define SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 +-//SION_CL1_WrRspPoolCredit_Alloc_REG0 +-#define SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 +-//SION_CL1_WrRspPoolCredit_Alloc_REG1 +-#define SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 +-//SION_CL2_RdRsp_BurstTarget_REG0 +-#define SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 +-//SION_CL2_RdRsp_BurstTarget_REG1 +-#define SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 +-//SION_CL2_RdRsp_TimeSlot_REG0 +-#define SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 +-//SION_CL2_RdRsp_TimeSlot_REG1 +-#define SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 +-//SION_CL2_WrRsp_BurstTarget_REG0 +-#define SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 +-//SION_CL2_WrRsp_BurstTarget_REG1 +-#define SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 +-//SION_CL2_WrRsp_TimeSlot_REG0 +-#define SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 +-//SION_CL2_WrRsp_TimeSlot_REG1 +-#define SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 +-//SION_CL2_Req_BurstTarget_REG0 +-#define SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 +-//SION_CL2_Req_BurstTarget_REG1 +-#define SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 +-//SION_CL2_Req_TimeSlot_REG0 +-#define SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 +-//SION_CL2_Req_TimeSlot_REG1 +-#define SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 +-//SION_CL2_ReqPoolCredit_Alloc_REG0 +-#define SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 +-//SION_CL2_ReqPoolCredit_Alloc_REG1 +-#define SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 +-//SION_CL2_DataPoolCredit_Alloc_REG0 +-#define SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 +-//SION_CL2_DataPoolCredit_Alloc_REG1 +-#define SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 +-//SION_CL2_RdRspPoolCredit_Alloc_REG0 +-#define SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 +-//SION_CL2_RdRspPoolCredit_Alloc_REG1 +-#define SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 +-//SION_CL2_WrRspPoolCredit_Alloc_REG0 +-#define SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 +-//SION_CL2_WrRspPoolCredit_Alloc_REG1 +-#define SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 +-//SION_CL3_RdRsp_BurstTarget_REG0 +-#define SION_CL3_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 +-//SION_CL3_RdRsp_BurstTarget_REG1 +-#define SION_CL3_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 +-//SION_CL3_RdRsp_TimeSlot_REG0 +-#define SION_CL3_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 +-//SION_CL3_RdRsp_TimeSlot_REG1 +-#define SION_CL3_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 +-//SION_CL3_WrRsp_BurstTarget_REG0 +-#define SION_CL3_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 +-//SION_CL3_WrRsp_BurstTarget_REG1 +-#define SION_CL3_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 +-//SION_CL3_WrRsp_TimeSlot_REG0 +-#define SION_CL3_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 +-//SION_CL3_WrRsp_TimeSlot_REG1 +-#define SION_CL3_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 +-//SION_CL3_Req_BurstTarget_REG0 +-#define SION_CL3_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 +-//SION_CL3_Req_BurstTarget_REG1 +-#define SION_CL3_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 +-//SION_CL3_Req_TimeSlot_REG0 +-#define SION_CL3_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 +-//SION_CL3_Req_TimeSlot_REG1 +-#define SION_CL3_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 +-//SION_CL3_ReqPoolCredit_Alloc_REG0 +-#define SION_CL3_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 +-//SION_CL3_ReqPoolCredit_Alloc_REG1 +-#define SION_CL3_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 +-//SION_CL3_DataPoolCredit_Alloc_REG0 +-#define SION_CL3_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 +-//SION_CL3_DataPoolCredit_Alloc_REG1 +-#define SION_CL3_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 +-//SION_CL3_RdRspPoolCredit_Alloc_REG0 +-#define SION_CL3_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 +-//SION_CL3_RdRspPoolCredit_Alloc_REG1 +-#define SION_CL3_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 +-//SION_CL3_WrRspPoolCredit_Alloc_REG0 +-#define SION_CL3_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 +-//SION_CL3_WrRspPoolCredit_Alloc_REG1 +-#define SION_CL3_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 +-//SION_CL4_RdRsp_BurstTarget_REG0 +-#define SION_CL4_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 +-//SION_CL4_RdRsp_BurstTarget_REG1 +-#define SION_CL4_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 +-//SION_CL4_RdRsp_TimeSlot_REG0 +-#define SION_CL4_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 +-//SION_CL4_RdRsp_TimeSlot_REG1 +-#define SION_CL4_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 +-//SION_CL4_WrRsp_BurstTarget_REG0 +-#define SION_CL4_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 +-//SION_CL4_WrRsp_BurstTarget_REG1 +-#define SION_CL4_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 +-//SION_CL4_WrRsp_TimeSlot_REG0 +-#define SION_CL4_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 +-//SION_CL4_WrRsp_TimeSlot_REG1 +-#define SION_CL4_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 +-//SION_CL4_Req_BurstTarget_REG0 +-#define SION_CL4_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 +-//SION_CL4_Req_BurstTarget_REG1 +-#define SION_CL4_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 +-//SION_CL4_Req_TimeSlot_REG0 +-#define SION_CL4_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 +-//SION_CL4_Req_TimeSlot_REG1 +-#define SION_CL4_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 +-//SION_CL4_ReqPoolCredit_Alloc_REG0 +-#define SION_CL4_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 +-//SION_CL4_ReqPoolCredit_Alloc_REG1 +-#define SION_CL4_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 +-//SION_CL4_DataPoolCredit_Alloc_REG0 +-#define SION_CL4_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 +-//SION_CL4_DataPoolCredit_Alloc_REG1 +-#define SION_CL4_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 +-//SION_CL4_RdRspPoolCredit_Alloc_REG0 +-#define SION_CL4_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 +-//SION_CL4_RdRspPoolCredit_Alloc_REG1 +-#define SION_CL4_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 +-//SION_CL4_WrRspPoolCredit_Alloc_REG0 +-#define SION_CL4_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 +-//SION_CL4_WrRspPoolCredit_Alloc_REG1 +-#define SION_CL4_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 +-//SION_CL5_RdRsp_BurstTarget_REG0 +-#define SION_CL5_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 +-//SION_CL5_RdRsp_BurstTarget_REG1 +-#define SION_CL5_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 +-//SION_CL5_RdRsp_TimeSlot_REG0 +-#define SION_CL5_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 +-//SION_CL5_RdRsp_TimeSlot_REG1 +-#define SION_CL5_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 +-//SION_CL5_WrRsp_BurstTarget_REG0 +-#define SION_CL5_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 +-//SION_CL5_WrRsp_BurstTarget_REG1 +-#define SION_CL5_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 +-//SION_CL5_WrRsp_TimeSlot_REG0 +-#define SION_CL5_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 +-//SION_CL5_WrRsp_TimeSlot_REG1 +-#define SION_CL5_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 +-//SION_CL5_Req_BurstTarget_REG0 +-#define SION_CL5_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 +-//SION_CL5_Req_BurstTarget_REG1 +-#define SION_CL5_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 +-//SION_CL5_Req_TimeSlot_REG0 +-#define SION_CL5_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 +-//SION_CL5_Req_TimeSlot_REG1 +-#define SION_CL5_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 +-//SION_CL5_ReqPoolCredit_Alloc_REG0 +-#define SION_CL5_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 +-//SION_CL5_ReqPoolCredit_Alloc_REG1 +-#define SION_CL5_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 +-//SION_CL5_DataPoolCredit_Alloc_REG0 +-#define SION_CL5_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 +-//SION_CL5_DataPoolCredit_Alloc_REG1 +-#define SION_CL5_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 +-//SION_CL5_RdRspPoolCredit_Alloc_REG0 +-#define SION_CL5_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 +-//SION_CL5_RdRspPoolCredit_Alloc_REG1 +-#define SION_CL5_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 +-//SION_CL5_WrRspPoolCredit_Alloc_REG0 +-#define SION_CL5_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 +-//SION_CL5_WrRspPoolCredit_Alloc_REG1 +-#define SION_CL5_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 +-//SION_CNTL_REG0 +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT 0x0 +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT 0x1 +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT 0x2 +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT 0x3 +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT 0x4 +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT 0x5 +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT 0x6 +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT 0x7 +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT 0x8 +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT 0x9 +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__SHIFT 0xa +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__SHIFT 0xb +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__SHIFT 0xc +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__SHIFT 0xd +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__SHIFT 0xe +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__SHIFT 0xf +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__SHIFT 0x10 +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__SHIFT 0x11 +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__SHIFT 0x12 +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__SHIFT 0x13 +-//SION_CNTL_REG1 +-#define SION_CNTL_REG1__LIVELOCK_WATCHDOG_THRESHOLD__SHIFT 0x0 +-#define SION_CNTL_REG1__CG_OFF_HYSTERESIS__SHIFT 0x8 +- +- +-// addressBlock: syshub_mmreg_direct_syshubdirect +-//SYSHUB_DS_CTRL_SOCCLK +-#define SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0 +-#define SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1 +-#define SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2 +-#define SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3 +-#define SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4 +-#define SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5 +-#define SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6 +-#define SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7 +-#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10 +-#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11 +-#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12 +-#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13 +-#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14 +-#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15 +-#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16 +-#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17 +-#define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c +-#define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__SHIFT 0x1f +-//SYSHUB_DS_CTRL2_SOCCLK +-#define SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__SHIFT 0x0 +-//SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK +-#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en__SHIFT 0x0 +-#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en__SHIFT 0x1 +-#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__SHIFT 0xf +-#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en__SHIFT 0x10 +-#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en__SHIFT 0x11 +-//SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK +-#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en__SHIFT 0x0 +-#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en__SHIFT 0x1 +-#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__SHIFT 0xf +-#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en__SHIFT 0x10 +-#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en__SHIFT 0x11 +-//DMA_CLK0_SW0_SYSHUB_QOS_CNTL +-#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 +-#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 +-#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 +-//DMA_CLK0_SW1_SYSHUB_QOS_CNTL +-#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 +-#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 +-#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 +-//DMA_CLK0_SW0_CL0_CNTL +-#define DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +-#define DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +-#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +-#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +-#define DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +-#define DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +-//DMA_CLK0_SW0_CL1_CNTL +-#define DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +-#define DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +-#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +-#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +-#define DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +-#define DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +-//DMA_CLK0_SW0_CL2_CNTL +-#define DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +-#define DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +-#define DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +-#define DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +-#define DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +-#define DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +-//DMA_CLK0_SW0_CL3_CNTL +-#define DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +-#define DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +-#define DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +-#define DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +-#define DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +-#define DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +-//DMA_CLK0_SW0_CL4_CNTL +-#define DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +-#define DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +-#define DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +-#define DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +-#define DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +-#define DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +-//DMA_CLK0_SW0_CL5_CNTL +-#define DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +-#define DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +-#define DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +-#define DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +-#define DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +-#define DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +-//DMA_CLK0_SW1_CL0_CNTL +-#define DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +-#define DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +-#define DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +-#define DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +-#define DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +-#define DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +-//DMA_CLK0_SW2_CL0_CNTL +-#define DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +-#define DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +-#define DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +-#define DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +-#define DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +-#define DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +-//SYSHUB_CG_CNTL +-#define SYSHUB_CG_CNTL__SYSHUB_CG_EN__SHIFT 0x0 +-#define SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER__SHIFT 0x8 +-#define SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER__SHIFT 0x10 +-//SYSHUB_TRANS_IDLE +-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0__SHIFT 0x0 +-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1__SHIFT 0x1 +-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2__SHIFT 0x2 +-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3__SHIFT 0x3 +-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4__SHIFT 0x4 +-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5__SHIFT 0x5 +-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6__SHIFT 0x6 +-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7__SHIFT 0x7 +-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8__SHIFT 0x8 +-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9__SHIFT 0x9 +-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10__SHIFT 0xa +-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11__SHIFT 0xb +-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12__SHIFT 0xc +-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13__SHIFT 0xd +-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14__SHIFT 0xe +-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15__SHIFT 0xf +-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF__SHIFT 0x10 +-//SYSHUB_HP_TIMER +-#define SYSHUB_HP_TIMER__SYSHUB_HP_TIMER__SHIFT 0x0 +-//SYSHUB_SCRATCH +-#define SYSHUB_SCRATCH__SCRATCH__SHIFT 0x0 +-//SYSHUB_DS_CTRL_SHUBCLK +-#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0 +-#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1 +-#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2 +-#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3 +-#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4 +-#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5 +-#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6 +-#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7 +-#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10 +-#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11 +-#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12 +-#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13 +-#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14 +-#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15 +-#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16 +-#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17 +-#define SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c +-#define SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN__SHIFT 0x1f +-//SYSHUB_DS_CTRL2_SHUBCLK +-#define SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER__SHIFT 0x0 +-//SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK +-#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en__SHIFT 0xf +-#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en__SHIFT 0x10 +-//SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK +-#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en__SHIFT 0xf +-#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en__SHIFT 0x10 +-//DMA_CLK1_SW0_SYSHUB_QOS_CNTL +-#define DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 +-#define DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 +-#define DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 +-//DMA_CLK1_SW1_SYSHUB_QOS_CNTL +-#define DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 +-#define DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 +-#define DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 +-//DMA_CLK1_SW0_CL0_CNTL +-#define DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +-#define DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +-#define DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +-#define DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +-#define DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +-#define DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +-//DMA_CLK1_SW0_CL1_CNTL +-#define DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +-#define DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +-#define DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +-#define DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +-#define DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +-#define DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +-//DMA_CLK1_SW0_CL2_CNTL +-#define DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +-#define DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +-#define DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +-#define DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +-#define DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +-#define DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +-//DMA_CLK1_SW0_CL3_CNTL +-#define DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +-#define DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +-#define DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +-#define DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +-#define DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +-#define DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +-//DMA_CLK1_SW0_CL4_CNTL +-#define DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +-#define DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +-#define DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +-#define DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +-#define DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +-#define DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +-//DMA_CLK1_SW1_CL0_CNTL +-#define DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +-#define DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +-#define DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +-#define DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +-#define DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +-#define DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +-//DMA_CLK1_SW1_CL1_CNTL +-#define DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +-#define DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +-#define DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +-#define DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +-#define DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +-#define DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +-//DMA_CLK1_SW1_CL2_CNTL +-#define DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +-#define DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +-#define DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +-#define DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +-#define DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +-#define DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +-//DMA_CLK1_SW1_CL3_CNTL +-#define DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +-#define DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +-#define DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +-#define DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +-#define DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +-#define DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +-//DMA_CLK1_SW1_CL4_CNTL +-#define DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +-#define DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +-#define DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +-#define DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +-#define DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +-#define DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +- +- +-// addressBlock: gdc_ras_gdc_ras_regblk +-//GDC_RAS_LEAF0_CTRL +-#define GDC_RAS_LEAF0_CTRL__POISON_DET_EN__SHIFT 0x0 +-#define GDC_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +-#define GDC_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT 0x2 +-#define GDC_RAS_LEAF0_CTRL__PARITY_DET_EN__SHIFT 0x4 +-#define GDC_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 +-#define GDC_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT 0x6 +-#define GDC_RAS_LEAF0_CTRL__ERR_EVENT_RECV__SHIFT 0x10 +-#define GDC_RAS_LEAF0_CTRL__LINK_DIS_RECV__SHIFT 0x11 +-#define GDC_RAS_LEAF0_CTRL__POISON_ERR_DET__SHIFT 0x12 +-#define GDC_RAS_LEAF0_CTRL__PARITY_ERR_DET__SHIFT 0x13 +-#define GDC_RAS_LEAF0_CTRL__ERR_EVENT_SENT__SHIFT 0x14 +-#define GDC_RAS_LEAF0_CTRL__EGRESS_STALLED__SHIFT 0x15 +-//GDC_RAS_LEAF1_CTRL +-#define GDC_RAS_LEAF1_CTRL__POISON_DET_EN__SHIFT 0x0 +-#define GDC_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +-#define GDC_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT 0x2 +-#define GDC_RAS_LEAF1_CTRL__PARITY_DET_EN__SHIFT 0x4 +-#define GDC_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 +-#define GDC_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT 0x6 +-#define GDC_RAS_LEAF1_CTRL__ERR_EVENT_RECV__SHIFT 0x10 +-#define GDC_RAS_LEAF1_CTRL__LINK_DIS_RECV__SHIFT 0x11 +-#define GDC_RAS_LEAF1_CTRL__POISON_ERR_DET__SHIFT 0x12 +-#define GDC_RAS_LEAF1_CTRL__PARITY_ERR_DET__SHIFT 0x13 +-#define GDC_RAS_LEAF1_CTRL__ERR_EVENT_SENT__SHIFT 0x14 +-#define GDC_RAS_LEAF1_CTRL__EGRESS_STALLED__SHIFT 0x15 +-//GDC_RAS_LEAF2_CTRL +-#define GDC_RAS_LEAF2_CTRL__POISON_DET_EN__SHIFT 0x0 +-#define GDC_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +-#define GDC_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT 0x2 +-#define GDC_RAS_LEAF2_CTRL__PARITY_DET_EN__SHIFT 0x4 +-#define GDC_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 +-#define GDC_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT 0x6 +-#define GDC_RAS_LEAF2_CTRL__ERR_EVENT_RECV__SHIFT 0x10 +-#define GDC_RAS_LEAF2_CTRL__LINK_DIS_RECV__SHIFT 0x11 +-#define GDC_RAS_LEAF2_CTRL__POISON_ERR_DET__SHIFT 0x12 +-#define GDC_RAS_LEAF2_CTRL__PARITY_ERR_DET__SHIFT 0x13 +-#define GDC_RAS_LEAF2_CTRL__ERR_EVENT_SENT__SHIFT 0x14 +-#define GDC_RAS_LEAF2_CTRL__EGRESS_STALLED__SHIFT 0x15 +-//GDC_RAS_LEAF3_CTRL +-#define GDC_RAS_LEAF3_CTRL__POISON_DET_EN__SHIFT 0x0 +-#define GDC_RAS_LEAF3_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +-#define GDC_RAS_LEAF3_CTRL__POISON_STALL_EN__SHIFT 0x2 +-#define GDC_RAS_LEAF3_CTRL__PARITY_DET_EN__SHIFT 0x4 +-#define GDC_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 +-#define GDC_RAS_LEAF3_CTRL__PARITY_STALL_EN__SHIFT 0x6 +-#define GDC_RAS_LEAF3_CTRL__ERR_EVENT_RECV__SHIFT 0x10 +-#define GDC_RAS_LEAF3_CTRL__LINK_DIS_RECV__SHIFT 0x11 +-#define GDC_RAS_LEAF3_CTRL__POISON_ERR_DET__SHIFT 0x12 +-#define GDC_RAS_LEAF3_CTRL__PARITY_ERR_DET__SHIFT 0x13 +-#define GDC_RAS_LEAF3_CTRL__ERR_EVENT_SENT__SHIFT 0x14 +-#define GDC_RAS_LEAF3_CTRL__EGRESS_STALLED__SHIFT 0x15 +-//GDC_RAS_LEAF4_CTRL +-#define GDC_RAS_LEAF4_CTRL__POISON_DET_EN__SHIFT 0x0 +-#define GDC_RAS_LEAF4_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +-#define GDC_RAS_LEAF4_CTRL__POISON_STALL_EN__SHIFT 0x2 +-#define GDC_RAS_LEAF4_CTRL__PARITY_DET_EN__SHIFT 0x4 +-#define GDC_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 +-#define GDC_RAS_LEAF4_CTRL__PARITY_STALL_EN__SHIFT 0x6 +-#define GDC_RAS_LEAF4_CTRL__ERR_EVENT_RECV__SHIFT 0x10 +-#define GDC_RAS_LEAF4_CTRL__LINK_DIS_RECV__SHIFT 0x11 +-#define GDC_RAS_LEAF4_CTRL__POISON_ERR_DET__SHIFT 0x12 +-#define GDC_RAS_LEAF4_CTRL__PARITY_ERR_DET__SHIFT 0x13 +-#define GDC_RAS_LEAF4_CTRL__ERR_EVENT_SENT__SHIFT 0x14 +-#define GDC_RAS_LEAF4_CTRL__EGRESS_STALLED__SHIFT 0x15 +-//GDC_RAS_LEAF5_CTRL +-#define GDC_RAS_LEAF5_CTRL__POISON_DET_EN__SHIFT 0x0 +-#define GDC_RAS_LEAF5_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +-#define GDC_RAS_LEAF5_CTRL__POISON_STALL_EN__SHIFT 0x2 +-#define GDC_RAS_LEAF5_CTRL__PARITY_DET_EN__SHIFT 0x4 +-#define GDC_RAS_LEAF5_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 +-#define GDC_RAS_LEAF5_CTRL__PARITY_STALL_EN__SHIFT 0x6 +-#define GDC_RAS_LEAF5_CTRL__ERR_EVENT_RECV__SHIFT 0x10 +-#define GDC_RAS_LEAF5_CTRL__LINK_DIS_RECV__SHIFT 0x11 +-#define GDC_RAS_LEAF5_CTRL__POISON_ERR_DET__SHIFT 0x12 +-#define GDC_RAS_LEAF5_CTRL__PARITY_ERR_DET__SHIFT 0x13 +-#define GDC_RAS_LEAF5_CTRL__ERR_EVENT_SENT__SHIFT 0x14 +-#define GDC_RAS_LEAF5_CTRL__EGRESS_STALLED__SHIFT 0x15 +- +- +-// addressBlock: gdc_rst_GDCRST_DEC +-//SHUB_PF_FLR_RST +-#define SHUB_PF_FLR_RST__PF0_FLR_RST__SHIFT 0x0 +-#define SHUB_PF_FLR_RST__PF1_FLR_RST__SHIFT 0x1 +-#define SHUB_PF_FLR_RST__PF2_FLR_RST__SHIFT 0x2 +-#define SHUB_PF_FLR_RST__PF3_FLR_RST__SHIFT 0x3 +-#define SHUB_PF_FLR_RST__PF4_FLR_RST__SHIFT 0x4 +-#define SHUB_PF_FLR_RST__PF5_FLR_RST__SHIFT 0x5 +-#define SHUB_PF_FLR_RST__PF6_FLR_RST__SHIFT 0x6 +-#define SHUB_PF_FLR_RST__PF7_FLR_RST__SHIFT 0x7 +-//SHUB_GFX_DRV_MODE1_RST +-#define SHUB_GFX_DRV_MODE1_RST__GFX_DRV_MODE1_RST__SHIFT 0x0 +-//SHUB_LINK_RESET +-#define SHUB_LINK_RESET__LINK_RESET__SHIFT 0x0 +-//SHUB_PF0_VF_FLR_RST +-#define SHUB_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__SHIFT 0x0 +-#define SHUB_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__SHIFT 0x1 +-#define SHUB_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__SHIFT 0x2 +-#define SHUB_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__SHIFT 0x3 +-#define SHUB_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__SHIFT 0x4 +-#define SHUB_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__SHIFT 0x5 +-#define SHUB_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__SHIFT 0x6 +-#define SHUB_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__SHIFT 0x7 +-#define SHUB_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__SHIFT 0x8 +-#define SHUB_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__SHIFT 0x9 +-#define SHUB_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__SHIFT 0xa +-#define SHUB_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__SHIFT 0xb +-#define SHUB_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__SHIFT 0xc +-#define SHUB_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__SHIFT 0xd +-#define SHUB_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__SHIFT 0xe +-#define SHUB_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__SHIFT 0xf +-#define SHUB_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__SHIFT 0x1f +-//SHUB_HARD_RST_CTRL +-#define SHUB_HARD_RST_CTRL__COR_RESET_EN__SHIFT 0x0 +-#define SHUB_HARD_RST_CTRL__REG_RESET_EN__SHIFT 0x1 +-#define SHUB_HARD_RST_CTRL__STY_RESET_EN__SHIFT 0x2 +-#define SHUB_HARD_RST_CTRL__NIC400_RESET_EN__SHIFT 0x3 +-#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4 +-//SHUB_SOFT_RST_CTRL +-#define SHUB_SOFT_RST_CTRL__COR_RESET_EN__SHIFT 0x0 +-#define SHUB_SOFT_RST_CTRL__REG_RESET_EN__SHIFT 0x1 +-#define SHUB_SOFT_RST_CTRL__STY_RESET_EN__SHIFT 0x2 +-#define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN__SHIFT 0x3 +-#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4 +-//SHUB_SDP_PORT_RST +-#define SHUB_SDP_PORT_RST__SDP_PORT_RST__SHIFT 0x0 +- +- +-// addressBlock: bif_bx_pf_SYSDEC +-//SBIOS_SCRATCH_0 +-#define SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__SHIFT 0x0 +-//SBIOS_SCRATCH_1 +-#define SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__SHIFT 0x0 +-//SBIOS_SCRATCH_2 +-#define SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__SHIFT 0x0 +-//SBIOS_SCRATCH_3 +-#define SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__SHIFT 0x0 +-//BIOS_SCRATCH_0 +-#define BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0 +-//BIOS_SCRATCH_1 +-#define BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0 +-//BIOS_SCRATCH_2 +-#define BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 +-//BIOS_SCRATCH_3 +-#define BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 +-//BIOS_SCRATCH_4 +-#define BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0 +-//BIOS_SCRATCH_5 +-#define BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0 +-//BIOS_SCRATCH_6 +-#define BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 +-//BIOS_SCRATCH_7 +-#define BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0 +-//BIOS_SCRATCH_8 +-#define BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0 +-//BIOS_SCRATCH_9 +-#define BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0 +-//BIOS_SCRATCH_10 +-#define BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0 +-//BIOS_SCRATCH_11 +-#define BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0 +-//BIOS_SCRATCH_12 +-#define BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0 +-//BIOS_SCRATCH_13 +-#define BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0 +-//BIOS_SCRATCH_14 +-#define BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0 +-//BIOS_SCRATCH_15 +-#define BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0 +-//BIF_RLC_INTR_CNTL +-#define BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__SHIFT 0x0 +-#define BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__SHIFT 0x1 +-#define BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__SHIFT 0x2 +-#define BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__SHIFT 0x3 +-//BIF_VCE_INTR_CNTL +-#define BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__SHIFT 0x0 +-#define BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__SHIFT 0x1 +-#define BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__SHIFT 0x2 +-#define BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__SHIFT 0x3 +-//BIF_UVD_INTR_CNTL +-#define BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__SHIFT 0x0 +-#define BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__SHIFT 0x1 +-#define BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__SHIFT 0x2 +-#define BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__SHIFT 0x3 +-//GFX_MMIOREG_CAM_ADDR0 +-#define GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0 +-//GFX_MMIOREG_CAM_REMAP_ADDR0 +-#define GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0 +-//GFX_MMIOREG_CAM_ADDR1 +-#define GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0 +-//GFX_MMIOREG_CAM_REMAP_ADDR1 +-#define GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0 +-//GFX_MMIOREG_CAM_ADDR2 +-#define GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0 +-//GFX_MMIOREG_CAM_REMAP_ADDR2 +-#define GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0 +-//GFX_MMIOREG_CAM_ADDR3 +-#define GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0 +-//GFX_MMIOREG_CAM_REMAP_ADDR3 +-#define GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0 +-//GFX_MMIOREG_CAM_ADDR4 +-#define GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0 +-//GFX_MMIOREG_CAM_REMAP_ADDR4 +-#define GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0 +-//GFX_MMIOREG_CAM_ADDR5 +-#define GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0 +-//GFX_MMIOREG_CAM_REMAP_ADDR5 +-#define GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0 +-//GFX_MMIOREG_CAM_ADDR6 +-#define GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0 +-//GFX_MMIOREG_CAM_REMAP_ADDR6 +-#define GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0 +-//GFX_MMIOREG_CAM_ADDR7 +-#define GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0 +-//GFX_MMIOREG_CAM_REMAP_ADDR7 +-#define GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0 +-//GFX_MMIOREG_CAM_CNTL +-#define GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0 +-//GFX_MMIOREG_CAM_ZERO_CPL +-#define GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0 +-//GFX_MMIOREG_CAM_ONE_CPL +-#define GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0 +-//GFX_MMIOREG_CAM_PROGRAMMABLE_CPL +-#define GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0 +- +- +-// addressBlock: bif_bx_pf_SYSPFVFDEC +-//MM_INDEX +-#define MM_INDEX__MM_OFFSET__SHIFT 0x0 +-#define MM_INDEX__MM_APER__SHIFT 0x1f +-//MM_DATA +-#define MM_DATA__MM_DATA__SHIFT 0x0 +-//MM_INDEX_HI +-#define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 +-//SYSHUB_INDEX_OVLP +-#define SYSHUB_INDEX_OVLP__SYSHUB_OFFSET__SHIFT 0x0 +-//SYSHUB_DATA_OVLP +-#define SYSHUB_DATA_OVLP__SYSHUB_DATA__SHIFT 0x0 +-//PCIE_INDEX +-#define PCIE_INDEX__PCIE_INDEX__SHIFT 0x0 +-//PCIE_DATA +-#define PCIE_DATA__PCIE_DATA__SHIFT 0x0 +-//PCIE_INDEX2 +-#define PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0 +-//PCIE_DATA2 +-#define PCIE_DATA2__PCIE_DATA2__SHIFT 0x0 +- +- +-// addressBlock: rcc_dwn_BIFDEC1 +-//DN_PCIE_RESERVED +-#define DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 +-//DN_PCIE_SCRATCH +-#define DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +-//DN_PCIE_CNTL +-#define DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 +-#define DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 +-#define DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +-//DN_PCIE_CONFIG_CNTL +-#define DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 +-//DN_PCIE_RX_CNTL2 +-#define DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c +-//DN_PCIE_BUS_CNTL +-#define DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +-#define DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 +-//DN_PCIE_CFG_CNTL +-#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +-#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +-#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +-//DN_PCIE_STRAP_F0 +-#define DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0 +-#define DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11 +-#define DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15 +-//DN_PCIE_STRAP_MISC +-#define DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18 +-#define DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +-//DN_PCIE_STRAP_MISC2 +-#define DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2 +- +- +-// addressBlock: rcc_dwnp_BIFDEC1 +-//PCIEP_RESERVED +-#define PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +-//PCIEP_SCRATCH +-#define PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 +-//PCIE_ERR_CNTL +-#define PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +-#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +-#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb +-#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +-//PCIE_RX_CNTL +-#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +-#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 +-#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +-#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 +-#define PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b +-//PCIE_LC_SPEED_CNTL +-#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +-#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +-//PCIE_LC_CNTL2 +-#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b +-//PCIEP_STRAP_MISC +-#define PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa +-//LTR_MSG_INFO_FROM_EP +-#define LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 +- +- +-// addressBlock: rcc_ep_BIFDEC1 +-//EP_PCIE_SCRATCH +-#define EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 +-//EP_PCIE_CNTL +-#define EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 +-#define EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 +-#define EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e +-//EP_PCIE_INT_CNTL +-#define EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 +-#define EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 +-#define EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 +-#define EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 +-#define EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 +-#define EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 +-//EP_PCIE_INT_STATUS +-#define EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 +-#define EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 +-#define EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 +-#define EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 +-#define EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 +-#define EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 +-//EP_PCIE_RX_CNTL2 +-#define EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 +-//EP_PCIE_BUS_CNTL +-#define EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 +-//EP_PCIE_CFG_CNTL +-#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 +-#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 +-#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 +-//EP_PCIE_OBFF_CNTL +-#define EP_PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE__SHIFT 0x0 +-#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN__SHIFT 0x1 +-#define EP_PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE__SHIFT 0x2 +-#define EP_PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE__SHIFT 0x3 +-#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH__SHIFT 0x4 +-#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH__SHIFT 0x8 +-#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD__SHIFT 0xc +-#define EP_PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE__SHIFT 0x10 +-#define EP_PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE__SHIFT 0x11 +-#define EP_PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE__SHIFT 0x12 +-#define EP_PCIE_OBFF_CNTL__TX_OBFF_ACCEPT_IN_NOND0__SHIFT 0x13 +-#define EP_PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE__SHIFT 0x14 +-//EP_PCIE_TX_LTR_CNTL +-#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 +-#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 +-#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 +-#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 +-#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa +-#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd +-#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe +-#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf +-#define EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 +-//EP_PCIE_STRAP_MISC +-#define EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d +-//EP_PCIE_STRAP_MISC2 +-#define EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4 +-//EP_PCIE_STRAP_PI +-//EP_PCIE_F0_DPA_CAP +-#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 +-#define EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc +-#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 +-#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 +-//EP_PCIE_F0_DPA_LATENCY_INDICATOR +-#define EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 +-//EP_PCIE_F0_DPA_CNTL +-#define EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 +-#define EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 +-//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 +-#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +-//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 +-#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +-//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 +-#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +-//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 +-#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +-//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 +-#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +-//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 +-#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +-//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 +-#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +-//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 +-#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 +-//EP_PCIE_PME_CONTROL +-#define EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 +-//EP_PCIEP_RESERVED +-#define EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 +-//EP_PCIE_TX_CNTL +-#define EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa +-#define EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc +-#define EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 +-#define EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 +-#define EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a +-//EP_PCIE_TX_REQUESTER_ID +-#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 +-#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 +-#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 +-//EP_PCIE_ERR_CNTL +-#define EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 +-#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 +-#define EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 +-#define EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 +-#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18 +-#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19 +-#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a +-#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b +-#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c +-#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d +-#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e +-#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f +-//EP_PCIE_RX_CNTL +-#define EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 +-#define EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 +-#define EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 +-#define EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 +-#define EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 +-#define EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 +-#define EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 +-#define EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a +-//EP_PCIE_LC_SPEED_CNTL +-#define EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 +-#define EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 +- +- +-// addressBlock: bif_bx_pf_BIFDEC1 +-//BIF_MM_INDACCESS_CNTL +-#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1 +-//BUS_CNTL +-#define BUS_CNTL__PMI_INT_DIS_EP__SHIFT 0x3 +-#define BUS_CNTL__PMI_INT_DIS_DN__SHIFT 0x4 +-#define BUS_CNTL__PMI_INT_DIS_SWUS__SHIFT 0x5 +-#define BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6 +-#define BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7 +-#define BUS_CNTL__SET_AZ_TC__SHIFT 0xa +-#define BUS_CNTL__SET_MC_TC__SHIFT 0xd +-#define BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10 +-#define BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11 +-#define BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12 +-#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT 0x13 +-#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT 0x14 +-#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT 0x15 +-#define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT 0x16 +-#define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT 0x17 +-#define BUS_CNTL__UR_OVRD_FOR_ECRC_EN__SHIFT 0x18 +-//BIF_SCRATCH0 +-#define BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0 +-//BIF_SCRATCH1 +-#define BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0 +-//BX_RESET_EN +-#define BX_RESET_EN__COR_RESET_EN__SHIFT 0x0 +-#define BX_RESET_EN__REG_RESET_EN__SHIFT 0x1 +-#define BX_RESET_EN__STY_RESET_EN__SHIFT 0x2 +-#define BX_RESET_EN__FLR_TWICE_EN__SHIFT 0x8 +-#define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10 +-//MM_CFGREGS_CNTL +-#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0 +-#define MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6 +-#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f +-//BX_RESET_CNTL +-#define BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0 +-//INTERRUPT_CNTL +-#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0 +-#define INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1 +-#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3 +-#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4 +-#define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8 +-#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf +-//INTERRUPT_CNTL2 +-#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0 +-//CLKREQB_PAD_CNTL +-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0 +-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1 +-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2 +-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3 +-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5 +-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6 +-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7 +-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8 +-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9 +-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa +-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb +-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc +-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd +-#define CLKREQB_PAD_CNTL__CLKREQB_PERF_COUNTER_UPPER__SHIFT 0x18 +-//CLKREQB_PERF_COUNTER +-#define CLKREQB_PERF_COUNTER__CLKREQB_PERF_COUNTER_LOWER__SHIFT 0x0 +-//BIF_CLK_CTRL +-#define BIF_CLK_CTRL__BIF_XSTCLK_READY__SHIFT 0x0 +-#define BIF_CLK_CTRL__BACO_XSTCLK_SWITCH_BYPASS__SHIFT 0x1 +-//BIF_FEATURES_CONTROL_MISC +-#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0 +-#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1 +-#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2 +-#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3 +-#define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS__SHIFT 0x9 +-#define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS__SHIFT 0xa +-#define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0xb +-#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc +-#define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd +-#define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf +-#define BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS__SHIFT 0x11 +-#define BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS__SHIFT 0x12 +-#define BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x18 +-//BIF_DOORBELL_CNTL +-#define BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0 +-#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1 +-#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2 +-#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3 +-#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4 +-#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18 +-#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19 +-#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a +-#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b +-//BIF_DOORBELL_INT_CNTL +-#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0 +-#define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS__SHIFT 0x1 +-#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10 +-#define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR__SHIFT 0x11 +-//BIF_SLVARB_MODE +-#define BIF_SLVARB_MODE__SLVARB_MODE__SHIFT 0x0 +-//BIF_FB_EN +-#define BIF_FB_EN__FB_READ_EN__SHIFT 0x0 +-#define BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1 +-//BIF_BUSY_DELAY_CNTR +-#define BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x0 +-//BIF_PERFMON_CNTL +-#define BIF_PERFMON_CNTL__PERFCOUNTER_EN__SHIFT 0x0 +-#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0__SHIFT 0x1 +-#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__SHIFT 0x2 +-#define BIF_PERFMON_CNTL__PERF_SEL0__SHIFT 0x8 +-#define BIF_PERFMON_CNTL__PERF_SEL1__SHIFT 0xd +-//BIF_PERFCOUNTER0_RESULT +-#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0 +-//BIF_PERFCOUNTER1_RESULT +-#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0 +-//BIF_MST_TRANS_PENDING_VF +-#define BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0 +-//BIF_SLV_TRANS_PENDING_VF +-#define BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0 +-//BACO_CNTL +-#define BACO_CNTL__BACO_EN__SHIFT 0x0 +-#define BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT 0x1 +-#define BACO_CNTL__BACO_DUMMY_EN__SHIFT 0x2 +-#define BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3 +-#define BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT 0x5 +-#define BACO_CNTL__BACO_RST_INTR_MASK__SHIFT 0x6 +-#define BACO_CNTL__BACO_MODE__SHIFT 0x8 +-#define BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x9 +-#define BACO_CNTL__BACO_AUTO_EXIT__SHIFT 0x1f +-//BIF_BACO_EXIT_TIME0 +-#define BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT 0x0 +-//BIF_BACO_EXIT_TIMER1 +-#define BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT 0x0 +-#define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT 0x1a +-#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT 0x1b +-#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT 0x1c +-#define BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT 0x1d +-#define BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT 0x1f +-//BIF_BACO_EXIT_TIMER2 +-#define BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT 0x0 +-//BIF_BACO_EXIT_TIMER3 +-#define BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT 0x0 +-//BIF_BACO_EXIT_TIMER4 +-#define BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT 0x0 +-//MEM_TYPE_CNTL +-#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0 +-//SMU_BIF_VDDGFX_PWR_STATUS +-#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__SHIFT 0x0 +-//BIF_VDDGFX_GFX0_LOWER +-#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__SHIFT 0x2 +-#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__SHIFT 0x1e +-#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__SHIFT 0x1f +-//BIF_VDDGFX_GFX0_UPPER +-#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__SHIFT 0x2 +-//BIF_VDDGFX_GFX1_LOWER +-#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__SHIFT 0x2 +-#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__SHIFT 0x1e +-#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__SHIFT 0x1f +-//BIF_VDDGFX_GFX1_UPPER +-#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__SHIFT 0x2 +-//BIF_VDDGFX_GFX2_LOWER +-#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__SHIFT 0x2 +-#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__SHIFT 0x1e +-#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__SHIFT 0x1f +-//BIF_VDDGFX_GFX2_UPPER +-#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__SHIFT 0x2 +-//BIF_VDDGFX_GFX3_LOWER +-#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__SHIFT 0x2 +-#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__SHIFT 0x1e +-#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__SHIFT 0x1f +-//BIF_VDDGFX_GFX3_UPPER +-#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__SHIFT 0x2 +-//BIF_VDDGFX_GFX4_LOWER +-#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__SHIFT 0x2 +-#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__SHIFT 0x1e +-#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__SHIFT 0x1f +-//BIF_VDDGFX_GFX4_UPPER +-#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2 +-//BIF_VDDGFX_GFX5_LOWER +-#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__SHIFT 0x2 +-#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__SHIFT 0x1e +-#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__SHIFT 0x1f +-//BIF_VDDGFX_GFX5_UPPER +-#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__SHIFT 0x2 +-//BIF_VDDGFX_RSV1_LOWER +-#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__SHIFT 0x2 +-#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__SHIFT 0x1e +-#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__SHIFT 0x1f +-//BIF_VDDGFX_RSV1_UPPER +-#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__SHIFT 0x2 +-//BIF_VDDGFX_RSV2_LOWER +-#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__SHIFT 0x2 +-#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__SHIFT 0x1e +-#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__SHIFT 0x1f +-//BIF_VDDGFX_RSV2_UPPER +-#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__SHIFT 0x2 +-//BIF_VDDGFX_RSV3_LOWER +-#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__SHIFT 0x2 +-#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT 0x1e +-#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__SHIFT 0x1f +-//BIF_VDDGFX_RSV3_UPPER +-#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__SHIFT 0x2 +-//BIF_VDDGFX_RSV4_LOWER +-#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__SHIFT 0x2 +-#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__SHIFT 0x1e +-#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__SHIFT 0x1f +-//BIF_VDDGFX_RSV4_UPPER +-#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__SHIFT 0x2 +-//BIF_VDDGFX_FB_CMP +-#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__SHIFT 0x0 +-#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__SHIFT 0x1 +-#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__SHIFT 0x2 +-#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__SHIFT 0x3 +-#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__SHIFT 0x4 +-#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__SHIFT 0x5 +-//BIF_DOORBELL_GBLAPER1_LOWER +-#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__SHIFT 0x2 +-#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__SHIFT 0x1f +-//BIF_DOORBELL_GBLAPER1_UPPER +-#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__SHIFT 0x2 +-//BIF_DOORBELL_GBLAPER2_LOWER +-#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__SHIFT 0x2 +-#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__SHIFT 0x1f +-//BIF_DOORBELL_GBLAPER2_UPPER +-#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__SHIFT 0x2 +-//REMAP_HDP_MEM_FLUSH_CNTL +-#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2 +-//REMAP_HDP_REG_FLUSH_CNTL +-#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2 +-//BIF_RB_CNTL +-#define BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0 +-#define BIF_RB_CNTL__RB_SIZE__SHIFT 0x1 +-#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 +-#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9 +-#define BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11 +-#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f +-//BIF_RB_BASE +-#define BIF_RB_BASE__ADDR__SHIFT 0x0 +-//BIF_RB_RPTR +-#define BIF_RB_RPTR__OFFSET__SHIFT 0x2 +-//BIF_RB_WPTR +-#define BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0 +-#define BIF_RB_WPTR__OFFSET__SHIFT 0x2 +-//BIF_RB_WPTR_ADDR_HI +-#define BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 +-//BIF_RB_WPTR_ADDR_LO +-#define BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 +-//MAILBOX_INDEX +-#define MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0 +-//BIF_GPUIOV_RESET_NOTIFICATION +-#define BIF_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION__SHIFT 0x0 +-//BIF_UVD_GPUIOV_CFG_SIZE +-#define BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE__SHIFT 0x0 +-//BIF_VCE_GPUIOV_CFG_SIZE +-#define BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE__SHIFT 0x0 +-//BIF_GFX_SDMA_GPUIOV_CFG_SIZE +-#define BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT 0x0 +-//BIF_GMI_WRR_WEIGHT +-#define BIF_GMI_WRR_WEIGHT__GMI_REQ_REALTIME_WEIGHT__SHIFT 0x0 +-#define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_P_WEIGHT__SHIFT 0x8 +-#define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_NP_WEIGHT__SHIFT 0x10 +-//NBIF_STRAP_WRITE_CTRL +-#define NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE__SHIFT 0x0 +-//BIF_PERSTB_PAD_CNTL +-#define BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT 0x0 +-//BIF_PX_EN_PAD_CNTL +-#define BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT 0x0 +-//BIF_REFPADKIN_PAD_CNTL +-#define BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT 0x0 +-//BIF_CLKREQB_PAD_CNTL +-#define BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT 0x0 +- +- +-// addressBlock: rcc_pf_0_BIFDEC1 +-//RCC_BACO_CNTL_MISC +-#define RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0 +-#define RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1 +-//RCC_RESET_EN +-#define RCC_RESET_EN__DB_APER_RESET_EN__SHIFT 0xf +-//RCC_VDM_SUPPORT +-#define RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0 +-#define RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1 +-#define RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2 +-#define RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3 +-#define RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4 +-//RCC_PEER_REG_RANGE0 +-#define RCC_PEER_REG_RANGE0__START_ADDR__SHIFT 0x0 +-#define RCC_PEER_REG_RANGE0__END_ADDR__SHIFT 0x10 +-//RCC_PEER_REG_RANGE1 +-#define RCC_PEER_REG_RANGE1__START_ADDR__SHIFT 0x0 +-#define RCC_PEER_REG_RANGE1__END_ADDR__SHIFT 0x10 +-//RCC_BUS_CNTL +-#define RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2 +-#define RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3 +-#define RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4 +-#define RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5 +-#define RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6 +-#define RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7 +-#define RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8 +-#define RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc +-#define RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd +-#define RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10 +-#define RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11 +-#define RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12 +-#define RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13 +-#define RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14 +-#define RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15 +-#define RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18 +-#define RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19 +-#define RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c +-#define RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d +-//RCC_CONFIG_CNTL +-#define RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0 +-#define RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2 +-#define RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3 +-//RCC_CONFIG_F0_BASE +-#define RCC_CONFIG_F0_BASE__F0_BASE__SHIFT 0x0 +-//RCC_CONFIG_APER_SIZE +-#define RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0 +-//RCC_CONFIG_REG_APER_SIZE +-#define RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0 +-//RCC_XDMA_LO +-#define RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0 +-#define RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f +-//RCC_XDMA_HI +-#define RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0 +-//RCC_FEATURES_CONTROL_MISC +-#define RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x4 +-#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x5 +-#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x6 +-#define RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8 +-#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9 +-#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa +-#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb +-#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc +-#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd +-#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe +-#define RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT 0xf +-#define RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10 +-#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11 +-#define RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12 +-//RCC_BUSNUM_CNTL1 +-#define RCC_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0 +-//RCC_BUSNUM_LIST0 +-#define RCC_BUSNUM_LIST0__ID0__SHIFT 0x0 +-#define RCC_BUSNUM_LIST0__ID1__SHIFT 0x8 +-#define RCC_BUSNUM_LIST0__ID2__SHIFT 0x10 +-#define RCC_BUSNUM_LIST0__ID3__SHIFT 0x18 +-//RCC_BUSNUM_LIST1 +-#define RCC_BUSNUM_LIST1__ID4__SHIFT 0x0 +-#define RCC_BUSNUM_LIST1__ID5__SHIFT 0x8 +-#define RCC_BUSNUM_LIST1__ID6__SHIFT 0x10 +-#define RCC_BUSNUM_LIST1__ID7__SHIFT 0x18 +-//RCC_BUSNUM_CNTL2 +-#define RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0 +-#define RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8 +-#define RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10 +-#define RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11 +-//RCC_CAPTURE_HOST_BUSNUM +-#define RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0 +-//RCC_HOST_BUSNUM +-#define RCC_HOST_BUSNUM__HOST_ID__SHIFT 0x0 +-//RCC_PEER0_FB_OFFSET_HI +-#define RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0 +-//RCC_PEER0_FB_OFFSET_LO +-#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0 +-#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f +-//RCC_PEER1_FB_OFFSET_HI +-#define RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0 +-//RCC_PEER1_FB_OFFSET_LO +-#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0 +-#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f +-//RCC_PEER2_FB_OFFSET_HI +-#define RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0 +-//RCC_PEER2_FB_OFFSET_LO +-#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0 +-#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f +-//RCC_PEER3_FB_OFFSET_HI +-#define RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0 +-//RCC_PEER3_FB_OFFSET_LO +-#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0 +-#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f +-//RCC_DEVFUNCNUM_LIST0 +-#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0 +-#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8 +-#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10 +-#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18 +-//RCC_DEVFUNCNUM_LIST1 +-#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0 +-#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8 +-#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10 +-#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18 +-//RCC_DEV0_LINK_CNTL +-#define RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x0 +-#define RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x8 +-//RCC_CMN_LINK_CNTL +-#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0 +-#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1 +-#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2 +-#define RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3 +-//RCC_EP_REQUESTERID_RESTORE +-#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0 +-#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8 +-//RCC_LTR_LSWITCH_CNTL +-#define RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0 +-//RCC_MH_ARB_CNTL +-#define RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0 +-#define RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1 +- +- +-// addressBlock: rcc_pf_0_BIFDEC2 +-//GFXMSIX_VECT0_ADDR_LO +-#define GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +-//GFXMSIX_VECT0_ADDR_HI +-#define GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +-//GFXMSIX_VECT0_MSG_DATA +-#define GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +-//GFXMSIX_VECT0_CONTROL +-#define GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +-//GFXMSIX_VECT1_ADDR_LO +-#define GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +-//GFXMSIX_VECT1_ADDR_HI +-#define GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +-//GFXMSIX_VECT1_MSG_DATA +-#define GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +-//GFXMSIX_VECT1_CONTROL +-#define GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +-//GFXMSIX_VECT2_ADDR_LO +-#define GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +-//GFXMSIX_VECT2_ADDR_HI +-#define GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +-//GFXMSIX_VECT2_MSG_DATA +-#define GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +-//GFXMSIX_VECT2_CONTROL +-#define GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +-//GFXMSIX_PBA +-#define GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 +-#define GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 +-#define GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 +- +- +-// addressBlock: rcc_strap_BIFDEC1 +-//RCC_DEV0_PORT_STRAP0 +-#define RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x1 +-#define RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x2 +-#define RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x3 +-#define RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x4 +-#define RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x5 +-#define RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15 +-#define RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18 +-#define RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19 +-#define RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c +-#define RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f +-//RCC_DEV0_PORT_STRAP1 +-#define RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0 +-#define RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10 +-//RCC_DEV0_PORT_STRAP2 +-#define RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0 +-#define RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1 +-#define RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2 +-#define RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3 +-#define RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4 +-#define RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5 +-#define RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT 0x6 +-#define RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7 +-#define RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8 +-#define RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9 +-#define RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc +-#define RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd +-#define RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe +-#define RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf +-#define RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10 +-#define RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x11 +-#define RCC_DEV0_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x13 +-#define RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14 +-#define RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17 +-#define RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a +-#define RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d +-//RCC_DEV0_PORT_STRAP3 +-#define RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0 +-#define RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1 +-#define RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2 +-#define RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3 +-#define RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6 +-#define RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7 +-#define RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8 +-#define RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9 +-#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb +-#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe +-#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12 +-#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15 +-#define RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19 +-#define RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b +-#define RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d +-#define RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0__SHIFT 0x1e +-#define RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f +-//RCC_DEV0_PORT_STRAP4 +-#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0 +-#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8 +-#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10 +-#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18 +-//RCC_DEV0_PORT_STRAP5 +-#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0 +-#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8 +-#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10 +-#define RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11 +-#define RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12 +-#define RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13 +-#define RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14 +-#define RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15 +-#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17 +-#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18 +-#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19 +-#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a +-#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b +-#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c +-#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d +-#define RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT 0x1e +-#define RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f +-//RCC_DEV0_PORT_STRAP6 +-#define RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0 +-#define RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1 +-//RCC_DEV0_PORT_STRAP7 +-#define RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0 +-#define RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8 +-#define RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc +-#define RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10 +-#define RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18 +-#define RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d +-//RCC_DEV0_EPF0_STRAP0 +-#define RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 +-#define RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 +-#define RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 +-#define RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 +-#define RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c +-#define RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d +-#define RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e +-#define RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f +-//RCC_DEV0_EPF0_STRAP1 +-#define RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0 +-#define RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10 +-//RCC_DEV0_EPF0_STRAP13 +-#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0 +-#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8 +-#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10 +-//RCC_DEV0_EPF0_STRAP2 +-#define RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0 +-#define RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x1 +-#define RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6 +-#define RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7 +-#define RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8 +-#define RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9 +-#define RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe +-#define RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf +-#define RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10 +-#define RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11 +-#define RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12 +-#define RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14 +-#define RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15 +-#define RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16 +-#define RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17 +-#define RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18 +-#define RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b +-#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c +-#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d +-#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e +-#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f +-//RCC_DEV0_EPF0_STRAP3 +-#define RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x0 +-#define RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x1 +-#define RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x2 +-#define RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12 +-#define RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13 +-#define RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14 +-#define RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15 +-#define RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18 +-#define RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0__SHIFT 0x19 +-#define RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a +-#define RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b +-//RCC_DEV0_EPF0_STRAP4 +-#define RCC_DEV0_EPF0_STRAP4__STRAP_MSIX_TABLE_OFFSET_DEV0_F0__SHIFT 0x0 +-#define RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14 +-#define RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15 +-#define RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16 +-#define RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17 +-#define RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c +-#define RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT 0x1f +-//RCC_DEV0_EPF0_STRAP5 +-#define RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0 +-//RCC_DEV0_EPF0_STRAP8 +-#define RCC_DEV0_EPF0_STRAP8__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x0 +-#define RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x1 +-#define RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3 +-#define RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x4 +-#define RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x5 +-#define RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7 +-#define RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8 +-#define RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0x9 +-#define RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xc +-#define RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0xe +-#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x10 +-#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x13 +-#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x16 +-#define RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT 0x18 +-#define RCC_DEV0_EPF0_STRAP8__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x19 +-#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x1a +-#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b +-#define RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e +-//RCC_DEV0_EPF0_STRAP9 +-//RCC_DEV0_EPF1_STRAP0 +-#define RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0 +-#define RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10 +-#define RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14 +-#define RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c +-#define RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d +-#define RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e +-#define RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f +-//RCC_DEV0_EPF1_STRAP10 +-#define RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1__SHIFT 0x0 +-#define RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1 +-//RCC_DEV0_EPF1_STRAP11 +-#define RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1__SHIFT 0x0 +-#define RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1 +-//RCC_DEV0_EPF1_STRAP12 +-#define RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1__SHIFT 0x0 +-#define RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1 +-//RCC_DEV0_EPF1_STRAP13 +-#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT 0x0 +-#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT 0x8 +-#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT 0x10 +-//RCC_DEV0_EPF1_STRAP2 +-#define RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7 +-#define RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8 +-#define RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe +-#define RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10 +-#define RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11 +-#define RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT 0x12 +-#define RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14 +-#define RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15 +-#define RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT 0x16 +-#define RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT 0x17 +-#define RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18 +-//RCC_DEV0_EPF1_STRAP3 +-#define RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x0 +-#define RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x1 +-#define RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x2 +-#define RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12 +-#define RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13 +-#define RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14 +-#define RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18 +-#define RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1__SHIFT 0x19 +-#define RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a +-#define RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b +-//RCC_DEV0_EPF1_STRAP4 +-#define RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14 +-#define RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15 +-#define RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16 +-#define RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17 +-#define RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c +-#define RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x1f +-//RCC_DEV0_EPF1_STRAP5 +-#define RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0 +-//RCC_DEV0_EPF1_STRAP6 +-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT 0x0 +-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x1 +-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT 0x2 +-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1__SHIFT 0x4 +-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__SHIFT 0x8 +-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x9 +-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__SHIFT 0x10 +-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x11 +-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__SHIFT 0x18 +-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x19 +-//RCC_DEV0_EPF1_STRAP7 +-#define RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1__SHIFT 0x0 +-#define RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1__SHIFT 0x1 +- +- +-// addressBlock: bif_bx_pf_BIFPFVFDEC1 +-//BIF_BME_STATUS +-#define BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 +-#define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 +-//BIF_ATOMIC_ERR_LOG +-#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 +-#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 +-#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 +-#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 +-//DOORBELL_SELFRING_GPA_APER_BASE_HIGH +-#define DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 +-//DOORBELL_SELFRING_GPA_APER_BASE_LOW +-#define DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 +-//DOORBELL_SELFRING_GPA_APER_CNTL +-#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 +-#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 +-//HDP_REG_COHERENCY_FLUSH_CNTL +-#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 +-//HDP_MEM_COHERENCY_FLUSH_CNTL +-#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 +-//GPU_HDP_FLUSH_REQ +-#define GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 +-#define GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 +-#define GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 +-#define GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 +-#define GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 +-#define GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 +-#define GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 +-#define GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 +-#define GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 +-#define GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 +-#define GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa +-#define GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb +-//GPU_HDP_FLUSH_DONE +-#define GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 +-#define GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 +-#define GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 +-#define GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 +-#define GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 +-#define GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 +-#define GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 +-#define GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 +-#define GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 +-#define GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 +-#define GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa +-#define GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb +-//BIF_TRANS_PENDING +-#define BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 +-#define BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 +-//MAILBOX_MSGBUF_TRN_DW0 +-#define MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 +-//MAILBOX_MSGBUF_TRN_DW1 +-#define MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 +-//MAILBOX_MSGBUF_TRN_DW2 +-#define MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 +-//MAILBOX_MSGBUF_TRN_DW3 +-#define MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 +-//MAILBOX_MSGBUF_RCV_DW0 +-#define MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 +-//MAILBOX_MSGBUF_RCV_DW1 +-#define MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 +-//MAILBOX_MSGBUF_RCV_DW2 +-#define MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 +-//MAILBOX_MSGBUF_RCV_DW3 +-#define MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 +-//MAILBOX_CONTROL +-#define MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 +-#define MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 +-#define MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 +-#define MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 +-//MAILBOX_INT_CNTL +-#define MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 +-#define MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 +-//BIF_VMHV_MAILBOX +-#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 +-#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 +-#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 +-#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf +-#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 +-#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 +-#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 +-#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 +- +- +-// addressBlock: rcc_pf_0_BIFPFVFDEC1 +-//RCC_DOORBELL_APER_EN +-#define RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 +-//RCC_CONFIG_MEMSIZE +-#define RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 +-//RCC_CONFIG_RESERVED +-#define RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 +-//RCC_IOV_FUNC_IDENTIFIER +-#define RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 +-#define RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f +- +- +-// addressBlock: syshub_mmreg_ind_syshubdec +-//SYSHUB_INDEX +-#define SYSHUB_INDEX__INDEX__SHIFT 0x0 +-//SYSHUB_DATA +-#define SYSHUB_DATA__DATA__SHIFT 0x0 +- +- +-// addressBlock: rcc_strap_rcc_strap_internal +-//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x1 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x2 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x3 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x4 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x5 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f +-//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10 +-//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT 0x6 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x11 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x13 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d +-//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0__SHIFT 0x1e +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f +-//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18 +-//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT 0x1e +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f +-//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1 +-//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d +-//RCC_DEV1_PORT_STRAP0 +-#define RCC_DEV1_PORT_STRAP0__STRAP_ARI_EN_DN_DEV1__SHIFT 0x1 +-#define RCC_DEV1_PORT_STRAP0__STRAP_ACS_EN_DN_DEV1__SHIFT 0x2 +-#define RCC_DEV1_PORT_STRAP0__STRAP_AER_EN_DN_DEV1__SHIFT 0x3 +-#define RCC_DEV1_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV1__SHIFT 0x4 +-#define RCC_DEV1_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV1__SHIFT 0x5 +-#define RCC_DEV1_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV1__SHIFT 0x15 +-#define RCC_DEV1_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV1__SHIFT 0x18 +-#define RCC_DEV1_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV1__SHIFT 0x19 +-#define RCC_DEV1_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV1__SHIFT 0x1c +-#define RCC_DEV1_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV1__SHIFT 0x1f +-//RCC_DEV1_PORT_STRAP1 +-#define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV1__SHIFT 0x0 +-#define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV1__SHIFT 0x10 +-//RCC_DEV1_PORT_STRAP2 +-#define RCC_DEV1_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV1__SHIFT 0x0 +-#define RCC_DEV1_PORT_STRAP2__STRAP_DSN_EN_DN_DEV1__SHIFT 0x1 +-#define RCC_DEV1_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV1__SHIFT 0x2 +-#define RCC_DEV1_PORT_STRAP2__STRAP_ECN1P1_EN_DEV1__SHIFT 0x3 +-#define RCC_DEV1_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV1__SHIFT 0x4 +-#define RCC_DEV1_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV1__SHIFT 0x5 +-#define RCC_DEV1_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV1__SHIFT 0x6 +-#define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV1__SHIFT 0x7 +-#define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV1__SHIFT 0x8 +-#define RCC_DEV1_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV1__SHIFT 0x9 +-#define RCC_DEV1_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV1__SHIFT 0xc +-#define RCC_DEV1_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV1__SHIFT 0xd +-#define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV1__SHIFT 0xe +-#define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_EN_DEV1__SHIFT 0xf +-#define RCC_DEV1_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV1__SHIFT 0x10 +-#define RCC_DEV1_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV1__SHIFT 0x11 +-#define RCC_DEV1_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV1__SHIFT 0x13 +-#define RCC_DEV1_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV1__SHIFT 0x14 +-#define RCC_DEV1_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV1__SHIFT 0x17 +-#define RCC_DEV1_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV1__SHIFT 0x1a +-#define RCC_DEV1_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV1__SHIFT 0x1d +-//RCC_DEV1_PORT_STRAP3 +-#define RCC_DEV1_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV1__SHIFT 0x0 +-#define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DEV1__SHIFT 0x1 +-#define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DN_DEV1__SHIFT 0x2 +-#define RCC_DEV1_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV1__SHIFT 0x3 +-#define RCC_DEV1_PORT_STRAP3__STRAP_MSI_EN_DN_DEV1__SHIFT 0x6 +-#define RCC_DEV1_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV1__SHIFT 0x7 +-#define RCC_DEV1_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV1__SHIFT 0x8 +-#define RCC_DEV1_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV1__SHIFT 0x9 +-#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV1__SHIFT 0xb +-#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV1__SHIFT 0xe +-#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV1__SHIFT 0x12 +-#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV1__SHIFT 0x15 +-#define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DEV1__SHIFT 0x19 +-#define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV1__SHIFT 0x1b +-#define RCC_DEV1_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV1__SHIFT 0x1d +-#define RCC_DEV1_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV1__SHIFT 0x1e +-#define RCC_DEV1_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV1__SHIFT 0x1f +-//RCC_DEV1_PORT_STRAP4 +-#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV1__SHIFT 0x0 +-#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV1__SHIFT 0x8 +-#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV1__SHIFT 0x10 +-#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV1__SHIFT 0x18 +-//RCC_DEV1_PORT_STRAP5 +-#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV1__SHIFT 0x0 +-#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV1__SHIFT 0x8 +-#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV1__SHIFT 0x10 +-#define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV1__SHIFT 0x11 +-#define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV1__SHIFT 0x12 +-#define RCC_DEV1_PORT_STRAP5__STRAP_VC_EN_DN_DEV1__SHIFT 0x13 +-#define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DEV1__SHIFT 0x14 +-#define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV1__SHIFT 0x15 +-#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV1__SHIFT 0x17 +-#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV1__SHIFT 0x18 +-#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV1__SHIFT 0x19 +-#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV1__SHIFT 0x1a +-#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV1__SHIFT 0x1b +-#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV1__SHIFT 0x1c +-#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV1__SHIFT 0x1d +-#define RCC_DEV1_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV1__SHIFT 0x1e +-#define RCC_DEV1_PORT_STRAP5__STRAP_SSID_EN_DEV1__SHIFT 0x1f +-//RCC_DEV1_PORT_STRAP6 +-#define RCC_DEV1_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV1__SHIFT 0x0 +-#define RCC_DEV1_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV1__SHIFT 0x1 +-//RCC_DEV1_PORT_STRAP7 +-#define RCC_DEV1_PORT_STRAP7__STRAP_PORT_NUMBER_DEV1__SHIFT 0x0 +-#define RCC_DEV1_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV1__SHIFT 0x8 +-#define RCC_DEV1_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV1__SHIFT 0xc +-#define RCC_DEV1_PORT_STRAP7__STRAP_RP_BUSNUM_DEV1__SHIFT 0x10 +-#define RCC_DEV1_PORT_STRAP7__STRAP_DN_DEVNUM_DEV1__SHIFT 0x18 +-#define RCC_DEV1_PORT_STRAP7__STRAP_DN_FUNCID_DEV1__SHIFT 0x1d +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10 +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x1 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x0 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x1 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x2 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0__SHIFT 0x19 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_MSIX_TABLE_OFFSET_DEV0_F0__SHIFT 0x0 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT 0x1f +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0 +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x0 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x1 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x4 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x5 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0x9 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xc +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0xe +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x10 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x13 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x16 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT 0x18 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x19 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x1a +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP9 +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10 +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT 0x12 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT 0x16 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT 0x17 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18 +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x0 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x1 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x2 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1__SHIFT 0x19 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x1f +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0 +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT 0x0 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x1 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT 0x2 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1__SHIFT 0x4 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__SHIFT 0x8 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x9 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__SHIFT 0x10 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x11 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__SHIFT 0x18 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x19 +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1__SHIFT 0x0 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1__SHIFT 0x1 +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1__SHIFT 0x0 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1 +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1__SHIFT 0x0 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1 +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1__SHIFT 0x0 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1 +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT 0x0 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT 0x8 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT 0x10 +-//RCC_DEV0_EPF2_STRAP0 +-#define RCC_DEV0_EPF2_STRAP0__STRAP_DEVICE_ID_DEV0_F2__SHIFT 0x0 +-#define RCC_DEV0_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F2__SHIFT 0x10 +-#define RCC_DEV0_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV0_F2__SHIFT 0x14 +-#define RCC_DEV0_EPF2_STRAP0__STRAP_FUNC_EN_DEV0_F2__SHIFT 0x1c +-#define RCC_DEV0_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F2__SHIFT 0x1d +-#define RCC_DEV0_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV0_F2__SHIFT 0x1e +-#define RCC_DEV0_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV0_F2__SHIFT 0x1f +-//RCC_DEV0_EPF2_STRAP2 +-#define RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2__SHIFT 0x7 +-#define RCC_DEV0_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F2__SHIFT 0x8 +-#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2__SHIFT 0xe +-#define RCC_DEV0_EPF2_STRAP2__STRAP_AER_EN_DEV0_F2__SHIFT 0x10 +-#define RCC_DEV0_EPF2_STRAP2__STRAP_ACS_EN_DEV0_F2__SHIFT 0x11 +-#define RCC_DEV0_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F2__SHIFT 0x14 +-#define RCC_DEV0_EPF2_STRAP2__STRAP_DPA_EN_DEV0_F2__SHIFT 0x15 +-#define RCC_DEV0_EPF2_STRAP2__STRAP_VC_EN_DEV0_F2__SHIFT 0x17 +-#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F2__SHIFT 0x18 +-//RCC_DEV0_EPF2_STRAP3 +-#define RCC_DEV0_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F2__SHIFT 0x0 +-#define RCC_DEV0_EPF2_STRAP3__STRAP_PWR_EN_DEV0_F2__SHIFT 0x1 +-#define RCC_DEV0_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV0_F2__SHIFT 0x2 +-#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_EN_DEV0_F2__SHIFT 0x12 +-#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F2__SHIFT 0x13 +-#define RCC_DEV0_EPF2_STRAP3__STRAP_MSIX_EN_DEV0_F2__SHIFT 0x14 +-#define RCC_DEV0_EPF2_STRAP3__STRAP_PMC_DSI_DEV0_F2__SHIFT 0x18 +-#define RCC_DEV0_EPF2_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F2__SHIFT 0x19 +-#define RCC_DEV0_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F2__SHIFT 0x1a +-#define RCC_DEV0_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F2__SHIFT 0x1b +-//RCC_DEV0_EPF2_STRAP4 +-#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F2__SHIFT 0x14 +-#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV0_F2__SHIFT 0x15 +-#define RCC_DEV0_EPF2_STRAP4__STRAP_FLR_EN_DEV0_F2__SHIFT 0x16 +-#define RCC_DEV0_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV0_F2__SHIFT 0x17 +-#define RCC_DEV0_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F2__SHIFT 0x1c +-#define RCC_DEV0_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F2__SHIFT 0x1f +-//RCC_DEV0_EPF2_STRAP5 +-#define RCC_DEV0_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F2__SHIFT 0x0 +-#define RCC_DEV0_EPF2_STRAP5__STRAP_SATAIDP_EN_DEV0_F2__SHIFT 0x18 +-//RCC_DEV0_EPF2_STRAP6 +-#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_EN_DEV0_F2__SHIFT 0x0 +-#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F2__SHIFT 0x1 +-#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F2__SHIFT 0x4 +-#define RCC_DEV0_EPF2_STRAP6__STRAP_APER1_EN_DEV0_F2__SHIFT 0x8 +-#define RCC_DEV0_EPF2_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F2__SHIFT 0x9 +-//RCC_DEV0_EPF2_STRAP13 +-#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F2__SHIFT 0x0 +-#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F2__SHIFT 0x8 +-#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F2__SHIFT 0x10 +-//RCC_DEV0_EPF3_STRAP0 +-#define RCC_DEV0_EPF3_STRAP0__STRAP_DEVICE_ID_DEV0_F3__SHIFT 0x0 +-#define RCC_DEV0_EPF3_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F3__SHIFT 0x10 +-#define RCC_DEV0_EPF3_STRAP0__STRAP_MINOR_REV_ID_DEV0_F3__SHIFT 0x14 +-#define RCC_DEV0_EPF3_STRAP0__STRAP_FUNC_EN_DEV0_F3__SHIFT 0x1c +-#define RCC_DEV0_EPF3_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F3__SHIFT 0x1d +-#define RCC_DEV0_EPF3_STRAP0__STRAP_D1_SUPPORT_DEV0_F3__SHIFT 0x1e +-#define RCC_DEV0_EPF3_STRAP0__STRAP_D2_SUPPORT_DEV0_F3__SHIFT 0x1f +-//RCC_DEV0_EPF3_STRAP2 +-#define RCC_DEV0_EPF3_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F3__SHIFT 0x7 +-#define RCC_DEV0_EPF3_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F3__SHIFT 0x8 +-#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F3__SHIFT 0xe +-#define RCC_DEV0_EPF3_STRAP2__STRAP_AER_EN_DEV0_F3__SHIFT 0x10 +-#define RCC_DEV0_EPF3_STRAP2__STRAP_ACS_EN_DEV0_F3__SHIFT 0x11 +-#define RCC_DEV0_EPF3_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F3__SHIFT 0x14 +-#define RCC_DEV0_EPF3_STRAP2__STRAP_DPA_EN_DEV0_F3__SHIFT 0x15 +-#define RCC_DEV0_EPF3_STRAP2__STRAP_VC_EN_DEV0_F3__SHIFT 0x17 +-#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F3__SHIFT 0x18 +-//RCC_DEV0_EPF3_STRAP3 +-#define RCC_DEV0_EPF3_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F3__SHIFT 0x0 +-#define RCC_DEV0_EPF3_STRAP3__STRAP_PWR_EN_DEV0_F3__SHIFT 0x1 +-#define RCC_DEV0_EPF3_STRAP3__STRAP_SUBSYS_ID_DEV0_F3__SHIFT 0x2 +-#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_EN_DEV0_F3__SHIFT 0x12 +-#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F3__SHIFT 0x13 +-#define RCC_DEV0_EPF3_STRAP3__STRAP_MSIX_EN_DEV0_F3__SHIFT 0x14 +-#define RCC_DEV0_EPF3_STRAP3__STRAP_PMC_DSI_DEV0_F3__SHIFT 0x18 +-#define RCC_DEV0_EPF3_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F3__SHIFT 0x19 +-#define RCC_DEV0_EPF3_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F3__SHIFT 0x1a +-#define RCC_DEV0_EPF3_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F3__SHIFT 0x1b +-//RCC_DEV0_EPF3_STRAP4 +-#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F3__SHIFT 0x14 +-#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_EN_DEV0_F3__SHIFT 0x15 +-#define RCC_DEV0_EPF3_STRAP4__STRAP_FLR_EN_DEV0_F3__SHIFT 0x16 +-#define RCC_DEV0_EPF3_STRAP4__STRAP_PME_SUPPORT_DEV0_F3__SHIFT 0x17 +-#define RCC_DEV0_EPF3_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F3__SHIFT 0x1c +-#define RCC_DEV0_EPF3_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F3__SHIFT 0x1f +-//RCC_DEV0_EPF3_STRAP5 +-#define RCC_DEV0_EPF3_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F3__SHIFT 0x0 +-#define RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESEL_DEV0_F3__SHIFT 0x10 +-#define RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESELD_DEV0_F3__SHIFT 0x14 +-//RCC_DEV0_EPF3_STRAP6 +-#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_EN_DEV0_F3__SHIFT 0x0 +-#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F3__SHIFT 0x1 +-#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F3__SHIFT 0x4 +-//RCC_DEV0_EPF3_STRAP13 +-#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F3__SHIFT 0x0 +-#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F3__SHIFT 0x8 +-#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F3__SHIFT 0x10 +-//RCC_DEV0_EPF4_STRAP0 +-#define RCC_DEV0_EPF4_STRAP0__STRAP_DEVICE_ID_DEV0_F4__SHIFT 0x0 +-#define RCC_DEV0_EPF4_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F4__SHIFT 0x10 +-#define RCC_DEV0_EPF4_STRAP0__STRAP_MINOR_REV_ID_DEV0_F4__SHIFT 0x14 +-#define RCC_DEV0_EPF4_STRAP0__STRAP_FUNC_EN_DEV0_F4__SHIFT 0x1c +-#define RCC_DEV0_EPF4_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F4__SHIFT 0x1d +-#define RCC_DEV0_EPF4_STRAP0__STRAP_D1_SUPPORT_DEV0_F4__SHIFT 0x1e +-#define RCC_DEV0_EPF4_STRAP0__STRAP_D2_SUPPORT_DEV0_F4__SHIFT 0x1f +-//RCC_DEV0_EPF4_STRAP2 +-#define RCC_DEV0_EPF4_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F4__SHIFT 0x7 +-#define RCC_DEV0_EPF4_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F4__SHIFT 0x8 +-#define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F4__SHIFT 0xe +-#define RCC_DEV0_EPF4_STRAP2__STRAP_AER_EN_DEV0_F4__SHIFT 0x10 +-#define RCC_DEV0_EPF4_STRAP2__STRAP_ACS_EN_DEV0_F4__SHIFT 0x11 +-#define RCC_DEV0_EPF4_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F4__SHIFT 0x14 +-#define RCC_DEV0_EPF4_STRAP2__STRAP_DPA_EN_DEV0_F4__SHIFT 0x15 +-#define RCC_DEV0_EPF4_STRAP2__STRAP_VC_EN_DEV0_F4__SHIFT 0x17 +-#define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F4__SHIFT 0x18 +-//RCC_DEV0_EPF4_STRAP3 +-#define RCC_DEV0_EPF4_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F4__SHIFT 0x0 +-#define RCC_DEV0_EPF4_STRAP3__STRAP_PWR_EN_DEV0_F4__SHIFT 0x1 +-#define RCC_DEV0_EPF4_STRAP3__STRAP_SUBSYS_ID_DEV0_F4__SHIFT 0x2 +-#define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_EN_DEV0_F4__SHIFT 0x12 +-#define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F4__SHIFT 0x13 +-#define RCC_DEV0_EPF4_STRAP3__STRAP_MSIX_EN_DEV0_F4__SHIFT 0x14 +-#define RCC_DEV0_EPF4_STRAP3__STRAP_PMC_DSI_DEV0_F4__SHIFT 0x18 +-#define RCC_DEV0_EPF4_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F4__SHIFT 0x19 +-#define RCC_DEV0_EPF4_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F4__SHIFT 0x1a +-#define RCC_DEV0_EPF4_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F4__SHIFT 0x1b +-//RCC_DEV0_EPF4_STRAP4 +-#define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F4__SHIFT 0x14 +-#define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_EN_DEV0_F4__SHIFT 0x15 +-#define RCC_DEV0_EPF4_STRAP4__STRAP_FLR_EN_DEV0_F4__SHIFT 0x16 +-#define RCC_DEV0_EPF4_STRAP4__STRAP_PME_SUPPORT_DEV0_F4__SHIFT 0x17 +-#define RCC_DEV0_EPF4_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F4__SHIFT 0x1c +-#define RCC_DEV0_EPF4_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F4__SHIFT 0x1f +-//RCC_DEV0_EPF4_STRAP5 +-#define RCC_DEV0_EPF4_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F4__SHIFT 0x0 +-#define RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESEL_DEV0_F4__SHIFT 0x10 +-#define RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESELD_DEV0_F4__SHIFT 0x14 +-//RCC_DEV0_EPF4_STRAP6 +-#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_EN_DEV0_F4__SHIFT 0x0 +-#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F4__SHIFT 0x1 +-#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F4__SHIFT 0x4 +-#define RCC_DEV0_EPF4_STRAP6__STRAP_APER1_EN_DEV0_F4__SHIFT 0x8 +-#define RCC_DEV0_EPF4_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F4__SHIFT 0x9 +-#define RCC_DEV0_EPF4_STRAP6__STRAP_APER2_EN_DEV0_F4__SHIFT 0x10 +-#define RCC_DEV0_EPF4_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F4__SHIFT 0x11 +-//RCC_DEV0_EPF4_STRAP13 +-#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F4__SHIFT 0x0 +-#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F4__SHIFT 0x8 +-#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F4__SHIFT 0x10 +-//RCC_DEV0_EPF5_STRAP0 +-#define RCC_DEV0_EPF5_STRAP0__STRAP_DEVICE_ID_DEV0_F5__SHIFT 0x0 +-#define RCC_DEV0_EPF5_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F5__SHIFT 0x10 +-#define RCC_DEV0_EPF5_STRAP0__STRAP_MINOR_REV_ID_DEV0_F5__SHIFT 0x14 +-#define RCC_DEV0_EPF5_STRAP0__STRAP_FUNC_EN_DEV0_F5__SHIFT 0x1c +-#define RCC_DEV0_EPF5_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F5__SHIFT 0x1d +-#define RCC_DEV0_EPF5_STRAP0__STRAP_D1_SUPPORT_DEV0_F5__SHIFT 0x1e +-#define RCC_DEV0_EPF5_STRAP0__STRAP_D2_SUPPORT_DEV0_F5__SHIFT 0x1f +-//RCC_DEV0_EPF5_STRAP2 +-#define RCC_DEV0_EPF5_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F5__SHIFT 0x7 +-#define RCC_DEV0_EPF5_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F5__SHIFT 0x8 +-#define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F5__SHIFT 0xe +-#define RCC_DEV0_EPF5_STRAP2__STRAP_AER_EN_DEV0_F5__SHIFT 0x10 +-#define RCC_DEV0_EPF5_STRAP2__STRAP_ACS_EN_DEV0_F5__SHIFT 0x11 +-#define RCC_DEV0_EPF5_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F5__SHIFT 0x14 +-#define RCC_DEV0_EPF5_STRAP2__STRAP_DPA_EN_DEV0_F5__SHIFT 0x15 +-#define RCC_DEV0_EPF5_STRAP2__STRAP_VC_EN_DEV0_F5__SHIFT 0x17 +-#define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F5__SHIFT 0x18 +-//RCC_DEV0_EPF5_STRAP3 +-#define RCC_DEV0_EPF5_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F5__SHIFT 0x0 +-#define RCC_DEV0_EPF5_STRAP3__STRAP_PWR_EN_DEV0_F5__SHIFT 0x1 +-#define RCC_DEV0_EPF5_STRAP3__STRAP_SUBSYS_ID_DEV0_F5__SHIFT 0x2 +-#define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_EN_DEV0_F5__SHIFT 0x12 +-#define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F5__SHIFT 0x13 +-#define RCC_DEV0_EPF5_STRAP3__STRAP_MSIX_EN_DEV0_F5__SHIFT 0x14 +-#define RCC_DEV0_EPF5_STRAP3__STRAP_PMC_DSI_DEV0_F5__SHIFT 0x18 +-#define RCC_DEV0_EPF5_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F5__SHIFT 0x19 +-#define RCC_DEV0_EPF5_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F5__SHIFT 0x1a +-#define RCC_DEV0_EPF5_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F5__SHIFT 0x1b +-//RCC_DEV0_EPF5_STRAP4 +-#define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F5__SHIFT 0x14 +-#define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_EN_DEV0_F5__SHIFT 0x15 +-#define RCC_DEV0_EPF5_STRAP4__STRAP_FLR_EN_DEV0_F5__SHIFT 0x16 +-#define RCC_DEV0_EPF5_STRAP4__STRAP_PME_SUPPORT_DEV0_F5__SHIFT 0x17 +-#define RCC_DEV0_EPF5_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F5__SHIFT 0x1c +-#define RCC_DEV0_EPF5_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F5__SHIFT 0x1f +-//RCC_DEV0_EPF5_STRAP5 +-#define RCC_DEV0_EPF5_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F5__SHIFT 0x0 +-//RCC_DEV0_EPF5_STRAP6 +-#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_EN_DEV0_F5__SHIFT 0x0 +-#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F5__SHIFT 0x1 +-#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F5__SHIFT 0x4 +-#define RCC_DEV0_EPF5_STRAP6__STRAP_APER1_EN_DEV0_F5__SHIFT 0x8 +-#define RCC_DEV0_EPF5_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F5__SHIFT 0x9 +-#define RCC_DEV0_EPF5_STRAP6__STRAP_APER2_EN_DEV0_F5__SHIFT 0x10 +-#define RCC_DEV0_EPF5_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F5__SHIFT 0x11 +-//RCC_DEV0_EPF5_STRAP13 +-#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F5__SHIFT 0x0 +-#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F5__SHIFT 0x8 +-#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F5__SHIFT 0x10 +-//RCC_DEV0_EPF6_STRAP0 +-#define RCC_DEV0_EPF6_STRAP0__STRAP_DEVICE_ID_DEV0_F6__SHIFT 0x0 +-#define RCC_DEV0_EPF6_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F6__SHIFT 0x10 +-#define RCC_DEV0_EPF6_STRAP0__STRAP_MINOR_REV_ID_DEV0_F6__SHIFT 0x14 +-#define RCC_DEV0_EPF6_STRAP0__STRAP_FUNC_EN_DEV0_F6__SHIFT 0x1c +-#define RCC_DEV0_EPF6_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F6__SHIFT 0x1d +-#define RCC_DEV0_EPF6_STRAP0__STRAP_D1_SUPPORT_DEV0_F6__SHIFT 0x1e +-#define RCC_DEV0_EPF6_STRAP0__STRAP_D2_SUPPORT_DEV0_F6__SHIFT 0x1f +-//RCC_DEV0_EPF6_STRAP2 +-#define RCC_DEV0_EPF6_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F6__SHIFT 0x7 +-#define RCC_DEV0_EPF6_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F6__SHIFT 0x8 +-#define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F6__SHIFT 0xe +-#define RCC_DEV0_EPF6_STRAP2__STRAP_AER_EN_DEV0_F6__SHIFT 0x10 +-#define RCC_DEV0_EPF6_STRAP2__STRAP_ACS_EN_DEV0_F6__SHIFT 0x11 +-#define RCC_DEV0_EPF6_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F6__SHIFT 0x14 +-#define RCC_DEV0_EPF6_STRAP2__STRAP_DPA_EN_DEV0_F6__SHIFT 0x15 +-#define RCC_DEV0_EPF6_STRAP2__STRAP_VC_EN_DEV0_F6__SHIFT 0x17 +-#define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F6__SHIFT 0x18 +-//RCC_DEV0_EPF6_STRAP3 +-#define RCC_DEV0_EPF6_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F6__SHIFT 0x0 +-#define RCC_DEV0_EPF6_STRAP3__STRAP_PWR_EN_DEV0_F6__SHIFT 0x1 +-#define RCC_DEV0_EPF6_STRAP3__STRAP_SUBSYS_ID_DEV0_F6__SHIFT 0x2 +-#define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_EN_DEV0_F6__SHIFT 0x12 +-#define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F6__SHIFT 0x13 +-#define RCC_DEV0_EPF6_STRAP3__STRAP_MSIX_EN_DEV0_F6__SHIFT 0x14 +-#define RCC_DEV0_EPF6_STRAP3__STRAP_PMC_DSI_DEV0_F6__SHIFT 0x18 +-#define RCC_DEV0_EPF6_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F6__SHIFT 0x19 +-#define RCC_DEV0_EPF6_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F6__SHIFT 0x1a +-#define RCC_DEV0_EPF6_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F6__SHIFT 0x1b +-//RCC_DEV0_EPF6_STRAP4 +-#define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F6__SHIFT 0x14 +-#define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_EN_DEV0_F6__SHIFT 0x15 +-#define RCC_DEV0_EPF6_STRAP4__STRAP_FLR_EN_DEV0_F6__SHIFT 0x16 +-#define RCC_DEV0_EPF6_STRAP4__STRAP_PME_SUPPORT_DEV0_F6__SHIFT 0x17 +-#define RCC_DEV0_EPF6_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F6__SHIFT 0x1c +-#define RCC_DEV0_EPF6_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F6__SHIFT 0x1f +-//RCC_DEV0_EPF6_STRAP5 +-#define RCC_DEV0_EPF6_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F6__SHIFT 0x0 +-//RCC_DEV0_EPF6_STRAP6 +-#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_EN_DEV0_F6__SHIFT 0x0 +-#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F6__SHIFT 0x1 +-#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F6__SHIFT 0x4 +-#define RCC_DEV0_EPF6_STRAP6__STRAP_APER1_EN_DEV0_F6__SHIFT 0x8 +-#define RCC_DEV0_EPF6_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F6__SHIFT 0x9 +-#define RCC_DEV0_EPF6_STRAP6__STRAP_APER2_EN_DEV0_F6__SHIFT 0x10 +-#define RCC_DEV0_EPF6_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F6__SHIFT 0x11 +-//RCC_DEV0_EPF6_STRAP13 +-#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F6__SHIFT 0x0 +-#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F6__SHIFT 0x8 +-#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F6__SHIFT 0x10 +-//RCC_DEV0_EPF7_STRAP0 +-#define RCC_DEV0_EPF7_STRAP0__STRAP_DEVICE_ID_DEV0_F7__SHIFT 0x0 +-#define RCC_DEV0_EPF7_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F7__SHIFT 0x10 +-#define RCC_DEV0_EPF7_STRAP0__STRAP_MINOR_REV_ID_DEV0_F7__SHIFT 0x14 +-#define RCC_DEV0_EPF7_STRAP0__STRAP_FUNC_EN_DEV0_F7__SHIFT 0x1c +-#define RCC_DEV0_EPF7_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F7__SHIFT 0x1d +-#define RCC_DEV0_EPF7_STRAP0__STRAP_D1_SUPPORT_DEV0_F7__SHIFT 0x1e +-#define RCC_DEV0_EPF7_STRAP0__STRAP_D2_SUPPORT_DEV0_F7__SHIFT 0x1f +-//RCC_DEV0_EPF7_STRAP2 +-#define RCC_DEV0_EPF7_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F7__SHIFT 0x7 +-#define RCC_DEV0_EPF7_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F7__SHIFT 0x8 +-#define RCC_DEV0_EPF7_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F7__SHIFT 0xe +-#define RCC_DEV0_EPF7_STRAP2__STRAP_AER_EN_DEV0_F7__SHIFT 0x10 +-#define RCC_DEV0_EPF7_STRAP2__STRAP_ACS_EN_DEV0_F7__SHIFT 0x11 +-#define RCC_DEV0_EPF7_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F7__SHIFT 0x14 +-#define RCC_DEV0_EPF7_STRAP2__STRAP_DPA_EN_DEV0_F7__SHIFT 0x15 +-#define RCC_DEV0_EPF7_STRAP2__STRAP_VC_EN_DEV0_F7__SHIFT 0x17 +-#define RCC_DEV0_EPF7_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F7__SHIFT 0x18 +-//RCC_DEV0_EPF7_STRAP3 +-#define RCC_DEV0_EPF7_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F7__SHIFT 0x0 +-#define RCC_DEV0_EPF7_STRAP3__STRAP_PWR_EN_DEV0_F7__SHIFT 0x1 +-#define RCC_DEV0_EPF7_STRAP3__STRAP_SUBSYS_ID_DEV0_F7__SHIFT 0x2 +-#define RCC_DEV0_EPF7_STRAP3__STRAP_MSI_EN_DEV0_F7__SHIFT 0x12 +-#define RCC_DEV0_EPF7_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F7__SHIFT 0x13 +-#define RCC_DEV0_EPF7_STRAP3__STRAP_MSIX_EN_DEV0_F7__SHIFT 0x14 +-#define RCC_DEV0_EPF7_STRAP3__STRAP_PMC_DSI_DEV0_F7__SHIFT 0x18 +-#define RCC_DEV0_EPF7_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F7__SHIFT 0x19 +-#define RCC_DEV0_EPF7_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F7__SHIFT 0x1a +-#define RCC_DEV0_EPF7_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F7__SHIFT 0x1b +-//RCC_DEV0_EPF7_STRAP4 +-#define RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F7__SHIFT 0x14 +-#define RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_EN_DEV0_F7__SHIFT 0x15 +-#define RCC_DEV0_EPF7_STRAP4__STRAP_FLR_EN_DEV0_F7__SHIFT 0x16 +-#define RCC_DEV0_EPF7_STRAP4__STRAP_PME_SUPPORT_DEV0_F7__SHIFT 0x17 +-#define RCC_DEV0_EPF7_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F7__SHIFT 0x1c +-#define RCC_DEV0_EPF7_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F7__SHIFT 0x1f +-//RCC_DEV0_EPF7_STRAP5 +-#define RCC_DEV0_EPF7_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F7__SHIFT 0x0 +-//RCC_DEV0_EPF7_STRAP6 +-#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_EN_DEV0_F7__SHIFT 0x0 +-#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F7__SHIFT 0x1 +-#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F7__SHIFT 0x4 +-#define RCC_DEV0_EPF7_STRAP6__STRAP_APER1_EN_DEV0_F7__SHIFT 0x8 +-#define RCC_DEV0_EPF7_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F7__SHIFT 0x9 +-#define RCC_DEV0_EPF7_STRAP6__STRAP_APER2_EN_DEV0_F7__SHIFT 0x10 +-#define RCC_DEV0_EPF7_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F7__SHIFT 0x11 +-//RCC_DEV0_EPF7_STRAP13 +-#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F7__SHIFT 0x0 +-#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F7__SHIFT 0x8 +-#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F7__SHIFT 0x10 +-//RCC_DEV1_EPF0_STRAP0 +-#define RCC_DEV1_EPF0_STRAP0__STRAP_DEVICE_ID_DEV1_F0__SHIFT 0x0 +-#define RCC_DEV1_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F0__SHIFT 0x10 +-#define RCC_DEV1_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV1_F0__SHIFT 0x14 +-#define RCC_DEV1_EPF0_STRAP0__STRAP_FUNC_EN_DEV1_F0__SHIFT 0x1c +-#define RCC_DEV1_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F0__SHIFT 0x1d +-#define RCC_DEV1_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV1_F0__SHIFT 0x1e +-#define RCC_DEV1_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV1_F0__SHIFT 0x1f +-//RCC_DEV1_EPF0_STRAP2 +-#define RCC_DEV1_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F0__SHIFT 0x7 +-#define RCC_DEV1_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F0__SHIFT 0x8 +-#define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F0__SHIFT 0xe +-#define RCC_DEV1_EPF0_STRAP2__STRAP_ARI_EN_DEV1_F0__SHIFT 0xf +-#define RCC_DEV1_EPF0_STRAP2__STRAP_AER_EN_DEV1_F0__SHIFT 0x10 +-#define RCC_DEV1_EPF0_STRAP2__STRAP_ACS_EN_DEV1_F0__SHIFT 0x11 +-#define RCC_DEV1_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F0__SHIFT 0x14 +-#define RCC_DEV1_EPF0_STRAP2__STRAP_DPA_EN_DEV1_F0__SHIFT 0x15 +-#define RCC_DEV1_EPF0_STRAP2__STRAP_VC_EN_DEV1_F0__SHIFT 0x17 +-#define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F0__SHIFT 0x18 +-//RCC_DEV1_EPF0_STRAP3 +-#define RCC_DEV1_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F0__SHIFT 0x0 +-#define RCC_DEV1_EPF0_STRAP3__STRAP_PWR_EN_DEV1_F0__SHIFT 0x1 +-#define RCC_DEV1_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV1_F0__SHIFT 0x2 +-#define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_EN_DEV1_F0__SHIFT 0x12 +-#define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F0__SHIFT 0x13 +-#define RCC_DEV1_EPF0_STRAP3__STRAP_MSIX_EN_DEV1_F0__SHIFT 0x14 +-#define RCC_DEV1_EPF0_STRAP3__STRAP_PMC_DSI_DEV1_F0__SHIFT 0x18 +-#define RCC_DEV1_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F0__SHIFT 0x19 +-#define RCC_DEV1_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F0__SHIFT 0x1a +-#define RCC_DEV1_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F0__SHIFT 0x1b +-//RCC_DEV1_EPF0_STRAP4 +-#define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F0__SHIFT 0x14 +-#define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV1_F0__SHIFT 0x15 +-#define RCC_DEV1_EPF0_STRAP4__STRAP_FLR_EN_DEV1_F0__SHIFT 0x16 +-#define RCC_DEV1_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV1_F0__SHIFT 0x17 +-#define RCC_DEV1_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F0__SHIFT 0x1c +-#define RCC_DEV1_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F0__SHIFT 0x1f +-//RCC_DEV1_EPF0_STRAP5 +-#define RCC_DEV1_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F0__SHIFT 0x0 +-#define RCC_DEV1_EPF0_STRAP5__STRAP_SATAIDP_EN_DEV1_F0__SHIFT 0x18 +-//RCC_DEV1_EPF0_STRAP6 +-#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_EN_DEV1_F0__SHIFT 0x0 +-#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F0__SHIFT 0x1 +-#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F0__SHIFT 0x4 +-//RCC_DEV1_EPF0_STRAP13 +-#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F0__SHIFT 0x0 +-#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F0__SHIFT 0x8 +-#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F0__SHIFT 0x10 +-//RCC_DEV1_EPF1_STRAP0 +-#define RCC_DEV1_EPF1_STRAP0__STRAP_DEVICE_ID_DEV1_F1__SHIFT 0x0 +-#define RCC_DEV1_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F1__SHIFT 0x10 +-#define RCC_DEV1_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV1_F1__SHIFT 0x14 +-#define RCC_DEV1_EPF1_STRAP0__STRAP_FUNC_EN_DEV1_F1__SHIFT 0x1c +-#define RCC_DEV1_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F1__SHIFT 0x1d +-#define RCC_DEV1_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV1_F1__SHIFT 0x1e +-#define RCC_DEV1_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV1_F1__SHIFT 0x1f +-//RCC_DEV1_EPF1_STRAP2 +-#define RCC_DEV1_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F1__SHIFT 0x7 +-#define RCC_DEV1_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F1__SHIFT 0x8 +-#define RCC_DEV1_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F1__SHIFT 0xe +-#define RCC_DEV1_EPF1_STRAP2__STRAP_AER_EN_DEV1_F1__SHIFT 0x10 +-#define RCC_DEV1_EPF1_STRAP2__STRAP_ACS_EN_DEV1_F1__SHIFT 0x11 +-#define RCC_DEV1_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F1__SHIFT 0x14 +-#define RCC_DEV1_EPF1_STRAP2__STRAP_DPA_EN_DEV1_F1__SHIFT 0x15 +-#define RCC_DEV1_EPF1_STRAP2__STRAP_VC_EN_DEV1_F1__SHIFT 0x17 +-#define RCC_DEV1_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F1__SHIFT 0x18 +-//RCC_DEV1_EPF1_STRAP3 +-#define RCC_DEV1_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F1__SHIFT 0x0 +-#define RCC_DEV1_EPF1_STRAP3__STRAP_PWR_EN_DEV1_F1__SHIFT 0x1 +-#define RCC_DEV1_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV1_F1__SHIFT 0x2 +-#define RCC_DEV1_EPF1_STRAP3__STRAP_MSI_EN_DEV1_F1__SHIFT 0x12 +-#define RCC_DEV1_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F1__SHIFT 0x13 +-#define RCC_DEV1_EPF1_STRAP3__STRAP_MSIX_EN_DEV1_F1__SHIFT 0x14 +-#define RCC_DEV1_EPF1_STRAP3__STRAP_PMC_DSI_DEV1_F1__SHIFT 0x18 +-#define RCC_DEV1_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F1__SHIFT 0x19 +-#define RCC_DEV1_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F1__SHIFT 0x1a +-#define RCC_DEV1_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F1__SHIFT 0x1b +-//RCC_DEV1_EPF1_STRAP4 +-#define RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F1__SHIFT 0x14 +-#define RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV1_F1__SHIFT 0x15 +-#define RCC_DEV1_EPF1_STRAP4__STRAP_FLR_EN_DEV1_F1__SHIFT 0x16 +-#define RCC_DEV1_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV1_F1__SHIFT 0x17 +-#define RCC_DEV1_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F1__SHIFT 0x1c +-#define RCC_DEV1_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F1__SHIFT 0x1f +-//RCC_DEV1_EPF1_STRAP5 +-#define RCC_DEV1_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F1__SHIFT 0x0 +-//RCC_DEV1_EPF1_STRAP6 +-#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_EN_DEV1_F1__SHIFT 0x0 +-#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F1__SHIFT 0x1 +-#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F1__SHIFT 0x4 +-#define RCC_DEV1_EPF1_STRAP6__STRAP_APER1_EN_DEV1_F1__SHIFT 0x8 +-#define RCC_DEV1_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV1_F1__SHIFT 0x9 +-#define RCC_DEV1_EPF1_STRAP6__STRAP_APER2_EN_DEV1_F1__SHIFT 0x10 +-#define RCC_DEV1_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV1_F1__SHIFT 0x11 +-#define RCC_DEV1_EPF1_STRAP6__STRAP_APER3_EN_DEV1_F1__SHIFT 0x18 +-#define RCC_DEV1_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV1_F1__SHIFT 0x19 +-//RCC_DEV1_EPF1_STRAP13 +-#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F1__SHIFT 0x0 +-#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F1__SHIFT 0x8 +-#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F1__SHIFT 0x10 +-//RCC_DEV1_EPF2_STRAP0 +-#define RCC_DEV1_EPF2_STRAP0__STRAP_DEVICE_ID_DEV1_F2__SHIFT 0x0 +-#define RCC_DEV1_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F2__SHIFT 0x10 +-#define RCC_DEV1_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV1_F2__SHIFT 0x14 +-#define RCC_DEV1_EPF2_STRAP0__STRAP_FUNC_EN_DEV1_F2__SHIFT 0x1c +-#define RCC_DEV1_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F2__SHIFT 0x1d +-#define RCC_DEV1_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV1_F2__SHIFT 0x1e +-#define RCC_DEV1_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV1_F2__SHIFT 0x1f +-//RCC_DEV1_EPF2_STRAP2 +-#define RCC_DEV1_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F2__SHIFT 0x7 +-#define RCC_DEV1_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F2__SHIFT 0x8 +-#define RCC_DEV1_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F2__SHIFT 0xe +-#define RCC_DEV1_EPF2_STRAP2__STRAP_AER_EN_DEV1_F2__SHIFT 0x10 +-#define RCC_DEV1_EPF2_STRAP2__STRAP_ACS_EN_DEV1_F2__SHIFT 0x11 +-#define RCC_DEV1_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F2__SHIFT 0x14 +-#define RCC_DEV1_EPF2_STRAP2__STRAP_DPA_EN_DEV1_F2__SHIFT 0x15 +-#define RCC_DEV1_EPF2_STRAP2__STRAP_VC_EN_DEV1_F2__SHIFT 0x17 +-#define RCC_DEV1_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F2__SHIFT 0x18 +-//RCC_DEV1_EPF2_STRAP3 +-#define RCC_DEV1_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F2__SHIFT 0x0 +-#define RCC_DEV1_EPF2_STRAP3__STRAP_PWR_EN_DEV1_F2__SHIFT 0x1 +-#define RCC_DEV1_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV1_F2__SHIFT 0x2 +-#define RCC_DEV1_EPF2_STRAP3__STRAP_MSI_EN_DEV1_F2__SHIFT 0x12 +-#define RCC_DEV1_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F2__SHIFT 0x13 +-#define RCC_DEV1_EPF2_STRAP3__STRAP_MSIX_EN_DEV1_F2__SHIFT 0x14 +-#define RCC_DEV1_EPF2_STRAP3__STRAP_PMC_DSI_DEV1_F2__SHIFT 0x18 +-#define RCC_DEV1_EPF2_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F2__SHIFT 0x19 +-#define RCC_DEV1_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F2__SHIFT 0x1a +-#define RCC_DEV1_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F2__SHIFT 0x1b +-//RCC_DEV1_EPF2_STRAP4 +-#define RCC_DEV1_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F2__SHIFT 0x14 +-#define RCC_DEV1_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV1_F2__SHIFT 0x15 +-#define RCC_DEV1_EPF2_STRAP4__STRAP_FLR_EN_DEV1_F2__SHIFT 0x16 +-#define RCC_DEV1_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV1_F2__SHIFT 0x17 +-#define RCC_DEV1_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F2__SHIFT 0x1c +-#define RCC_DEV1_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F2__SHIFT 0x1f +-//RCC_DEV1_EPF2_STRAP5 +-#define RCC_DEV1_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F2__SHIFT 0x0 +-//RCC_DEV1_EPF2_STRAP6 +-#define RCC_DEV1_EPF2_STRAP6__STRAP_APER0_EN_DEV1_F2__SHIFT 0x0 +-#define RCC_DEV1_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F2__SHIFT 0x1 +-#define RCC_DEV1_EPF2_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F2__SHIFT 0x4 +-#define RCC_DEV1_EPF2_STRAP6__STRAP_APER1_EN_DEV1_F2__SHIFT 0x8 +-#define RCC_DEV1_EPF2_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV1_F2__SHIFT 0x9 +-#define RCC_DEV1_EPF2_STRAP6__STRAP_APER2_EN_DEV1_F2__SHIFT 0x10 +-#define RCC_DEV1_EPF2_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV1_F2__SHIFT 0x11 +-#define RCC_DEV1_EPF2_STRAP6__STRAP_APER3_EN_DEV1_F2__SHIFT 0x18 +-#define RCC_DEV1_EPF2_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV1_F2__SHIFT 0x19 +-//RCC_DEV1_EPF2_STRAP13 +-#define RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F2__SHIFT 0x0 +-#define RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F2__SHIFT 0x8 +-#define RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F2__SHIFT 0x10 +- +- +-// addressBlock: bif_rst_bif_rst_regblk +-//HARD_RST_CTRL +-#define HARD_RST_CTRL__DSPT_CFG_RST_EN__SHIFT 0x0 +-#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT 0x1 +-#define HARD_RST_CTRL__DSPT_PRV_RST_EN__SHIFT 0x2 +-#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT 0x3 +-#define HARD_RST_CTRL__EP_CFG_RST_EN__SHIFT 0x4 +-#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT 0x5 +-#define HARD_RST_CTRL__EP_PRV_RST_EN__SHIFT 0x6 +-#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT 0x7 +-#define HARD_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT 0x1c +-#define HARD_RST_CTRL__CORE_STICKY_RST_EN__SHIFT 0x1d +-#define HARD_RST_CTRL__RELOAD_STRAP_EN__SHIFT 0x1e +-#define HARD_RST_CTRL__CORE_RST_EN__SHIFT 0x1f +-//RSMU_SOFT_RST_CTRL +-#define RSMU_SOFT_RST_CTRL__DSPT_CFG_RST_EN__SHIFT 0x0 +-#define RSMU_SOFT_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT 0x1 +-#define RSMU_SOFT_RST_CTRL__DSPT_PRV_RST_EN__SHIFT 0x2 +-#define RSMU_SOFT_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT 0x3 +-#define RSMU_SOFT_RST_CTRL__EP_CFG_RST_EN__SHIFT 0x4 +-#define RSMU_SOFT_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT 0x5 +-#define RSMU_SOFT_RST_CTRL__EP_PRV_RST_EN__SHIFT 0x6 +-#define RSMU_SOFT_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT 0x7 +-#define RSMU_SOFT_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT 0x1c +-#define RSMU_SOFT_RST_CTRL__CORE_STICKY_RST_EN__SHIFT 0x1d +-#define RSMU_SOFT_RST_CTRL__RELOAD_STRAP_EN__SHIFT 0x1e +-#define RSMU_SOFT_RST_CTRL__CORE_RST_EN__SHIFT 0x1f +-//SELF_SOFT_RST +-#define SELF_SOFT_RST__DSPT0_CFG_RST__SHIFT 0x0 +-#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST__SHIFT 0x1 +-#define SELF_SOFT_RST__DSPT0_PRV_RST__SHIFT 0x2 +-#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST__SHIFT 0x3 +-#define SELF_SOFT_RST__EP0_CFG_RST__SHIFT 0x4 +-#define SELF_SOFT_RST__EP0_CFG_STICKY_RST__SHIFT 0x5 +-#define SELF_SOFT_RST__EP0_PRV_RST__SHIFT 0x6 +-#define SELF_SOFT_RST__EP0_PRV_STICKY_RST__SHIFT 0x7 +-#define SELF_SOFT_RST__SDP_PORT_RST__SHIFT 0x1b +-#define SELF_SOFT_RST__SWUS_SHADOW_RST__SHIFT 0x1c +-#define SELF_SOFT_RST__CORE_STICKY_RST__SHIFT 0x1d +-#define SELF_SOFT_RST__RELOAD_STRAP__SHIFT 0x1e +-#define SELF_SOFT_RST__CORE_RST__SHIFT 0x1f +-//GFX_DRV_MODE1_RST_CTRL +-#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_RST__SHIFT 0x0 +-#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_FLR_EXC_RST__SHIFT 0x1 +-#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_STICKY_RST__SHIFT 0x2 +-#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_PRV_RST__SHIFT 0x3 +-#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_PRV_STICKY_RST__SHIFT 0x4 +-#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_CFG_RST__SHIFT 0x5 +-#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_CFG_STICKY_RST__SHIFT 0x6 +-#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_PRV_RST__SHIFT 0x7 +-//BIF_RST_MISC_CTRL +-#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB__SHIFT 0x0 +-#define BIF_RST_MISC_CTRL__DRV_RST_MODE__SHIFT 0x2 +-#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK__SHIFT 0x4 +-#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR__SHIFT 0x5 +-#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR__SHIFT 0x6 +-#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN__SHIFT 0x8 +-#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE__SHIFT 0x9 +-#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT__SHIFT 0xa +-#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL__SHIFT 0xd +-#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL__SHIFT 0xf +-#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT 0x11 +-#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS__SHIFT 0x17 +-#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS__SHIFT 0x18 +-//BIF_RST_MISC_CTRL2 +-#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE__SHIFT 0x10 +-#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE__SHIFT 0x11 +-#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE__SHIFT 0x12 +-#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE__SHIFT 0x1f +-//BIF_RST_MISC_CTRL3 +-#define BIF_RST_MISC_CTRL3__TIMER_SCALE__SHIFT 0x0 +-#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT__SHIFT 0x4 +-#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE__SHIFT 0x6 +-#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD__SHIFT 0x7 +-#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT__SHIFT 0xa +-#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF__SHIFT 0xd +-//BIF_RST_GFXVF_FLR_IDLE +-#define BIF_RST_GFXVF_FLR_IDLE__VF0_TRANS_IDLE__SHIFT 0x0 +-#define BIF_RST_GFXVF_FLR_IDLE__VF1_TRANS_IDLE__SHIFT 0x1 +-#define BIF_RST_GFXVF_FLR_IDLE__VF2_TRANS_IDLE__SHIFT 0x2 +-#define BIF_RST_GFXVF_FLR_IDLE__VF3_TRANS_IDLE__SHIFT 0x3 +-#define BIF_RST_GFXVF_FLR_IDLE__VF4_TRANS_IDLE__SHIFT 0x4 +-#define BIF_RST_GFXVF_FLR_IDLE__VF5_TRANS_IDLE__SHIFT 0x5 +-#define BIF_RST_GFXVF_FLR_IDLE__VF6_TRANS_IDLE__SHIFT 0x6 +-#define BIF_RST_GFXVF_FLR_IDLE__VF7_TRANS_IDLE__SHIFT 0x7 +-#define BIF_RST_GFXVF_FLR_IDLE__VF8_TRANS_IDLE__SHIFT 0x8 +-#define BIF_RST_GFXVF_FLR_IDLE__VF9_TRANS_IDLE__SHIFT 0x9 +-#define BIF_RST_GFXVF_FLR_IDLE__VF10_TRANS_IDLE__SHIFT 0xa +-#define BIF_RST_GFXVF_FLR_IDLE__VF11_TRANS_IDLE__SHIFT 0xb +-#define BIF_RST_GFXVF_FLR_IDLE__VF12_TRANS_IDLE__SHIFT 0xc +-#define BIF_RST_GFXVF_FLR_IDLE__VF13_TRANS_IDLE__SHIFT 0xd +-#define BIF_RST_GFXVF_FLR_IDLE__VF14_TRANS_IDLE__SHIFT 0xe +-#define BIF_RST_GFXVF_FLR_IDLE__VF15_TRANS_IDLE__SHIFT 0xf +-#define BIF_RST_GFXVF_FLR_IDLE__SOFTPF_TRANS_IDLE__SHIFT 0x1f +-//DEV0_PF0_FLR_RST_CTRL +-#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +-#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +-#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +-#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +-#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +-#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN__SHIFT 0x5 +-#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN__SHIFT 0x6 +-#define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN__SHIFT 0x7 +-#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN__SHIFT 0x8 +-#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN__SHIFT 0x9 +-#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN__SHIFT 0xa +-#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN__SHIFT 0xb +-#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN__SHIFT 0xc +-#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN__SHIFT 0xd +-#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN__SHIFT 0xe +-#define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN__SHIFT 0xf +-#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN__SHIFT 0x10 +-#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 +-#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 +-#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 +-#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 +-//DEV0_PF1_FLR_RST_CTRL +-#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +-#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +-#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +-#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +-#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +-#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 +-#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 +-#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 +-#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 +-//DEV0_PF2_FLR_RST_CTRL +-#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +-#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +-#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +-#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +-#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +-#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 +-#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 +-#define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 +-#define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 +-//DEV0_PF3_FLR_RST_CTRL +-#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +-#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +-#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +-#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +-#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +-#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 +-#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 +-#define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 +-#define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 +-//DEV0_PF4_FLR_RST_CTRL +-#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +-#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +-#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +-#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +-#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +-#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 +-#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 +-#define DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 +-#define DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 +-//DEV0_PF5_FLR_RST_CTRL +-#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +-#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +-#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +-#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +-#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +-#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 +-#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 +-#define DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 +-#define DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 +-//DEV0_PF6_FLR_RST_CTRL +-#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +-#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +-#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +-#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +-#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +-#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 +-#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 +-#define DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 +-#define DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 +-//DEV0_PF7_FLR_RST_CTRL +-#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +-#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +-#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +-#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +-#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +-#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 +-#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 +-#define DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 +-#define DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 +-//BIF_INST_RESET_INTR_STS +-#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS__SHIFT 0x0 +-#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT 0x1 +-#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS__SHIFT 0x2 +-#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS__SHIFT 0x3 +-#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS__SHIFT 0x4 +-//BIF_PF_FLR_INTR_STS +-#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS__SHIFT 0x0 +-#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS__SHIFT 0x1 +-#define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS__SHIFT 0x2 +-#define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS__SHIFT 0x3 +-#define BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS__SHIFT 0x4 +-#define BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS__SHIFT 0x5 +-#define BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS__SHIFT 0x6 +-#define BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS__SHIFT 0x7 +-//BIF_D3HOTD0_INTR_STS +-#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS__SHIFT 0x0 +-#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS__SHIFT 0x1 +-#define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS__SHIFT 0x2 +-#define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS__SHIFT 0x3 +-#define BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS__SHIFT 0x4 +-#define BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS__SHIFT 0x5 +-#define BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS__SHIFT 0x6 +-#define BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS__SHIFT 0x7 +-//BIF_POWER_INTR_STS +-#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS__SHIFT 0x0 +-#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS__SHIFT 0x10 +-//BIF_PF_DSTATE_INTR_STS +-#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS__SHIFT 0x0 +-#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS__SHIFT 0x1 +-#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS__SHIFT 0x2 +-#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS__SHIFT 0x3 +-#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS__SHIFT 0x4 +-#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS__SHIFT 0x5 +-#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS__SHIFT 0x6 +-#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS__SHIFT 0x7 +-//BIF_PF0_VF_FLR_INTR_STS +-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF0_FLR_INTR_STS__SHIFT 0x0 +-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF1_FLR_INTR_STS__SHIFT 0x1 +-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF2_FLR_INTR_STS__SHIFT 0x2 +-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF3_FLR_INTR_STS__SHIFT 0x3 +-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF4_FLR_INTR_STS__SHIFT 0x4 +-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF5_FLR_INTR_STS__SHIFT 0x5 +-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF6_FLR_INTR_STS__SHIFT 0x6 +-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF7_FLR_INTR_STS__SHIFT 0x7 +-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF8_FLR_INTR_STS__SHIFT 0x8 +-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF9_FLR_INTR_STS__SHIFT 0x9 +-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF10_FLR_INTR_STS__SHIFT 0xa +-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF11_FLR_INTR_STS__SHIFT 0xb +-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF12_FLR_INTR_STS__SHIFT 0xc +-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF13_FLR_INTR_STS__SHIFT 0xd +-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF14_FLR_INTR_STS__SHIFT 0xe +-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF15_FLR_INTR_STS__SHIFT 0xf +-#define BIF_PF0_VF_FLR_INTR_STS__PF0_SOFTPF_FLR_INTR_STS__SHIFT 0x1f +-//BIF_INST_RESET_INTR_MASK +-#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK__SHIFT 0x0 +-#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT 0x1 +-#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK__SHIFT 0x2 +-#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK__SHIFT 0x3 +-#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK__SHIFT 0x4 +-//BIF_PF_FLR_INTR_MASK +-#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK__SHIFT 0x0 +-#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK__SHIFT 0x1 +-#define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK__SHIFT 0x2 +-#define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK__SHIFT 0x3 +-#define BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK__SHIFT 0x4 +-#define BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK__SHIFT 0x5 +-#define BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK__SHIFT 0x6 +-#define BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK__SHIFT 0x7 +-//BIF_D3HOTD0_INTR_MASK +-#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK__SHIFT 0x0 +-#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK__SHIFT 0x1 +-#define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK__SHIFT 0x2 +-#define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK__SHIFT 0x3 +-#define BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK__SHIFT 0x4 +-#define BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK__SHIFT 0x5 +-#define BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK__SHIFT 0x6 +-#define BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK__SHIFT 0x7 +-//BIF_POWER_INTR_MASK +-#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK__SHIFT 0x0 +-#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__SHIFT 0x10 +-//BIF_PF_DSTATE_INTR_MASK +-#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK__SHIFT 0x0 +-#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK__SHIFT 0x1 +-#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK__SHIFT 0x2 +-#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK__SHIFT 0x3 +-#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK__SHIFT 0x4 +-#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK__SHIFT 0x5 +-#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK__SHIFT 0x6 +-#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK__SHIFT 0x7 +-//BIF_PF0_VF_FLR_INTR_MASK +-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF0_FLR_INTR_MASK__SHIFT 0x0 +-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF1_FLR_INTR_MASK__SHIFT 0x1 +-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF2_FLR_INTR_MASK__SHIFT 0x2 +-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF3_FLR_INTR_MASK__SHIFT 0x3 +-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF4_FLR_INTR_MASK__SHIFT 0x4 +-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF5_FLR_INTR_MASK__SHIFT 0x5 +-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF6_FLR_INTR_MASK__SHIFT 0x6 +-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF7_FLR_INTR_MASK__SHIFT 0x7 +-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF8_FLR_INTR_MASK__SHIFT 0x8 +-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF9_FLR_INTR_MASK__SHIFT 0x9 +-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF10_FLR_INTR_MASK__SHIFT 0xa +-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF11_FLR_INTR_MASK__SHIFT 0xb +-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF12_FLR_INTR_MASK__SHIFT 0xc +-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF13_FLR_INTR_MASK__SHIFT 0xd +-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF14_FLR_INTR_MASK__SHIFT 0xe +-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF15_FLR_INTR_MASK__SHIFT 0xf +-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_SOFTPF_FLR_INTR_MASK__SHIFT 0x1f +-//BIF_PF_FLR_RST +-#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT 0x0 +-#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT 0x1 +-#define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST__SHIFT 0x2 +-#define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST__SHIFT 0x3 +-#define BIF_PF_FLR_RST__DEV0_PF4_FLR_RST__SHIFT 0x4 +-#define BIF_PF_FLR_RST__DEV0_PF5_FLR_RST__SHIFT 0x5 +-#define BIF_PF_FLR_RST__DEV0_PF6_FLR_RST__SHIFT 0x6 +-#define BIF_PF_FLR_RST__DEV0_PF7_FLR_RST__SHIFT 0x7 +-//BIF_PF0_VF_FLR_RST +-#define BIF_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__SHIFT 0x0 +-#define BIF_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__SHIFT 0x1 +-#define BIF_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__SHIFT 0x2 +-#define BIF_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__SHIFT 0x3 +-#define BIF_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__SHIFT 0x4 +-#define BIF_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__SHIFT 0x5 +-#define BIF_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__SHIFT 0x6 +-#define BIF_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__SHIFT 0x7 +-#define BIF_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__SHIFT 0x8 +-#define BIF_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__SHIFT 0x9 +-#define BIF_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__SHIFT 0xa +-#define BIF_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__SHIFT 0xb +-#define BIF_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__SHIFT 0xc +-#define BIF_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__SHIFT 0xd +-#define BIF_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__SHIFT 0xe +-#define BIF_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__SHIFT 0xf +-#define BIF_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__SHIFT 0x1f +-//BIF_DEV0_PF0_DSTATE_VALUE +-#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE__SHIFT 0x0 +-#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 +-#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE__SHIFT 0x10 +-//BIF_DEV0_PF1_DSTATE_VALUE +-#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE__SHIFT 0x0 +-#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 +-#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE__SHIFT 0x10 +-//BIF_DEV0_PF2_DSTATE_VALUE +-#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE__SHIFT 0x0 +-#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 +-#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE__SHIFT 0x10 +-//BIF_DEV0_PF3_DSTATE_VALUE +-#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE__SHIFT 0x0 +-#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 +-#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE__SHIFT 0x10 +-//BIF_DEV0_PF4_DSTATE_VALUE +-#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE__SHIFT 0x0 +-#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 +-#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE__SHIFT 0x10 +-//BIF_DEV0_PF5_DSTATE_VALUE +-#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE__SHIFT 0x0 +-#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 +-#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE__SHIFT 0x10 +-//BIF_DEV0_PF6_DSTATE_VALUE +-#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE__SHIFT 0x0 +-#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 +-#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE__SHIFT 0x10 +-//BIF_DEV0_PF7_DSTATE_VALUE +-#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE__SHIFT 0x0 +-#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 +-#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE__SHIFT 0x10 +-//DEV0_PF0_D3HOTD0_RST_CTRL +-#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +-#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +-#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +-#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +-#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +-//DEV0_PF1_D3HOTD0_RST_CTRL +-#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +-#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +-#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +-#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +-#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +-//DEV0_PF2_D3HOTD0_RST_CTRL +-#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +-#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +-#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +-#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +-#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +-//DEV0_PF3_D3HOTD0_RST_CTRL +-#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +-#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +-#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +-#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +-#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +-//DEV0_PF4_D3HOTD0_RST_CTRL +-#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +-#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +-#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +-#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +-#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +-//DEV0_PF5_D3HOTD0_RST_CTRL +-#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +-#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +-#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +-#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +-#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +-//DEV0_PF6_D3HOTD0_RST_CTRL +-#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +-#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +-#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +-#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +-#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +-//DEV0_PF7_D3HOTD0_RST_CTRL +-#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 +-#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 +-#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 +-#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 +-#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 +-//BIF_PORT0_DSTATE_VALUE +-#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE__SHIFT 0x0 +-#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE__SHIFT 0x10 +- +- +-// addressBlock: bif_misc_bif_misc_regblk +-//MISC_SCRATCH +-#define MISC_SCRATCH__MISC_SCRATCH0__SHIFT 0x0 +-//INTR_LINE_POLARITY +-#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0__SHIFT 0x0 +-//INTR_LINE_ENABLE +-#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0__SHIFT 0x0 +-//OUTSTANDING_VC_ALLOC +-#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC__SHIFT 0x0 +-#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC__SHIFT 0x2 +-#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC__SHIFT 0x4 +-#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC__SHIFT 0x6 +-#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC__SHIFT 0x8 +-#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC__SHIFT 0xa +-#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC__SHIFT 0xc +-#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC__SHIFT 0xe +-#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD__SHIFT 0x10 +-#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC__SHIFT 0x18 +-#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC__SHIFT 0x1a +-#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD__SHIFT 0x1c +-//BIFC_MISC_CTRL0 +-#define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN__SHIFT 0x0 +-#define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN__SHIFT 0x1 +-#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE__SHIFT 0x8 +-#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK__SHIFT 0x9 +-#define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK__SHIFT 0xa +-#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS__SHIFT 0x10 +-#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL__SHIFT 0x11 +-#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS__SHIFT 0x18 +-#define BIFC_MISC_CTRL0__VC7_DMA_IOCFG_DIS__SHIFT 0x19 +-#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS__SHIFT 0x1a +-#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE__SHIFT 0x1b +-#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE__SHIFT 0x1c +-#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION__SHIFT 0x1f +-//BIFC_MISC_CTRL1 +-#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT__SHIFT 0x0 +-#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT__SHIFT 0x1 +-#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT__SHIFT 0x2 +-#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT__SHIFT 0x3 +-#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS__SHIFT 0x4 +-#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR__SHIFT 0x5 +-#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS__SHIFT 0x6 +-#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL__SHIFT 0x7 +-#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS__SHIFT 0x8 +-#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS__SHIFT 0xa +-#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ__SHIFT 0xc +-#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE__SHIFT 0xd +-#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE__SHIFT 0xe +-#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1__SHIFT 0xf +-#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS__SHIFT 0x10 +-#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS__SHIFT 0x11 +-#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS__SHIFT 0x12 +-#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS__SHIFT 0x13 +-//BIFC_BME_ERR_LOG +-#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x0 +-#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x1 +-#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F2__SHIFT 0x2 +-#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F3__SHIFT 0x3 +-#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F4__SHIFT 0x4 +-#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F5__SHIFT 0x5 +-#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F6__SHIFT 0x6 +-#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F7__SHIFT 0x7 +-#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x10 +-#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x11 +-#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F2__SHIFT 0x12 +-#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F3__SHIFT 0x13 +-#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F4__SHIFT 0x14 +-#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F5__SHIFT 0x15 +-#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F6__SHIFT 0x16 +-#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F7__SHIFT 0x17 +-//BIFC_RCCBIH_BME_ERR_LOG +-#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x0 +-#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x1 +-#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT 0x2 +-#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT 0x3 +-#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT 0x4 +-#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT 0x5 +-#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT 0x6 +-#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT 0x7 +-#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x10 +-#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x11 +-#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT 0x12 +-#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT 0x13 +-#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT 0x14 +-#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT 0x15 +-#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT 0x16 +-#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT 0x17 +-//BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0__SHIFT 0x0 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0__SHIFT 0x2 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0__SHIFT 0x6 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0__SHIFT 0x8 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0__SHIFT 0xa +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0__SHIFT 0xc +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1__SHIFT 0x10 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1__SHIFT 0x12 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1__SHIFT 0x16 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1__SHIFT 0x18 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1__SHIFT 0x1a +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1__SHIFT 0x1c +-//BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2__SHIFT 0x0 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2__SHIFT 0x2 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2__SHIFT 0x6 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2__SHIFT 0x8 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2__SHIFT 0xa +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2__SHIFT 0xc +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3__SHIFT 0x10 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3__SHIFT 0x12 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3__SHIFT 0x16 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3__SHIFT 0x18 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3__SHIFT 0x1a +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3__SHIFT 0x1c +-//BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4__SHIFT 0x0 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4__SHIFT 0x2 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4__SHIFT 0x6 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4__SHIFT 0x8 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4__SHIFT 0xa +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4__SHIFT 0xc +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5__SHIFT 0x10 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5__SHIFT 0x12 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5__SHIFT 0x16 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5__SHIFT 0x18 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5__SHIFT 0x1a +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5__SHIFT 0x1c +-//BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6__SHIFT 0x0 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6__SHIFT 0x2 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6__SHIFT 0x6 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6__SHIFT 0x8 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6__SHIFT 0xa +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6__SHIFT 0xc +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7__SHIFT 0x10 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7__SHIFT 0x12 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7__SHIFT 0x16 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7__SHIFT 0x18 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7__SHIFT 0x1a +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7__SHIFT 0x1c +-//NBIF_VWIRE_CTRL +-#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT__SHIFT 0x4 +-#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED__SHIFT 0x8 +-#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT__SHIFT 0x14 +-#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL__SHIFT 0x1a +-//NBIF_SMN_VWR_VCHG_DIS_CTRL +-#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS__SHIFT 0x0 +-#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS__SHIFT 0x1 +-#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS__SHIFT 0x2 +-#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS__SHIFT 0x3 +-#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS__SHIFT 0x4 +-#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS__SHIFT 0x5 +-#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS__SHIFT 0x6 +-//NBIF_SMN_VWR_VCHG_RST_CTRL0 +-#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV__SHIFT 0x0 +-#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV__SHIFT 0x1 +-#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV__SHIFT 0x2 +-#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV__SHIFT 0x3 +-#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV__SHIFT 0x4 +-#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV__SHIFT 0x5 +-#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV__SHIFT 0x6 +-//NBIF_SMN_VWR_VCHG_TRIG +-#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG__SHIFT 0x0 +-#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG__SHIFT 0x1 +-#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG__SHIFT 0x2 +-#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG__SHIFT 0x3 +-#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG__SHIFT 0x4 +-#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG__SHIFT 0x5 +-#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG__SHIFT 0x6 +-//NBIF_SMN_VWR_WTRIG_CNTL +-#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS__SHIFT 0x0 +-#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS__SHIFT 0x1 +-#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS__SHIFT 0x2 +-#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS__SHIFT 0x3 +-#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS__SHIFT 0x4 +-#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS__SHIFT 0x5 +-#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS__SHIFT 0x6 +-//NBIF_SMN_VWR_VCHG_DIS_CTRL_1 +-#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV__SHIFT 0x0 +-#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV__SHIFT 0x1 +-#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV__SHIFT 0x2 +-#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV__SHIFT 0x3 +-#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV__SHIFT 0x4 +-#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV__SHIFT 0x5 +-#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV__SHIFT 0x6 +-//NBIF_MGCG_CTRL +-#define NBIF_MGCG_CTRL__NBIF_MGCG_EN__SHIFT 0x0 +-#define NBIF_MGCG_CTRL__NBIF_MGCG_MODE__SHIFT 0x1 +-#define NBIF_MGCG_CTRL__NBIF_MGCG_HYSTERESIS__SHIFT 0x2 +-//NBIF_DS_CTRL_LCLK +-#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN__SHIFT 0x0 +-#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER__SHIFT 0x10 +-//SMN_MST_CNTL0 +-#define SMN_MST_CNTL0__SMN_ARB_MODE__SHIFT 0x0 +-#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS__SHIFT 0x8 +-#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS__SHIFT 0x9 +-#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS__SHIFT 0xa +-#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS__SHIFT 0xb +-#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0__SHIFT 0x10 +-#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0__SHIFT 0x14 +-#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0__SHIFT 0x18 +-#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0__SHIFT 0x1c +-//SMN_MST_EP_CNTL1 +-#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0__SHIFT 0x0 +-#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1__SHIFT 0x1 +-#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2__SHIFT 0x2 +-#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3__SHIFT 0x3 +-#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4__SHIFT 0x4 +-#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5__SHIFT 0x5 +-#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6__SHIFT 0x6 +-#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7__SHIFT 0x7 +-//SMN_MST_EP_CNTL2 +-#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0__SHIFT 0x0 +-#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1__SHIFT 0x1 +-#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2__SHIFT 0x2 +-#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3__SHIFT 0x3 +-#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4__SHIFT 0x4 +-#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5__SHIFT 0x5 +-#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6__SHIFT 0x6 +-#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7__SHIFT 0x7 +-//NBIF_SDP_VWR_VCHG_DIS_CTRL +-#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS__SHIFT 0x0 +-#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS__SHIFT 0x1 +-#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS__SHIFT 0x2 +-#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS__SHIFT 0x3 +-#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS__SHIFT 0x4 +-#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS__SHIFT 0x5 +-#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS__SHIFT 0x6 +-#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS__SHIFT 0x7 +-#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS__SHIFT 0x18 +-//NBIF_SDP_VWR_VCHG_RST_CTRL0 +-#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN__SHIFT 0x0 +-#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN__SHIFT 0x1 +-#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN__SHIFT 0x2 +-#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN__SHIFT 0x3 +-#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN__SHIFT 0x4 +-#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN__SHIFT 0x5 +-#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN__SHIFT 0x6 +-#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN__SHIFT 0x7 +-#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN__SHIFT 0x18 +-//NBIF_SDP_VWR_VCHG_RST_CTRL1 +-#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL__SHIFT 0x0 +-#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL__SHIFT 0x1 +-#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL__SHIFT 0x2 +-#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL__SHIFT 0x3 +-#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL__SHIFT 0x4 +-#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL__SHIFT 0x5 +-#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL__SHIFT 0x6 +-#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL__SHIFT 0x7 +-#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL__SHIFT 0x18 +-//NBIF_SDP_VWR_VCHG_TRIG +-#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG__SHIFT 0x0 +-#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG__SHIFT 0x1 +-#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG__SHIFT 0x2 +-#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG__SHIFT 0x3 +-#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG__SHIFT 0x4 +-#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG__SHIFT 0x5 +-#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG__SHIFT 0x6 +-#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG__SHIFT 0x7 +-#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG__SHIFT 0x18 +-//BME_DUMMY_CNTL_0 +-#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0__SHIFT 0x0 +-#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1__SHIFT 0x2 +-#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2__SHIFT 0x4 +-#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3__SHIFT 0x6 +-#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4__SHIFT 0x8 +-#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5__SHIFT 0xa +-#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6__SHIFT 0xc +-#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7__SHIFT 0xe +-//BIFC_THT_CNTL +-#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0__SHIFT 0x0 +-#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0__SHIFT 0x4 +-#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1__SHIFT 0x8 +-//BIFC_HSTARB_CNTL +-#define BIFC_HSTARB_CNTL__SLVARB_MODE__SHIFT 0x0 +-//BIFC_GSI_CNTL +-#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE__SHIFT 0x0 +-#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE__SHIFT 0x2 +-#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN__SHIFT 0x5 +-#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN__SHIFT 0x6 +-#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN__SHIFT 0x7 +-#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN__SHIFT 0x8 +-#define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN__SHIFT 0x9 +-#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE__SHIFT 0xa +-#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE__SHIFT 0xc +-//BIFC_PCIEFUNC_CNTL +-#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC__SHIFT 0x0 +-#define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC__SHIFT 0x10 +-//BIFC_SDP_CNTL_0 +-#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS__SHIFT 0x0 +-#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS__SHIFT 0x6 +-#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS__SHIFT 0xc +-#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS__SHIFT 0x12 +-//BIFC_PERF_CNTL_0 +-#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN__SHIFT 0x0 +-#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN__SHIFT 0x1 +-#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET__SHIFT 0x8 +-#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET__SHIFT 0x9 +-#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL__SHIFT 0x10 +-#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL__SHIFT 0x18 +-//BIFC_PERF_CNTL_1 +-#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN__SHIFT 0x0 +-#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN__SHIFT 0x1 +-#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET__SHIFT 0x8 +-#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET__SHIFT 0x9 +-#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL__SHIFT 0x10 +-#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL__SHIFT 0x18 +-//BIFC_PERF_CNT_MMIO_RD +-#define BIFC_PERF_CNT_MMIO_RD__PERF_CNT_MMIO_RD_VALUE__SHIFT 0x0 +-//BIFC_PERF_CNT_MMIO_WR +-#define BIFC_PERF_CNT_MMIO_WR__PERF_CNT_MMIO_WR_VALUE__SHIFT 0x0 +-//BIFC_PERF_CNT_DMA_RD +-#define BIFC_PERF_CNT_DMA_RD__PERF_CNT_DMA_RD_VALUE__SHIFT 0x0 +-//BIFC_PERF_CNT_DMA_WR +-#define BIFC_PERF_CNT_DMA_WR__PERF_CNT_DMA_WR_VALUE__SHIFT 0x0 +-//NBIF_REGIF_ERRSET_CTRL +-#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0 +-//SMN_MST_EP_CNTL3 +-#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0__SHIFT 0x0 +-#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1__SHIFT 0x1 +-#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2__SHIFT 0x2 +-#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3__SHIFT 0x3 +-#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4__SHIFT 0x4 +-#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5__SHIFT 0x5 +-#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6__SHIFT 0x6 +-#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7__SHIFT 0x7 +-//SMN_MST_EP_CNTL4 +-#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0__SHIFT 0x0 +-#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1__SHIFT 0x1 +-#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2__SHIFT 0x2 +-#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3__SHIFT 0x3 +-#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4__SHIFT 0x4 +-#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5__SHIFT 0x5 +-#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6__SHIFT 0x6 +-#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7__SHIFT 0x7 +-//BIF_SELFRING_BUFFER_VID +-#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID__SHIFT 0x0 +-#define BIF_SELFRING_BUFFER_VID__IOHUB_RAS_INTR_CID__SHIFT 0x8 +-//BIF_SELFRING_VECTOR_CNTL +-#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS__SHIFT 0x0 +- +- +-// addressBlock: bif_ras_bif_ras_regblk +-//BIF_RAS_LEAF0_CTRL +-#define BIF_RAS_LEAF0_CTRL__POISON_DET_EN__SHIFT 0x0 +-#define BIF_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +-#define BIF_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT 0x2 +-#define BIF_RAS_LEAF0_CTRL__PARITY_DET_EN__SHIFT 0x4 +-#define BIF_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 +-#define BIF_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT 0x6 +-#define BIF_RAS_LEAF0_CTRL__ERR_EVENT_RECV__SHIFT 0x10 +-#define BIF_RAS_LEAF0_CTRL__LINK_DIS_RECV__SHIFT 0x11 +-#define BIF_RAS_LEAF0_CTRL__POISON_ERR_DET__SHIFT 0x12 +-#define BIF_RAS_LEAF0_CTRL__PARITY_ERR_DET__SHIFT 0x13 +-#define BIF_RAS_LEAF0_CTRL__ERR_EVENT_SENT__SHIFT 0x14 +-#define BIF_RAS_LEAF0_CTRL__EGRESS_STALLED__SHIFT 0x15 +-//BIF_RAS_LEAF1_CTRL +-#define BIF_RAS_LEAF1_CTRL__POISON_DET_EN__SHIFT 0x0 +-#define BIF_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +-#define BIF_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT 0x2 +-#define BIF_RAS_LEAF1_CTRL__PARITY_DET_EN__SHIFT 0x4 +-#define BIF_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 +-#define BIF_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT 0x6 +-#define BIF_RAS_LEAF1_CTRL__ERR_EVENT_RECV__SHIFT 0x10 +-#define BIF_RAS_LEAF1_CTRL__LINK_DIS_RECV__SHIFT 0x11 +-#define BIF_RAS_LEAF1_CTRL__POISON_ERR_DET__SHIFT 0x12 +-#define BIF_RAS_LEAF1_CTRL__PARITY_ERR_DET__SHIFT 0x13 +-#define BIF_RAS_LEAF1_CTRL__ERR_EVENT_SENT__SHIFT 0x14 +-#define BIF_RAS_LEAF1_CTRL__EGRESS_STALLED__SHIFT 0x15 +-//BIF_RAS_LEAF2_CTRL +-#define BIF_RAS_LEAF2_CTRL__POISON_DET_EN__SHIFT 0x0 +-#define BIF_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 +-#define BIF_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT 0x2 +-#define BIF_RAS_LEAF2_CTRL__PARITY_DET_EN__SHIFT 0x4 +-#define BIF_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 +-#define BIF_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT 0x6 +-#define BIF_RAS_LEAF2_CTRL__ERR_EVENT_RECV__SHIFT 0x10 +-#define BIF_RAS_LEAF2_CTRL__LINK_DIS_RECV__SHIFT 0x11 +-#define BIF_RAS_LEAF2_CTRL__POISON_ERR_DET__SHIFT 0x12 +-#define BIF_RAS_LEAF2_CTRL__PARITY_ERR_DET__SHIFT 0x13 +-#define BIF_RAS_LEAF2_CTRL__ERR_EVENT_SENT__SHIFT 0x14 +-#define BIF_RAS_LEAF2_CTRL__EGRESS_STALLED__SHIFT 0x15 +-//BIF_RAS_MISC_CTRL +-#define BIF_RAS_MISC_CTRL__LINKDIS_TRIG_ERREVENT_EN__SHIFT 0x0 +-//BIF_IOHUB_RAS_IH_CNTL +-#define BIF_IOHUB_RAS_IH_CNTL__RAS_IH_INTR_EN__SHIFT 0x0 +-//BIF_RAS_VWR_FROM_IOHUB +-#define BIF_RAS_VWR_FROM_IOHUB__RAS_IH_INTR_TRIG__SHIFT 0x0 +- +- +-// addressBlock: rcc_pfc_amdgfx_RCCPFCDEC +-//RCC_PFC_LTR_CNTL +-#define RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 +-#define RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa +-#define RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf +-#define RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 +-#define RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a +-#define RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f +-//RCC_PFC_PME_RESTORE +-#define RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 +-#define RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 +-//RCC_PFC_STICKY_RESTORE_0 +-#define RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 +-#define RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 +-#define RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 +-#define RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 +-#define RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 +-#define RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 +-#define RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 +-#define RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 +-//RCC_PFC_STICKY_RESTORE_1 +-#define RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 +-//RCC_PFC_STICKY_RESTORE_2 +-#define RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 +-//RCC_PFC_STICKY_RESTORE_3 +-#define RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 +-//RCC_PFC_STICKY_RESTORE_4 +-#define RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 +-//RCC_PFC_STICKY_RESTORE_5 +-#define RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 +-//RCC_PFC_AUXPWR_CNTL +-#define RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 +-#define RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 +- +- +-// addressBlock: rcc_pfc_amdgfxaz_RCCPFCDEC +-//RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL +-#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 +-#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa +-#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf +-#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 +-#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a +-#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f +-//RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE +-#define RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 +-#define RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 +-//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0 +-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 +-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 +-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 +-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 +-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 +-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 +-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 +-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 +-//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1 +-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 +-//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2 +-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 +-//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3 +-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 +-//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4 +-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 +-//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5 +-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 +-//RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL +-#define RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 +-#define RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 +- +- +-// addressBlock: pciemsix_amdgfx_MSIXTDEC +-//PCIEMSIX_VECT0_ADDR_LO +-#define PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +-//PCIEMSIX_VECT0_ADDR_HI +-#define PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +-//PCIEMSIX_VECT0_MSG_DATA +-#define PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 +-//PCIEMSIX_VECT0_CONTROL +-#define PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 +-//PCIEMSIX_VECT1_ADDR_LO +-#define PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +-//PCIEMSIX_VECT1_ADDR_HI +-#define PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +-//PCIEMSIX_VECT1_MSG_DATA +-#define PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 +-//PCIEMSIX_VECT1_CONTROL +-#define PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 +-//PCIEMSIX_VECT2_ADDR_LO +-#define PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +-//PCIEMSIX_VECT2_ADDR_HI +-#define PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +-//PCIEMSIX_VECT2_MSG_DATA +-#define PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 +-//PCIEMSIX_VECT2_CONTROL +-#define PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 +-//PCIEMSIX_VECT3_ADDR_LO +-#define PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +-//PCIEMSIX_VECT3_ADDR_HI +-#define PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +-//PCIEMSIX_VECT3_MSG_DATA +-#define PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 +-//PCIEMSIX_VECT3_CONTROL +-#define PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 +-//PCIEMSIX_VECT4_ADDR_LO +-#define PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +-//PCIEMSIX_VECT4_ADDR_HI +-#define PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +-//PCIEMSIX_VECT4_MSG_DATA +-#define PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 +-//PCIEMSIX_VECT4_CONTROL +-#define PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 +-//PCIEMSIX_VECT5_ADDR_LO +-#define PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +-//PCIEMSIX_VECT5_ADDR_HI +-#define PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +-//PCIEMSIX_VECT5_MSG_DATA +-#define PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 +-//PCIEMSIX_VECT5_CONTROL +-#define PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 +-//PCIEMSIX_VECT6_ADDR_LO +-#define PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +-//PCIEMSIX_VECT6_ADDR_HI +-#define PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +-//PCIEMSIX_VECT6_MSG_DATA +-#define PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 +-//PCIEMSIX_VECT6_CONTROL +-#define PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 +-//PCIEMSIX_VECT7_ADDR_LO +-#define PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +-//PCIEMSIX_VECT7_ADDR_HI +-#define PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +-//PCIEMSIX_VECT7_MSG_DATA +-#define PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 +-//PCIEMSIX_VECT7_CONTROL +-#define PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 +-//PCIEMSIX_VECT8_ADDR_LO +-#define PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +-//PCIEMSIX_VECT8_ADDR_HI +-#define PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +-//PCIEMSIX_VECT8_MSG_DATA +-#define PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 +-//PCIEMSIX_VECT8_CONTROL +-#define PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 +-//PCIEMSIX_VECT9_ADDR_LO +-#define PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +-//PCIEMSIX_VECT9_ADDR_HI +-#define PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +-//PCIEMSIX_VECT9_MSG_DATA +-#define PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT 0x0 +-//PCIEMSIX_VECT9_CONTROL +-#define PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT 0x0 +-//PCIEMSIX_VECT10_ADDR_LO +-#define PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +-//PCIEMSIX_VECT10_ADDR_HI +-#define PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +-//PCIEMSIX_VECT10_MSG_DATA +-#define PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT 0x0 +-//PCIEMSIX_VECT10_CONTROL +-#define PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT 0x0 +-//PCIEMSIX_VECT11_ADDR_LO +-#define PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +-//PCIEMSIX_VECT11_ADDR_HI +-#define PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +-//PCIEMSIX_VECT11_MSG_DATA +-#define PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT 0x0 +-//PCIEMSIX_VECT11_CONTROL +-#define PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT 0x0 +-//PCIEMSIX_VECT12_ADDR_LO +-#define PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +-//PCIEMSIX_VECT12_ADDR_HI +-#define PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +-//PCIEMSIX_VECT12_MSG_DATA +-#define PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT 0x0 +-//PCIEMSIX_VECT12_CONTROL +-#define PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT 0x0 +-//PCIEMSIX_VECT13_ADDR_LO +-#define PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +-//PCIEMSIX_VECT13_ADDR_HI +-#define PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +-//PCIEMSIX_VECT13_MSG_DATA +-#define PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT 0x0 +-//PCIEMSIX_VECT13_CONTROL +-#define PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT 0x0 +-//PCIEMSIX_VECT14_ADDR_LO +-#define PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +-//PCIEMSIX_VECT14_ADDR_HI +-#define PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +-//PCIEMSIX_VECT14_MSG_DATA +-#define PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT 0x0 +-//PCIEMSIX_VECT14_CONTROL +-#define PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT 0x0 +-//PCIEMSIX_VECT15_ADDR_LO +-#define PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +-//PCIEMSIX_VECT15_ADDR_HI +-#define PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +-//PCIEMSIX_VECT15_MSG_DATA +-#define PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT 0x0 +-//PCIEMSIX_VECT15_CONTROL +-#define PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT 0x0 +-//PCIEMSIX_VECT16_ADDR_LO +-#define PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +-//PCIEMSIX_VECT16_ADDR_HI +-#define PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +-//PCIEMSIX_VECT16_MSG_DATA +-#define PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT 0x0 +-//PCIEMSIX_VECT16_CONTROL +-#define PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT 0x0 +-//PCIEMSIX_VECT17_ADDR_LO +-#define PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +-//PCIEMSIX_VECT17_ADDR_HI +-#define PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +-//PCIEMSIX_VECT17_MSG_DATA +-#define PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT 0x0 +-//PCIEMSIX_VECT17_CONTROL +-#define PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT 0x0 +-//PCIEMSIX_VECT18_ADDR_LO +-#define PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +-//PCIEMSIX_VECT18_ADDR_HI +-#define PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +-//PCIEMSIX_VECT18_MSG_DATA +-#define PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT 0x0 +-//PCIEMSIX_VECT18_CONTROL +-#define PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT 0x0 +-//PCIEMSIX_VECT19_ADDR_LO +-#define PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +-//PCIEMSIX_VECT19_ADDR_HI +-#define PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +-//PCIEMSIX_VECT19_MSG_DATA +-#define PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT 0x0 +-//PCIEMSIX_VECT19_CONTROL +-#define PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT 0x0 +-//PCIEMSIX_VECT20_ADDR_LO +-#define PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +-//PCIEMSIX_VECT20_ADDR_HI +-#define PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +-//PCIEMSIX_VECT20_MSG_DATA +-#define PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT 0x0 +-//PCIEMSIX_VECT20_CONTROL +-#define PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT 0x0 +-//PCIEMSIX_VECT21_ADDR_LO +-#define PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +-//PCIEMSIX_VECT21_ADDR_HI +-#define PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +-//PCIEMSIX_VECT21_MSG_DATA +-#define PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT 0x0 +-//PCIEMSIX_VECT21_CONTROL +-#define PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT 0x0 +-//PCIEMSIX_VECT22_ADDR_LO +-#define PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +-//PCIEMSIX_VECT22_ADDR_HI +-#define PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +-//PCIEMSIX_VECT22_MSG_DATA +-#define PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT 0x0 +-//PCIEMSIX_VECT22_CONTROL +-#define PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT 0x0 +-//PCIEMSIX_VECT23_ADDR_LO +-#define PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +-//PCIEMSIX_VECT23_ADDR_HI +-#define PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +-//PCIEMSIX_VECT23_MSG_DATA +-#define PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT 0x0 +-//PCIEMSIX_VECT23_CONTROL +-#define PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT 0x0 +-//PCIEMSIX_VECT24_ADDR_LO +-#define PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +-//PCIEMSIX_VECT24_ADDR_HI +-#define PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +-//PCIEMSIX_VECT24_MSG_DATA +-#define PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT 0x0 +-//PCIEMSIX_VECT24_CONTROL +-#define PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT 0x0 +-//PCIEMSIX_VECT25_ADDR_LO +-#define PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +-//PCIEMSIX_VECT25_ADDR_HI +-#define PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +-//PCIEMSIX_VECT25_MSG_DATA +-#define PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT 0x0 +-//PCIEMSIX_VECT25_CONTROL +-#define PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT 0x0 +-//PCIEMSIX_VECT26_ADDR_LO +-#define PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +-//PCIEMSIX_VECT26_ADDR_HI +-#define PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +-//PCIEMSIX_VECT26_MSG_DATA +-#define PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT 0x0 +-//PCIEMSIX_VECT26_CONTROL +-#define PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT 0x0 +-//PCIEMSIX_VECT27_ADDR_LO +-#define PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +-//PCIEMSIX_VECT27_ADDR_HI +-#define PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +-//PCIEMSIX_VECT27_MSG_DATA +-#define PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT 0x0 +-//PCIEMSIX_VECT27_CONTROL +-#define PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT 0x0 +-//PCIEMSIX_VECT28_ADDR_LO +-#define PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +-//PCIEMSIX_VECT28_ADDR_HI +-#define PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +-//PCIEMSIX_VECT28_MSG_DATA +-#define PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT 0x0 +-//PCIEMSIX_VECT28_CONTROL +-#define PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT 0x0 +-//PCIEMSIX_VECT29_ADDR_LO +-#define PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +-//PCIEMSIX_VECT29_ADDR_HI +-#define PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +-//PCIEMSIX_VECT29_MSG_DATA +-#define PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT 0x0 +-//PCIEMSIX_VECT29_CONTROL +-#define PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT 0x0 +-//PCIEMSIX_VECT30_ADDR_LO +-#define PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +-//PCIEMSIX_VECT30_ADDR_HI +-#define PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +-//PCIEMSIX_VECT30_MSG_DATA +-#define PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT 0x0 +-//PCIEMSIX_VECT30_CONTROL +-#define PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT 0x0 +-//PCIEMSIX_VECT31_ADDR_LO +-#define PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 +-//PCIEMSIX_VECT31_ADDR_HI +-#define PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 +-//PCIEMSIX_VECT31_MSG_DATA +-#define PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT 0x0 +-//PCIEMSIX_VECT31_CONTROL +-#define PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT 0x0 +- +- +-// addressBlock: pciemsix_amdgfx_MSIXPDEC +-//PCIEMSIX_PBA +-#define PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT 0x0 +- +- +-// addressBlock: syshub_mmreg_ind_syshubind +-//SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0 +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1 +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2 +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3 +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4 +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5 +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6 +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7 +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10 +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11 +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12 +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13 +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14 +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15 +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16 +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17 +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__SHIFT 0x1f +-//SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__SHIFT 0x0 +-//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK +-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en__SHIFT 0x0 +-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en__SHIFT 0x1 +-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__SHIFT 0xf +-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en__SHIFT 0x10 +-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en__SHIFT 0x11 +-//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK +-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en__SHIFT 0x0 +-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en__SHIFT 0x1 +-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__SHIFT 0xf +-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en__SHIFT 0x10 +-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en__SHIFT 0x11 +-//SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 +-//SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL +-#define SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 +-#define SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 +-#define SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 +-//SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +-//SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +-//SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +-//SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +-//SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +-//SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +-//SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL +-#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +-#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +-#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +-#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +-#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +-#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +-//SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL +-#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +-#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +-#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +-#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +-#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +-#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +-//SYSHUBMMREGIND_SYSHUB_CG_CNTL +-#define SYSHUBMMREGIND_SYSHUB_CG_CNTL__SYSHUB_CG_EN__SHIFT 0x0 +-#define SYSHUBMMREGIND_SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER__SHIFT 0x8 +-#define SYSHUBMMREGIND_SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER__SHIFT 0x10 +-//SYSHUBMMREGIND_SYSHUB_TRANS_IDLE +-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0__SHIFT 0x0 +-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1__SHIFT 0x1 +-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2__SHIFT 0x2 +-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3__SHIFT 0x3 +-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4__SHIFT 0x4 +-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5__SHIFT 0x5 +-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6__SHIFT 0x6 +-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7__SHIFT 0x7 +-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8__SHIFT 0x8 +-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9__SHIFT 0x9 +-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10__SHIFT 0xa +-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11__SHIFT 0xb +-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12__SHIFT 0xc +-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13__SHIFT 0xd +-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14__SHIFT 0xe +-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15__SHIFT 0xf +-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF__SHIFT 0x10 +-//SYSHUBMMREGIND_SYSHUB_HP_TIMER +-#define SYSHUBMMREGIND_SYSHUB_HP_TIMER__SYSHUB_HP_TIMER__SHIFT 0x0 +-//SYSHUBMMREGIND_SYSHUB_SCRATCH +-#define SYSHUBMMREGIND_SYSHUB_SCRATCH__SCRATCH__SHIFT 0x0 +-//SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0 +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1 +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2 +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3 +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4 +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5 +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6 +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7 +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10 +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11 +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12 +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13 +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14 +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15 +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16 +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17 +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN__SHIFT 0x1f +-//SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER__SHIFT 0x0 +-//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK +-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en__SHIFT 0xf +-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en__SHIFT 0x10 +-//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK +-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en__SHIFT 0xf +-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en__SHIFT 0x10 +-//SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 +-//SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 +-//SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +-//SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +-//SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +-//SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +-//SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +-//SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +-//SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +-//SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +-//SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +-//SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 +-//MASK +- +- +-// addressBlock: bif_cfg_dev0_epf0_bifcfgdecp +-//VENDOR_ID +-#define VENDOR_ID__VENDOR_ID__MASK 0xFFFFL +-//DEVICE_ID +-#define DEVICE_ID__DEVICE_ID__MASK 0xFFFFL +-//COMMAND +-#define COMMAND__IO_ACCESS_EN__MASK 0x0001L +-#define COMMAND__MEM_ACCESS_EN__MASK 0x0002L +-#define COMMAND__BUS_MASTER_EN__MASK 0x0004L +-#define COMMAND__SPECIAL_CYCLE_EN__MASK 0x0008L +-#define COMMAND__MEM_WRITE_INVALIDATE_EN__MASK 0x0010L +-#define COMMAND__PAL_SNOOP_EN__MASK 0x0020L +-#define COMMAND__PARITY_ERROR_RESPONSE__MASK 0x0040L +-#define COMMAND__AD_STEPPING__MASK 0x0080L +-#define COMMAND__SERR_EN__MASK 0x0100L +-#define COMMAND__FAST_B2B_EN__MASK 0x0200L +-#define COMMAND__INT_DIS__MASK 0x0400L +-//STATUS +-#define STATUS__INT_STATUS__MASK 0x0008L +-#define STATUS__CAP_LIST__MASK 0x0010L +-#define STATUS__PCI_66_EN__MASK 0x0020L +-#define STATUS__FAST_BACK_CAPABLE__MASK 0x0080L +-#define STATUS__MASTER_DATA_PARITY_ERROR__MASK 0x0100L +-#define STATUS__DEVSEL_TIMING__MASK 0x0600L +-#define STATUS__SIGNAL_TARGET_ABORT__MASK 0x0800L +-#define STATUS__RECEIVED_TARGET_ABORT__MASK 0x1000L +-#define STATUS__RECEIVED_MASTER_ABORT__MASK 0x2000L +-#define STATUS__SIGNALED_SYSTEM_ERROR__MASK 0x4000L +-#define STATUS__PARITY_ERROR_DETECTED__MASK 0x8000L +-//REVISION_ID +-#define REVISION_ID__MINOR_REV_ID__MASK 0x0FL +-#define REVISION_ID__MAJOR_REV_ID__MASK 0xF0L +-//PROG_INTERFACE +-#define PROG_INTERFACE__PROG_INTERFACE__MASK 0xFFL +-//SUB_CLASS +-#define SUB_CLASS__SUB_CLASS__MASK 0xFFL +-//BASE_CLASS +-#define BASE_CLASS__BASE_CLASS__MASK 0xFFL +-//CACHE_LINE +-#define CACHE_LINE__CACHE_LINE_SIZE__MASK 0xFFL +-//LATENCY +-#define LATENCY__LATENCY_TIMER__MASK 0xFFL +-//HEADER +-#define HEADER__HEADER_TYPE__MASK 0x7FL +-#define HEADER__DEVICE_TYPE__MASK 0x80L +-//BIST +-#define BIST__BIST_COMP__MASK 0x0FL +-#define BIST__BIST_STRT__MASK 0x40L +-#define BIST__BIST_CAP__MASK 0x80L +-//BASE_ADDR_1 +-#define BASE_ADDR_1__BASE_ADDR__MASK 0xFFFFFFFFL +-//BASE_ADDR_2 +-#define BASE_ADDR_2__BASE_ADDR__MASK 0xFFFFFFFFL +-//BASE_ADDR_3 +-#define BASE_ADDR_3__BASE_ADDR__MASK 0xFFFFFFFFL +-//BASE_ADDR_4 +-#define BASE_ADDR_4__BASE_ADDR__MASK 0xFFFFFFFFL +-//BASE_ADDR_5 +-#define BASE_ADDR_5__BASE_ADDR__MASK 0xFFFFFFFFL +-//BASE_ADDR_6 +-#define BASE_ADDR_6__BASE_ADDR__MASK 0xFFFFFFFFL +-//ADAPTER_ID +-#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID__MASK 0x0000FFFFL +-#define ADAPTER_ID__SUBSYSTEM_ID__MASK 0xFFFF0000L +-//ROM_BASE_ADDR +-#define ROM_BASE_ADDR__BASE_ADDR__MASK 0xFFFFFFFFL +-//CAP_PTR +-#define CAP_PTR__CAP_PTR__MASK 0x000000FFL +-//INTERRUPT_LINE +-#define INTERRUPT_LINE__INTERRUPT_LINE__MASK 0xFFL +-//INTERRUPT_PIN +-#define INTERRUPT_PIN__INTERRUPT_PIN__MASK 0xFFL +-//MIN_GRANT +-#define MIN_GRANT__MIN_GNT__MASK 0xFFL +-//MAX_LATENCY +-#define MAX_LATENCY__MAX_LAT__MASK 0xFFL +-//VENDOR_CAP_LIST +-#define VENDOR_CAP_LIST__CAP_ID__MASK 0x000000FFL +-#define VENDOR_CAP_LIST__NEXT_PTR__MASK 0x0000FF00L +-#define VENDOR_CAP_LIST__LENGTH__MASK 0x00FF0000L +-//ADAPTER_ID_W +-#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__MASK 0x0000FFFFL +-#define ADAPTER_ID_W__SUBSYSTEM_ID__MASK 0xFFFF0000L +-//PMI_CAP_LIST +-#define PMI_CAP_LIST__CAP_ID__MASK 0x00FFL +-#define PMI_CAP_LIST__NEXT_PTR__MASK 0xFF00L +-//PMI_CAP +-#define PMI_CAP__VERSION__MASK 0x0007L +-#define PMI_CAP__PME_CLOCK__MASK 0x0008L +-#define PMI_CAP__DEV_SPECIFIC_INIT__MASK 0x0020L +-#define PMI_CAP__AUX_CURRENT__MASK 0x01C0L +-#define PMI_CAP__D1_SUPPORT__MASK 0x0200L +-#define PMI_CAP__D2_SUPPORT__MASK 0x0400L +-#define PMI_CAP__PME_SUPPORT__MASK 0xF800L +-//PMI_STATUS_CNTL +-#define PMI_STATUS_CNTL__POWER_STATE__MASK 0x00000003L +-#define PMI_STATUS_CNTL__NO_SOFT_RESET__MASK 0x00000008L +-#define PMI_STATUS_CNTL__PME_EN__MASK 0x00000100L +-#define PMI_STATUS_CNTL__DATA_SELECT__MASK 0x00001E00L +-#define PMI_STATUS_CNTL__DATA_SCALE__MASK 0x00006000L +-#define PMI_STATUS_CNTL__PME_STATUS__MASK 0x00008000L +-#define PMI_STATUS_CNTL__B2_B3_SUPPORT__MASK 0x00400000L +-#define PMI_STATUS_CNTL__BUS_PWR_EN__MASK 0x00800000L +-#define PMI_STATUS_CNTL__PMI_DATA__MASK 0xFF000000L +-//PCIE_CAP_LIST +-#define PCIE_CAP_LIST__CAP_ID__MASK 0x00FFL +-#define PCIE_CAP_LIST__NEXT_PTR__MASK 0xFF00L +-//PCIE_CAP +-#define PCIE_CAP__VERSION__MASK 0x000FL +-#define PCIE_CAP__DEVICE_TYPE__MASK 0x00F0L +-#define PCIE_CAP__SLOT_IMPLEMENTED__MASK 0x0100L +-#define PCIE_CAP__INT_MESSAGE_NUM__MASK 0x3E00L +-//DEVICE_CAP +-#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT__MASK 0x00000007L +-#define DEVICE_CAP__PHANTOM_FUNC__MASK 0x00000018L +-#define DEVICE_CAP__EXTENDED_TAG__MASK 0x00000020L +-#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__MASK 0x000001C0L +-#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY__MASK 0x00000E00L +-#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING__MASK 0x00008000L +-#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__MASK 0x03FC0000L +-#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__MASK 0x0C000000L +-#define DEVICE_CAP__FLR_CAPABLE__MASK 0x10000000L +-//DEVICE_CNTL +-#define DEVICE_CNTL__CORR_ERR_EN__MASK 0x0001L +-#define DEVICE_CNTL__NON_FATAL_ERR_EN__MASK 0x0002L +-#define DEVICE_CNTL__FATAL_ERR_EN__MASK 0x0004L +-#define DEVICE_CNTL__USR_REPORT_EN__MASK 0x0008L +-#define DEVICE_CNTL__RELAXED_ORD_EN__MASK 0x0010L +-#define DEVICE_CNTL__MAX_PAYLOAD_SIZE__MASK 0x00E0L +-#define DEVICE_CNTL__EXTENDED_TAG_EN__MASK 0x0100L +-#define DEVICE_CNTL__PHANTOM_FUNC_EN__MASK 0x0200L +-#define DEVICE_CNTL__AUX_POWER_PM_EN__MASK 0x0400L +-#define DEVICE_CNTL__NO_SNOOP_EN__MASK 0x0800L +-#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE__MASK 0x7000L +-#define DEVICE_CNTL__INITIATE_FLR__MASK 0x8000L +-//DEVICE_STATUS +-#define DEVICE_STATUS__CORR_ERR__MASK 0x0001L +-#define DEVICE_STATUS__NON_FATAL_ERR__MASK 0x0002L +-#define DEVICE_STATUS__FATAL_ERR__MASK 0x0004L +-#define DEVICE_STATUS__USR_DETECTED__MASK 0x0008L +-#define DEVICE_STATUS__AUX_PWR__MASK 0x0010L +-#define DEVICE_STATUS__TRANSACTIONS_PEND__MASK 0x0020L +-//LINK_CAP +-#define LINK_CAP__LINK_SPEED__MASK 0x0000000FL +-#define LINK_CAP__LINK_WIDTH__MASK 0x000003F0L +-#define LINK_CAP__PM_SUPPORT__MASK 0x00000C00L +-#define LINK_CAP__L0S_EXIT_LATENCY__MASK 0x00007000L +-#define LINK_CAP__L1_EXIT_LATENCY__MASK 0x00038000L +-#define LINK_CAP__CLOCK_POWER_MANAGEMENT__MASK 0x00040000L +-#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__MASK 0x00080000L +-#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__MASK 0x00100000L +-#define LINK_CAP__LINK_BW_NOTIFICATION_CAP__MASK 0x00200000L +-#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__MASK 0x00400000L +-#define LINK_CAP__PORT_NUMBER__MASK 0xFF000000L +-//LINK_CNTL +-#define LINK_CNTL__PM_CONTROL__MASK 0x0003L +-#define LINK_CNTL__READ_CPL_BOUNDARY__MASK 0x0008L +-#define LINK_CNTL__LINK_DIS__MASK 0x0010L +-#define LINK_CNTL__RETRAIN_LINK__MASK 0x0020L +-#define LINK_CNTL__COMMON_CLOCK_CFG__MASK 0x0040L +-#define LINK_CNTL__EXTENDED_SYNC__MASK 0x0080L +-#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__MASK 0x0100L +-#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__MASK 0x0200L +-#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__MASK 0x0400L +-#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__MASK 0x0800L +-//LINK_STATUS +-#define LINK_STATUS__CURRENT_LINK_SPEED__MASK 0x000FL +-#define LINK_STATUS__NEGOTIATED_LINK_WIDTH__MASK 0x03F0L +-#define LINK_STATUS__LINK_TRAINING__MASK 0x0800L +-#define LINK_STATUS__SLOT_CLOCK_CFG__MASK 0x1000L +-#define LINK_STATUS__DL_ACTIVE__MASK 0x2000L +-#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__MASK 0x4000L +-#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__MASK 0x8000L +-//DEVICE_CAP2 +-#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__MASK 0x0000000FL +-#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__MASK 0x00000010L +-#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__MASK 0x00000020L +-#define DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__MASK 0x00000040L +-#define DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__MASK 0x00000080L +-#define DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__MASK 0x00000100L +-#define DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__MASK 0x00000200L +-#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__MASK 0x00000400L +-#define DEVICE_CAP2__LTR_SUPPORTED__MASK 0x00000800L +-#define DEVICE_CAP2__TPH_CPLR_SUPPORTED__MASK 0x00003000L +-#define DEVICE_CAP2__OBFF_SUPPORTED__MASK 0x000C0000L +-#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__MASK 0x00100000L +-#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__MASK 0x00200000L +-#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__MASK 0x00C00000L +-//DEVICE_CNTL2 +-#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE__MASK 0x000FL +-#define DEVICE_CNTL2__CPL_TIMEOUT_DIS__MASK 0x0010L +-#define DEVICE_CNTL2__ARI_FORWARDING_EN__MASK 0x0020L +-#define DEVICE_CNTL2__ATOMICOP_REQUEST_EN__MASK 0x0040L +-#define DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__MASK 0x0080L +-#define DEVICE_CNTL2__IDO_REQUEST_ENABLE__MASK 0x0100L +-#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE__MASK 0x0200L +-#define DEVICE_CNTL2__LTR_EN__MASK 0x0400L +-#define DEVICE_CNTL2__OBFF_EN__MASK 0x6000L +-#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__MASK 0x8000L +-//DEVICE_STATUS2 +-#define DEVICE_STATUS2__RESERVED__MASK 0xFFFFL +-//LINK_CAP2 +-#define LINK_CAP2__SUPPORTED_LINK_SPEED__MASK 0x000000FEL +-#define LINK_CAP2__CROSSLINK_SUPPORTED__MASK 0x00000100L +-#define LINK_CAP2__RESERVED__MASK 0xFFFFFE00L +-//LINK_CNTL2 +-#define LINK_CNTL2__TARGET_LINK_SPEED__MASK 0x000FL +-#define LINK_CNTL2__ENTER_COMPLIANCE__MASK 0x0010L +-#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__MASK 0x0020L +-#define LINK_CNTL2__SELECTABLE_DEEMPHASIS__MASK 0x0040L +-#define LINK_CNTL2__XMIT_MARGIN__MASK 0x0380L +-#define LINK_CNTL2__ENTER_MOD_COMPLIANCE__MASK 0x0400L +-#define LINK_CNTL2__COMPLIANCE_SOS__MASK 0x0800L +-#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS__MASK 0xF000L +-//LINK_STATUS2 +-#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__MASK 0x0001L +-#define LINK_STATUS2__EQUALIZATION_COMPLETE__MASK 0x0002L +-#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__MASK 0x0004L +-#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__MASK 0x0008L +-#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__MASK 0x0010L +-#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST__MASK 0x0020L +-//SLOT_CAP2 +-#define SLOT_CAP2__RESERVED__MASK 0xFFFFFFFFL +-//SLOT_CNTL2 +-#define SLOT_CNTL2__RESERVED__MASK 0xFFFFL +-//SLOT_STATUS2 +-#define SLOT_STATUS2__RESERVED__MASK 0xFFFFL +-//MSI_CAP_LIST +-#define MSI_CAP_LIST__CAP_ID__MASK 0x00FFL +-#define MSI_CAP_LIST__NEXT_PTR__MASK 0xFF00L +-//MSI_MSG_CNTL +-#define MSI_MSG_CNTL__MSI_EN__MASK 0x0001L +-#define MSI_MSG_CNTL__MSI_MULTI_CAP__MASK 0x000EL +-#define MSI_MSG_CNTL__MSI_MULTI_EN__MASK 0x0070L +-#define MSI_MSG_CNTL__MSI_64BIT__MASK 0x0080L +-#define MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__MASK 0x0100L +-//MSI_MSG_ADDR_LO +-#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__MASK 0xFFFFFFFCL +-//MSI_MSG_ADDR_HI +-#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__MASK 0xFFFFFFFFL +-//MSI_MSG_DATA +-#define MSI_MSG_DATA__MSI_DATA__MASK 0x0000FFFFL +-//MSI_MSG_DATA_64 +-#define MSI_MSG_DATA_64__MSI_DATA_64__MASK 0x0000FFFFL +-//MSI_MASK +-#define MSI_MASK__MSI_MASK__MASK 0xFFFFFFFFL +-//MSI_PENDING +-#define MSI_PENDING__MSI_PENDING__MASK 0xFFFFFFFFL +-//MSI_MASK_64 +-#define MSI_MASK_64__MSI_MASK_64__MASK 0xFFFFFFFFL +-//MSI_PENDING_64 +-#define MSI_PENDING_64__MSI_PENDING_64__MASK 0xFFFFFFFFL +-//MSIX_CAP_LIST +-#define MSIX_CAP_LIST__CAP_ID__MASK 0x00FFL +-#define MSIX_CAP_LIST__NEXT_PTR__MASK 0xFF00L +-//MSIX_MSG_CNTL +-#define MSIX_MSG_CNTL__MSIX_TABLE_SIZE__MASK 0x07FFL +-#define MSIX_MSG_CNTL__MSIX_FUNC_MASK__MASK 0x4000L +-#define MSIX_MSG_CNTL__MSIX_EN__MASK 0x8000L +-//MSIX_TABLE +-#define MSIX_TABLE__MSIX_TABLE_BIR__MASK 0x00000007L +-#define MSIX_TABLE__MSIX_TABLE_OFFSET__MASK 0xFFFFFFF8L +-//MSIX_PBA +-#define MSIX_PBA__MSIX_PBA_BIR__MASK 0x00000007L +-#define MSIX_PBA__MSIX_PBA_OFFSET__MASK 0xFFFFFFF8L +-//PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST +-#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL +-#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L +-#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L +-//PCIE_VENDOR_SPECIFIC_HDR +-#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__MASK 0x0000FFFFL +-#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__MASK 0x000F0000L +-#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__MASK 0xFFF00000L +-//PCIE_VENDOR_SPECIFIC1 +-#define PCIE_VENDOR_SPECIFIC1__SCRATCH__MASK 0xFFFFFFFFL +-//PCIE_VENDOR_SPECIFIC2 +-#define PCIE_VENDOR_SPECIFIC2__SCRATCH__MASK 0xFFFFFFFFL +-//PCIE_VC_ENH_CAP_LIST +-#define PCIE_VC_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL +-#define PCIE_VC_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L +-#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L +-//PCIE_PORT_VC_CAP_REG1 +-#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__MASK 0x00000007L +-#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__MASK 0x00000070L +-#define PCIE_PORT_VC_CAP_REG1__REF_CLK__MASK 0x00000300L +-#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__MASK 0x00000C00L +-//PCIE_PORT_VC_CAP_REG2 +-#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__MASK 0x000000FFL +-#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__MASK 0xFF000000L +-//PCIE_PORT_VC_CNTL +-#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__MASK 0x0001L +-#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT__MASK 0x000EL +-//PCIE_PORT_VC_STATUS +-#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__MASK 0x0001L +-//PCIE_VC0_RESOURCE_CAP +-#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__MASK 0x000000FFL +-#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__MASK 0x00008000L +-#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__MASK 0x003F0000L +-#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__MASK 0xFF000000L +-//PCIE_VC0_RESOURCE_CNTL +-#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__MASK 0x00000001L +-#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__MASK 0x000000FEL +-#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__MASK 0x00010000L +-#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__MASK 0x000E0000L +-#define PCIE_VC0_RESOURCE_CNTL__VC_ID__MASK 0x07000000L +-#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__MASK 0x80000000L +-//PCIE_VC0_RESOURCE_STATUS +-#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__MASK 0x0001L +-#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__MASK 0x0002L +-//PCIE_VC1_RESOURCE_CAP +-#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__MASK 0x000000FFL +-#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__MASK 0x00008000L +-#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__MASK 0x003F0000L +-#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__MASK 0xFF000000L +-//PCIE_VC1_RESOURCE_CNTL +-#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__MASK 0x00000001L +-#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__MASK 0x000000FEL +-#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__MASK 0x00010000L +-#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__MASK 0x000E0000L +-#define PCIE_VC1_RESOURCE_CNTL__VC_ID__MASK 0x07000000L +-#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__MASK 0x80000000L +-//PCIE_VC1_RESOURCE_STATUS +-#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__MASK 0x0001L +-#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__MASK 0x0002L +-//PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST +-#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL +-#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L +-#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L +-//PCIE_DEV_SERIAL_NUM_DW1 +-#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__MASK 0xFFFFFFFFL +-//PCIE_DEV_SERIAL_NUM_DW2 +-#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__MASK 0xFFFFFFFFL +-//PCIE_ADV_ERR_RPT_ENH_CAP_LIST +-#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL +-#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L +-#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L +-//PCIE_UNCORR_ERR_STATUS +-#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__MASK 0x00000010L +-#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__MASK 0x00000020L +-#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__MASK 0x00001000L +-#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__MASK 0x00002000L +-#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__MASK 0x00004000L +-#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__MASK 0x00008000L +-#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__MASK 0x00010000L +-#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__MASK 0x00020000L +-#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__MASK 0x00040000L +-#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__MASK 0x00080000L +-#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__MASK 0x00100000L +-#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__MASK 0x00200000L +-#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__MASK 0x00400000L +-#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__MASK 0x00800000L +-#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__MASK 0x01000000L +-#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__MASK 0x02000000L +-//PCIE_UNCORR_ERR_MASK +-#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__MASK 0x00000010L +-#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__MASK 0x00000020L +-#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__MASK 0x00001000L +-#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__MASK 0x00002000L +-#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__MASK 0x00004000L +-#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__MASK 0x00008000L +-#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__MASK 0x00010000L +-#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__MASK 0x00020000L +-#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__MASK 0x00040000L +-#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__MASK 0x00080000L +-#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__MASK 0x00100000L +-#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__MASK 0x00200000L +-#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__MASK 0x00400000L +-#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__MASK 0x00800000L +-#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__MASK 0x01000000L +-#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__MASK 0x02000000L +-//PCIE_UNCORR_ERR_SEVERITY +-#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__MASK 0x00000010L +-#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__MASK 0x00000020L +-#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__MASK 0x00001000L +-#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__MASK 0x00002000L +-#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__MASK 0x00004000L +-#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__MASK 0x00008000L +-#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__MASK 0x00010000L +-#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__MASK 0x00020000L +-#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__MASK 0x00040000L +-#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__MASK 0x00080000L +-#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__MASK 0x00100000L +-#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__MASK 0x00200000L +-#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__MASK 0x00400000L +-#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__MASK 0x00800000L +-#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__MASK 0x01000000L +-#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__MASK 0x02000000L +-//PCIE_CORR_ERR_STATUS +-#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__MASK 0x00000001L +-#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__MASK 0x00000040L +-#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__MASK 0x00000080L +-#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__MASK 0x00000100L +-#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__MASK 0x00001000L +-#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__MASK 0x00002000L +-#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__MASK 0x00004000L +-#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__MASK 0x00008000L +-//PCIE_CORR_ERR_MASK +-#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK__MASK 0x00000001L +-#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK__MASK 0x00000040L +-#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__MASK 0x00000080L +-#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__MASK 0x00000100L +-#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__MASK 0x00001000L +-#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__MASK 0x00002000L +-#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__MASK 0x00004000L +-#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__MASK 0x00008000L +-//PCIE_ADV_ERR_CAP_CNTL +-#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__MASK 0x0000001FL +-#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__MASK 0x00000020L +-#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__MASK 0x00000040L +-#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__MASK 0x00000080L +-#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__MASK 0x00000100L +-#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__MASK 0x00000200L +-#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__MASK 0x00000400L +-#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__MASK 0x00000800L +-//PCIE_HDR_LOG0 +-#define PCIE_HDR_LOG0__TLP_HDR__MASK 0xFFFFFFFFL +-//PCIE_HDR_LOG1 +-#define PCIE_HDR_LOG1__TLP_HDR__MASK 0xFFFFFFFFL +-//PCIE_HDR_LOG2 +-#define PCIE_HDR_LOG2__TLP_HDR__MASK 0xFFFFFFFFL +-//PCIE_HDR_LOG3 +-#define PCIE_HDR_LOG3__TLP_HDR__MASK 0xFFFFFFFFL +-//PCIE_ROOT_ERR_CMD +-#define PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__MASK 0x00000001L +-#define PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__MASK 0x00000002L +-#define PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__MASK 0x00000004L +-//PCIE_ROOT_ERR_STATUS +-#define PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__MASK 0x00000001L +-#define PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__MASK 0x00000002L +-#define PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__MASK 0x00000004L +-#define PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__MASK 0x00000008L +-#define PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__MASK 0x00000010L +-#define PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__MASK 0x00000020L +-#define PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__MASK 0x00000040L +-#define PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__MASK 0xF8000000L +-//PCIE_ERR_SRC_ID +-#define PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__MASK 0x0000FFFFL +-#define PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__MASK 0xFFFF0000L +-//PCIE_TLP_PREFIX_LOG0 +-#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__MASK 0xFFFFFFFFL +-//PCIE_TLP_PREFIX_LOG1 +-#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__MASK 0xFFFFFFFFL +-//PCIE_TLP_PREFIX_LOG2 +-#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__MASK 0xFFFFFFFFL +-//PCIE_TLP_PREFIX_LOG3 +-#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__MASK 0xFFFFFFFFL +-//PCIE_BAR_ENH_CAP_LIST +-#define PCIE_BAR_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL +-#define PCIE_BAR_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L +-#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L +-//PCIE_BAR1_CAP +-#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__MASK 0x00FFFFF0L +-//PCIE_BAR1_CNTL +-#define PCIE_BAR1_CNTL__BAR_INDEX__MASK 0x0007L +-#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM__MASK 0x00E0L +-#define PCIE_BAR1_CNTL__BAR_SIZE__MASK 0x1F00L +-//PCIE_BAR2_CAP +-#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__MASK 0x00FFFFF0L +-//PCIE_BAR2_CNTL +-#define PCIE_BAR2_CNTL__BAR_INDEX__MASK 0x0007L +-#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM__MASK 0x00E0L +-#define PCIE_BAR2_CNTL__BAR_SIZE__MASK 0x1F00L +-//PCIE_BAR3_CAP +-#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__MASK 0x00FFFFF0L +-//PCIE_BAR3_CNTL +-#define PCIE_BAR3_CNTL__BAR_INDEX__MASK 0x0007L +-#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM__MASK 0x00E0L +-#define PCIE_BAR3_CNTL__BAR_SIZE__MASK 0x1F00L +-//PCIE_BAR4_CAP +-#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__MASK 0x00FFFFF0L +-//PCIE_BAR4_CNTL +-#define PCIE_BAR4_CNTL__BAR_INDEX__MASK 0x0007L +-#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM__MASK 0x00E0L +-#define PCIE_BAR4_CNTL__BAR_SIZE__MASK 0x1F00L +-//PCIE_BAR5_CAP +-#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__MASK 0x00FFFFF0L +-//PCIE_BAR5_CNTL +-#define PCIE_BAR5_CNTL__BAR_INDEX__MASK 0x0007L +-#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM__MASK 0x00E0L +-#define PCIE_BAR5_CNTL__BAR_SIZE__MASK 0x1F00L +-//PCIE_BAR6_CAP +-#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__MASK 0x00FFFFF0L +-//PCIE_BAR6_CNTL +-#define PCIE_BAR6_CNTL__BAR_INDEX__MASK 0x0007L +-#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM__MASK 0x00E0L +-#define PCIE_BAR6_CNTL__BAR_SIZE__MASK 0x1F00L +-//PCIE_PWR_BUDGET_ENH_CAP_LIST +-#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL +-#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L +-#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L +-//PCIE_PWR_BUDGET_DATA_SELECT +-#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__MASK 0xFFL +-//PCIE_PWR_BUDGET_DATA +-#define PCIE_PWR_BUDGET_DATA__BASE_POWER__MASK 0x000000FFL +-#define PCIE_PWR_BUDGET_DATA__DATA_SCALE__MASK 0x00000300L +-#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__MASK 0x00001C00L +-#define PCIE_PWR_BUDGET_DATA__PM_STATE__MASK 0x00006000L +-#define PCIE_PWR_BUDGET_DATA__TYPE__MASK 0x00038000L +-#define PCIE_PWR_BUDGET_DATA__POWER_RAIL__MASK 0x001C0000L +-//PCIE_PWR_BUDGET_CAP +-#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__MASK 0x01L +-//PCIE_DPA_ENH_CAP_LIST +-#define PCIE_DPA_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL +-#define PCIE_DPA_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L +-#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L +-//PCIE_DPA_CAP +-#define PCIE_DPA_CAP__SUBSTATE_MAX__MASK 0x0000001FL +-#define PCIE_DPA_CAP__TRANS_LAT_UNIT__MASK 0x00000300L +-#define PCIE_DPA_CAP__PWR_ALLOC_SCALE__MASK 0x00003000L +-#define PCIE_DPA_CAP__TRANS_LAT_VAL_0__MASK 0x00FF0000L +-#define PCIE_DPA_CAP__TRANS_LAT_VAL_1__MASK 0xFF000000L +-//PCIE_DPA_LATENCY_INDICATOR +-#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__MASK 0xFFL +-//PCIE_DPA_STATUS +-#define PCIE_DPA_STATUS__SUBSTATE_STATUS__MASK 0x001FL +-#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__MASK 0x0100L +-//PCIE_DPA_CNTL +-#define PCIE_DPA_CNTL__SUBSTATE_CNTL__MASK 0x1FL +-//PCIE_DPA_SUBSTATE_PWR_ALLOC_0 +-#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__MASK 0xFFL +-//PCIE_DPA_SUBSTATE_PWR_ALLOC_1 +-#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__MASK 0xFFL +-//PCIE_DPA_SUBSTATE_PWR_ALLOC_2 +-#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__MASK 0xFFL +-//PCIE_DPA_SUBSTATE_PWR_ALLOC_3 +-#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__MASK 0xFFL +-//PCIE_DPA_SUBSTATE_PWR_ALLOC_4 +-#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__MASK 0xFFL +-//PCIE_DPA_SUBSTATE_PWR_ALLOC_5 +-#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__MASK 0xFFL +-//PCIE_DPA_SUBSTATE_PWR_ALLOC_6 +-#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__MASK 0xFFL +-//PCIE_DPA_SUBSTATE_PWR_ALLOC_7 +-#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__MASK 0xFFL +-//PCIE_SECONDARY_ENH_CAP_LIST +-#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL +-#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L +-#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L +-//PCIE_LINK_CNTL3 +-#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__MASK 0x00000001L +-#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__MASK 0x00000002L +-#define PCIE_LINK_CNTL3__RESERVED__MASK 0xFFFFFFFCL +-//PCIE_LANE_ERROR_STATUS +-#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__MASK 0x0000FFFFL +-#define PCIE_LANE_ERROR_STATUS__RESERVED__MASK 0xFFFF0000L +-//PCIE_LANE_0_EQUALIZATION_CNTL +-#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL +-#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L +-#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L +-#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L +-#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L +-//PCIE_LANE_1_EQUALIZATION_CNTL +-#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL +-#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L +-#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L +-#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L +-#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L +-//PCIE_LANE_2_EQUALIZATION_CNTL +-#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL +-#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L +-#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L +-#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L +-#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L +-//PCIE_LANE_3_EQUALIZATION_CNTL +-#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL +-#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L +-#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L +-#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L +-#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L +-//PCIE_LANE_4_EQUALIZATION_CNTL +-#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL +-#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L +-#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L +-#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L +-#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L +-//PCIE_LANE_5_EQUALIZATION_CNTL +-#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL +-#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L +-#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L +-#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L +-#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L +-//PCIE_LANE_6_EQUALIZATION_CNTL +-#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL +-#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L +-#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L +-#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L +-#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L +-//PCIE_LANE_7_EQUALIZATION_CNTL +-#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL +-#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L +-#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L +-#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L +-#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L +-//PCIE_LANE_8_EQUALIZATION_CNTL +-#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL +-#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L +-#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L +-#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L +-#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L +-//PCIE_LANE_9_EQUALIZATION_CNTL +-#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL +-#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L +-#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L +-#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L +-#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L +-//PCIE_LANE_10_EQUALIZATION_CNTL +-#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL +-#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L +-#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L +-#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L +-#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L +-//PCIE_LANE_11_EQUALIZATION_CNTL +-#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL +-#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L +-#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L +-#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L +-#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L +-//PCIE_LANE_12_EQUALIZATION_CNTL +-#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL +-#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L +-#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L +-#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L +-#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L +-//PCIE_LANE_13_EQUALIZATION_CNTL +-#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL +-#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L +-#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L +-#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L +-#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L +-//PCIE_LANE_14_EQUALIZATION_CNTL +-#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL +-#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L +-#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L +-#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L +-#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L +-//PCIE_LANE_15_EQUALIZATION_CNTL +-#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL +-#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L +-#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L +-#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L +-#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L +-//PCIE_ACS_ENH_CAP_LIST +-#define PCIE_ACS_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL +-#define PCIE_ACS_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L +-#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L +-//PCIE_ACS_CAP +-#define PCIE_ACS_CAP__SOURCE_VALIDATION__MASK 0x0001L +-#define PCIE_ACS_CAP__TRANSLATION_BLOCKING__MASK 0x0002L +-#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__MASK 0x0004L +-#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__MASK 0x0008L +-#define PCIE_ACS_CAP__UPSTREAM_FORWARDING__MASK 0x0010L +-#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL__MASK 0x0020L +-#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__MASK 0x0040L +-#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__MASK 0xFF00L +-//PCIE_ACS_CNTL +-#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__MASK 0x0001L +-#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__MASK 0x0002L +-#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__MASK 0x0004L +-#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__MASK 0x0008L +-#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__MASK 0x0010L +-#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__MASK 0x0020L +-#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__MASK 0x0040L +-//PCIE_ATS_ENH_CAP_LIST +-#define PCIE_ATS_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL +-#define PCIE_ATS_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L +-#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L +-//PCIE_ATS_CAP +-#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__MASK 0x001FL +-#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__MASK 0x0020L +-#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__MASK 0x0040L +-//PCIE_ATS_CNTL +-#define PCIE_ATS_CNTL__STU__MASK 0x001FL +-#define PCIE_ATS_CNTL__ATC_ENABLE__MASK 0x8000L +-//PCIE_PAGE_REQ_ENH_CAP_LIST +-#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL +-#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L +-#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L +-//PCIE_PAGE_REQ_CNTL +-#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE__MASK 0x0001L +-#define PCIE_PAGE_REQ_CNTL__PRI_RESET__MASK 0x0002L +-//PCIE_PAGE_REQ_STATUS +-#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__MASK 0x0001L +-#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__MASK 0x0002L +-#define PCIE_PAGE_REQ_STATUS__STOPPED__MASK 0x0100L +-#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__MASK 0x8000L +-//PCIE_OUTSTAND_PAGE_REQ_CAPACITY +-#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__MASK 0xFFFFFFFFL +-//PCIE_OUTSTAND_PAGE_REQ_ALLOC +-#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__MASK 0xFFFFFFFFL +-//PCIE_PASID_ENH_CAP_LIST +-#define PCIE_PASID_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL +-#define PCIE_PASID_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L +-#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L +-//PCIE_PASID_CAP +-#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__MASK 0x0002L +-#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__MASK 0x0004L +-#define PCIE_PASID_CAP__MAX_PASID_WIDTH__MASK 0x1F00L +-//PCIE_PASID_CNTL +-#define PCIE_PASID_CNTL__PASID_ENABLE__MASK 0x0001L +-#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__MASK 0x0002L +-#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__MASK 0x0004L +-//PCIE_TPH_REQR_ENH_CAP_LIST +-#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL +-#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L +-#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L +-//PCIE_TPH_REQR_CAP +-#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__MASK 0x00000001L +-#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__MASK 0x00000002L +-#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__MASK 0x00000004L +-#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__MASK 0x00000100L +-#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__MASK 0x00000600L +-#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__MASK 0x07FF0000L +-//PCIE_TPH_REQR_CNTL +-#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__MASK 0x00000007L +-#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN__MASK 0x00000300L +-//PCIE_MC_ENH_CAP_LIST +-#define PCIE_MC_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL +-#define PCIE_MC_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L +-#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L +-//PCIE_MC_CAP +-#define PCIE_MC_CAP__MC_MAX_GROUP__MASK 0x003FL +-#define PCIE_MC_CAP__MC_WIN_SIZE_REQ__MASK 0x3F00L +-#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__MASK 0x8000L +-//PCIE_MC_CNTL +-#define PCIE_MC_CNTL__MC_NUM_GROUP__MASK 0x003FL +-#define PCIE_MC_CNTL__MC_ENABLE__MASK 0x8000L +-//PCIE_MC_ADDR0 +-#define PCIE_MC_ADDR0__MC_INDEX_POS__MASK 0x0000003FL +-#define PCIE_MC_ADDR0__MC_BASE_ADDR_0__MASK 0xFFFFF000L +-//PCIE_MC_ADDR1 +-#define PCIE_MC_ADDR1__MC_BASE_ADDR_1__MASK 0xFFFFFFFFL +-//PCIE_MC_RCV0 +-#define PCIE_MC_RCV0__MC_RECEIVE_0__MASK 0xFFFFFFFFL +-//PCIE_MC_RCV1 +-#define PCIE_MC_RCV1__MC_RECEIVE_1__MASK 0xFFFFFFFFL +-//PCIE_MC_BLOCK_ALL0 +-#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__MASK 0xFFFFFFFFL +-//PCIE_MC_BLOCK_ALL1 +-#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__MASK 0xFFFFFFFFL +-//PCIE_MC_BLOCK_UNTRANSLATED_0 +-#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__MASK 0xFFFFFFFFL +-//PCIE_MC_BLOCK_UNTRANSLATED_1 +-#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__MASK 0xFFFFFFFFL +-//PCIE_LTR_ENH_CAP_LIST +-#define PCIE_LTR_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL +-#define PCIE_LTR_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L +-#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L +-//PCIE_LTR_CAP +-#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__MASK 0x000003FFL +-#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__MASK 0x00001C00L +-#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__MASK 0x03FF0000L +-#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__MASK 0x1C000000L +-//PCIE_ARI_ENH_CAP_LIST +-#define PCIE_ARI_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL +-#define PCIE_ARI_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L +-#define PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L +-//PCIE_ARI_CAP +-#define PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__MASK 0x0001L +-#define PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__MASK 0x0002L +-#define PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__MASK 0xFF00L +-//PCIE_ARI_CNTL +-#define PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__MASK 0x0001L +-#define PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__MASK 0x0002L +-#define PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__MASK 0x0070L +-//PCIE_SRIOV_ENH_CAP_LIST +-#define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL +-#define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L +-#define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L +-//PCIE_SRIOV_CAP +-#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__MASK 0x00000001L +-#define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__MASK 0x00000002L +-#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__MASK 0xFFE00000L +-//PCIE_SRIOV_CONTROL +-#define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__MASK 0x0001L +-#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__MASK 0x0002L +-#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__MASK 0x0004L +-#define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__MASK 0x0008L +-#define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__MASK 0x0010L +-//PCIE_SRIOV_STATUS +-#define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__MASK 0x0001L +-//PCIE_SRIOV_INITIAL_VFS +-#define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__MASK 0xFFFFL +-//PCIE_SRIOV_TOTAL_VFS +-#define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__MASK 0xFFFFL +-//PCIE_SRIOV_NUM_VFS +-#define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__MASK 0xFFFFL +-//PCIE_SRIOV_FUNC_DEP_LINK +-#define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__MASK 0x00FFL +-//PCIE_SRIOV_FIRST_VF_OFFSET +-#define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__MASK 0xFFFFL +-//PCIE_SRIOV_VF_STRIDE +-#define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__MASK 0xFFFFL +-//PCIE_SRIOV_VF_DEVICE_ID +-#define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__MASK 0xFFFFL +-//PCIE_SRIOV_SUPPORTED_PAGE_SIZE +-#define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__MASK 0xFFFFFFFFL +-//PCIE_SRIOV_SYSTEM_PAGE_SIZE +-#define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__MASK 0xFFFFFFFFL +-//PCIE_SRIOV_VF_BASE_ADDR_0 +-#define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__MASK 0xFFFFFFFFL +-//PCIE_SRIOV_VF_BASE_ADDR_1 +-#define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__MASK 0xFFFFFFFFL +-//PCIE_SRIOV_VF_BASE_ADDR_2 +-#define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__MASK 0xFFFFFFFFL +-//PCIE_SRIOV_VF_BASE_ADDR_3 +-#define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__MASK 0xFFFFFFFFL +-//PCIE_SRIOV_VF_BASE_ADDR_4 +-#define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__MASK 0xFFFFFFFFL +-//PCIE_SRIOV_VF_BASE_ADDR_5 +-#define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__MASK 0xFFFFFFFFL +-//PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET +-#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__MASK 0x00000007L +-#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__MASK 0xFFFFFFF8L +-//PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV +-#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__MASK 0x0000FFFFL +-#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__MASK 0x000F0000L +-#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__MASK 0xFFF00000L +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__MASK 0x0000FFFFL +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__MASK 0x000F0000L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__MASK 0xFFF00000L +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__MASK 0x00000001L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__MASK 0xFFFF0000L +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__MASK 0x00000001L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__MASK 0x00000002L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__MASK 0x00000004L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__MASK 0x00000008L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__MASK 0x00000100L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__MASK 0x00000200L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__MASK 0x00000400L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__MASK 0x00000800L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__MASK 0x00010000L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__MASK 0x00020000L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__MASK 0x00040000L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__MASK 0x00080000L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__MASK 0x01000000L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__MASK 0x02000000L +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__MASK 0x00000001L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__MASK 0x00000002L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__MASK 0x00000004L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__MASK 0x00000008L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__MASK 0x00000100L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__MASK 0x00000200L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__MASK 0x00000400L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__MASK 0x00000800L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__MASK 0x00010000L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__MASK 0x00020000L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__MASK 0x00040000L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__MASK 0x00080000L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__MASK 0x01000000L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__MASK 0x02000000L +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__MASK 0x0001L +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__MASK 0x000000FFL +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__MASK 0x00000F00L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__MASK 0x00008000L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__MASK 0x000F0000L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__MASK 0x01000000L +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__MASK 0x00000001L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__MASK 0x00000002L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__MASK 0x00000004L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__MASK 0x00000008L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__MASK 0x00000010L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__MASK 0x00000020L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__MASK 0x00000040L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__MASK 0x00000080L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__MASK 0x00000100L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__MASK 0x00000200L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__MASK 0x00000400L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__MASK 0x00000800L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__MASK 0x00001000L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__MASK 0x00002000L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__MASK 0x00004000L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__MASK 0x00008000L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__MASK 0x00010000L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__MASK 0x00020000L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__MASK 0x00040000L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__MASK 0x00080000L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__MASK 0x00100000L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__MASK 0x00200000L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__MASK 0x00400000L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__MASK 0x00800000L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__MASK 0x01000000L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__MASK 0x02000000L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__MASK 0x04000000L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__MASK 0x08000000L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__MASK 0x10000000L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__MASK 0x20000000L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__MASK 0x40000000L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__MASK 0x80000000L +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__MASK 0x00000001L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__MASK 0x00000002L +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__MASK 0x0000007FL +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__MASK 0x00000080L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__MASK 0xFFFFFC00L +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__MASK 0x0000FFFFL +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__MASK 0xFFFF0000L +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__MASK 0x000000FFL +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__MASK 0x0000FF00L +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__MASK 0x00FF0000L +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__MASK 0x0000FFFFL +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__MASK 0xFFFF0000L +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__MASK 0x0000FFFFL +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__MASK 0xFFFF0000L +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__MASK 0x0000FFFFL +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__MASK 0xFFFF0000L +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__MASK 0x0000FFFFL +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__MASK 0xFFFF0000L +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__MASK 0x0000FFFFL +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__MASK 0xFFFF0000L +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__MASK 0x0000FFFFL +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__MASK 0xFFFF0000L +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__MASK 0x0000FFFFL +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__MASK 0xFFFF0000L +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__MASK 0x0000FFFFL +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__MASK 0xFFFF0000L +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__MASK 0x0000FFFFL +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__MASK 0xFFFF0000L +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__MASK 0x0000FFFFL +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__MASK 0xFFFF0000L +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__MASK 0x0000FFFFL +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__MASK 0xFFFF0000L +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__MASK 0x0000FFFFL +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__MASK 0xFFFF0000L +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__MASK 0x0000FFFFL +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__MASK 0xFFFF0000L +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__MASK 0x0000FFFFL +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__MASK 0xFFFF0000L +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__MASK 0x0000FFFFL +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__MASK 0xFFFF0000L +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__MASK 0x0000FFFFL +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__MASK 0xFFFF0000L +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__MASK 0xFFFFFFFFL +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__MASK 0xFFFFFFFFL +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__MASK 0xFFFFFFFFL +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__MASK 0xFFFFFFFFL +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__MASK 0xFFFFFFFFL +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__MASK 0xFFFFFFFFL +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__MASK 0xFFFFFFFFL +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__MASK 0xFFFFFFFFL +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__MASK 0xFFFFFFFFL +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__MASK 0xFFFFFFFFL +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__MASK 0xFFFFFFFFL +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__MASK 0xFFFFFFFFL +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__MASK 0xFFFFFFFFL +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__MASK 0xFFFFFFFFL +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__MASK 0xFFFFFFFFL +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__MASK 0xFFFFFFFFL +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__MASK 0xFFFFFFFFL +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__MASK 0xFFFFFFFFL +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__MASK 0xFFFFFFFFL +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__MASK 0xFFFFFFFFL +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__MASK 0xFFFFFFFFL +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__MASK 0xFFFFFFFFL +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__MASK 0xFFFFFFFFL +-//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 +-#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__MASK 0xFFFFFFFFL +- +- +-// addressBlock: bif_cfg_dev0_swds_bifcfgdecp +-//SUB_BUS_NUMBER_LATENCY +-#define SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__MASK 0x000000FFL +-#define SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__MASK 0x0000FF00L +-#define SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__MASK 0x00FF0000L +-#define SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__MASK 0xFF000000L +-//IO_BASE_LIMIT +-#define IO_BASE_LIMIT__IO_BASE_TYPE__MASK 0x000FL +-#define IO_BASE_LIMIT__IO_BASE__MASK 0x00F0L +-#define IO_BASE_LIMIT__IO_LIMIT_TYPE__MASK 0x0F00L +-#define IO_BASE_LIMIT__IO_LIMIT__MASK 0xF000L +-//SECONDARY_STATUS +-#define SECONDARY_STATUS__CAP_LIST__MASK 0x0010L +-#define SECONDARY_STATUS__PCI_66_EN__MASK 0x0020L +-#define SECONDARY_STATUS__FAST_BACK_CAPABLE__MASK 0x0080L +-#define SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__MASK 0x0100L +-#define SECONDARY_STATUS__DEVSEL_TIMING__MASK 0x0600L +-#define SECONDARY_STATUS__SIGNAL_TARGET_ABORT__MASK 0x0800L +-#define SECONDARY_STATUS__RECEIVED_TARGET_ABORT__MASK 0x1000L +-#define SECONDARY_STATUS__RECEIVED_MASTER_ABORT__MASK 0x2000L +-#define SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__MASK 0x4000L +-#define SECONDARY_STATUS__PARITY_ERROR_DETECTED__MASK 0x8000L +-//MEM_BASE_LIMIT +-#define MEM_BASE_LIMIT__MEM_BASE_TYPE__MASK 0x0000000FL +-#define MEM_BASE_LIMIT__MEM_BASE_31_20__MASK 0x0000FFF0L +-#define MEM_BASE_LIMIT__MEM_LIMIT_TYPE__MASK 0x000F0000L +-#define MEM_BASE_LIMIT__MEM_LIMIT_31_20__MASK 0xFFF00000L +-//PREF_BASE_LIMIT +-#define PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__MASK 0x0000000FL +-#define PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__MASK 0x0000FFF0L +-#define PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__MASK 0x000F0000L +-#define PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__MASK 0xFFF00000L +-//PREF_BASE_UPPER +-#define PREF_BASE_UPPER__PREF_BASE_UPPER__MASK 0xFFFFFFFFL +-//PREF_LIMIT_UPPER +-#define PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__MASK 0xFFFFFFFFL +-//IO_BASE_LIMIT_HI +-#define IO_BASE_LIMIT_HI__IO_BASE_31_16__MASK 0x0000FFFFL +-#define IO_BASE_LIMIT_HI__IO_LIMIT_31_16__MASK 0xFFFF0000L +-//IRQ_BRIDGE_CNTL +-#define IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__MASK 0x0001L +-#define IRQ_BRIDGE_CNTL__SERR_EN__MASK 0x0002L +-#define IRQ_BRIDGE_CNTL__ISA_EN__MASK 0x0004L +-#define IRQ_BRIDGE_CNTL__VGA_EN__MASK 0x0008L +-#define IRQ_BRIDGE_CNTL__VGA_DEC__MASK 0x0010L +-#define IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__MASK 0x0020L +-#define IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__MASK 0x0040L +-#define IRQ_BRIDGE_CNTL__FAST_B2B_EN__MASK 0x0080L +-//SLOT_CAP +-#define SLOT_CAP__ATTN_BUTTON_PRESENT__MASK 0x00000001L +-#define SLOT_CAP__PWR_CONTROLLER_PRESENT__MASK 0x00000002L +-#define SLOT_CAP__MRL_SENSOR_PRESENT__MASK 0x00000004L +-#define SLOT_CAP__ATTN_INDICATOR_PRESENT__MASK 0x00000008L +-#define SLOT_CAP__PWR_INDICATOR_PRESENT__MASK 0x00000010L +-#define SLOT_CAP__HOTPLUG_SURPRISE__MASK 0x00000020L +-#define SLOT_CAP__HOTPLUG_CAPABLE__MASK 0x00000040L +-#define SLOT_CAP__SLOT_PWR_LIMIT_VALUE__MASK 0x00007F80L +-#define SLOT_CAP__SLOT_PWR_LIMIT_SCALE__MASK 0x00018000L +-#define SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__MASK 0x00020000L +-#define SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__MASK 0x00040000L +-#define SLOT_CAP__PHYSICAL_SLOT_NUM__MASK 0xFFF80000L +-//SLOT_CNTL +-#define SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__MASK 0x0001L +-#define SLOT_CNTL__PWR_FAULT_DETECTED_EN__MASK 0x0002L +-#define SLOT_CNTL__MRL_SENSOR_CHANGED_EN__MASK 0x0004L +-#define SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__MASK 0x0008L +-#define SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__MASK 0x0010L +-#define SLOT_CNTL__HOTPLUG_INTR_EN__MASK 0x0020L +-#define SLOT_CNTL__ATTN_INDICATOR_CNTL__MASK 0x00C0L +-#define SLOT_CNTL__PWR_INDICATOR_CNTL__MASK 0x0300L +-#define SLOT_CNTL__PWR_CONTROLLER_CNTL__MASK 0x0400L +-#define SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__MASK 0x0800L +-#define SLOT_CNTL__DL_STATE_CHANGED_EN__MASK 0x1000L +-//SLOT_STATUS +-#define SLOT_STATUS__ATTN_BUTTON_PRESSED__MASK 0x0001L +-#define SLOT_STATUS__PWR_FAULT_DETECTED__MASK 0x0002L +-#define SLOT_STATUS__MRL_SENSOR_CHANGED__MASK 0x0004L +-#define SLOT_STATUS__PRESENCE_DETECT_CHANGED__MASK 0x0008L +-#define SLOT_STATUS__COMMAND_COMPLETED__MASK 0x0010L +-#define SLOT_STATUS__MRL_SENSOR_STATE__MASK 0x0020L +-#define SLOT_STATUS__PRESENCE_DETECT_STATE__MASK 0x0040L +-#define SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__MASK 0x0080L +-#define SLOT_STATUS__DL_STATE_CHANGED__MASK 0x0100L +-//SSID_CAP_LIST +-#define SSID_CAP_LIST__CAP_ID__MASK 0x00FFL +-#define SSID_CAP_LIST__NEXT_PTR__MASK 0xFF00L +-//SSID_CAP +-#define SSID_CAP__SUBSYSTEM_VENDOR_ID__MASK 0x0000FFFFL +-#define SSID_CAP__SUBSYSTEM_ID__MASK 0xFFFF0000L +- +- +-// addressBlock: rcc_shadow_reg_shadowdec +-//SHADOW_COMMAND +-#define SHADOW_COMMAND__IOEN_UP__MASK 0x0001L +-#define SHADOW_COMMAND__MEMEN_UP__MASK 0x0002L +-//SHADOW_BASE_ADDR_1 +-#define SHADOW_BASE_ADDR_1__BAR1_UP__MASK 0xFFFFFFFFL +-//SHADOW_BASE_ADDR_2 +-#define SHADOW_BASE_ADDR_2__BAR2_UP__MASK 0xFFFFFFFFL +-//SHADOW_SUB_BUS_NUMBER_LATENCY +-#define SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP__MASK 0x0000FF00L +-#define SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP__MASK 0x00FF0000L +-//SHADOW_IO_BASE_LIMIT +-#define SHADOW_IO_BASE_LIMIT__IO_BASE_UP__MASK 0x00F0L +-#define SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP__MASK 0xF000L +-//SHADOW_MEM_BASE_LIMIT +-#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE__MASK 0x0000000FL +-#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP__MASK 0x0000FFF0L +-#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__MASK 0x000F0000L +-#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP__MASK 0xFFF00000L +-//SHADOW_PREF_BASE_LIMIT +-#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__MASK 0x0000000FL +-#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP__MASK 0x0000FFF0L +-#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__MASK 0x000F0000L +-#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP__MASK 0xFFF00000L +-//SHADOW_PREF_BASE_UPPER +-#define SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP__MASK 0xFFFFFFFFL +-//SHADOW_PREF_LIMIT_UPPER +-#define SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP__MASK 0xFFFFFFFFL +-//SHADOW_IO_BASE_LIMIT_HI +-#define SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP__MASK 0x0000FFFFL +-#define SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP__MASK 0xFFFF0000L +-//SHADOW_IRQ_BRIDGE_CNTL +-#define SHADOW_IRQ_BRIDGE_CNTL__ISA_EN_UP__MASK 0x0004L +-#define SHADOW_IRQ_BRIDGE_CNTL__VGA_EN_UP__MASK 0x0008L +-#define SHADOW_IRQ_BRIDGE_CNTL__VGA_DEC_UP__MASK 0x0010L +-#define SHADOW_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_UP__MASK 0x0040L +-//SUC_INDEX +-#define SUC_INDEX__SUC_INDEX__MASK 0xFFFFFFFFL +-//SUC_DATA +-#define SUC_DATA__SUC_DATA__MASK 0xFFFFFFFFL +- +- +-// addressBlock: bif_bx_pf_SUMDEC +-//SUM_INDEX +-#define SUM_INDEX__SUM_INDEX__MASK 0xFFFFFFFFL +-//SUM_DATA +-#define SUM_DATA__SUM_DATA__MASK 0xFFFFFFFFL +- +- +-// addressBlock: gdc_GDCDEC +-//A2S_CNTL_CL0 +-#define A2S_CNTL_CL0__NSNOOP_MAP__MASK 0x00000003L +-#define A2S_CNTL_CL0__REQPASSPW_VC0_MAP__MASK 0x0000000CL +-#define A2S_CNTL_CL0__REQPASSPW_NVC0_MAP__MASK 0x00000030L +-#define A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP__MASK 0x000000C0L +-#define A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP__MASK 0x00000300L +-#define A2S_CNTL_CL0__BLKLVL_MAP__MASK 0x00000C00L +-#define A2S_CNTL_CL0__DATERR_MAP__MASK 0x00003000L +-#define A2S_CNTL_CL0__EXOKAY_WR_MAP__MASK 0x0000C000L +-#define A2S_CNTL_CL0__EXOKAY_RD_MAP__MASK 0x00030000L +-#define A2S_CNTL_CL0__RESP_WR_MAP__MASK 0x000C0000L +-#define A2S_CNTL_CL0__RESP_RD_MAP__MASK 0x00300000L +-//A2S_CNTL_CL1 +-#define A2S_CNTL_CL1__NSNOOP_MAP__MASK 0x00000003L +-#define A2S_CNTL_CL1__REQPASSPW_VC0_MAP__MASK 0x0000000CL +-#define A2S_CNTL_CL1__REQPASSPW_NVC0_MAP__MASK 0x00000030L +-#define A2S_CNTL_CL1__REQRSPPASSPW_VC0_MAP__MASK 0x000000C0L +-#define A2S_CNTL_CL1__REQRSPPASSPW_NVC0_MAP__MASK 0x00000300L +-#define A2S_CNTL_CL1__BLKLVL_MAP__MASK 0x00000C00L +-#define A2S_CNTL_CL1__DATERR_MAP__MASK 0x00003000L +-#define A2S_CNTL_CL1__EXOKAY_WR_MAP__MASK 0x0000C000L +-#define A2S_CNTL_CL1__EXOKAY_RD_MAP__MASK 0x00030000L +-#define A2S_CNTL_CL1__RESP_WR_MAP__MASK 0x000C0000L +-#define A2S_CNTL_CL1__RESP_RD_MAP__MASK 0x00300000L +-//A2S_CNTL_CL2 +-#define A2S_CNTL_CL2__NSNOOP_MAP__MASK 0x00000003L +-#define A2S_CNTL_CL2__REQPASSPW_VC0_MAP__MASK 0x0000000CL +-#define A2S_CNTL_CL2__REQPASSPW_NVC0_MAP__MASK 0x00000030L +-#define A2S_CNTL_CL2__REQRSPPASSPW_VC0_MAP__MASK 0x000000C0L +-#define A2S_CNTL_CL2__REQRSPPASSPW_NVC0_MAP__MASK 0x00000300L +-#define A2S_CNTL_CL2__BLKLVL_MAP__MASK 0x00000C00L +-#define A2S_CNTL_CL2__DATERR_MAP__MASK 0x00003000L +-#define A2S_CNTL_CL2__EXOKAY_WR_MAP__MASK 0x0000C000L +-#define A2S_CNTL_CL2__EXOKAY_RD_MAP__MASK 0x00030000L +-#define A2S_CNTL_CL2__RESP_WR_MAP__MASK 0x000C0000L +-#define A2S_CNTL_CL2__RESP_RD_MAP__MASK 0x00300000L +-//A2S_CNTL_CL3 +-#define A2S_CNTL_CL3__NSNOOP_MAP__MASK 0x00000003L +-#define A2S_CNTL_CL3__REQPASSPW_VC0_MAP__MASK 0x0000000CL +-#define A2S_CNTL_CL3__REQPASSPW_NVC0_MAP__MASK 0x00000030L +-#define A2S_CNTL_CL3__REQRSPPASSPW_VC0_MAP__MASK 0x000000C0L +-#define A2S_CNTL_CL3__REQRSPPASSPW_NVC0_MAP__MASK 0x00000300L +-#define A2S_CNTL_CL3__BLKLVL_MAP__MASK 0x00000C00L +-#define A2S_CNTL_CL3__DATERR_MAP__MASK 0x00003000L +-#define A2S_CNTL_CL3__EXOKAY_WR_MAP__MASK 0x0000C000L +-#define A2S_CNTL_CL3__EXOKAY_RD_MAP__MASK 0x00030000L +-#define A2S_CNTL_CL3__RESP_WR_MAP__MASK 0x000C0000L +-#define A2S_CNTL_CL3__RESP_RD_MAP__MASK 0x00300000L +-//A2S_CNTL_CL4 +-#define A2S_CNTL_CL4__NSNOOP_MAP__MASK 0x00000003L +-#define A2S_CNTL_CL4__REQPASSPW_VC0_MAP__MASK 0x0000000CL +-#define A2S_CNTL_CL4__REQPASSPW_NVC0_MAP__MASK 0x00000030L +-#define A2S_CNTL_CL4__REQRSPPASSPW_VC0_MAP__MASK 0x000000C0L +-#define A2S_CNTL_CL4__REQRSPPASSPW_NVC0_MAP__MASK 0x00000300L +-#define A2S_CNTL_CL4__BLKLVL_MAP__MASK 0x00000C00L +-#define A2S_CNTL_CL4__DATERR_MAP__MASK 0x00003000L +-#define A2S_CNTL_CL4__EXOKAY_WR_MAP__MASK 0x0000C000L +-#define A2S_CNTL_CL4__EXOKAY_RD_MAP__MASK 0x00030000L +-#define A2S_CNTL_CL4__RESP_WR_MAP__MASK 0x000C0000L +-#define A2S_CNTL_CL4__RESP_RD_MAP__MASK 0x00300000L +-//A2S_CNTL_SW0 +-#define A2S_CNTL_SW0__WR_TAG_SET_MIN__MASK 0x00000007L +-#define A2S_CNTL_SW0__RD_TAG_SET_MIN__MASK 0x00000038L +-#define A2S_CNTL_SW0__FORCE_RSP_REORDER_EN__MASK 0x00000040L +-#define A2S_CNTL_SW0__RSP_REORDER_DIS__MASK 0x00000080L +-#define A2S_CNTL_SW0__WRRSP_ACCUM_SEL__MASK 0x00000100L +-#define A2S_CNTL_SW0__SDP_WR_CHAIN_DIS__MASK 0x00000200L +-#define A2S_CNTL_SW0__WRRSP_TAGFIFO_CONT_RD_DIS__MASK 0x00000400L +-#define A2S_CNTL_SW0__RDRSP_TAGFIFO_CONT_RD_DIS__MASK 0x00000800L +-#define A2S_CNTL_SW0__RDRSP_STS_DATSTS_PRIORITY__MASK 0x00001000L +-#define A2S_CNTL_SW0__WRR_RD_WEIGHT__MASK 0x00FF0000L +-#define A2S_CNTL_SW0__WRR_WR_WEIGHT__MASK 0xFF000000L +-//A2S_CNTL_SW1 +-#define A2S_CNTL_SW1__WR_TAG_SET_MIN__MASK 0x00000007L +-#define A2S_CNTL_SW1__RD_TAG_SET_MIN__MASK 0x00000038L +-#define A2S_CNTL_SW1__FORCE_RSP_REORDER_EN__MASK 0x00000040L +-#define A2S_CNTL_SW1__RSP_REORDER_DIS__MASK 0x00000080L +-#define A2S_CNTL_SW1__WRRSP_ACCUM_SEL__MASK 0x00000100L +-#define A2S_CNTL_SW1__SDP_WR_CHAIN_DIS__MASK 0x00000200L +-#define A2S_CNTL_SW1__WRRSP_TAGFIFO_CONT_RD_DIS__MASK 0x00000400L +-#define A2S_CNTL_SW1__RDRSP_TAGFIFO_CONT_RD_DIS__MASK 0x00000800L +-#define A2S_CNTL_SW1__RDRSP_STS_DATSTS_PRIORITY__MASK 0x00001000L +-#define A2S_CNTL_SW1__WRR_RD_WEIGHT__MASK 0x00FF0000L +-#define A2S_CNTL_SW1__WRR_WR_WEIGHT__MASK 0xFF000000L +-//A2S_CNTL_SW2 +-#define A2S_CNTL_SW2__WR_TAG_SET_MIN__MASK 0x00000007L +-#define A2S_CNTL_SW2__RD_TAG_SET_MIN__MASK 0x00000038L +-#define A2S_CNTL_SW2__FORCE_RSP_REORDER_EN__MASK 0x00000040L +-#define A2S_CNTL_SW2__RSP_REORDER_DIS__MASK 0x00000080L +-#define A2S_CNTL_SW2__WRRSP_ACCUM_SEL__MASK 0x00000100L +-#define A2S_CNTL_SW2__SDP_WR_CHAIN_DIS__MASK 0x00000200L +-#define A2S_CNTL_SW2__WRRSP_TAGFIFO_CONT_RD_DIS__MASK 0x00000400L +-#define A2S_CNTL_SW2__RDRSP_TAGFIFO_CONT_RD_DIS__MASK 0x00000800L +-#define A2S_CNTL_SW2__RDRSP_STS_DATSTS_PRIORITY__MASK 0x00001000L +-#define A2S_CNTL_SW2__WRR_RD_WEIGHT__MASK 0x00FF0000L +-#define A2S_CNTL_SW2__WRR_WR_WEIGHT__MASK 0xFF000000L +-//NGDC_MGCG_CTRL +-#define NGDC_MGCG_CTRL__NGDC_MGCG_EN__MASK 0x00000001L +-#define NGDC_MGCG_CTRL__NGDC_MGCG_MODE__MASK 0x00000002L +-#define NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__MASK 0x000003FCL +-//A2S_MISC_CNTL +-#define A2S_MISC_CNTL__BLKLVL_FOR_MSG__MASK 0x00000003L +-#define A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS__MASK 0x00000004L +-//NGDC_SDP_PORT_CTRL +-#define NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__MASK 0x0000003FL +-//NGDC_RESERVED_0 +-#define NGDC_RESERVED_0__RESERVED__MASK 0xFFFFFFFFL +-//NGDC_RESERVED_1 +-#define NGDC_RESERVED_1__RESERVED__MASK 0xFFFFFFFFL +-//BIF_SDMA0_DOORBELL_RANGE +-#define BIF_SDMA0_DOORBELL_RANGE__OFFSET__MASK 0x00000FFCL +-#define BIF_SDMA0_DOORBELL_RANGE__SIZE__MASK 0x001F0000L +-//BIF_SDMA1_DOORBELL_RANGE +-#define BIF_SDMA1_DOORBELL_RANGE__OFFSET__MASK 0x00000FFCL +-#define BIF_SDMA1_DOORBELL_RANGE__SIZE__MASK 0x001F0000L +-//BIF_IH_DOORBELL_RANGE +-#define BIF_IH_DOORBELL_RANGE__OFFSET__MASK 0x00000FFCL +-#define BIF_IH_DOORBELL_RANGE__SIZE__MASK 0x001F0000L +-//BIF_MMSCH0_DOORBELL_RANGE +-#define BIF_MMSCH0_DOORBELL_RANGE__OFFSET__MASK 0x00000FFCL +-#define BIF_MMSCH0_DOORBELL_RANGE__SIZE__MASK 0x001F0000L +-//BIF_DOORBELL_FENCE_CNTL +-#define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE__MASK 0x00000001L +-//S2A_MISC_CNTL +-#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__MASK 0x00000001L +-#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__MASK 0x00000002L +-#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__MASK 0x00000004L +-//A2S_CNTL2_SEC_CL0 +-#define A2S_CNTL2_SEC_CL0__SECLVL_MAP__MASK 0x00000007L +-//A2S_CNTL2_SEC_CL1 +-#define A2S_CNTL2_SEC_CL1__SECLVL_MAP__MASK 0x00000007L +-//A2S_CNTL2_SEC_CL2 +-#define A2S_CNTL2_SEC_CL2__SECLVL_MAP__MASK 0x00000007L +-//A2S_CNTL2_SEC_CL3 +-#define A2S_CNTL2_SEC_CL3__SECLVL_MAP__MASK 0x00000007L +-//A2S_CNTL2_SEC_CL4 +-#define A2S_CNTL2_SEC_CL4__SECLVL_MAP__MASK 0x00000007L +- +- +-// addressBlock: nbif_sion_SIONDEC +-//SION_CL0_RdRsp_BurstTarget_REG0 +-#define SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL +-//SION_CL0_RdRsp_BurstTarget_REG1 +-#define SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL +-//SION_CL0_RdRsp_TimeSlot_REG0 +-#define SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL +-//SION_CL0_RdRsp_TimeSlot_REG1 +-#define SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL +-//SION_CL0_WrRsp_BurstTarget_REG0 +-#define SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL +-//SION_CL0_WrRsp_BurstTarget_REG1 +-#define SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL +-//SION_CL0_WrRsp_TimeSlot_REG0 +-#define SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL +-//SION_CL0_WrRsp_TimeSlot_REG1 +-#define SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL +-//SION_CL0_Req_BurstTarget_REG0 +-#define SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__MASK 0xFFFFFFFFL +-//SION_CL0_Req_BurstTarget_REG1 +-#define SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__MASK 0xFFFFFFFFL +-//SION_CL0_Req_TimeSlot_REG0 +-#define SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__MASK 0xFFFFFFFFL +-//SION_CL0_Req_TimeSlot_REG1 +-#define SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__MASK 0xFFFFFFFFL +-//SION_CL0_ReqPoolCredit_Alloc_REG0 +-#define SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL +-//SION_CL0_ReqPoolCredit_Alloc_REG1 +-#define SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL +-//SION_CL0_DataPoolCredit_Alloc_REG0 +-#define SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL +-//SION_CL0_DataPoolCredit_Alloc_REG1 +-#define SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL +-//SION_CL0_RdRspPoolCredit_Alloc_REG0 +-#define SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL +-//SION_CL0_RdRspPoolCredit_Alloc_REG1 +-#define SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL +-//SION_CL0_WrRspPoolCredit_Alloc_REG0 +-#define SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL +-//SION_CL0_WrRspPoolCredit_Alloc_REG1 +-#define SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL +-//SION_CL1_RdRsp_BurstTarget_REG0 +-#define SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL +-//SION_CL1_RdRsp_BurstTarget_REG1 +-#define SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL +-//SION_CL1_RdRsp_TimeSlot_REG0 +-#define SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL +-//SION_CL1_RdRsp_TimeSlot_REG1 +-#define SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL +-//SION_CL1_WrRsp_BurstTarget_REG0 +-#define SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL +-//SION_CL1_WrRsp_BurstTarget_REG1 +-#define SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL +-//SION_CL1_WrRsp_TimeSlot_REG0 +-#define SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL +-//SION_CL1_WrRsp_TimeSlot_REG1 +-#define SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL +-//SION_CL1_Req_BurstTarget_REG0 +-#define SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__MASK 0xFFFFFFFFL +-//SION_CL1_Req_BurstTarget_REG1 +-#define SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__MASK 0xFFFFFFFFL +-//SION_CL1_Req_TimeSlot_REG0 +-#define SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__MASK 0xFFFFFFFFL +-//SION_CL1_Req_TimeSlot_REG1 +-#define SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__MASK 0xFFFFFFFFL +-//SION_CL1_ReqPoolCredit_Alloc_REG0 +-#define SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL +-//SION_CL1_ReqPoolCredit_Alloc_REG1 +-#define SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL +-//SION_CL1_DataPoolCredit_Alloc_REG0 +-#define SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL +-//SION_CL1_DataPoolCredit_Alloc_REG1 +-#define SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL +-//SION_CL1_RdRspPoolCredit_Alloc_REG0 +-#define SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL +-//SION_CL1_RdRspPoolCredit_Alloc_REG1 +-#define SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL +-//SION_CL1_WrRspPoolCredit_Alloc_REG0 +-#define SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL +-//SION_CL1_WrRspPoolCredit_Alloc_REG1 +-#define SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL +-//SION_CL2_RdRsp_BurstTarget_REG0 +-#define SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL +-//SION_CL2_RdRsp_BurstTarget_REG1 +-#define SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL +-//SION_CL2_RdRsp_TimeSlot_REG0 +-#define SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL +-//SION_CL2_RdRsp_TimeSlot_REG1 +-#define SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL +-//SION_CL2_WrRsp_BurstTarget_REG0 +-#define SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL +-//SION_CL2_WrRsp_BurstTarget_REG1 +-#define SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL +-//SION_CL2_WrRsp_TimeSlot_REG0 +-#define SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL +-//SION_CL2_WrRsp_TimeSlot_REG1 +-#define SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL +-//SION_CL2_Req_BurstTarget_REG0 +-#define SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0__MASK 0xFFFFFFFFL +-//SION_CL2_Req_BurstTarget_REG1 +-#define SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32__MASK 0xFFFFFFFFL +-//SION_CL2_Req_TimeSlot_REG0 +-#define SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0__MASK 0xFFFFFFFFL +-//SION_CL2_Req_TimeSlot_REG1 +-#define SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32__MASK 0xFFFFFFFFL +-//SION_CL2_ReqPoolCredit_Alloc_REG0 +-#define SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL +-//SION_CL2_ReqPoolCredit_Alloc_REG1 +-#define SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL +-//SION_CL2_DataPoolCredit_Alloc_REG0 +-#define SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL +-//SION_CL2_DataPoolCredit_Alloc_REG1 +-#define SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL +-//SION_CL2_RdRspPoolCredit_Alloc_REG0 +-#define SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL +-//SION_CL2_RdRspPoolCredit_Alloc_REG1 +-#define SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL +-//SION_CL2_WrRspPoolCredit_Alloc_REG0 +-#define SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL +-//SION_CL2_WrRspPoolCredit_Alloc_REG1 +-#define SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL +-//SION_CL3_RdRsp_BurstTarget_REG0 +-#define SION_CL3_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL +-//SION_CL3_RdRsp_BurstTarget_REG1 +-#define SION_CL3_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL +-//SION_CL3_RdRsp_TimeSlot_REG0 +-#define SION_CL3_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL +-//SION_CL3_RdRsp_TimeSlot_REG1 +-#define SION_CL3_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL +-//SION_CL3_WrRsp_BurstTarget_REG0 +-#define SION_CL3_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL +-//SION_CL3_WrRsp_BurstTarget_REG1 +-#define SION_CL3_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL +-//SION_CL3_WrRsp_TimeSlot_REG0 +-#define SION_CL3_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL +-//SION_CL3_WrRsp_TimeSlot_REG1 +-#define SION_CL3_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL +-//SION_CL3_Req_BurstTarget_REG0 +-#define SION_CL3_Req_BurstTarget_REG0__Req_BurstTarget_31_0__MASK 0xFFFFFFFFL +-//SION_CL3_Req_BurstTarget_REG1 +-#define SION_CL3_Req_BurstTarget_REG1__Req_BurstTarget_63_32__MASK 0xFFFFFFFFL +-//SION_CL3_Req_TimeSlot_REG0 +-#define SION_CL3_Req_TimeSlot_REG0__Req_TimeSlot_31_0__MASK 0xFFFFFFFFL +-//SION_CL3_Req_TimeSlot_REG1 +-#define SION_CL3_Req_TimeSlot_REG1__Req_TimeSlot_63_32__MASK 0xFFFFFFFFL +-//SION_CL3_ReqPoolCredit_Alloc_REG0 +-#define SION_CL3_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL +-//SION_CL3_ReqPoolCredit_Alloc_REG1 +-#define SION_CL3_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL +-//SION_CL3_DataPoolCredit_Alloc_REG0 +-#define SION_CL3_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL +-//SION_CL3_DataPoolCredit_Alloc_REG1 +-#define SION_CL3_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL +-//SION_CL3_RdRspPoolCredit_Alloc_REG0 +-#define SION_CL3_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL +-//SION_CL3_RdRspPoolCredit_Alloc_REG1 +-#define SION_CL3_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL +-//SION_CL3_WrRspPoolCredit_Alloc_REG0 +-#define SION_CL3_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL +-//SION_CL3_WrRspPoolCredit_Alloc_REG1 +-#define SION_CL3_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL +-//SION_CL4_RdRsp_BurstTarget_REG0 +-#define SION_CL4_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL +-//SION_CL4_RdRsp_BurstTarget_REG1 +-#define SION_CL4_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL +-//SION_CL4_RdRsp_TimeSlot_REG0 +-#define SION_CL4_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL +-//SION_CL4_RdRsp_TimeSlot_REG1 +-#define SION_CL4_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL +-//SION_CL4_WrRsp_BurstTarget_REG0 +-#define SION_CL4_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL +-//SION_CL4_WrRsp_BurstTarget_REG1 +-#define SION_CL4_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL +-//SION_CL4_WrRsp_TimeSlot_REG0 +-#define SION_CL4_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL +-//SION_CL4_WrRsp_TimeSlot_REG1 +-#define SION_CL4_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL +-//SION_CL4_Req_BurstTarget_REG0 +-#define SION_CL4_Req_BurstTarget_REG0__Req_BurstTarget_31_0__MASK 0xFFFFFFFFL +-//SION_CL4_Req_BurstTarget_REG1 +-#define SION_CL4_Req_BurstTarget_REG1__Req_BurstTarget_63_32__MASK 0xFFFFFFFFL +-//SION_CL4_Req_TimeSlot_REG0 +-#define SION_CL4_Req_TimeSlot_REG0__Req_TimeSlot_31_0__MASK 0xFFFFFFFFL +-//SION_CL4_Req_TimeSlot_REG1 +-#define SION_CL4_Req_TimeSlot_REG1__Req_TimeSlot_63_32__MASK 0xFFFFFFFFL +-//SION_CL4_ReqPoolCredit_Alloc_REG0 +-#define SION_CL4_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL +-//SION_CL4_ReqPoolCredit_Alloc_REG1 +-#define SION_CL4_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL +-//SION_CL4_DataPoolCredit_Alloc_REG0 +-#define SION_CL4_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL +-//SION_CL4_DataPoolCredit_Alloc_REG1 +-#define SION_CL4_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL +-//SION_CL4_RdRspPoolCredit_Alloc_REG0 +-#define SION_CL4_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL +-//SION_CL4_RdRspPoolCredit_Alloc_REG1 +-#define SION_CL4_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL +-//SION_CL4_WrRspPoolCredit_Alloc_REG0 +-#define SION_CL4_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL +-//SION_CL4_WrRspPoolCredit_Alloc_REG1 +-#define SION_CL4_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL +-//SION_CL5_RdRsp_BurstTarget_REG0 +-#define SION_CL5_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL +-//SION_CL5_RdRsp_BurstTarget_REG1 +-#define SION_CL5_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL +-//SION_CL5_RdRsp_TimeSlot_REG0 +-#define SION_CL5_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL +-//SION_CL5_RdRsp_TimeSlot_REG1 +-#define SION_CL5_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL +-//SION_CL5_WrRsp_BurstTarget_REG0 +-#define SION_CL5_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL +-//SION_CL5_WrRsp_BurstTarget_REG1 +-#define SION_CL5_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL +-//SION_CL5_WrRsp_TimeSlot_REG0 +-#define SION_CL5_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL +-//SION_CL5_WrRsp_TimeSlot_REG1 +-#define SION_CL5_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL +-//SION_CL5_Req_BurstTarget_REG0 +-#define SION_CL5_Req_BurstTarget_REG0__Req_BurstTarget_31_0__MASK 0xFFFFFFFFL +-//SION_CL5_Req_BurstTarget_REG1 +-#define SION_CL5_Req_BurstTarget_REG1__Req_BurstTarget_63_32__MASK 0xFFFFFFFFL +-//SION_CL5_Req_TimeSlot_REG0 +-#define SION_CL5_Req_TimeSlot_REG0__Req_TimeSlot_31_0__MASK 0xFFFFFFFFL +-//SION_CL5_Req_TimeSlot_REG1 +-#define SION_CL5_Req_TimeSlot_REG1__Req_TimeSlot_63_32__MASK 0xFFFFFFFFL +-//SION_CL5_ReqPoolCredit_Alloc_REG0 +-#define SION_CL5_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL +-//SION_CL5_ReqPoolCredit_Alloc_REG1 +-#define SION_CL5_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL +-//SION_CL5_DataPoolCredit_Alloc_REG0 +-#define SION_CL5_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL +-//SION_CL5_DataPoolCredit_Alloc_REG1 +-#define SION_CL5_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL +-//SION_CL5_RdRspPoolCredit_Alloc_REG0 +-#define SION_CL5_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL +-//SION_CL5_RdRspPoolCredit_Alloc_REG1 +-#define SION_CL5_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL +-//SION_CL5_WrRspPoolCredit_Alloc_REG0 +-#define SION_CL5_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL +-//SION_CL5_WrRspPoolCredit_Alloc_REG1 +-#define SION_CL5_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL +-//SION_CNTL_REG0 +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__MASK 0x00000001L +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__MASK 0x00000002L +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__MASK 0x00000004L +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__MASK 0x00000008L +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__MASK 0x00000010L +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__MASK 0x00000020L +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__MASK 0x00000040L +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__MASK 0x00000080L +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__MASK 0x00000100L +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__MASK 0x00000200L +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__MASK 0x00000400L +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__MASK 0x00000800L +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__MASK 0x00001000L +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__MASK 0x00002000L +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__MASK 0x00004000L +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__MASK 0x00008000L +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__MASK 0x00010000L +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__MASK 0x00020000L +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__MASK 0x00040000L +-#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__MASK 0x00080000L +-//SION_CNTL_REG1 +-#define SION_CNTL_REG1__LIVELOCK_WATCHDOG_THRESHOLD__MASK 0x000000FFL +-#define SION_CNTL_REG1__CG_OFF_HYSTERESIS__MASK 0x0000FF00L +- +- +-// addressBlock: syshub_mmreg_direct_syshubdirect +-//SYSHUB_DS_CTRL_SOCCLK +-#define SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000001L +-#define SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000002L +-#define SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000004L +-#define SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000008L +-#define SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000010L +-#define SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000020L +-#define SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000040L +-#define SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000080L +-#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00010000L +-#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00020000L +-#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00040000L +-#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00080000L +-#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00100000L +-#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00200000L +-#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00400000L +-#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00800000L +-#define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x10000000L +-#define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__MASK 0x80000000L +-//SYSHUB_DS_CTRL2_SOCCLK +-#define SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__MASK 0x0000FFFFL +-//SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK +-#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en__MASK 0x00000001L +-#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en__MASK 0x00000002L +-#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__MASK 0x00008000L +-#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en__MASK 0x00010000L +-#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en__MASK 0x00020000L +-//SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK +-#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en__MASK 0x00000001L +-#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en__MASK 0x00000002L +-#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__MASK 0x00008000L +-#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en__MASK 0x00010000L +-#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en__MASK 0x00020000L +-//DMA_CLK0_SW0_SYSHUB_QOS_CNTL +-#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L +-#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL +-#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L +-//DMA_CLK0_SW1_SYSHUB_QOS_CNTL +-#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L +-#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL +-#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L +-//DMA_CLK0_SW0_CL0_CNTL +-#define DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L +-#define DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L +-#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L +-#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L +-#define DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L +-#define DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L +-//DMA_CLK0_SW0_CL1_CNTL +-#define DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L +-#define DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L +-#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L +-#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L +-#define DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L +-#define DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L +-//DMA_CLK0_SW0_CL2_CNTL +-#define DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L +-#define DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L +-#define DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L +-#define DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L +-#define DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L +-#define DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L +-//DMA_CLK0_SW0_CL3_CNTL +-#define DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L +-#define DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L +-#define DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L +-#define DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L +-#define DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L +-#define DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L +-//DMA_CLK0_SW0_CL4_CNTL +-#define DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L +-#define DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L +-#define DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L +-#define DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L +-#define DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L +-#define DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L +-//DMA_CLK0_SW0_CL5_CNTL +-#define DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L +-#define DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L +-#define DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L +-#define DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L +-#define DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L +-#define DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L +-//DMA_CLK0_SW1_CL0_CNTL +-#define DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L +-#define DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L +-#define DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L +-#define DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L +-#define DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L +-#define DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L +-//DMA_CLK0_SW2_CL0_CNTL +-#define DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L +-#define DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L +-#define DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L +-#define DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L +-#define DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L +-#define DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L +-//SYSHUB_CG_CNTL +-#define SYSHUB_CG_CNTL__SYSHUB_CG_EN__MASK 0x00000001L +-#define SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER__MASK 0x0000FF00L +-#define SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER__MASK 0x00FF0000L +-//SYSHUB_TRANS_IDLE +-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0__MASK 0x00000001L +-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1__MASK 0x00000002L +-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2__MASK 0x00000004L +-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3__MASK 0x00000008L +-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4__MASK 0x00000010L +-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5__MASK 0x00000020L +-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6__MASK 0x00000040L +-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7__MASK 0x00000080L +-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8__MASK 0x00000100L +-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9__MASK 0x00000200L +-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10__MASK 0x00000400L +-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11__MASK 0x00000800L +-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12__MASK 0x00001000L +-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13__MASK 0x00002000L +-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14__MASK 0x00004000L +-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15__MASK 0x00008000L +-#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF__MASK 0x00010000L +-//SYSHUB_HP_TIMER +-#define SYSHUB_HP_TIMER__SYSHUB_HP_TIMER__MASK 0xFFFFFFFFL +-//SYSHUB_SCRATCH +-#define SYSHUB_SCRATCH__SCRATCH__MASK 0xFFFFFFFFL +-//SYSHUB_DS_CTRL_SHUBCLK +-#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000001L +-#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000002L +-#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000004L +-#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000008L +-#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000010L +-#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000020L +-#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000040L +-#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000080L +-#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00010000L +-#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00020000L +-#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00040000L +-#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00080000L +-#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00100000L +-#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00200000L +-#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00400000L +-#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00800000L +-#define SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x10000000L +-#define SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN__MASK 0x80000000L +-//SYSHUB_DS_CTRL2_SHUBCLK +-#define SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER__MASK 0x0000FFFFL +-//SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK +-#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en__MASK 0x00008000L +-#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en__MASK 0x00010000L +-//SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK +-#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en__MASK 0x00008000L +-#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en__MASK 0x00010000L +-//DMA_CLK1_SW0_SYSHUB_QOS_CNTL +-#define DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L +-#define DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL +-#define DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L +-//DMA_CLK1_SW1_SYSHUB_QOS_CNTL +-#define DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L +-#define DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL +-#define DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L +-//DMA_CLK1_SW0_CL0_CNTL +-#define DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L +-#define DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L +-#define DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L +-#define DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L +-#define DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L +-#define DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L +-//DMA_CLK1_SW0_CL1_CNTL +-#define DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L +-#define DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L +-#define DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L +-#define DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L +-#define DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L +-#define DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L +-//DMA_CLK1_SW0_CL2_CNTL +-#define DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L +-#define DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L +-#define DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L +-#define DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L +-#define DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L +-#define DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L +-//DMA_CLK1_SW0_CL3_CNTL +-#define DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L +-#define DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L +-#define DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L +-#define DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L +-#define DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L +-#define DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L +-//DMA_CLK1_SW0_CL4_CNTL +-#define DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L +-#define DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L +-#define DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L +-#define DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L +-#define DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L +-#define DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L +-//DMA_CLK1_SW1_CL0_CNTL +-#define DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L +-#define DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L +-#define DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L +-#define DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L +-#define DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L +-#define DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L +-//DMA_CLK1_SW1_CL1_CNTL +-#define DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L +-#define DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L +-#define DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L +-#define DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L +-#define DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L +-#define DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L +-//DMA_CLK1_SW1_CL2_CNTL +-#define DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L +-#define DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L +-#define DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L +-#define DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L +-#define DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L +-#define DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L +-//DMA_CLK1_SW1_CL3_CNTL +-#define DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L +-#define DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L +-#define DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L +-#define DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L +-#define DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L +-#define DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L +-//DMA_CLK1_SW1_CL4_CNTL +-#define DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L +-#define DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L +-#define DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L +-#define DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L +-#define DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L +-#define DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L +- +- +-// addressBlock: gdc_ras_gdc_ras_regblk +-//GDC_RAS_LEAF0_CTRL +-#define GDC_RAS_LEAF0_CTRL__POISON_DET_EN__MASK 0x00000001L +-#define GDC_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L +-#define GDC_RAS_LEAF0_CTRL__POISON_STALL_EN__MASK 0x00000004L +-#define GDC_RAS_LEAF0_CTRL__PARITY_DET_EN__MASK 0x00000010L +-#define GDC_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L +-#define GDC_RAS_LEAF0_CTRL__PARITY_STALL_EN__MASK 0x00000040L +-#define GDC_RAS_LEAF0_CTRL__ERR_EVENT_RECV__MASK 0x00010000L +-#define GDC_RAS_LEAF0_CTRL__LINK_DIS_RECV__MASK 0x00020000L +-#define GDC_RAS_LEAF0_CTRL__POISON_ERR_DET__MASK 0x00040000L +-#define GDC_RAS_LEAF0_CTRL__PARITY_ERR_DET__MASK 0x00080000L +-#define GDC_RAS_LEAF0_CTRL__ERR_EVENT_SENT__MASK 0x00100000L +-#define GDC_RAS_LEAF0_CTRL__EGRESS_STALLED__MASK 0x00200000L +-//GDC_RAS_LEAF1_CTRL +-#define GDC_RAS_LEAF1_CTRL__POISON_DET_EN__MASK 0x00000001L +-#define GDC_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L +-#define GDC_RAS_LEAF1_CTRL__POISON_STALL_EN__MASK 0x00000004L +-#define GDC_RAS_LEAF1_CTRL__PARITY_DET_EN__MASK 0x00000010L +-#define GDC_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L +-#define GDC_RAS_LEAF1_CTRL__PARITY_STALL_EN__MASK 0x00000040L +-#define GDC_RAS_LEAF1_CTRL__ERR_EVENT_RECV__MASK 0x00010000L +-#define GDC_RAS_LEAF1_CTRL__LINK_DIS_RECV__MASK 0x00020000L +-#define GDC_RAS_LEAF1_CTRL__POISON_ERR_DET__MASK 0x00040000L +-#define GDC_RAS_LEAF1_CTRL__PARITY_ERR_DET__MASK 0x00080000L +-#define GDC_RAS_LEAF1_CTRL__ERR_EVENT_SENT__MASK 0x00100000L +-#define GDC_RAS_LEAF1_CTRL__EGRESS_STALLED__MASK 0x00200000L +-//GDC_RAS_LEAF2_CTRL +-#define GDC_RAS_LEAF2_CTRL__POISON_DET_EN__MASK 0x00000001L +-#define GDC_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L +-#define GDC_RAS_LEAF2_CTRL__POISON_STALL_EN__MASK 0x00000004L +-#define GDC_RAS_LEAF2_CTRL__PARITY_DET_EN__MASK 0x00000010L +-#define GDC_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L +-#define GDC_RAS_LEAF2_CTRL__PARITY_STALL_EN__MASK 0x00000040L +-#define GDC_RAS_LEAF2_CTRL__ERR_EVENT_RECV__MASK 0x00010000L +-#define GDC_RAS_LEAF2_CTRL__LINK_DIS_RECV__MASK 0x00020000L +-#define GDC_RAS_LEAF2_CTRL__POISON_ERR_DET__MASK 0x00040000L +-#define GDC_RAS_LEAF2_CTRL__PARITY_ERR_DET__MASK 0x00080000L +-#define GDC_RAS_LEAF2_CTRL__ERR_EVENT_SENT__MASK 0x00100000L +-#define GDC_RAS_LEAF2_CTRL__EGRESS_STALLED__MASK 0x00200000L +-//GDC_RAS_LEAF3_CTRL +-#define GDC_RAS_LEAF3_CTRL__POISON_DET_EN__MASK 0x00000001L +-#define GDC_RAS_LEAF3_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L +-#define GDC_RAS_LEAF3_CTRL__POISON_STALL_EN__MASK 0x00000004L +-#define GDC_RAS_LEAF3_CTRL__PARITY_DET_EN__MASK 0x00000010L +-#define GDC_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L +-#define GDC_RAS_LEAF3_CTRL__PARITY_STALL_EN__MASK 0x00000040L +-#define GDC_RAS_LEAF3_CTRL__ERR_EVENT_RECV__MASK 0x00010000L +-#define GDC_RAS_LEAF3_CTRL__LINK_DIS_RECV__MASK 0x00020000L +-#define GDC_RAS_LEAF3_CTRL__POISON_ERR_DET__MASK 0x00040000L +-#define GDC_RAS_LEAF3_CTRL__PARITY_ERR_DET__MASK 0x00080000L +-#define GDC_RAS_LEAF3_CTRL__ERR_EVENT_SENT__MASK 0x00100000L +-#define GDC_RAS_LEAF3_CTRL__EGRESS_STALLED__MASK 0x00200000L +-//GDC_RAS_LEAF4_CTRL +-#define GDC_RAS_LEAF4_CTRL__POISON_DET_EN__MASK 0x00000001L +-#define GDC_RAS_LEAF4_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L +-#define GDC_RAS_LEAF4_CTRL__POISON_STALL_EN__MASK 0x00000004L +-#define GDC_RAS_LEAF4_CTRL__PARITY_DET_EN__MASK 0x00000010L +-#define GDC_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L +-#define GDC_RAS_LEAF4_CTRL__PARITY_STALL_EN__MASK 0x00000040L +-#define GDC_RAS_LEAF4_CTRL__ERR_EVENT_RECV__MASK 0x00010000L +-#define GDC_RAS_LEAF4_CTRL__LINK_DIS_RECV__MASK 0x00020000L +-#define GDC_RAS_LEAF4_CTRL__POISON_ERR_DET__MASK 0x00040000L +-#define GDC_RAS_LEAF4_CTRL__PARITY_ERR_DET__MASK 0x00080000L +-#define GDC_RAS_LEAF4_CTRL__ERR_EVENT_SENT__MASK 0x00100000L +-#define GDC_RAS_LEAF4_CTRL__EGRESS_STALLED__MASK 0x00200000L +-//GDC_RAS_LEAF5_CTRL +-#define GDC_RAS_LEAF5_CTRL__POISON_DET_EN__MASK 0x00000001L +-#define GDC_RAS_LEAF5_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L +-#define GDC_RAS_LEAF5_CTRL__POISON_STALL_EN__MASK 0x00000004L +-#define GDC_RAS_LEAF5_CTRL__PARITY_DET_EN__MASK 0x00000010L +-#define GDC_RAS_LEAF5_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L +-#define GDC_RAS_LEAF5_CTRL__PARITY_STALL_EN__MASK 0x00000040L +-#define GDC_RAS_LEAF5_CTRL__ERR_EVENT_RECV__MASK 0x00010000L +-#define GDC_RAS_LEAF5_CTRL__LINK_DIS_RECV__MASK 0x00020000L +-#define GDC_RAS_LEAF5_CTRL__POISON_ERR_DET__MASK 0x00040000L +-#define GDC_RAS_LEAF5_CTRL__PARITY_ERR_DET__MASK 0x00080000L +-#define GDC_RAS_LEAF5_CTRL__ERR_EVENT_SENT__MASK 0x00100000L +-#define GDC_RAS_LEAF5_CTRL__EGRESS_STALLED__MASK 0x00200000L +- +- +-// addressBlock: gdc_rst_GDCRST_DEC +-//SHUB_PF_FLR_RST +-#define SHUB_PF_FLR_RST__PF0_FLR_RST__MASK 0x00000001L +-#define SHUB_PF_FLR_RST__PF1_FLR_RST__MASK 0x00000002L +-#define SHUB_PF_FLR_RST__PF2_FLR_RST__MASK 0x00000004L +-#define SHUB_PF_FLR_RST__PF3_FLR_RST__MASK 0x00000008L +-#define SHUB_PF_FLR_RST__PF4_FLR_RST__MASK 0x00000010L +-#define SHUB_PF_FLR_RST__PF5_FLR_RST__MASK 0x00000020L +-#define SHUB_PF_FLR_RST__PF6_FLR_RST__MASK 0x00000040L +-#define SHUB_PF_FLR_RST__PF7_FLR_RST__MASK 0x00000080L +-//SHUB_GFX_DRV_MODE1_RST +-#define SHUB_GFX_DRV_MODE1_RST__GFX_DRV_MODE1_RST__MASK 0x00000001L +-//SHUB_LINK_RESET +-#define SHUB_LINK_RESET__LINK_RESET__MASK 0x00000001L +-//SHUB_PF0_VF_FLR_RST +-#define SHUB_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__MASK 0x00000001L +-#define SHUB_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__MASK 0x00000002L +-#define SHUB_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__MASK 0x00000004L +-#define SHUB_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__MASK 0x00000008L +-#define SHUB_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__MASK 0x00000010L +-#define SHUB_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__MASK 0x00000020L +-#define SHUB_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__MASK 0x00000040L +-#define SHUB_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__MASK 0x00000080L +-#define SHUB_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__MASK 0x00000100L +-#define SHUB_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__MASK 0x00000200L +-#define SHUB_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__MASK 0x00000400L +-#define SHUB_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__MASK 0x00000800L +-#define SHUB_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__MASK 0x00001000L +-#define SHUB_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__MASK 0x00002000L +-#define SHUB_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__MASK 0x00004000L +-#define SHUB_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__MASK 0x00008000L +-#define SHUB_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__MASK 0x80000000L +-//SHUB_HARD_RST_CTRL +-#define SHUB_HARD_RST_CTRL__COR_RESET_EN__MASK 0x00000001L +-#define SHUB_HARD_RST_CTRL__REG_RESET_EN__MASK 0x00000002L +-#define SHUB_HARD_RST_CTRL__STY_RESET_EN__MASK 0x00000004L +-#define SHUB_HARD_RST_CTRL__NIC400_RESET_EN__MASK 0x00000008L +-#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN__MASK 0x00000010L +-//SHUB_SOFT_RST_CTRL +-#define SHUB_SOFT_RST_CTRL__COR_RESET_EN__MASK 0x00000001L +-#define SHUB_SOFT_RST_CTRL__REG_RESET_EN__MASK 0x00000002L +-#define SHUB_SOFT_RST_CTRL__STY_RESET_EN__MASK 0x00000004L +-#define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN__MASK 0x00000008L +-#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN__MASK 0x00000010L +-//SHUB_SDP_PORT_RST +-#define SHUB_SDP_PORT_RST__SDP_PORT_RST__MASK 0x00000001L +- +- +-// addressBlock: bif_bx_pf_SYSDEC +-//SBIOS_SCRATCH_0 +-#define SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__MASK 0xFFFFFFFFL +-//SBIOS_SCRATCH_1 +-#define SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__MASK 0xFFFFFFFFL +-//SBIOS_SCRATCH_2 +-#define SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__MASK 0xFFFFFFFFL +-//SBIOS_SCRATCH_3 +-#define SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__MASK 0xFFFFFFFFL +-//BIOS_SCRATCH_0 +-#define BIOS_SCRATCH_0__BIOS_SCRATCH_0__MASK 0xFFFFFFFFL +-//BIOS_SCRATCH_1 +-#define BIOS_SCRATCH_1__BIOS_SCRATCH_1__MASK 0xFFFFFFFFL +-//BIOS_SCRATCH_2 +-#define BIOS_SCRATCH_2__BIOS_SCRATCH_2__MASK 0xFFFFFFFFL +-//BIOS_SCRATCH_3 +-#define BIOS_SCRATCH_3__BIOS_SCRATCH_3__MASK 0xFFFFFFFFL +-//BIOS_SCRATCH_4 +-#define BIOS_SCRATCH_4__BIOS_SCRATCH_4__MASK 0xFFFFFFFFL +-//BIOS_SCRATCH_5 +-#define BIOS_SCRATCH_5__BIOS_SCRATCH_5__MASK 0xFFFFFFFFL +-//BIOS_SCRATCH_6 +-#define BIOS_SCRATCH_6__BIOS_SCRATCH_6__MASK 0xFFFFFFFFL +-//BIOS_SCRATCH_7 +-#define BIOS_SCRATCH_7__BIOS_SCRATCH_7__MASK 0xFFFFFFFFL +-//BIOS_SCRATCH_8 +-#define BIOS_SCRATCH_8__BIOS_SCRATCH_8__MASK 0xFFFFFFFFL +-//BIOS_SCRATCH_9 +-#define BIOS_SCRATCH_9__BIOS_SCRATCH_9__MASK 0xFFFFFFFFL +-//BIOS_SCRATCH_10 +-#define BIOS_SCRATCH_10__BIOS_SCRATCH_10__MASK 0xFFFFFFFFL +-//BIOS_SCRATCH_11 +-#define BIOS_SCRATCH_11__BIOS_SCRATCH_11__MASK 0xFFFFFFFFL +-//BIOS_SCRATCH_12 +-#define BIOS_SCRATCH_12__BIOS_SCRATCH_12__MASK 0xFFFFFFFFL +-//BIOS_SCRATCH_13 +-#define BIOS_SCRATCH_13__BIOS_SCRATCH_13__MASK 0xFFFFFFFFL +-//BIOS_SCRATCH_14 +-#define BIOS_SCRATCH_14__BIOS_SCRATCH_14__MASK 0xFFFFFFFFL +-//BIOS_SCRATCH_15 +-#define BIOS_SCRATCH_15__BIOS_SCRATCH_15__MASK 0xFFFFFFFFL +-//BIF_RLC_INTR_CNTL +-#define BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__MASK 0x00000001L +-#define BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__MASK 0x00000002L +-#define BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__MASK 0x00000004L +-#define BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__MASK 0x00000008L +-//BIF_VCE_INTR_CNTL +-#define BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__MASK 0x00000001L +-#define BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__MASK 0x00000002L +-#define BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__MASK 0x00000004L +-#define BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__MASK 0x00000008L +-//BIF_UVD_INTR_CNTL +-#define BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__MASK 0x00000001L +-#define BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__MASK 0x00000002L +-#define BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__MASK 0x00000004L +-#define BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__MASK 0x00000008L +-//GFX_MMIOREG_CAM_ADDR0 +-#define GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__MASK 0x000FFFFFL +-//GFX_MMIOREG_CAM_REMAP_ADDR0 +-#define GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__MASK 0x000FFFFFL +-//GFX_MMIOREG_CAM_ADDR1 +-#define GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__MASK 0x000FFFFFL +-//GFX_MMIOREG_CAM_REMAP_ADDR1 +-#define GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__MASK 0x000FFFFFL +-//GFX_MMIOREG_CAM_ADDR2 +-#define GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__MASK 0x000FFFFFL +-//GFX_MMIOREG_CAM_REMAP_ADDR2 +-#define GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__MASK 0x000FFFFFL +-//GFX_MMIOREG_CAM_ADDR3 +-#define GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__MASK 0x000FFFFFL +-//GFX_MMIOREG_CAM_REMAP_ADDR3 +-#define GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__MASK 0x000FFFFFL +-//GFX_MMIOREG_CAM_ADDR4 +-#define GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__MASK 0x000FFFFFL +-//GFX_MMIOREG_CAM_REMAP_ADDR4 +-#define GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__MASK 0x000FFFFFL +-//GFX_MMIOREG_CAM_ADDR5 +-#define GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__MASK 0x000FFFFFL +-//GFX_MMIOREG_CAM_REMAP_ADDR5 +-#define GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__MASK 0x000FFFFFL +-//GFX_MMIOREG_CAM_ADDR6 +-#define GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__MASK 0x000FFFFFL +-//GFX_MMIOREG_CAM_REMAP_ADDR6 +-#define GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__MASK 0x000FFFFFL +-//GFX_MMIOREG_CAM_ADDR7 +-#define GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__MASK 0x000FFFFFL +-//GFX_MMIOREG_CAM_REMAP_ADDR7 +-#define GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__MASK 0x000FFFFFL +-//GFX_MMIOREG_CAM_CNTL +-#define GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__MASK 0x000000FFL +-//GFX_MMIOREG_CAM_ZERO_CPL +-#define GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__MASK 0xFFFFFFFFL +-//GFX_MMIOREG_CAM_ONE_CPL +-#define GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__MASK 0xFFFFFFFFL +-//GFX_MMIOREG_CAM_PROGRAMMABLE_CPL +-#define GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__MASK 0xFFFFFFFFL +- +- +-// addressBlock: bif_bx_pf_SYSPFVFDEC +-//MM_INDEX +-#define MM_INDEX__MM_OFFSET__MASK 0x7FFFFFFFL +-#define MM_INDEX__MM_APER__MASK 0x80000000L +-//MM_DATA +-#define MM_DATA__MM_DATA__MASK 0xFFFFFFFFL +-//MM_INDEX_HI +-#define MM_INDEX_HI__MM_OFFSET_HI__MASK 0xFFFFFFFFL +-//SYSHUB_INDEX_OVLP +-#define SYSHUB_INDEX_OVLP__SYSHUB_OFFSET__MASK 0x003FFFFFL +-//SYSHUB_DATA_OVLP +-#define SYSHUB_DATA_OVLP__SYSHUB_DATA__MASK 0xFFFFFFFFL +-//PCIE_INDEX +-#define PCIE_INDEX__PCIE_INDEX__MASK 0xFFFFFFFFL +-//PCIE_DATA +-#define PCIE_DATA__PCIE_DATA__MASK 0xFFFFFFFFL +-//PCIE_INDEX2 +-#define PCIE_INDEX2__PCIE_INDEX2__MASK 0xFFFFFFFFL +-//PCIE_DATA2 +-#define PCIE_DATA2__PCIE_DATA2__MASK 0xFFFFFFFFL +- +- +-// addressBlock: rcc_dwn_BIFDEC1 +-//DN_PCIE_RESERVED +-#define DN_PCIE_RESERVED__PCIE_RESERVED__MASK 0xFFFFFFFFL +-//DN_PCIE_SCRATCH +-#define DN_PCIE_SCRATCH__PCIE_SCRATCH__MASK 0xFFFFFFFFL +-//DN_PCIE_CNTL +-#define DN_PCIE_CNTL__HWINIT_WR_LOCK__MASK 0x00000001L +-#define DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__MASK 0x00000080L +-#define DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__MASK 0x40000000L +-//DN_PCIE_CONFIG_CNTL +-#define DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__MASK 0x06000000L +-//DN_PCIE_RX_CNTL2 +-#define DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__MASK 0x70000000L +-//DN_PCIE_BUS_CNTL +-#define DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__MASK 0x00000080L +-#define DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__MASK 0x00000100L +-//DN_PCIE_CFG_CNTL +-#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__MASK 0x00000001L +-#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__MASK 0x00000002L +-#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__MASK 0x00000004L +-//DN_PCIE_STRAP_F0 +-#define DN_PCIE_STRAP_F0__STRAP_F0_EN__MASK 0x00000001L +-#define DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__MASK 0x00020000L +-#define DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__MASK 0x00E00000L +-//DN_PCIE_STRAP_MISC +-#define DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__MASK 0x01000000L +-#define DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__MASK 0x20000000L +-//DN_PCIE_STRAP_MISC2 +-#define DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__MASK 0x00000004L +- +- +-// addressBlock: rcc_dwnp_BIFDEC1 +-//PCIEP_RESERVED +-#define PCIEP_RESERVED__PCIEP_RESERVED__MASK 0xFFFFFFFFL +-//PCIEP_SCRATCH +-#define PCIEP_SCRATCH__PCIEP_SCRATCH__MASK 0xFFFFFFFFL +-//PCIE_ERR_CNTL +-#define PCIE_ERR_CNTL__ERR_REPORTING_DIS__MASK 0x00000001L +-#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__MASK 0x00000700L +-#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__MASK 0x00000800L +-#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__MASK 0x00020000L +-//PCIE_RX_CNTL +-#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__MASK 0x00000100L +-#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__MASK 0x00000200L +-#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__MASK 0x00100000L +-#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__MASK 0x00200000L +-#define PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__MASK 0x08000000L +-//PCIE_LC_SPEED_CNTL +-#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__MASK 0x00000001L +-#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__MASK 0x00000002L +-//PCIE_LC_CNTL2 +-#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__MASK 0x08000000L +-//PCIEP_STRAP_MISC +-#define PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__MASK 0x00000400L +-//LTR_MSG_INFO_FROM_EP +-#define LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__MASK 0xFFFFFFFFL +- +- +-// addressBlock: rcc_ep_BIFDEC1 +-//EP_PCIE_SCRATCH +-#define EP_PCIE_SCRATCH__PCIE_SCRATCH__MASK 0xFFFFFFFFL +-//EP_PCIE_CNTL +-#define EP_PCIE_CNTL__UR_ERR_REPORT_DIS__MASK 0x00000080L +-#define EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__MASK 0x00000100L +-#define EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__MASK 0x40000000L +-//EP_PCIE_INT_CNTL +-#define EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__MASK 0x00000001L +-#define EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__MASK 0x00000002L +-#define EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__MASK 0x00000004L +-#define EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__MASK 0x00000008L +-#define EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__MASK 0x00000010L +-#define EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__MASK 0x00000040L +-//EP_PCIE_INT_STATUS +-#define EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__MASK 0x00000001L +-#define EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__MASK 0x00000002L +-#define EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__MASK 0x00000004L +-#define EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__MASK 0x00000008L +-#define EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__MASK 0x00000010L +-#define EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__MASK 0x00000040L +-//EP_PCIE_RX_CNTL2 +-#define EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__MASK 0x00000001L +-//EP_PCIE_BUS_CNTL +-#define EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__MASK 0x00000080L +-//EP_PCIE_CFG_CNTL +-#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__MASK 0x00000001L +-#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__MASK 0x00000002L +-#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__MASK 0x00000004L +-//EP_PCIE_OBFF_CNTL +-#define EP_PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE__MASK 0x00000001L +-#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN__MASK 0x00000002L +-#define EP_PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE__MASK 0x00000004L +-#define EP_PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE__MASK 0x00000008L +-#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH__MASK 0x000000F0L +-#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH__MASK 0x00000F00L +-#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD__MASK 0x0000F000L +-#define EP_PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE__MASK 0x00010000L +-#define EP_PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE__MASK 0x00020000L +-#define EP_PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE__MASK 0x00040000L +-#define EP_PCIE_OBFF_CNTL__TX_OBFF_ACCEPT_IN_NOND0__MASK 0x00080000L +-#define EP_PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE__MASK 0x00F00000L +-//EP_PCIE_TX_LTR_CNTL +-#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__MASK 0x00000007L +-#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__MASK 0x00000038L +-#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__MASK 0x00000040L +-#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__MASK 0x00000380L +-#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__MASK 0x00001C00L +-#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__MASK 0x00002000L +-#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__MASK 0x00004000L +-#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__MASK 0x00008000L +-#define EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__MASK 0x00010000L +-//EP_PCIE_STRAP_MISC +-#define EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__MASK 0x20000000L +-//EP_PCIE_STRAP_MISC2 +-#define EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__MASK 0x00000010L +-//EP_PCIE_STRAP_PI +-//EP_PCIE_F0_DPA_CAP +-#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__MASK 0x00000300L +-#define EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__MASK 0x00003000L +-#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__MASK 0x00FF0000L +-#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__MASK 0xFF000000L +-//EP_PCIE_F0_DPA_LATENCY_INDICATOR +-#define EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__MASK 0xFFL +-//EP_PCIE_F0_DPA_CNTL +-#define EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__MASK 0x001FL +-#define EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__MASK 0x0100L +-//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 +-#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__MASK 0xFFL +-//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 +-#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__MASK 0xFFL +-//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 +-#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__MASK 0xFFL +-//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 +-#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__MASK 0xFFL +-//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 +-#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__MASK 0xFFL +-//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 +-#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__MASK 0xFFL +-//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 +-#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__MASK 0xFFL +-//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 +-#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__MASK 0xFFL +-//EP_PCIE_PME_CONTROL +-#define EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__MASK 0x1FL +-//EP_PCIEP_RESERVED +-#define EP_PCIEP_RESERVED__PCIEP_RESERVED__MASK 0xFFFFFFFFL +-//EP_PCIE_TX_CNTL +-#define EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__MASK 0x00000C00L +-#define EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__MASK 0x00003000L +-#define EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__MASK 0x01000000L +-#define EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__MASK 0x02000000L +-#define EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__MASK 0x04000000L +-//EP_PCIE_TX_REQUESTER_ID +-#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__MASK 0x00000007L +-#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__MASK 0x000000F8L +-#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__MASK 0x0000FF00L +-//EP_PCIE_ERR_CNTL +-#define EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__MASK 0x00000001L +-#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__MASK 0x00000700L +-#define EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__MASK 0x00020000L +-#define EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__MASK 0x00040000L +-#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__MASK 0x01000000L +-#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__MASK 0x02000000L +-#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__MASK 0x04000000L +-#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__MASK 0x08000000L +-#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__MASK 0x10000000L +-#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__MASK 0x20000000L +-#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__MASK 0x40000000L +-#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__MASK 0x80000000L +-//EP_PCIE_RX_CNTL +-#define EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__MASK 0x00000100L +-#define EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__MASK 0x00000200L +-#define EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__MASK 0x00100000L +-#define EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__MASK 0x00200000L +-#define EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__MASK 0x00400000L +-#define EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__MASK 0x01000000L +-#define EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__MASK 0x02000000L +-#define EP_PCIE_RX_CNTL__RX_TPH_DIS__MASK 0x04000000L +-//EP_PCIE_LC_SPEED_CNTL +-#define EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__MASK 0x00000001L +-#define EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__MASK 0x00000002L +- +- +-// addressBlock: bif_bx_pf_BIFDEC1 +-//BIF_MM_INDACCESS_CNTL +-#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__MASK 0x00000002L +-//BUS_CNTL +-#define BUS_CNTL__PMI_INT_DIS_EP__MASK 0x00000008L +-#define BUS_CNTL__PMI_INT_DIS_DN__MASK 0x00000010L +-#define BUS_CNTL__PMI_INT_DIS_SWUS__MASK 0x00000020L +-#define BUS_CNTL__VGA_REG_COHERENCY_DIS__MASK 0x00000040L +-#define BUS_CNTL__VGA_MEM_COHERENCY_DIS__MASK 0x00000080L +-#define BUS_CNTL__SET_AZ_TC__MASK 0x00001C00L +-#define BUS_CNTL__SET_MC_TC__MASK 0x0000E000L +-#define BUS_CNTL__ZERO_BE_WR_EN__MASK 0x00010000L +-#define BUS_CNTL__ZERO_BE_RD_EN__MASK 0x00020000L +-#define BUS_CNTL__RD_STALL_IO_WR__MASK 0x00040000L +-#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__MASK 0x00080000L +-#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__MASK 0x00100000L +-#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__MASK 0x00200000L +-#define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__MASK 0x00400000L +-#define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__MASK 0x00800000L +-#define BUS_CNTL__UR_OVRD_FOR_ECRC_EN__MASK 0x01000000L +-//BIF_SCRATCH0 +-#define BIF_SCRATCH0__BIF_SCRATCH0__MASK 0xFFFFFFFFL +-//BIF_SCRATCH1 +-#define BIF_SCRATCH1__BIF_SCRATCH1__MASK 0xFFFFFFFFL +-//BX_RESET_EN +-#define BX_RESET_EN__COR_RESET_EN__MASK 0x00000001L +-#define BX_RESET_EN__REG_RESET_EN__MASK 0x00000002L +-#define BX_RESET_EN__STY_RESET_EN__MASK 0x00000004L +-#define BX_RESET_EN__FLR_TWICE_EN__MASK 0x00000100L +-#define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__MASK 0x00010000L +-//MM_CFGREGS_CNTL +-#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__MASK 0x00000007L +-#define MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__MASK 0x000000C0L +-#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__MASK 0x80000000L +-//BX_RESET_CNTL +-#define BX_RESET_CNTL__LINK_TRAIN_EN__MASK 0x00000001L +-//INTERRUPT_CNTL +-#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__MASK 0x00000001L +-#define INTERRUPT_CNTL__IH_DUMMY_RD_EN__MASK 0x00000002L +-#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__MASK 0x00000008L +-#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__MASK 0x000000F0L +-#define INTERRUPT_CNTL__GEN_IH_INT_EN__MASK 0x00000100L +-#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__MASK 0x00008000L +-//INTERRUPT_CNTL2 +-#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__MASK 0xFFFFFFFFL +-//CLKREQB_PAD_CNTL +-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__MASK 0x00000001L +-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__MASK 0x00000002L +-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__MASK 0x00000004L +-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__MASK 0x00000018L +-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__MASK 0x00000020L +-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__MASK 0x00000040L +-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__MASK 0x00000080L +-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__MASK 0x00000100L +-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__MASK 0x00000200L +-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__MASK 0x00000400L +-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__MASK 0x00000800L +-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__MASK 0x00001000L +-#define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__MASK 0x00002000L +-#define CLKREQB_PAD_CNTL__CLKREQB_PERF_COUNTER_UPPER__MASK 0xFF000000L +-//CLKREQB_PERF_COUNTER +-#define CLKREQB_PERF_COUNTER__CLKREQB_PERF_COUNTER_LOWER__MASK 0xFFFFFFFFL +-//BIF_CLK_CTRL +-#define BIF_CLK_CTRL__BIF_XSTCLK_READY__MASK 0x00000001L +-#define BIF_CLK_CTRL__BACO_XSTCLK_SWITCH_BYPASS__MASK 0x00000002L +-//BIF_FEATURES_CONTROL_MISC +-#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__MASK 0x00000001L +-#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__MASK 0x00000002L +-#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__MASK 0x00000004L +-#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__MASK 0x00000008L +-#define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS__MASK 0x00000200L +-#define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS__MASK 0x00000400L +-#define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__MASK 0x00000800L +-#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__MASK 0x00001000L +-#define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__MASK 0x00002000L +-#define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__MASK 0x00008000L +-#define BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS__MASK 0x00020000L +-#define BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS__MASK 0x00040000L +-#define BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__MASK 0x01000000L +-//BIF_DOORBELL_CNTL +-#define BIF_DOORBELL_CNTL__SELF_RING_DIS__MASK 0x00000001L +-#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__MASK 0x00000002L +-#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__MASK 0x00000004L +-#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__MASK 0x00000008L +-#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__MASK 0x00000010L +-#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__MASK 0x01000000L +-#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__MASK 0x02000000L +-#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__MASK 0x04000000L +-#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__MASK 0x08000000L +-//BIF_DOORBELL_INT_CNTL +-#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__MASK 0x00000001L +-#define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS__MASK 0x00000002L +-#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__MASK 0x00010000L +-#define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR__MASK 0x00020000L +-//BIF_SLVARB_MODE +-#define BIF_SLVARB_MODE__SLVARB_MODE__MASK 0x00000003L +-//BIF_FB_EN +-#define BIF_FB_EN__FB_READ_EN__MASK 0x00000001L +-#define BIF_FB_EN__FB_WRITE_EN__MASK 0x00000002L +-//BIF_BUSY_DELAY_CNTR +-#define BIF_BUSY_DELAY_CNTR__DELAY_CNT__MASK 0x0000003FL +-//BIF_PERFMON_CNTL +-#define BIF_PERFMON_CNTL__PERFCOUNTER_EN__MASK 0x00000001L +-#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0__MASK 0x00000002L +-#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__MASK 0x00000004L +-#define BIF_PERFMON_CNTL__PERF_SEL0__MASK 0x00001F00L +-#define BIF_PERFMON_CNTL__PERF_SEL1__MASK 0x0003E000L +-//BIF_PERFCOUNTER0_RESULT +-#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT__MASK 0xFFFFFFFFL +-//BIF_PERFCOUNTER1_RESULT +-#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT__MASK 0xFFFFFFFFL +-//BIF_MST_TRANS_PENDING_VF +-#define BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__MASK 0x0000FFFFL +-//BIF_SLV_TRANS_PENDING_VF +-#define BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__MASK 0x0000FFFFL +-//BACO_CNTL +-#define BACO_CNTL__BACO_EN__MASK 0x00000001L +-#define BACO_CNTL__BACO_BIF_LCLK_SWITCH__MASK 0x00000002L +-#define BACO_CNTL__BACO_DUMMY_EN__MASK 0x00000004L +-#define BACO_CNTL__BACO_POWER_OFF__MASK 0x00000008L +-#define BACO_CNTL__BACO_DSTATE_BYPASS__MASK 0x00000020L +-#define BACO_CNTL__BACO_RST_INTR_MASK__MASK 0x00000040L +-#define BACO_CNTL__BACO_MODE__MASK 0x00000100L +-#define BACO_CNTL__RCU_BIF_CONFIG_DONE__MASK 0x00000200L +-#define BACO_CNTL__BACO_AUTO_EXIT__MASK 0x80000000L +-//BIF_BACO_EXIT_TIME0 +-#define BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__MASK 0x000FFFFFL +-//BIF_BACO_EXIT_TIMER1 +-#define BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__MASK 0x000FFFFFL +-#define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__MASK 0x04000000L +-#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__MASK 0x08000000L +-#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__MASK 0x10000000L +-#define BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__MASK 0x60000000L +-#define BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__MASK 0x80000000L +-//BIF_BACO_EXIT_TIMER2 +-#define BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__MASK 0x000FFFFFL +-//BIF_BACO_EXIT_TIMER3 +-#define BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__MASK 0x000FFFFFL +-//BIF_BACO_EXIT_TIMER4 +-#define BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__MASK 0x000FFFFFL +-//MEM_TYPE_CNTL +-#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__MASK 0x00000001L +-//SMU_BIF_VDDGFX_PWR_STATUS +-#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__MASK 0x00000001L +-//BIF_VDDGFX_GFX0_LOWER +-#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__MASK 0x0003FFFCL +-#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__MASK 0x40000000L +-#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__MASK 0x80000000L +-//BIF_VDDGFX_GFX0_UPPER +-#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__MASK 0x0003FFFCL +-//BIF_VDDGFX_GFX1_LOWER +-#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__MASK 0x0003FFFCL +-#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__MASK 0x40000000L +-#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__MASK 0x80000000L +-//BIF_VDDGFX_GFX1_UPPER +-#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__MASK 0x0003FFFCL +-//BIF_VDDGFX_GFX2_LOWER +-#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__MASK 0x0003FFFCL +-#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__MASK 0x40000000L +-#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__MASK 0x80000000L +-//BIF_VDDGFX_GFX2_UPPER +-#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__MASK 0x0003FFFCL +-//BIF_VDDGFX_GFX3_LOWER +-#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__MASK 0x0003FFFCL +-#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__MASK 0x40000000L +-#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__MASK 0x80000000L +-//BIF_VDDGFX_GFX3_UPPER +-#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__MASK 0x0003FFFCL +-//BIF_VDDGFX_GFX4_LOWER +-#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__MASK 0x0003FFFCL +-#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__MASK 0x40000000L +-#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__MASK 0x80000000L +-//BIF_VDDGFX_GFX4_UPPER +-#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__MASK 0x0003FFFCL +-//BIF_VDDGFX_GFX5_LOWER +-#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__MASK 0x0003FFFCL +-#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__MASK 0x40000000L +-#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__MASK 0x80000000L +-//BIF_VDDGFX_GFX5_UPPER +-#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__MASK 0x0003FFFCL +-//BIF_VDDGFX_RSV1_LOWER +-#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__MASK 0x0003FFFCL +-#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__MASK 0x40000000L +-#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__MASK 0x80000000L +-//BIF_VDDGFX_RSV1_UPPER +-#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__MASK 0x0003FFFCL +-//BIF_VDDGFX_RSV2_LOWER +-#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__MASK 0x0003FFFCL +-#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__MASK 0x40000000L +-#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__MASK 0x80000000L +-//BIF_VDDGFX_RSV2_UPPER +-#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__MASK 0x0003FFFCL +-//BIF_VDDGFX_RSV3_LOWER +-#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__MASK 0x0003FFFCL +-#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__MASK 0x40000000L +-#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__MASK 0x80000000L +-//BIF_VDDGFX_RSV3_UPPER +-#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__MASK 0x0003FFFCL +-//BIF_VDDGFX_RSV4_LOWER +-#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__MASK 0x0003FFFCL +-#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__MASK 0x40000000L +-#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__MASK 0x80000000L +-//BIF_VDDGFX_RSV4_UPPER +-#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__MASK 0x0003FFFCL +-//BIF_VDDGFX_FB_CMP +-#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__MASK 0x00000001L +-#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__MASK 0x00000002L +-#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__MASK 0x00000004L +-#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__MASK 0x00000008L +-#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__MASK 0x00000010L +-#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__MASK 0x00000020L +-//BIF_DOORBELL_GBLAPER1_LOWER +-#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__MASK 0x00000FFCL +-#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__MASK 0x80000000L +-//BIF_DOORBELL_GBLAPER1_UPPER +-#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__MASK 0x00000FFCL +-//BIF_DOORBELL_GBLAPER2_LOWER +-#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__MASK 0x00000FFCL +-#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__MASK 0x80000000L +-//BIF_DOORBELL_GBLAPER2_UPPER +-#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__MASK 0x00000FFCL +-//REMAP_HDP_MEM_FLUSH_CNTL +-#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__MASK 0x0007FFFCL +-//REMAP_HDP_REG_FLUSH_CNTL +-#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__MASK 0x0007FFFCL +-//BIF_RB_CNTL +-#define BIF_RB_CNTL__RB_ENABLE__MASK 0x00000001L +-#define BIF_RB_CNTL__RB_SIZE__MASK 0x0000003EL +-#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__MASK 0x00000100L +-#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__MASK 0x00003E00L +-#define BIF_RB_CNTL__BIF_RB_TRAN__MASK 0x00020000L +-#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__MASK 0x80000000L +-//BIF_RB_BASE +-#define BIF_RB_BASE__ADDR__MASK 0xFFFFFFFFL +-//BIF_RB_RPTR +-#define BIF_RB_RPTR__OFFSET__MASK 0x0003FFFCL +-//BIF_RB_WPTR +-#define BIF_RB_WPTR__BIF_RB_OVERFLOW__MASK 0x00000001L +-#define BIF_RB_WPTR__OFFSET__MASK 0x0003FFFCL +-//BIF_RB_WPTR_ADDR_HI +-#define BIF_RB_WPTR_ADDR_HI__ADDR__MASK 0x000000FFL +-//BIF_RB_WPTR_ADDR_LO +-#define BIF_RB_WPTR_ADDR_LO__ADDR__MASK 0xFFFFFFFCL +-//MAILBOX_INDEX +-#define MAILBOX_INDEX__MAILBOX_INDEX__MASK 0x0000001FL +-//BIF_GPUIOV_RESET_NOTIFICATION +-#define BIF_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION__MASK 0xFFFFFFFFL +-//BIF_UVD_GPUIOV_CFG_SIZE +-#define BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE__MASK 0x0000000FL +-//BIF_VCE_GPUIOV_CFG_SIZE +-#define BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE__MASK 0x0000000FL +-//BIF_GFX_SDMA_GPUIOV_CFG_SIZE +-#define BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__MASK 0x0000000FL +-//BIF_GMI_WRR_WEIGHT +-#define BIF_GMI_WRR_WEIGHT__GMI_REQ_REALTIME_WEIGHT__MASK 0x000000FFL +-#define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_P_WEIGHT__MASK 0x0000FF00L +-#define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_NP_WEIGHT__MASK 0x00FF0000L +-//NBIF_STRAP_WRITE_CTRL +-#define NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE__MASK 0x00000001L +-//BIF_PERSTB_PAD_CNTL +-#define BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__MASK 0x0000FFFFL +-//BIF_PX_EN_PAD_CNTL +-#define BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__MASK 0x000000FFL +-//BIF_REFPADKIN_PAD_CNTL +-#define BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__MASK 0x000000FFL +-//BIF_CLKREQB_PAD_CNTL +-#define BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__MASK 0x00FFFFFFL +- +- +-// addressBlock: rcc_pf_0_BIFDEC1 +-//RCC_BACO_CNTL_MISC +-#define RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__MASK 0x00000001L +-#define RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__MASK 0x00000002L +-//RCC_RESET_EN +-#define RCC_RESET_EN__DB_APER_RESET_EN__MASK 0x00008000L +-//RCC_VDM_SUPPORT +-#define RCC_VDM_SUPPORT__MCTP_SUPPORT__MASK 0x00000001L +-#define RCC_VDM_SUPPORT__AMPTP_SUPPORT__MASK 0x00000002L +-#define RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__MASK 0x00000004L +-#define RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__MASK 0x00000008L +-#define RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__MASK 0x00000010L +-//RCC_PEER_REG_RANGE0 +-#define RCC_PEER_REG_RANGE0__START_ADDR__MASK 0x0000FFFFL +-#define RCC_PEER_REG_RANGE0__END_ADDR__MASK 0xFFFF0000L +-//RCC_PEER_REG_RANGE1 +-#define RCC_PEER_REG_RANGE1__START_ADDR__MASK 0x0000FFFFL +-#define RCC_PEER_REG_RANGE1__END_ADDR__MASK 0xFFFF0000L +-//RCC_BUS_CNTL +-#define RCC_BUS_CNTL__PMI_IO_DIS__MASK 0x00000004L +-#define RCC_BUS_CNTL__PMI_MEM_DIS__MASK 0x00000008L +-#define RCC_BUS_CNTL__PMI_BM_DIS__MASK 0x00000010L +-#define RCC_BUS_CNTL__PMI_IO_DIS_DN__MASK 0x00000020L +-#define RCC_BUS_CNTL__PMI_MEM_DIS_DN__MASK 0x00000040L +-#define RCC_BUS_CNTL__PMI_IO_DIS_UP__MASK 0x00000080L +-#define RCC_BUS_CNTL__PMI_MEM_DIS_UP__MASK 0x00000100L +-#define RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__MASK 0x00001000L +-#define RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__MASK 0x00002000L +-#define RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__MASK 0x00010000L +-#define RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__MASK 0x00020000L +-#define RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__MASK 0x00040000L +-#define RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__MASK 0x00080000L +-#define RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__MASK 0x00100000L +-#define RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__MASK 0x00200000L +-#define RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__MASK 0x01000000L +-#define RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__MASK 0x0E000000L +-#define RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__MASK 0x10000000L +-#define RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__MASK 0xE0000000L +-//RCC_CONFIG_CNTL +-#define RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__MASK 0x00000001L +-#define RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__MASK 0x00000004L +-#define RCC_CONFIG_CNTL__GRPH_ADRSEL__MASK 0x00000018L +-//RCC_CONFIG_F0_BASE +-#define RCC_CONFIG_F0_BASE__F0_BASE__MASK 0xFFFFFFFFL +-//RCC_CONFIG_APER_SIZE +-#define RCC_CONFIG_APER_SIZE__APER_SIZE__MASK 0xFFFFFFFFL +-//RCC_CONFIG_REG_APER_SIZE +-#define RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__MASK 0x000FFFFFL +-//RCC_XDMA_LO +-#define RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__MASK 0x1FFFFFFFL +-#define RCC_XDMA_LO__BIF_XDMA_APER_EN__MASK 0x80000000L +-//RCC_XDMA_HI +-#define RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__MASK 0x1FFFFFFFL +-//RCC_FEATURES_CONTROL_MISC +-#define RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__MASK 0x00000010L +-#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__MASK 0x00000020L +-#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__MASK 0x00000040L +-#define RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__MASK 0x00000100L +-#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__MASK 0x00000200L +-#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__MASK 0x00000400L +-#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__MASK 0x00000800L +-#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__MASK 0x00001000L +-#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__MASK 0x00002000L +-#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__MASK 0x00004000L +-#define RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__MASK 0x00008000L +-#define RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__MASK 0x00010000L +-#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__MASK 0x00020000L +-#define RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__MASK 0x00040000L +-//RCC_BUSNUM_CNTL1 +-#define RCC_BUSNUM_CNTL1__ID_MASK__MASK 0x000000FFL +-//RCC_BUSNUM_LIST0 +-#define RCC_BUSNUM_LIST0__ID0__MASK 0x000000FFL +-#define RCC_BUSNUM_LIST0__ID1__MASK 0x0000FF00L +-#define RCC_BUSNUM_LIST0__ID2__MASK 0x00FF0000L +-#define RCC_BUSNUM_LIST0__ID3__MASK 0xFF000000L +-//RCC_BUSNUM_LIST1 +-#define RCC_BUSNUM_LIST1__ID4__MASK 0x000000FFL +-#define RCC_BUSNUM_LIST1__ID5__MASK 0x0000FF00L +-#define RCC_BUSNUM_LIST1__ID6__MASK 0x00FF0000L +-#define RCC_BUSNUM_LIST1__ID7__MASK 0xFF000000L +-//RCC_BUSNUM_CNTL2 +-#define RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__MASK 0x000000FFL +-#define RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__MASK 0x00000100L +-#define RCC_BUSNUM_CNTL2__HDPREG_CNTL__MASK 0x00010000L +-#define RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__MASK 0x00020000L +-//RCC_CAPTURE_HOST_BUSNUM +-#define RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__MASK 0x00000001L +-//RCC_HOST_BUSNUM +-#define RCC_HOST_BUSNUM__HOST_ID__MASK 0x0000FFFFL +-//RCC_PEER0_FB_OFFSET_HI +-#define RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__MASK 0x000FFFFFL +-//RCC_PEER0_FB_OFFSET_LO +-#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__MASK 0x000FFFFFL +-#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__MASK 0x80000000L +-//RCC_PEER1_FB_OFFSET_HI +-#define RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__MASK 0x000FFFFFL +-//RCC_PEER1_FB_OFFSET_LO +-#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__MASK 0x000FFFFFL +-#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__MASK 0x80000000L +-//RCC_PEER2_FB_OFFSET_HI +-#define RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__MASK 0x000FFFFFL +-//RCC_PEER2_FB_OFFSET_LO +-#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__MASK 0x000FFFFFL +-#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__MASK 0x80000000L +-//RCC_PEER3_FB_OFFSET_HI +-#define RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__MASK 0x000FFFFFL +-//RCC_PEER3_FB_OFFSET_LO +-#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__MASK 0x000FFFFFL +-#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__MASK 0x80000000L +-//RCC_DEVFUNCNUM_LIST0 +-#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__MASK 0x000000FFL +-#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__MASK 0x0000FF00L +-#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__MASK 0x00FF0000L +-#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__MASK 0xFF000000L +-//RCC_DEVFUNCNUM_LIST1 +-#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__MASK 0x000000FFL +-#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__MASK 0x0000FF00L +-#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__MASK 0x00FF0000L +-#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__MASK 0xFF000000L +-//RCC_DEV0_LINK_CNTL +-#define RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__MASK 0x00000001L +-#define RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__MASK 0x00000100L +-//RCC_CMN_LINK_CNTL +-#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__MASK 0x00000001L +-#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__MASK 0x00000002L +-#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__MASK 0x00000004L +-#define RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__MASK 0x00000008L +-//RCC_EP_REQUESTERID_RESTORE +-#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__MASK 0x000000FFL +-#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__MASK 0x00001F00L +-//RCC_LTR_LSWITCH_CNTL +-#define RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__MASK 0x000003FFL +-//RCC_MH_ARB_CNTL +-#define RCC_MH_ARB_CNTL__MH_ARB_MODE__MASK 0x00000001L +-#define RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__MASK 0x00007FFEL +- +- +-// addressBlock: rcc_pf_0_BIFDEC2 +-//GFXMSIX_VECT0_ADDR_LO +-#define GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL +-//GFXMSIX_VECT0_ADDR_HI +-#define GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL +-//GFXMSIX_VECT0_MSG_DATA +-#define GFXMSIX_VECT0_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL +-//GFXMSIX_VECT0_CONTROL +-#define GFXMSIX_VECT0_CONTROL__MASK_BIT__MASK 0x00000001L +-//GFXMSIX_VECT1_ADDR_LO +-#define GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL +-//GFXMSIX_VECT1_ADDR_HI +-#define GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL +-//GFXMSIX_VECT1_MSG_DATA +-#define GFXMSIX_VECT1_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL +-//GFXMSIX_VECT1_CONTROL +-#define GFXMSIX_VECT1_CONTROL__MASK_BIT__MASK 0x00000001L +-//GFXMSIX_VECT2_ADDR_LO +-#define GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL +-//GFXMSIX_VECT2_ADDR_HI +-#define GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL +-//GFXMSIX_VECT2_MSG_DATA +-#define GFXMSIX_VECT2_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL +-//GFXMSIX_VECT2_CONTROL +-#define GFXMSIX_VECT2_CONTROL__MASK_BIT__MASK 0x00000001L +-//GFXMSIX_PBA +-#define GFXMSIX_PBA__MSIX_PENDING_BITS_0__MASK 0x00000001L +-#define GFXMSIX_PBA__MSIX_PENDING_BITS_1__MASK 0x00000002L +-#define GFXMSIX_PBA__MSIX_PENDING_BITS_2__MASK 0x00000004L +- +- +-// addressBlock: rcc_strap_BIFDEC1 +-//RCC_DEV0_PORT_STRAP0 +-#define RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__MASK 0x00000002L +-#define RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__MASK 0x00000004L +-#define RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__MASK 0x00000008L +-#define RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__MASK 0x00000010L +-#define RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__MASK 0x001FFFE0L +-#define RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__MASK 0x00E00000L +-#define RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__MASK 0x01000000L +-#define RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__MASK 0x0E000000L +-#define RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__MASK 0x70000000L +-#define RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__MASK 0x80000000L +-//RCC_DEV0_PORT_STRAP1 +-#define RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__MASK 0x0000FFFFL +-#define RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__MASK 0xFFFF0000L +-//RCC_DEV0_PORT_STRAP2 +-#define RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__MASK 0x00000001L +-#define RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__MASK 0x00000002L +-#define RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__MASK 0x00000004L +-#define RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__MASK 0x00000008L +-#define RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__MASK 0x00000010L +-#define RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__MASK 0x00000020L +-#define RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__MASK 0x00000040L +-#define RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__MASK 0x00000080L +-#define RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__MASK 0x00000100L +-#define RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__MASK 0x00000E00L +-#define RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__MASK 0x00001000L +-#define RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__MASK 0x00002000L +-#define RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__MASK 0x00004000L +-#define RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__MASK 0x00008000L +-#define RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__MASK 0x00010000L +-#define RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__MASK 0x00060000L +-#define RCC_DEV0_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV0__MASK 0x00080000L +-#define RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__MASK 0x00700000L +-#define RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__MASK 0x03800000L +-#define RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__MASK 0x1C000000L +-#define RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__MASK 0xE0000000L +-//RCC_DEV0_PORT_STRAP3 +-#define RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__MASK 0x00000001L +-#define RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__MASK 0x00000002L +-#define RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__MASK 0x00000004L +-#define RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__MASK 0x00000038L +-#define RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__MASK 0x00000040L +-#define RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__MASK 0x00000080L +-#define RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__MASK 0x00000100L +-#define RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__MASK 0x00000600L +-#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__MASK 0x00003800L +-#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__MASK 0x0003C000L +-#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__MASK 0x001C0000L +-#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__MASK 0x01E00000L +-#define RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__MASK 0x06000000L +-#define RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__MASK 0x18000000L +-#define RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__MASK 0x20000000L +-#define RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0__MASK 0x40000000L +-#define RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__MASK 0x80000000L +-//RCC_DEV0_PORT_STRAP4 +-#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__MASK 0x000000FFL +-#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__MASK 0x0000FF00L +-#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__MASK 0x00FF0000L +-#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__MASK 0xFF000000L +-//RCC_DEV0_PORT_STRAP5 +-#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__MASK 0x000000FFL +-#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__MASK 0x0000FF00L +-#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__MASK 0x00010000L +-#define RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__MASK 0x00020000L +-#define RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__MASK 0x00040000L +-#define RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__MASK 0x00080000L +-#define RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__MASK 0x00100000L +-#define RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__MASK 0x00200000L +-#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__MASK 0x00800000L +-#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__MASK 0x01000000L +-#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__MASK 0x02000000L +-#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__MASK 0x04000000L +-#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__MASK 0x08000000L +-#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__MASK 0x10000000L +-#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__MASK 0x20000000L +-#define RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__MASK 0x40000000L +-#define RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__MASK 0x80000000L +-//RCC_DEV0_PORT_STRAP6 +-#define RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__MASK 0x00000001L +-#define RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__MASK 0x00000002L +-//RCC_DEV0_PORT_STRAP7 +-#define RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__MASK 0x000000FFL +-#define RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__MASK 0x00000F00L +-#define RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__MASK 0x0000F000L +-#define RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__MASK 0x00FF0000L +-#define RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__MASK 0x1F000000L +-#define RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__MASK 0xE0000000L +-//RCC_DEV0_EPF0_STRAP0 +-#define RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__MASK 0x0000FFFFL +-#define RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__MASK 0x000F0000L +-#define RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__MASK 0x00F00000L +-#define RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__MASK 0x0F000000L +-#define RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__MASK 0x10000000L +-#define RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__MASK 0x20000000L +-#define RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__MASK 0x40000000L +-#define RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__MASK 0x80000000L +-//RCC_DEV0_EPF0_STRAP1 +-#define RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__MASK 0x0000FFFFL +-#define RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__MASK 0xFFFF0000L +-//RCC_DEV0_EPF0_STRAP13 +-#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__MASK 0x000000FFL +-#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__MASK 0x0000FF00L +-#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__MASK 0x00FF0000L +-//RCC_DEV0_EPF0_STRAP2 +-#define RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__MASK 0x00000001L +-#define RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__MASK 0x0000003EL +-#define RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__MASK 0x00000040L +-#define RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__MASK 0x00000080L +-#define RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__MASK 0x00000100L +-#define RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__MASK 0x00003E00L +-#define RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__MASK 0x00004000L +-#define RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__MASK 0x00008000L +-#define RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__MASK 0x00010000L +-#define RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__MASK 0x00020000L +-#define RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__MASK 0x00040000L +-#define RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__MASK 0x00100000L +-#define RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__MASK 0x00200000L +-#define RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__MASK 0x00400000L +-#define RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__MASK 0x00800000L +-#define RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__MASK 0x07000000L +-#define RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__MASK 0x08000000L +-#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__MASK 0x10000000L +-#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__MASK 0x20000000L +-#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__MASK 0x40000000L +-#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__MASK 0x80000000L +-//RCC_DEV0_EPF0_STRAP3 +-#define RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__MASK 0x00000001L +-#define RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__MASK 0x00000002L +-#define RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__MASK 0x0003FFFCL +-#define RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__MASK 0x00040000L +-#define RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__MASK 0x00080000L +-#define RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__MASK 0x00100000L +-#define RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__MASK 0x00E00000L +-#define RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__MASK 0x01000000L +-#define RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0__MASK 0x02000000L +-#define RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__MASK 0x04000000L +-#define RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__MASK 0x08000000L +-//RCC_DEV0_EPF0_STRAP4 +-#define RCC_DEV0_EPF0_STRAP4__STRAP_MSIX_TABLE_OFFSET_DEV0_F0__MASK 0x000FFFFFL +-#define RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__MASK 0x00100000L +-#define RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__MASK 0x00200000L +-#define RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__MASK 0x00400000L +-#define RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__MASK 0x0F800000L +-#define RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__MASK 0x70000000L +-#define RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__MASK 0x80000000L +-//RCC_DEV0_EPF0_STRAP5 +-#define RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__MASK 0x0000FFFFL +-//RCC_DEV0_EPF0_STRAP8 +-#define RCC_DEV0_EPF0_STRAP8__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__MASK 0x00000001L +-#define RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__MASK 0x00000006L +-#define RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__MASK 0x00000008L +-#define RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0__MASK 0x00000010L +-#define RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__MASK 0x00000060L +-#define RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__MASK 0x00000080L +-#define RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__MASK 0x00000100L +-#define RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__MASK 0x00000E00L +-#define RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__MASK 0x00003000L +-#define RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__MASK 0x0000C000L +-#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__MASK 0x00070000L +-#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__MASK 0x00380000L +-#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__MASK 0x00C00000L +-#define RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__MASK 0x01000000L +-#define RCC_DEV0_EPF0_STRAP8__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__MASK 0x02000000L +-#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_PROT_DIS_DEV0_F0__MASK 0x04000000L +-#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__MASK 0x38000000L +-#define RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__MASK 0xC0000000L +-//RCC_DEV0_EPF0_STRAP9 +-//RCC_DEV0_EPF1_STRAP0 +-#define RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__MASK 0x0000FFFFL +-#define RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__MASK 0x000F0000L +-#define RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__MASK 0x00F00000L +-#define RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__MASK 0x10000000L +-#define RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__MASK 0x20000000L +-#define RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__MASK 0x40000000L +-#define RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__MASK 0x80000000L +-//RCC_DEV0_EPF1_STRAP10 +-#define RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1__MASK 0x00000001L +-#define RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1__MASK 0x001FFFFEL +-//RCC_DEV0_EPF1_STRAP11 +-#define RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1__MASK 0x00000001L +-#define RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1__MASK 0x001FFFFEL +-//RCC_DEV0_EPF1_STRAP12 +-#define RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1__MASK 0x00000001L +-#define RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1__MASK 0x001FFFFEL +-//RCC_DEV0_EPF1_STRAP13 +-#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__MASK 0x000000FFL +-#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__MASK 0x0000FF00L +-#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__MASK 0x00FF0000L +-//RCC_DEV0_EPF1_STRAP2 +-#define RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__MASK 0x00000080L +-#define RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__MASK 0x00000100L +-#define RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__MASK 0x00004000L +-#define RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__MASK 0x00010000L +-#define RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__MASK 0x00020000L +-#define RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__MASK 0x00040000L +-#define RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__MASK 0x00100000L +-#define RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__MASK 0x00200000L +-#define RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__MASK 0x00400000L +-#define RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__MASK 0x00800000L +-#define RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__MASK 0x07000000L +-//RCC_DEV0_EPF1_STRAP3 +-#define RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__MASK 0x00000001L +-#define RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__MASK 0x00000002L +-#define RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__MASK 0x0003FFFCL +-#define RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__MASK 0x00040000L +-#define RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__MASK 0x00080000L +-#define RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__MASK 0x00100000L +-#define RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__MASK 0x01000000L +-#define RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1__MASK 0x02000000L +-#define RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__MASK 0x04000000L +-#define RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__MASK 0x08000000L +-//RCC_DEV0_EPF1_STRAP4 +-#define RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__MASK 0x00100000L +-#define RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__MASK 0x00200000L +-#define RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__MASK 0x00400000L +-#define RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__MASK 0x0F800000L +-#define RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__MASK 0x70000000L +-#define RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__MASK 0x80000000L +-//RCC_DEV0_EPF1_STRAP5 +-#define RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__MASK 0x0000FFFFL +-//RCC_DEV0_EPF1_STRAP6 +-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__MASK 0x00000001L +-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__MASK 0x00000002L +-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__MASK 0x00000004L +-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1__MASK 0x00000070L +-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__MASK 0x00000100L +-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__MASK 0x00000200L +-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__MASK 0x00010000L +-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__MASK 0x00020000L +-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__MASK 0x01000000L +-#define RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__MASK 0x02000000L +-//RCC_DEV0_EPF1_STRAP7 +-#define RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1__MASK 0x00000001L +-#define RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1__MASK 0x0000001EL +- +- +-// addressBlock: bif_bx_pf_BIFPFVFDEC1 +-//BIF_BME_STATUS +-#define BIF_BME_STATUS__DMA_ON_BME_LOW__MASK 0x00000001L +-#define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__MASK 0x00010000L +-//BIF_ATOMIC_ERR_LOG +-#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__MASK 0x00000001L +-#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__MASK 0x00000002L +-#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__MASK 0x00010000L +-#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__MASK 0x00020000L +-//DOORBELL_SELFRING_GPA_APER_BASE_HIGH +-#define DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__MASK 0xFFFFFFFFL +-//DOORBELL_SELFRING_GPA_APER_BASE_LOW +-#define DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__MASK 0xFFFFFFFFL +-//DOORBELL_SELFRING_GPA_APER_CNTL +-#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__MASK 0x00000001L +-#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__MASK 0x0000FF00L +-//HDP_REG_COHERENCY_FLUSH_CNTL +-#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__MASK 0x00000001L +-//HDP_MEM_COHERENCY_FLUSH_CNTL +-#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__MASK 0x00000001L +-//GPU_HDP_FLUSH_REQ +-#define GPU_HDP_FLUSH_REQ__CP0__MASK 0x00000001L +-#define GPU_HDP_FLUSH_REQ__CP1__MASK 0x00000002L +-#define GPU_HDP_FLUSH_REQ__CP2__MASK 0x00000004L +-#define GPU_HDP_FLUSH_REQ__CP3__MASK 0x00000008L +-#define GPU_HDP_FLUSH_REQ__CP4__MASK 0x00000010L +-#define GPU_HDP_FLUSH_REQ__CP5__MASK 0x00000020L +-#define GPU_HDP_FLUSH_REQ__CP6__MASK 0x00000040L +-#define GPU_HDP_FLUSH_REQ__CP7__MASK 0x00000080L +-#define GPU_HDP_FLUSH_REQ__CP8__MASK 0x00000100L +-#define GPU_HDP_FLUSH_REQ__CP9__MASK 0x00000200L +-#define GPU_HDP_FLUSH_REQ__SDMA0__MASK 0x00000400L +-#define GPU_HDP_FLUSH_REQ__SDMA1__MASK 0x00000800L +-//GPU_HDP_FLUSH_DONE +-#define GPU_HDP_FLUSH_DONE__CP0__MASK 0x00000001L +-#define GPU_HDP_FLUSH_DONE__CP1__MASK 0x00000002L +-#define GPU_HDP_FLUSH_DONE__CP2__MASK 0x00000004L +-#define GPU_HDP_FLUSH_DONE__CP3__MASK 0x00000008L +-#define GPU_HDP_FLUSH_DONE__CP4__MASK 0x00000010L +-#define GPU_HDP_FLUSH_DONE__CP5__MASK 0x00000020L +-#define GPU_HDP_FLUSH_DONE__CP6__MASK 0x00000040L +-#define GPU_HDP_FLUSH_DONE__CP7__MASK 0x00000080L +-#define GPU_HDP_FLUSH_DONE__CP8__MASK 0x00000100L +-#define GPU_HDP_FLUSH_DONE__CP9__MASK 0x00000200L +-#define GPU_HDP_FLUSH_DONE__SDMA0__MASK 0x00000400L +-#define GPU_HDP_FLUSH_DONE__SDMA1__MASK 0x00000800L +-//BIF_TRANS_PENDING +-#define BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__MASK 0x00000001L +-#define BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__MASK 0x00000002L +-//MAILBOX_MSGBUF_TRN_DW0 +-#define MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__MASK 0xFFFFFFFFL +-//MAILBOX_MSGBUF_TRN_DW1 +-#define MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__MASK 0xFFFFFFFFL +-//MAILBOX_MSGBUF_TRN_DW2 +-#define MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__MASK 0xFFFFFFFFL +-//MAILBOX_MSGBUF_TRN_DW3 +-#define MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__MASK 0xFFFFFFFFL +-//MAILBOX_MSGBUF_RCV_DW0 +-#define MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__MASK 0xFFFFFFFFL +-//MAILBOX_MSGBUF_RCV_DW1 +-#define MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__MASK 0xFFFFFFFFL +-//MAILBOX_MSGBUF_RCV_DW2 +-#define MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__MASK 0xFFFFFFFFL +-//MAILBOX_MSGBUF_RCV_DW3 +-#define MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__MASK 0xFFFFFFFFL +-//MAILBOX_CONTROL +-#define MAILBOX_CONTROL__TRN_MSG_VALID__MASK 0x00000001L +-#define MAILBOX_CONTROL__TRN_MSG_ACK__MASK 0x00000002L +-#define MAILBOX_CONTROL__RCV_MSG_VALID__MASK 0x00000100L +-#define MAILBOX_CONTROL__RCV_MSG_ACK__MASK 0x00000200L +-//MAILBOX_INT_CNTL +-#define MAILBOX_INT_CNTL__VALID_INT_EN__MASK 0x00000001L +-#define MAILBOX_INT_CNTL__ACK_INT_EN__MASK 0x00000002L +-//BIF_VMHV_MAILBOX +-#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__MASK 0x00000001L +-#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__MASK 0x00000002L +-#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__MASK 0x00000F00L +-#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__MASK 0x00008000L +-#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__MASK 0x000F0000L +-#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__MASK 0x00800000L +-#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__MASK 0x01000000L +-#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__MASK 0x02000000L +- +- +-// addressBlock: rcc_pf_0_BIFPFVFDEC1 +-//RCC_DOORBELL_APER_EN +-#define RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__MASK 0x00000001L +-//RCC_CONFIG_MEMSIZE +-#define RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__MASK 0xFFFFFFFFL +-//RCC_CONFIG_RESERVED +-#define RCC_CONFIG_RESERVED__CONFIG_RESERVED__MASK 0xFFFFFFFFL +-//RCC_IOV_FUNC_IDENTIFIER +-#define RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__MASK 0x00000001L +-#define RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__MASK 0x80000000L +- +- +-// addressBlock: syshub_mmreg_ind_syshubdec +-//SYSHUB_INDEX +-#define SYSHUB_INDEX__INDEX__MASK 0xFFFFFFFFL +-//SYSHUB_DATA +-#define SYSHUB_DATA__DATA__MASK 0xFFFFFFFFL +- +- +-// addressBlock: rcc_strap_rcc_strap_internal +-//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__MASK 0x00000002L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__MASK 0x00000004L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__MASK 0x00000008L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__MASK 0x00000010L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__MASK 0x001FFFE0L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__MASK 0x00E00000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__MASK 0x01000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__MASK 0x0E000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__MASK 0x70000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__MASK 0x80000000L +-//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__MASK 0x0000FFFFL +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__MASK 0xFFFF0000L +-//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__MASK 0x00000001L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__MASK 0x00000002L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__MASK 0x00000004L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__MASK 0x00000008L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__MASK 0x00000010L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__MASK 0x00000020L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__MASK 0x00000040L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__MASK 0x00000080L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__MASK 0x00000100L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__MASK 0x00000E00L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__MASK 0x00001000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__MASK 0x00002000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__MASK 0x00004000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__MASK 0x00008000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__MASK 0x00010000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__MASK 0x00060000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV0__MASK 0x00080000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__MASK 0x00700000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__MASK 0x03800000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__MASK 0x1C000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__MASK 0xE0000000L +-//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__MASK 0x00000001L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__MASK 0x00000002L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__MASK 0x00000004L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__MASK 0x00000038L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__MASK 0x00000040L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__MASK 0x00000080L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__MASK 0x00000100L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__MASK 0x00000600L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__MASK 0x00003800L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__MASK 0x0003C000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__MASK 0x001C0000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__MASK 0x01E00000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__MASK 0x06000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__MASK 0x18000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__MASK 0x20000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0__MASK 0x40000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__MASK 0x80000000L +-//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__MASK 0x000000FFL +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__MASK 0x0000FF00L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__MASK 0x00FF0000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__MASK 0xFF000000L +-//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__MASK 0x000000FFL +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__MASK 0x0000FF00L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__MASK 0x00010000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__MASK 0x00020000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__MASK 0x00040000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__MASK 0x00080000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__MASK 0x00100000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__MASK 0x00200000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__MASK 0x00800000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__MASK 0x01000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__MASK 0x02000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__MASK 0x04000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__MASK 0x08000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__MASK 0x10000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__MASK 0x20000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__MASK 0x40000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__MASK 0x80000000L +-//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__MASK 0x00000001L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__MASK 0x00000002L +-//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__MASK 0x000000FFL +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__MASK 0x00000F00L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__MASK 0x0000F000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__MASK 0x00FF0000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__MASK 0x1F000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__MASK 0xE0000000L +-//RCC_DEV1_PORT_STRAP0 +-#define RCC_DEV1_PORT_STRAP0__STRAP_ARI_EN_DN_DEV1__MASK 0x00000002L +-#define RCC_DEV1_PORT_STRAP0__STRAP_ACS_EN_DN_DEV1__MASK 0x00000004L +-#define RCC_DEV1_PORT_STRAP0__STRAP_AER_EN_DN_DEV1__MASK 0x00000008L +-#define RCC_DEV1_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV1__MASK 0x00000010L +-#define RCC_DEV1_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV1__MASK 0x001FFFE0L +-#define RCC_DEV1_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV1__MASK 0x00E00000L +-#define RCC_DEV1_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV1__MASK 0x01000000L +-#define RCC_DEV1_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV1__MASK 0x0E000000L +-#define RCC_DEV1_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV1__MASK 0x70000000L +-#define RCC_DEV1_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV1__MASK 0x80000000L +-//RCC_DEV1_PORT_STRAP1 +-#define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV1__MASK 0x0000FFFFL +-#define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV1__MASK 0xFFFF0000L +-//RCC_DEV1_PORT_STRAP2 +-#define RCC_DEV1_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV1__MASK 0x00000001L +-#define RCC_DEV1_PORT_STRAP2__STRAP_DSN_EN_DN_DEV1__MASK 0x00000002L +-#define RCC_DEV1_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV1__MASK 0x00000004L +-#define RCC_DEV1_PORT_STRAP2__STRAP_ECN1P1_EN_DEV1__MASK 0x00000008L +-#define RCC_DEV1_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV1__MASK 0x00000010L +-#define RCC_DEV1_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV1__MASK 0x00000020L +-#define RCC_DEV1_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV1__MASK 0x00000040L +-#define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV1__MASK 0x00000080L +-#define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV1__MASK 0x00000100L +-#define RCC_DEV1_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV1__MASK 0x00000E00L +-#define RCC_DEV1_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV1__MASK 0x00001000L +-#define RCC_DEV1_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV1__MASK 0x00002000L +-#define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV1__MASK 0x00004000L +-#define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_EN_DEV1__MASK 0x00008000L +-#define RCC_DEV1_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV1__MASK 0x00010000L +-#define RCC_DEV1_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV1__MASK 0x00060000L +-#define RCC_DEV1_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV1__MASK 0x00080000L +-#define RCC_DEV1_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV1__MASK 0x00700000L +-#define RCC_DEV1_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV1__MASK 0x03800000L +-#define RCC_DEV1_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV1__MASK 0x1C000000L +-#define RCC_DEV1_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV1__MASK 0xE0000000L +-//RCC_DEV1_PORT_STRAP3 +-#define RCC_DEV1_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV1__MASK 0x00000001L +-#define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DEV1__MASK 0x00000002L +-#define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DN_DEV1__MASK 0x00000004L +-#define RCC_DEV1_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV1__MASK 0x00000038L +-#define RCC_DEV1_PORT_STRAP3__STRAP_MSI_EN_DN_DEV1__MASK 0x00000040L +-#define RCC_DEV1_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV1__MASK 0x00000080L +-#define RCC_DEV1_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV1__MASK 0x00000100L +-#define RCC_DEV1_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV1__MASK 0x00000600L +-#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV1__MASK 0x00003800L +-#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV1__MASK 0x0003C000L +-#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV1__MASK 0x001C0000L +-#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV1__MASK 0x01E00000L +-#define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DEV1__MASK 0x06000000L +-#define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV1__MASK 0x18000000L +-#define RCC_DEV1_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV1__MASK 0x20000000L +-#define RCC_DEV1_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV1__MASK 0x40000000L +-#define RCC_DEV1_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV1__MASK 0x80000000L +-//RCC_DEV1_PORT_STRAP4 +-#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV1__MASK 0x000000FFL +-#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV1__MASK 0x0000FF00L +-#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV1__MASK 0x00FF0000L +-#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV1__MASK 0xFF000000L +-//RCC_DEV1_PORT_STRAP5 +-#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV1__MASK 0x000000FFL +-#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV1__MASK 0x0000FF00L +-#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV1__MASK 0x00010000L +-#define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV1__MASK 0x00020000L +-#define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV1__MASK 0x00040000L +-#define RCC_DEV1_PORT_STRAP5__STRAP_VC_EN_DN_DEV1__MASK 0x00080000L +-#define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DEV1__MASK 0x00100000L +-#define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV1__MASK 0x00200000L +-#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV1__MASK 0x00800000L +-#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV1__MASK 0x01000000L +-#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV1__MASK 0x02000000L +-#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV1__MASK 0x04000000L +-#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV1__MASK 0x08000000L +-#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV1__MASK 0x10000000L +-#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV1__MASK 0x20000000L +-#define RCC_DEV1_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV1__MASK 0x40000000L +-#define RCC_DEV1_PORT_STRAP5__STRAP_SSID_EN_DEV1__MASK 0x80000000L +-//RCC_DEV1_PORT_STRAP6 +-#define RCC_DEV1_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV1__MASK 0x00000001L +-#define RCC_DEV1_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV1__MASK 0x00000002L +-//RCC_DEV1_PORT_STRAP7 +-#define RCC_DEV1_PORT_STRAP7__STRAP_PORT_NUMBER_DEV1__MASK 0x000000FFL +-#define RCC_DEV1_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV1__MASK 0x00000F00L +-#define RCC_DEV1_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV1__MASK 0x0000F000L +-#define RCC_DEV1_PORT_STRAP7__STRAP_RP_BUSNUM_DEV1__MASK 0x00FF0000L +-#define RCC_DEV1_PORT_STRAP7__STRAP_DN_DEVNUM_DEV1__MASK 0x1F000000L +-#define RCC_DEV1_PORT_STRAP7__STRAP_DN_FUNCID_DEV1__MASK 0xE0000000L +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__MASK 0x0000FFFFL +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__MASK 0x000F0000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__MASK 0x00F00000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__MASK 0x0F000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__MASK 0x10000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__MASK 0x20000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__MASK 0x40000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__MASK 0x80000000L +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__MASK 0x0000FFFFL +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__MASK 0xFFFF0000L +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__MASK 0x00000001L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__MASK 0x0000003EL +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__MASK 0x00000040L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__MASK 0x00000080L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__MASK 0x00000100L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__MASK 0x00003E00L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__MASK 0x00004000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__MASK 0x00008000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__MASK 0x00010000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__MASK 0x00020000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__MASK 0x00040000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__MASK 0x00100000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__MASK 0x00200000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__MASK 0x00400000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__MASK 0x00800000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__MASK 0x07000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__MASK 0x08000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__MASK 0x10000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__MASK 0x20000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__MASK 0x40000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__MASK 0x80000000L +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__MASK 0x00000001L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__MASK 0x00000002L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__MASK 0x0003FFFCL +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__MASK 0x00040000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__MASK 0x00080000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__MASK 0x00100000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__MASK 0x00E00000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__MASK 0x01000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0__MASK 0x02000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__MASK 0x04000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__MASK 0x08000000L +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_MSIX_TABLE_OFFSET_DEV0_F0__MASK 0x000FFFFFL +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__MASK 0x00100000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__MASK 0x00200000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__MASK 0x00400000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__MASK 0x0F800000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__MASK 0x70000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__MASK 0x80000000L +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__MASK 0x0000FFFFL +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__MASK 0x00000001L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__MASK 0x00000006L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__MASK 0x00000008L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0__MASK 0x00000010L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__MASK 0x00000060L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__MASK 0x00000080L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__MASK 0x00000100L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__MASK 0x00000E00L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__MASK 0x00003000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__MASK 0x0000C000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__MASK 0x00070000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__MASK 0x00380000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__MASK 0x00C00000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__MASK 0x01000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__MASK 0x02000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_PROT_DIS_DEV0_F0__MASK 0x04000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__MASK 0x38000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__MASK 0xC0000000L +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP9 +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__MASK 0x000000FFL +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__MASK 0x0000FF00L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__MASK 0x00FF0000L +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__MASK 0x0000FFFFL +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__MASK 0x000F0000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__MASK 0x00F00000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__MASK 0x10000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__MASK 0x20000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__MASK 0x40000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__MASK 0x80000000L +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__MASK 0x00000080L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__MASK 0x00000100L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__MASK 0x00004000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__MASK 0x00010000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__MASK 0x00020000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__MASK 0x00040000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__MASK 0x00100000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__MASK 0x00200000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__MASK 0x00400000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__MASK 0x00800000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__MASK 0x07000000L +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__MASK 0x00000001L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__MASK 0x00000002L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__MASK 0x0003FFFCL +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__MASK 0x00040000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__MASK 0x00080000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__MASK 0x00100000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__MASK 0x01000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1__MASK 0x02000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__MASK 0x04000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__MASK 0x08000000L +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__MASK 0x00100000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__MASK 0x00200000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__MASK 0x00400000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__MASK 0x0F800000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__MASK 0x70000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__MASK 0x80000000L +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__MASK 0x0000FFFFL +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__MASK 0x00000001L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__MASK 0x00000002L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__MASK 0x00000004L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1__MASK 0x00000070L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__MASK 0x00000100L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__MASK 0x00000200L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__MASK 0x00010000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__MASK 0x00020000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__MASK 0x01000000L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__MASK 0x02000000L +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1__MASK 0x00000001L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1__MASK 0x0000001EL +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1__MASK 0x00000001L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1__MASK 0x001FFFFEL +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1__MASK 0x00000001L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1__MASK 0x001FFFFEL +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1__MASK 0x00000001L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1__MASK 0x001FFFFEL +-//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13 +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__MASK 0x000000FFL +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__MASK 0x0000FF00L +-#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__MASK 0x00FF0000L +-//RCC_DEV0_EPF2_STRAP0 +-#define RCC_DEV0_EPF2_STRAP0__STRAP_DEVICE_ID_DEV0_F2__MASK 0x0000FFFFL +-#define RCC_DEV0_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F2__MASK 0x000F0000L +-#define RCC_DEV0_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV0_F2__MASK 0x00F00000L +-#define RCC_DEV0_EPF2_STRAP0__STRAP_FUNC_EN_DEV0_F2__MASK 0x10000000L +-#define RCC_DEV0_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F2__MASK 0x20000000L +-#define RCC_DEV0_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV0_F2__MASK 0x40000000L +-#define RCC_DEV0_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV0_F2__MASK 0x80000000L +-//RCC_DEV0_EPF2_STRAP2 +-#define RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2__MASK 0x00000080L +-#define RCC_DEV0_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F2__MASK 0x00000100L +-#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2__MASK 0x00004000L +-#define RCC_DEV0_EPF2_STRAP2__STRAP_AER_EN_DEV0_F2__MASK 0x00010000L +-#define RCC_DEV0_EPF2_STRAP2__STRAP_ACS_EN_DEV0_F2__MASK 0x00020000L +-#define RCC_DEV0_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F2__MASK 0x00100000L +-#define RCC_DEV0_EPF2_STRAP2__STRAP_DPA_EN_DEV0_F2__MASK 0x00200000L +-#define RCC_DEV0_EPF2_STRAP2__STRAP_VC_EN_DEV0_F2__MASK 0x00800000L +-#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F2__MASK 0x07000000L +-//RCC_DEV0_EPF2_STRAP3 +-#define RCC_DEV0_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F2__MASK 0x00000001L +-#define RCC_DEV0_EPF2_STRAP3__STRAP_PWR_EN_DEV0_F2__MASK 0x00000002L +-#define RCC_DEV0_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV0_F2__MASK 0x0003FFFCL +-#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_EN_DEV0_F2__MASK 0x00040000L +-#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F2__MASK 0x00080000L +-#define RCC_DEV0_EPF2_STRAP3__STRAP_MSIX_EN_DEV0_F2__MASK 0x00100000L +-#define RCC_DEV0_EPF2_STRAP3__STRAP_PMC_DSI_DEV0_F2__MASK 0x01000000L +-#define RCC_DEV0_EPF2_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F2__MASK 0x02000000L +-#define RCC_DEV0_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F2__MASK 0x04000000L +-#define RCC_DEV0_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F2__MASK 0x08000000L +-//RCC_DEV0_EPF2_STRAP4 +-#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F2__MASK 0x00100000L +-#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV0_F2__MASK 0x00200000L +-#define RCC_DEV0_EPF2_STRAP4__STRAP_FLR_EN_DEV0_F2__MASK 0x00400000L +-#define RCC_DEV0_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV0_F2__MASK 0x0F800000L +-#define RCC_DEV0_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F2__MASK 0x70000000L +-#define RCC_DEV0_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F2__MASK 0x80000000L +-//RCC_DEV0_EPF2_STRAP5 +-#define RCC_DEV0_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F2__MASK 0x0000FFFFL +-#define RCC_DEV0_EPF2_STRAP5__STRAP_SATAIDP_EN_DEV0_F2__MASK 0x01000000L +-//RCC_DEV0_EPF2_STRAP6 +-#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_EN_DEV0_F2__MASK 0x00000001L +-#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F2__MASK 0x00000002L +-#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F2__MASK 0x00000070L +-#define RCC_DEV0_EPF2_STRAP6__STRAP_APER1_EN_DEV0_F2__MASK 0x00000100L +-#define RCC_DEV0_EPF2_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F2__MASK 0x00000200L +-//RCC_DEV0_EPF2_STRAP13 +-#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F2__MASK 0x000000FFL +-#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F2__MASK 0x0000FF00L +-#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F2__MASK 0x00FF0000L +-//RCC_DEV0_EPF3_STRAP0 +-#define RCC_DEV0_EPF3_STRAP0__STRAP_DEVICE_ID_DEV0_F3__MASK 0x0000FFFFL +-#define RCC_DEV0_EPF3_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F3__MASK 0x000F0000L +-#define RCC_DEV0_EPF3_STRAP0__STRAP_MINOR_REV_ID_DEV0_F3__MASK 0x00F00000L +-#define RCC_DEV0_EPF3_STRAP0__STRAP_FUNC_EN_DEV0_F3__MASK 0x10000000L +-#define RCC_DEV0_EPF3_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F3__MASK 0x20000000L +-#define RCC_DEV0_EPF3_STRAP0__STRAP_D1_SUPPORT_DEV0_F3__MASK 0x40000000L +-#define RCC_DEV0_EPF3_STRAP0__STRAP_D2_SUPPORT_DEV0_F3__MASK 0x80000000L +-//RCC_DEV0_EPF3_STRAP2 +-#define RCC_DEV0_EPF3_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F3__MASK 0x00000080L +-#define RCC_DEV0_EPF3_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F3__MASK 0x00000100L +-#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F3__MASK 0x00004000L +-#define RCC_DEV0_EPF3_STRAP2__STRAP_AER_EN_DEV0_F3__MASK 0x00010000L +-#define RCC_DEV0_EPF3_STRAP2__STRAP_ACS_EN_DEV0_F3__MASK 0x00020000L +-#define RCC_DEV0_EPF3_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F3__MASK 0x00100000L +-#define RCC_DEV0_EPF3_STRAP2__STRAP_DPA_EN_DEV0_F3__MASK 0x00200000L +-#define RCC_DEV0_EPF3_STRAP2__STRAP_VC_EN_DEV0_F3__MASK 0x00800000L +-#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F3__MASK 0x07000000L +-//RCC_DEV0_EPF3_STRAP3 +-#define RCC_DEV0_EPF3_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F3__MASK 0x00000001L +-#define RCC_DEV0_EPF3_STRAP3__STRAP_PWR_EN_DEV0_F3__MASK 0x00000002L +-#define RCC_DEV0_EPF3_STRAP3__STRAP_SUBSYS_ID_DEV0_F3__MASK 0x0003FFFCL +-#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_EN_DEV0_F3__MASK 0x00040000L +-#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F3__MASK 0x00080000L +-#define RCC_DEV0_EPF3_STRAP3__STRAP_MSIX_EN_DEV0_F3__MASK 0x00100000L +-#define RCC_DEV0_EPF3_STRAP3__STRAP_PMC_DSI_DEV0_F3__MASK 0x01000000L +-#define RCC_DEV0_EPF3_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F3__MASK 0x02000000L +-#define RCC_DEV0_EPF3_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F3__MASK 0x04000000L +-#define RCC_DEV0_EPF3_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F3__MASK 0x08000000L +-//RCC_DEV0_EPF3_STRAP4 +-#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F3__MASK 0x00100000L +-#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_EN_DEV0_F3__MASK 0x00200000L +-#define RCC_DEV0_EPF3_STRAP4__STRAP_FLR_EN_DEV0_F3__MASK 0x00400000L +-#define RCC_DEV0_EPF3_STRAP4__STRAP_PME_SUPPORT_DEV0_F3__MASK 0x0F800000L +-#define RCC_DEV0_EPF3_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F3__MASK 0x70000000L +-#define RCC_DEV0_EPF3_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F3__MASK 0x80000000L +-//RCC_DEV0_EPF3_STRAP5 +-#define RCC_DEV0_EPF3_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F3__MASK 0x0000FFFFL +-#define RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESEL_DEV0_F3__MASK 0x000F0000L +-#define RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESELD_DEV0_F3__MASK 0x00F00000L +-//RCC_DEV0_EPF3_STRAP6 +-#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_EN_DEV0_F3__MASK 0x00000001L +-#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F3__MASK 0x00000002L +-#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F3__MASK 0x00000070L +-//RCC_DEV0_EPF3_STRAP13 +-#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F3__MASK 0x000000FFL +-#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F3__MASK 0x0000FF00L +-#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F3__MASK 0x00FF0000L +-//RCC_DEV0_EPF4_STRAP0 +-#define RCC_DEV0_EPF4_STRAP0__STRAP_DEVICE_ID_DEV0_F4__MASK 0x0000FFFFL +-#define RCC_DEV0_EPF4_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F4__MASK 0x000F0000L +-#define RCC_DEV0_EPF4_STRAP0__STRAP_MINOR_REV_ID_DEV0_F4__MASK 0x00F00000L +-#define RCC_DEV0_EPF4_STRAP0__STRAP_FUNC_EN_DEV0_F4__MASK 0x10000000L +-#define RCC_DEV0_EPF4_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F4__MASK 0x20000000L +-#define RCC_DEV0_EPF4_STRAP0__STRAP_D1_SUPPORT_DEV0_F4__MASK 0x40000000L +-#define RCC_DEV0_EPF4_STRAP0__STRAP_D2_SUPPORT_DEV0_F4__MASK 0x80000000L +-//RCC_DEV0_EPF4_STRAP2 +-#define RCC_DEV0_EPF4_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F4__MASK 0x00000080L +-#define RCC_DEV0_EPF4_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F4__MASK 0x00000100L +-#define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F4__MASK 0x00004000L +-#define RCC_DEV0_EPF4_STRAP2__STRAP_AER_EN_DEV0_F4__MASK 0x00010000L +-#define RCC_DEV0_EPF4_STRAP2__STRAP_ACS_EN_DEV0_F4__MASK 0x00020000L +-#define RCC_DEV0_EPF4_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F4__MASK 0x00100000L +-#define RCC_DEV0_EPF4_STRAP2__STRAP_DPA_EN_DEV0_F4__MASK 0x00200000L +-#define RCC_DEV0_EPF4_STRAP2__STRAP_VC_EN_DEV0_F4__MASK 0x00800000L +-#define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F4__MASK 0x07000000L +-//RCC_DEV0_EPF4_STRAP3 +-#define RCC_DEV0_EPF4_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F4__MASK 0x00000001L +-#define RCC_DEV0_EPF4_STRAP3__STRAP_PWR_EN_DEV0_F4__MASK 0x00000002L +-#define RCC_DEV0_EPF4_STRAP3__STRAP_SUBSYS_ID_DEV0_F4__MASK 0x0003FFFCL +-#define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_EN_DEV0_F4__MASK 0x00040000L +-#define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F4__MASK 0x00080000L +-#define RCC_DEV0_EPF4_STRAP3__STRAP_MSIX_EN_DEV0_F4__MASK 0x00100000L +-#define RCC_DEV0_EPF4_STRAP3__STRAP_PMC_DSI_DEV0_F4__MASK 0x01000000L +-#define RCC_DEV0_EPF4_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F4__MASK 0x02000000L +-#define RCC_DEV0_EPF4_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F4__MASK 0x04000000L +-#define RCC_DEV0_EPF4_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F4__MASK 0x08000000L +-//RCC_DEV0_EPF4_STRAP4 +-#define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F4__MASK 0x00100000L +-#define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_EN_DEV0_F4__MASK 0x00200000L +-#define RCC_DEV0_EPF4_STRAP4__STRAP_FLR_EN_DEV0_F4__MASK 0x00400000L +-#define RCC_DEV0_EPF4_STRAP4__STRAP_PME_SUPPORT_DEV0_F4__MASK 0x0F800000L +-#define RCC_DEV0_EPF4_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F4__MASK 0x70000000L +-#define RCC_DEV0_EPF4_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F4__MASK 0x80000000L +-//RCC_DEV0_EPF4_STRAP5 +-#define RCC_DEV0_EPF4_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F4__MASK 0x0000FFFFL +-#define RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESEL_DEV0_F4__MASK 0x000F0000L +-#define RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESELD_DEV0_F4__MASK 0x00F00000L +-//RCC_DEV0_EPF4_STRAP6 +-#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_EN_DEV0_F4__MASK 0x00000001L +-#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F4__MASK 0x00000002L +-#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F4__MASK 0x00000070L +-#define RCC_DEV0_EPF4_STRAP6__STRAP_APER1_EN_DEV0_F4__MASK 0x00000100L +-#define RCC_DEV0_EPF4_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F4__MASK 0x00000200L +-#define RCC_DEV0_EPF4_STRAP6__STRAP_APER2_EN_DEV0_F4__MASK 0x00010000L +-#define RCC_DEV0_EPF4_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F4__MASK 0x00020000L +-//RCC_DEV0_EPF4_STRAP13 +-#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F4__MASK 0x000000FFL +-#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F4__MASK 0x0000FF00L +-#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F4__MASK 0x00FF0000L +-//RCC_DEV0_EPF5_STRAP0 +-#define RCC_DEV0_EPF5_STRAP0__STRAP_DEVICE_ID_DEV0_F5__MASK 0x0000FFFFL +-#define RCC_DEV0_EPF5_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F5__MASK 0x000F0000L +-#define RCC_DEV0_EPF5_STRAP0__STRAP_MINOR_REV_ID_DEV0_F5__MASK 0x00F00000L +-#define RCC_DEV0_EPF5_STRAP0__STRAP_FUNC_EN_DEV0_F5__MASK 0x10000000L +-#define RCC_DEV0_EPF5_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F5__MASK 0x20000000L +-#define RCC_DEV0_EPF5_STRAP0__STRAP_D1_SUPPORT_DEV0_F5__MASK 0x40000000L +-#define RCC_DEV0_EPF5_STRAP0__STRAP_D2_SUPPORT_DEV0_F5__MASK 0x80000000L +-//RCC_DEV0_EPF5_STRAP2 +-#define RCC_DEV0_EPF5_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F5__MASK 0x00000080L +-#define RCC_DEV0_EPF5_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F5__MASK 0x00000100L +-#define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F5__MASK 0x00004000L +-#define RCC_DEV0_EPF5_STRAP2__STRAP_AER_EN_DEV0_F5__MASK 0x00010000L +-#define RCC_DEV0_EPF5_STRAP2__STRAP_ACS_EN_DEV0_F5__MASK 0x00020000L +-#define RCC_DEV0_EPF5_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F5__MASK 0x00100000L +-#define RCC_DEV0_EPF5_STRAP2__STRAP_DPA_EN_DEV0_F5__MASK 0x00200000L +-#define RCC_DEV0_EPF5_STRAP2__STRAP_VC_EN_DEV0_F5__MASK 0x00800000L +-#define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F5__MASK 0x07000000L +-//RCC_DEV0_EPF5_STRAP3 +-#define RCC_DEV0_EPF5_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F5__MASK 0x00000001L +-#define RCC_DEV0_EPF5_STRAP3__STRAP_PWR_EN_DEV0_F5__MASK 0x00000002L +-#define RCC_DEV0_EPF5_STRAP3__STRAP_SUBSYS_ID_DEV0_F5__MASK 0x0003FFFCL +-#define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_EN_DEV0_F5__MASK 0x00040000L +-#define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F5__MASK 0x00080000L +-#define RCC_DEV0_EPF5_STRAP3__STRAP_MSIX_EN_DEV0_F5__MASK 0x00100000L +-#define RCC_DEV0_EPF5_STRAP3__STRAP_PMC_DSI_DEV0_F5__MASK 0x01000000L +-#define RCC_DEV0_EPF5_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F5__MASK 0x02000000L +-#define RCC_DEV0_EPF5_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F5__MASK 0x04000000L +-#define RCC_DEV0_EPF5_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F5__MASK 0x08000000L +-//RCC_DEV0_EPF5_STRAP4 +-#define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F5__MASK 0x00100000L +-#define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_EN_DEV0_F5__MASK 0x00200000L +-#define RCC_DEV0_EPF5_STRAP4__STRAP_FLR_EN_DEV0_F5__MASK 0x00400000L +-#define RCC_DEV0_EPF5_STRAP4__STRAP_PME_SUPPORT_DEV0_F5__MASK 0x0F800000L +-#define RCC_DEV0_EPF5_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F5__MASK 0x70000000L +-#define RCC_DEV0_EPF5_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F5__MASK 0x80000000L +-//RCC_DEV0_EPF5_STRAP5 +-#define RCC_DEV0_EPF5_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F5__MASK 0x0000FFFFL +-//RCC_DEV0_EPF5_STRAP6 +-#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_EN_DEV0_F5__MASK 0x00000001L +-#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F5__MASK 0x00000002L +-#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F5__MASK 0x00000070L +-#define RCC_DEV0_EPF5_STRAP6__STRAP_APER1_EN_DEV0_F5__MASK 0x00000100L +-#define RCC_DEV0_EPF5_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F5__MASK 0x00000200L +-#define RCC_DEV0_EPF5_STRAP6__STRAP_APER2_EN_DEV0_F5__MASK 0x00010000L +-#define RCC_DEV0_EPF5_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F5__MASK 0x00020000L +-//RCC_DEV0_EPF5_STRAP13 +-#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F5__MASK 0x000000FFL +-#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F5__MASK 0x0000FF00L +-#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F5__MASK 0x00FF0000L +-//RCC_DEV0_EPF6_STRAP0 +-#define RCC_DEV0_EPF6_STRAP0__STRAP_DEVICE_ID_DEV0_F6__MASK 0x0000FFFFL +-#define RCC_DEV0_EPF6_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F6__MASK 0x000F0000L +-#define RCC_DEV0_EPF6_STRAP0__STRAP_MINOR_REV_ID_DEV0_F6__MASK 0x00F00000L +-#define RCC_DEV0_EPF6_STRAP0__STRAP_FUNC_EN_DEV0_F6__MASK 0x10000000L +-#define RCC_DEV0_EPF6_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F6__MASK 0x20000000L +-#define RCC_DEV0_EPF6_STRAP0__STRAP_D1_SUPPORT_DEV0_F6__MASK 0x40000000L +-#define RCC_DEV0_EPF6_STRAP0__STRAP_D2_SUPPORT_DEV0_F6__MASK 0x80000000L +-//RCC_DEV0_EPF6_STRAP2 +-#define RCC_DEV0_EPF6_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F6__MASK 0x00000080L +-#define RCC_DEV0_EPF6_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F6__MASK 0x00000100L +-#define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F6__MASK 0x00004000L +-#define RCC_DEV0_EPF6_STRAP2__STRAP_AER_EN_DEV0_F6__MASK 0x00010000L +-#define RCC_DEV0_EPF6_STRAP2__STRAP_ACS_EN_DEV0_F6__MASK 0x00020000L +-#define RCC_DEV0_EPF6_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F6__MASK 0x00100000L +-#define RCC_DEV0_EPF6_STRAP2__STRAP_DPA_EN_DEV0_F6__MASK 0x00200000L +-#define RCC_DEV0_EPF6_STRAP2__STRAP_VC_EN_DEV0_F6__MASK 0x00800000L +-#define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F6__MASK 0x07000000L +-//RCC_DEV0_EPF6_STRAP3 +-#define RCC_DEV0_EPF6_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F6__MASK 0x00000001L +-#define RCC_DEV0_EPF6_STRAP3__STRAP_PWR_EN_DEV0_F6__MASK 0x00000002L +-#define RCC_DEV0_EPF6_STRAP3__STRAP_SUBSYS_ID_DEV0_F6__MASK 0x0003FFFCL +-#define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_EN_DEV0_F6__MASK 0x00040000L +-#define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F6__MASK 0x00080000L +-#define RCC_DEV0_EPF6_STRAP3__STRAP_MSIX_EN_DEV0_F6__MASK 0x00100000L +-#define RCC_DEV0_EPF6_STRAP3__STRAP_PMC_DSI_DEV0_F6__MASK 0x01000000L +-#define RCC_DEV0_EPF6_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F6__MASK 0x02000000L +-#define RCC_DEV0_EPF6_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F6__MASK 0x04000000L +-#define RCC_DEV0_EPF6_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F6__MASK 0x08000000L +-//RCC_DEV0_EPF6_STRAP4 +-#define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F6__MASK 0x00100000L +-#define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_EN_DEV0_F6__MASK 0x00200000L +-#define RCC_DEV0_EPF6_STRAP4__STRAP_FLR_EN_DEV0_F6__MASK 0x00400000L +-#define RCC_DEV0_EPF6_STRAP4__STRAP_PME_SUPPORT_DEV0_F6__MASK 0x0F800000L +-#define RCC_DEV0_EPF6_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F6__MASK 0x70000000L +-#define RCC_DEV0_EPF6_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F6__MASK 0x80000000L +-//RCC_DEV0_EPF6_STRAP5 +-#define RCC_DEV0_EPF6_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F6__MASK 0x0000FFFFL +-//RCC_DEV0_EPF6_STRAP6 +-#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_EN_DEV0_F6__MASK 0x00000001L +-#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F6__MASK 0x00000002L +-#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F6__MASK 0x00000070L +-#define RCC_DEV0_EPF6_STRAP6__STRAP_APER1_EN_DEV0_F6__MASK 0x00000100L +-#define RCC_DEV0_EPF6_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F6__MASK 0x00000200L +-#define RCC_DEV0_EPF6_STRAP6__STRAP_APER2_EN_DEV0_F6__MASK 0x00010000L +-#define RCC_DEV0_EPF6_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F6__MASK 0x00020000L +-//RCC_DEV0_EPF6_STRAP13 +-#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F6__MASK 0x000000FFL +-#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F6__MASK 0x0000FF00L +-#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F6__MASK 0x00FF0000L +-//RCC_DEV0_EPF7_STRAP0 +-#define RCC_DEV0_EPF7_STRAP0__STRAP_DEVICE_ID_DEV0_F7__MASK 0x0000FFFFL +-#define RCC_DEV0_EPF7_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F7__MASK 0x000F0000L +-#define RCC_DEV0_EPF7_STRAP0__STRAP_MINOR_REV_ID_DEV0_F7__MASK 0x00F00000L +-#define RCC_DEV0_EPF7_STRAP0__STRAP_FUNC_EN_DEV0_F7__MASK 0x10000000L +-#define RCC_DEV0_EPF7_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F7__MASK 0x20000000L +-#define RCC_DEV0_EPF7_STRAP0__STRAP_D1_SUPPORT_DEV0_F7__MASK 0x40000000L +-#define RCC_DEV0_EPF7_STRAP0__STRAP_D2_SUPPORT_DEV0_F7__MASK 0x80000000L +-//RCC_DEV0_EPF7_STRAP2 +-#define RCC_DEV0_EPF7_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F7__MASK 0x00000080L +-#define RCC_DEV0_EPF7_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F7__MASK 0x00000100L +-#define RCC_DEV0_EPF7_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F7__MASK 0x00004000L +-#define RCC_DEV0_EPF7_STRAP2__STRAP_AER_EN_DEV0_F7__MASK 0x00010000L +-#define RCC_DEV0_EPF7_STRAP2__STRAP_ACS_EN_DEV0_F7__MASK 0x00020000L +-#define RCC_DEV0_EPF7_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F7__MASK 0x00100000L +-#define RCC_DEV0_EPF7_STRAP2__STRAP_DPA_EN_DEV0_F7__MASK 0x00200000L +-#define RCC_DEV0_EPF7_STRAP2__STRAP_VC_EN_DEV0_F7__MASK 0x00800000L +-#define RCC_DEV0_EPF7_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F7__MASK 0x07000000L +-//RCC_DEV0_EPF7_STRAP3 +-#define RCC_DEV0_EPF7_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F7__MASK 0x00000001L +-#define RCC_DEV0_EPF7_STRAP3__STRAP_PWR_EN_DEV0_F7__MASK 0x00000002L +-#define RCC_DEV0_EPF7_STRAP3__STRAP_SUBSYS_ID_DEV0_F7__MASK 0x0003FFFCL +-#define RCC_DEV0_EPF7_STRAP3__STRAP_MSI_EN_DEV0_F7__MASK 0x00040000L +-#define RCC_DEV0_EPF7_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F7__MASK 0x00080000L +-#define RCC_DEV0_EPF7_STRAP3__STRAP_MSIX_EN_DEV0_F7__MASK 0x00100000L +-#define RCC_DEV0_EPF7_STRAP3__STRAP_PMC_DSI_DEV0_F7__MASK 0x01000000L +-#define RCC_DEV0_EPF7_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F7__MASK 0x02000000L +-#define RCC_DEV0_EPF7_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F7__MASK 0x04000000L +-#define RCC_DEV0_EPF7_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F7__MASK 0x08000000L +-//RCC_DEV0_EPF7_STRAP4 +-#define RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F7__MASK 0x00100000L +-#define RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_EN_DEV0_F7__MASK 0x00200000L +-#define RCC_DEV0_EPF7_STRAP4__STRAP_FLR_EN_DEV0_F7__MASK 0x00400000L +-#define RCC_DEV0_EPF7_STRAP4__STRAP_PME_SUPPORT_DEV0_F7__MASK 0x0F800000L +-#define RCC_DEV0_EPF7_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F7__MASK 0x70000000L +-#define RCC_DEV0_EPF7_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F7__MASK 0x80000000L +-//RCC_DEV0_EPF7_STRAP5 +-#define RCC_DEV0_EPF7_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F7__MASK 0x0000FFFFL +-//RCC_DEV0_EPF7_STRAP6 +-#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_EN_DEV0_F7__MASK 0x00000001L +-#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F7__MASK 0x00000002L +-#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F7__MASK 0x00000070L +-#define RCC_DEV0_EPF7_STRAP6__STRAP_APER1_EN_DEV0_F7__MASK 0x00000100L +-#define RCC_DEV0_EPF7_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F7__MASK 0x00000200L +-#define RCC_DEV0_EPF7_STRAP6__STRAP_APER2_EN_DEV0_F7__MASK 0x00010000L +-#define RCC_DEV0_EPF7_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F7__MASK 0x00020000L +-//RCC_DEV0_EPF7_STRAP13 +-#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F7__MASK 0x000000FFL +-#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F7__MASK 0x0000FF00L +-#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F7__MASK 0x00FF0000L +-//RCC_DEV1_EPF0_STRAP0 +-#define RCC_DEV1_EPF0_STRAP0__STRAP_DEVICE_ID_DEV1_F0__MASK 0x0000FFFFL +-#define RCC_DEV1_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F0__MASK 0x000F0000L +-#define RCC_DEV1_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV1_F0__MASK 0x00F00000L +-#define RCC_DEV1_EPF0_STRAP0__STRAP_FUNC_EN_DEV1_F0__MASK 0x10000000L +-#define RCC_DEV1_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F0__MASK 0x20000000L +-#define RCC_DEV1_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV1_F0__MASK 0x40000000L +-#define RCC_DEV1_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV1_F0__MASK 0x80000000L +-//RCC_DEV1_EPF0_STRAP2 +-#define RCC_DEV1_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F0__MASK 0x00000080L +-#define RCC_DEV1_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F0__MASK 0x00000100L +-#define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F0__MASK 0x00004000L +-#define RCC_DEV1_EPF0_STRAP2__STRAP_ARI_EN_DEV1_F0__MASK 0x00008000L +-#define RCC_DEV1_EPF0_STRAP2__STRAP_AER_EN_DEV1_F0__MASK 0x00010000L +-#define RCC_DEV1_EPF0_STRAP2__STRAP_ACS_EN_DEV1_F0__MASK 0x00020000L +-#define RCC_DEV1_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F0__MASK 0x00100000L +-#define RCC_DEV1_EPF0_STRAP2__STRAP_DPA_EN_DEV1_F0__MASK 0x00200000L +-#define RCC_DEV1_EPF0_STRAP2__STRAP_VC_EN_DEV1_F0__MASK 0x00800000L +-#define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F0__MASK 0x07000000L +-//RCC_DEV1_EPF0_STRAP3 +-#define RCC_DEV1_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F0__MASK 0x00000001L +-#define RCC_DEV1_EPF0_STRAP3__STRAP_PWR_EN_DEV1_F0__MASK 0x00000002L +-#define RCC_DEV1_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV1_F0__MASK 0x0003FFFCL +-#define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_EN_DEV1_F0__MASK 0x00040000L +-#define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F0__MASK 0x00080000L +-#define RCC_DEV1_EPF0_STRAP3__STRAP_MSIX_EN_DEV1_F0__MASK 0x00100000L +-#define RCC_DEV1_EPF0_STRAP3__STRAP_PMC_DSI_DEV1_F0__MASK 0x01000000L +-#define RCC_DEV1_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F0__MASK 0x02000000L +-#define RCC_DEV1_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F0__MASK 0x04000000L +-#define RCC_DEV1_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F0__MASK 0x08000000L +-//RCC_DEV1_EPF0_STRAP4 +-#define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F0__MASK 0x00100000L +-#define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV1_F0__MASK 0x00200000L +-#define RCC_DEV1_EPF0_STRAP4__STRAP_FLR_EN_DEV1_F0__MASK 0x00400000L +-#define RCC_DEV1_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV1_F0__MASK 0x0F800000L +-#define RCC_DEV1_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F0__MASK 0x70000000L +-#define RCC_DEV1_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F0__MASK 0x80000000L +-//RCC_DEV1_EPF0_STRAP5 +-#define RCC_DEV1_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F0__MASK 0x0000FFFFL +-#define RCC_DEV1_EPF0_STRAP5__STRAP_SATAIDP_EN_DEV1_F0__MASK 0x01000000L +-//RCC_DEV1_EPF0_STRAP6 +-#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_EN_DEV1_F0__MASK 0x00000001L +-#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F0__MASK 0x00000002L +-#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F0__MASK 0x00000070L +-//RCC_DEV1_EPF0_STRAP13 +-#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F0__MASK 0x000000FFL +-#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F0__MASK 0x0000FF00L +-#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F0__MASK 0x00FF0000L +-//RCC_DEV1_EPF1_STRAP0 +-#define RCC_DEV1_EPF1_STRAP0__STRAP_DEVICE_ID_DEV1_F1__MASK 0x0000FFFFL +-#define RCC_DEV1_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F1__MASK 0x000F0000L +-#define RCC_DEV1_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV1_F1__MASK 0x00F00000L +-#define RCC_DEV1_EPF1_STRAP0__STRAP_FUNC_EN_DEV1_F1__MASK 0x10000000L +-#define RCC_DEV1_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F1__MASK 0x20000000L +-#define RCC_DEV1_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV1_F1__MASK 0x40000000L +-#define RCC_DEV1_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV1_F1__MASK 0x80000000L +-//RCC_DEV1_EPF1_STRAP2 +-#define RCC_DEV1_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F1__MASK 0x00000080L +-#define RCC_DEV1_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F1__MASK 0x00000100L +-#define RCC_DEV1_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F1__MASK 0x00004000L +-#define RCC_DEV1_EPF1_STRAP2__STRAP_AER_EN_DEV1_F1__MASK 0x00010000L +-#define RCC_DEV1_EPF1_STRAP2__STRAP_ACS_EN_DEV1_F1__MASK 0x00020000L +-#define RCC_DEV1_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F1__MASK 0x00100000L +-#define RCC_DEV1_EPF1_STRAP2__STRAP_DPA_EN_DEV1_F1__MASK 0x00200000L +-#define RCC_DEV1_EPF1_STRAP2__STRAP_VC_EN_DEV1_F1__MASK 0x00800000L +-#define RCC_DEV1_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F1__MASK 0x07000000L +-//RCC_DEV1_EPF1_STRAP3 +-#define RCC_DEV1_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F1__MASK 0x00000001L +-#define RCC_DEV1_EPF1_STRAP3__STRAP_PWR_EN_DEV1_F1__MASK 0x00000002L +-#define RCC_DEV1_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV1_F1__MASK 0x0003FFFCL +-#define RCC_DEV1_EPF1_STRAP3__STRAP_MSI_EN_DEV1_F1__MASK 0x00040000L +-#define RCC_DEV1_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F1__MASK 0x00080000L +-#define RCC_DEV1_EPF1_STRAP3__STRAP_MSIX_EN_DEV1_F1__MASK 0x00100000L +-#define RCC_DEV1_EPF1_STRAP3__STRAP_PMC_DSI_DEV1_F1__MASK 0x01000000L +-#define RCC_DEV1_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F1__MASK 0x02000000L +-#define RCC_DEV1_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F1__MASK 0x04000000L +-#define RCC_DEV1_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F1__MASK 0x08000000L +-//RCC_DEV1_EPF1_STRAP4 +-#define RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F1__MASK 0x00100000L +-#define RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV1_F1__MASK 0x00200000L +-#define RCC_DEV1_EPF1_STRAP4__STRAP_FLR_EN_DEV1_F1__MASK 0x00400000L +-#define RCC_DEV1_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV1_F1__MASK 0x0F800000L +-#define RCC_DEV1_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F1__MASK 0x70000000L +-#define RCC_DEV1_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F1__MASK 0x80000000L +-//RCC_DEV1_EPF1_STRAP5 +-#define RCC_DEV1_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F1__MASK 0x0000FFFFL +-//RCC_DEV1_EPF1_STRAP6 +-#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_EN_DEV1_F1__MASK 0x00000001L +-#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F1__MASK 0x00000002L +-#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F1__MASK 0x00000070L +-#define RCC_DEV1_EPF1_STRAP6__STRAP_APER1_EN_DEV1_F1__MASK 0x00000100L +-#define RCC_DEV1_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV1_F1__MASK 0x00000200L +-#define RCC_DEV1_EPF1_STRAP6__STRAP_APER2_EN_DEV1_F1__MASK 0x00010000L +-#define RCC_DEV1_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV1_F1__MASK 0x00020000L +-#define RCC_DEV1_EPF1_STRAP6__STRAP_APER3_EN_DEV1_F1__MASK 0x01000000L +-#define RCC_DEV1_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV1_F1__MASK 0x02000000L +-//RCC_DEV1_EPF1_STRAP13 +-#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F1__MASK 0x000000FFL +-#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F1__MASK 0x0000FF00L +-#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F1__MASK 0x00FF0000L +-//RCC_DEV1_EPF2_STRAP0 +-#define RCC_DEV1_EPF2_STRAP0__STRAP_DEVICE_ID_DEV1_F2__MASK 0x0000FFFFL +-#define RCC_DEV1_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F2__MASK 0x000F0000L +-#define RCC_DEV1_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV1_F2__MASK 0x00F00000L +-#define RCC_DEV1_EPF2_STRAP0__STRAP_FUNC_EN_DEV1_F2__MASK 0x10000000L +-#define RCC_DEV1_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F2__MASK 0x20000000L +-#define RCC_DEV1_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV1_F2__MASK 0x40000000L +-#define RCC_DEV1_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV1_F2__MASK 0x80000000L +-//RCC_DEV1_EPF2_STRAP2 +-#define RCC_DEV1_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F2__MASK 0x00000080L +-#define RCC_DEV1_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F2__MASK 0x00000100L +-#define RCC_DEV1_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F2__MASK 0x00004000L +-#define RCC_DEV1_EPF2_STRAP2__STRAP_AER_EN_DEV1_F2__MASK 0x00010000L +-#define RCC_DEV1_EPF2_STRAP2__STRAP_ACS_EN_DEV1_F2__MASK 0x00020000L +-#define RCC_DEV1_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F2__MASK 0x00100000L +-#define RCC_DEV1_EPF2_STRAP2__STRAP_DPA_EN_DEV1_F2__MASK 0x00200000L +-#define RCC_DEV1_EPF2_STRAP2__STRAP_VC_EN_DEV1_F2__MASK 0x00800000L +-#define RCC_DEV1_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F2__MASK 0x07000000L +-//RCC_DEV1_EPF2_STRAP3 +-#define RCC_DEV1_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F2__MASK 0x00000001L +-#define RCC_DEV1_EPF2_STRAP3__STRAP_PWR_EN_DEV1_F2__MASK 0x00000002L +-#define RCC_DEV1_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV1_F2__MASK 0x0003FFFCL +-#define RCC_DEV1_EPF2_STRAP3__STRAP_MSI_EN_DEV1_F2__MASK 0x00040000L +-#define RCC_DEV1_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F2__MASK 0x00080000L +-#define RCC_DEV1_EPF2_STRAP3__STRAP_MSIX_EN_DEV1_F2__MASK 0x00100000L +-#define RCC_DEV1_EPF2_STRAP3__STRAP_PMC_DSI_DEV1_F2__MASK 0x01000000L +-#define RCC_DEV1_EPF2_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F2__MASK 0x02000000L +-#define RCC_DEV1_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F2__MASK 0x04000000L +-#define RCC_DEV1_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F2__MASK 0x08000000L +-//RCC_DEV1_EPF2_STRAP4 +-#define RCC_DEV1_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F2__MASK 0x00100000L +-#define RCC_DEV1_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV1_F2__MASK 0x00200000L +-#define RCC_DEV1_EPF2_STRAP4__STRAP_FLR_EN_DEV1_F2__MASK 0x00400000L +-#define RCC_DEV1_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV1_F2__MASK 0x0F800000L +-#define RCC_DEV1_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F2__MASK 0x70000000L +-#define RCC_DEV1_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F2__MASK 0x80000000L +-//RCC_DEV1_EPF2_STRAP5 +-#define RCC_DEV1_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F2__MASK 0x0000FFFFL +-//RCC_DEV1_EPF2_STRAP6 +-#define RCC_DEV1_EPF2_STRAP6__STRAP_APER0_EN_DEV1_F2__MASK 0x00000001L +-#define RCC_DEV1_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F2__MASK 0x00000002L +-#define RCC_DEV1_EPF2_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F2__MASK 0x00000070L +-#define RCC_DEV1_EPF2_STRAP6__STRAP_APER1_EN_DEV1_F2__MASK 0x00000100L +-#define RCC_DEV1_EPF2_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV1_F2__MASK 0x00000200L +-#define RCC_DEV1_EPF2_STRAP6__STRAP_APER2_EN_DEV1_F2__MASK 0x00010000L +-#define RCC_DEV1_EPF2_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV1_F2__MASK 0x00020000L +-#define RCC_DEV1_EPF2_STRAP6__STRAP_APER3_EN_DEV1_F2__MASK 0x01000000L +-#define RCC_DEV1_EPF2_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV1_F2__MASK 0x02000000L +-//RCC_DEV1_EPF2_STRAP13 +-#define RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F2__MASK 0x000000FFL +-#define RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F2__MASK 0x0000FF00L +-#define RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F2__MASK 0x00FF0000L +- +- +-// addressBlock: bif_rst_bif_rst_regblk +-//HARD_RST_CTRL +-#define HARD_RST_CTRL__DSPT_CFG_RST_EN__MASK 0x00000001L +-#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN__MASK 0x00000002L +-#define HARD_RST_CTRL__DSPT_PRV_RST_EN__MASK 0x00000004L +-#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN__MASK 0x00000008L +-#define HARD_RST_CTRL__EP_CFG_RST_EN__MASK 0x00000010L +-#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN__MASK 0x00000020L +-#define HARD_RST_CTRL__EP_PRV_RST_EN__MASK 0x00000040L +-#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN__MASK 0x00000080L +-#define HARD_RST_CTRL__SWUS_SHADOW_RST_EN__MASK 0x10000000L +-#define HARD_RST_CTRL__CORE_STICKY_RST_EN__MASK 0x20000000L +-#define HARD_RST_CTRL__RELOAD_STRAP_EN__MASK 0x40000000L +-#define HARD_RST_CTRL__CORE_RST_EN__MASK 0x80000000L +-//RSMU_SOFT_RST_CTRL +-#define RSMU_SOFT_RST_CTRL__DSPT_CFG_RST_EN__MASK 0x00000001L +-#define RSMU_SOFT_RST_CTRL__DSPT_CFG_STICKY_RST_EN__MASK 0x00000002L +-#define RSMU_SOFT_RST_CTRL__DSPT_PRV_RST_EN__MASK 0x00000004L +-#define RSMU_SOFT_RST_CTRL__DSPT_PRV_STICKY_RST_EN__MASK 0x00000008L +-#define RSMU_SOFT_RST_CTRL__EP_CFG_RST_EN__MASK 0x00000010L +-#define RSMU_SOFT_RST_CTRL__EP_CFG_STICKY_RST_EN__MASK 0x00000020L +-#define RSMU_SOFT_RST_CTRL__EP_PRV_RST_EN__MASK 0x00000040L +-#define RSMU_SOFT_RST_CTRL__EP_PRV_STICKY_RST_EN__MASK 0x00000080L +-#define RSMU_SOFT_RST_CTRL__SWUS_SHADOW_RST_EN__MASK 0x10000000L +-#define RSMU_SOFT_RST_CTRL__CORE_STICKY_RST_EN__MASK 0x20000000L +-#define RSMU_SOFT_RST_CTRL__RELOAD_STRAP_EN__MASK 0x40000000L +-#define RSMU_SOFT_RST_CTRL__CORE_RST_EN__MASK 0x80000000L +-//SELF_SOFT_RST +-#define SELF_SOFT_RST__DSPT0_CFG_RST__MASK 0x00000001L +-#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST__MASK 0x00000002L +-#define SELF_SOFT_RST__DSPT0_PRV_RST__MASK 0x00000004L +-#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST__MASK 0x00000008L +-#define SELF_SOFT_RST__EP0_CFG_RST__MASK 0x00000010L +-#define SELF_SOFT_RST__EP0_CFG_STICKY_RST__MASK 0x00000020L +-#define SELF_SOFT_RST__EP0_PRV_RST__MASK 0x00000040L +-#define SELF_SOFT_RST__EP0_PRV_STICKY_RST__MASK 0x00000080L +-#define SELF_SOFT_RST__SDP_PORT_RST__MASK 0x08000000L +-#define SELF_SOFT_RST__SWUS_SHADOW_RST__MASK 0x10000000L +-#define SELF_SOFT_RST__CORE_STICKY_RST__MASK 0x20000000L +-#define SELF_SOFT_RST__RELOAD_STRAP__MASK 0x40000000L +-#define SELF_SOFT_RST__CORE_RST__MASK 0x80000000L +-//GFX_DRV_MODE1_RST_CTRL +-#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_RST__MASK 0x00000001L +-#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_FLR_EXC_RST__MASK 0x00000002L +-#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_STICKY_RST__MASK 0x00000004L +-#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_PRV_RST__MASK 0x00000008L +-#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_PRV_STICKY_RST__MASK 0x00000010L +-#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_CFG_RST__MASK 0x00000020L +-#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_CFG_STICKY_RST__MASK 0x00000040L +-#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_PRV_RST__MASK 0x00000080L +-//BIF_RST_MISC_CTRL +-#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB__MASK 0x00000001L +-#define BIF_RST_MISC_CTRL__DRV_RST_MODE__MASK 0x0000000CL +-#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK__MASK 0x00000010L +-#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR__MASK 0x00000020L +-#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR__MASK 0x00000040L +-#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN__MASK 0x00000100L +-#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE__MASK 0x00000200L +-#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT__MASK 0x00001C00L +-#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL__MASK 0x00006000L +-#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL__MASK 0x00018000L +-#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__MASK 0x00060000L +-#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS__MASK 0x00800000L +-#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS__MASK 0x03000000L +-//BIF_RST_MISC_CTRL2 +-#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE__MASK 0x00010000L +-#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE__MASK 0x00020000L +-#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE__MASK 0x00040000L +-#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE__MASK 0x80000000L +-//BIF_RST_MISC_CTRL3 +-#define BIF_RST_MISC_CTRL3__TIMER_SCALE__MASK 0x0000000FL +-#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT__MASK 0x00000030L +-#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE__MASK 0x00000040L +-#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD__MASK 0x00000380L +-#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT__MASK 0x00001C00L +-#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF__MASK 0x0000E000L +-//BIF_RST_GFXVF_FLR_IDLE +-#define BIF_RST_GFXVF_FLR_IDLE__VF0_TRANS_IDLE__MASK 0x00000001L +-#define BIF_RST_GFXVF_FLR_IDLE__VF1_TRANS_IDLE__MASK 0x00000002L +-#define BIF_RST_GFXVF_FLR_IDLE__VF2_TRANS_IDLE__MASK 0x00000004L +-#define BIF_RST_GFXVF_FLR_IDLE__VF3_TRANS_IDLE__MASK 0x00000008L +-#define BIF_RST_GFXVF_FLR_IDLE__VF4_TRANS_IDLE__MASK 0x00000010L +-#define BIF_RST_GFXVF_FLR_IDLE__VF5_TRANS_IDLE__MASK 0x00000020L +-#define BIF_RST_GFXVF_FLR_IDLE__VF6_TRANS_IDLE__MASK 0x00000040L +-#define BIF_RST_GFXVF_FLR_IDLE__VF7_TRANS_IDLE__MASK 0x00000080L +-#define BIF_RST_GFXVF_FLR_IDLE__VF8_TRANS_IDLE__MASK 0x00000100L +-#define BIF_RST_GFXVF_FLR_IDLE__VF9_TRANS_IDLE__MASK 0x00000200L +-#define BIF_RST_GFXVF_FLR_IDLE__VF10_TRANS_IDLE__MASK 0x00000400L +-#define BIF_RST_GFXVF_FLR_IDLE__VF11_TRANS_IDLE__MASK 0x00000800L +-#define BIF_RST_GFXVF_FLR_IDLE__VF12_TRANS_IDLE__MASK 0x00001000L +-#define BIF_RST_GFXVF_FLR_IDLE__VF13_TRANS_IDLE__MASK 0x00002000L +-#define BIF_RST_GFXVF_FLR_IDLE__VF14_TRANS_IDLE__MASK 0x00004000L +-#define BIF_RST_GFXVF_FLR_IDLE__VF15_TRANS_IDLE__MASK 0x00008000L +-#define BIF_RST_GFXVF_FLR_IDLE__SOFTPF_TRANS_IDLE__MASK 0x80000000L +-//DEV0_PF0_FLR_RST_CTRL +-#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L +-#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L +-#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L +-#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L +-#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L +-#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN__MASK 0x00000020L +-#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN__MASK 0x00000040L +-#define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN__MASK 0x00000080L +-#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN__MASK 0x00000100L +-#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN__MASK 0x00000200L +-#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN__MASK 0x00000400L +-#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN__MASK 0x00000800L +-#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN__MASK 0x00001000L +-#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN__MASK 0x00002000L +-#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN__MASK 0x00004000L +-#define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN__MASK 0x00008000L +-#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN__MASK 0x00010000L +-#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L +-#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L +-#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L +-#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L +-//DEV0_PF1_FLR_RST_CTRL +-#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L +-#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L +-#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L +-#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L +-#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L +-#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L +-#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L +-#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L +-#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L +-//DEV0_PF2_FLR_RST_CTRL +-#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L +-#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L +-#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L +-#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L +-#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L +-#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L +-#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L +-#define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L +-#define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L +-//DEV0_PF3_FLR_RST_CTRL +-#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L +-#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L +-#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L +-#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L +-#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L +-#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L +-#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L +-#define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L +-#define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L +-//DEV0_PF4_FLR_RST_CTRL +-#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L +-#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L +-#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L +-#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L +-#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L +-#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L +-#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L +-#define DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L +-#define DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L +-//DEV0_PF5_FLR_RST_CTRL +-#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L +-#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L +-#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L +-#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L +-#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L +-#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L +-#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L +-#define DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L +-#define DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L +-//DEV0_PF6_FLR_RST_CTRL +-#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L +-#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L +-#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L +-#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L +-#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L +-#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L +-#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L +-#define DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L +-#define DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L +-//DEV0_PF7_FLR_RST_CTRL +-#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L +-#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L +-#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L +-#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L +-#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L +-#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L +-#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L +-#define DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L +-#define DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L +-//BIF_INST_RESET_INTR_STS +-#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS__MASK 0x00000001L +-#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS__MASK 0x00000002L +-#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS__MASK 0x00000004L +-#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS__MASK 0x00000008L +-#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS__MASK 0x00000010L +-//BIF_PF_FLR_INTR_STS +-#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS__MASK 0x00000001L +-#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS__MASK 0x00000002L +-#define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS__MASK 0x00000004L +-#define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS__MASK 0x00000008L +-#define BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS__MASK 0x00000010L +-#define BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS__MASK 0x00000020L +-#define BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS__MASK 0x00000040L +-#define BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS__MASK 0x00000080L +-//BIF_D3HOTD0_INTR_STS +-#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS__MASK 0x00000001L +-#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS__MASK 0x00000002L +-#define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS__MASK 0x00000004L +-#define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS__MASK 0x00000008L +-#define BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS__MASK 0x00000010L +-#define BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS__MASK 0x00000020L +-#define BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS__MASK 0x00000040L +-#define BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS__MASK 0x00000080L +-//BIF_POWER_INTR_STS +-#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS__MASK 0x00000001L +-#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS__MASK 0x00010000L +-//BIF_PF_DSTATE_INTR_STS +-#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS__MASK 0x00000001L +-#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS__MASK 0x00000002L +-#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS__MASK 0x00000004L +-#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS__MASK 0x00000008L +-#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS__MASK 0x00000010L +-#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS__MASK 0x00000020L +-#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS__MASK 0x00000040L +-#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS__MASK 0x00000080L +-//BIF_PF0_VF_FLR_INTR_STS +-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF0_FLR_INTR_STS__MASK 0x00000001L +-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF1_FLR_INTR_STS__MASK 0x00000002L +-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF2_FLR_INTR_STS__MASK 0x00000004L +-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF3_FLR_INTR_STS__MASK 0x00000008L +-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF4_FLR_INTR_STS__MASK 0x00000010L +-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF5_FLR_INTR_STS__MASK 0x00000020L +-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF6_FLR_INTR_STS__MASK 0x00000040L +-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF7_FLR_INTR_STS__MASK 0x00000080L +-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF8_FLR_INTR_STS__MASK 0x00000100L +-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF9_FLR_INTR_STS__MASK 0x00000200L +-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF10_FLR_INTR_STS__MASK 0x00000400L +-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF11_FLR_INTR_STS__MASK 0x00000800L +-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF12_FLR_INTR_STS__MASK 0x00001000L +-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF13_FLR_INTR_STS__MASK 0x00002000L +-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF14_FLR_INTR_STS__MASK 0x00004000L +-#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF15_FLR_INTR_STS__MASK 0x00008000L +-#define BIF_PF0_VF_FLR_INTR_STS__PF0_SOFTPF_FLR_INTR_STS__MASK 0x80000000L +-//BIF_INST_RESET_INTR_MASK +-#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK__MASK 0x00000001L +-#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK__MASK 0x00000002L +-#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK__MASK 0x00000004L +-#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK__MASK 0x00000008L +-#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK__MASK 0x00000010L +-//BIF_PF_FLR_INTR_MASK +-#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK__MASK 0x00000001L +-#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK__MASK 0x00000002L +-#define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK__MASK 0x00000004L +-#define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK__MASK 0x00000008L +-#define BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK__MASK 0x00000010L +-#define BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK__MASK 0x00000020L +-#define BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK__MASK 0x00000040L +-#define BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK__MASK 0x00000080L +-//BIF_D3HOTD0_INTR_MASK +-#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK__MASK 0x00000001L +-#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK__MASK 0x00000002L +-#define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK__MASK 0x00000004L +-#define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK__MASK 0x00000008L +-#define BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK__MASK 0x00000010L +-#define BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK__MASK 0x00000020L +-#define BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK__MASK 0x00000040L +-#define BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK__MASK 0x00000080L +-//BIF_POWER_INTR_MASK +-#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK__MASK 0x00000001L +-#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__MASK 0x00010000L +-//BIF_PF_DSTATE_INTR_MASK +-#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK__MASK 0x00000001L +-#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK__MASK 0x00000002L +-#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK__MASK 0x00000004L +-#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK__MASK 0x00000008L +-#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK__MASK 0x00000010L +-#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK__MASK 0x00000020L +-#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK__MASK 0x00000040L +-#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK__MASK 0x00000080L +-//BIF_PF0_VF_FLR_INTR_MASK +-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF0_FLR_INTR_MASK__MASK 0x00000001L +-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF1_FLR_INTR_MASK__MASK 0x00000002L +-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF2_FLR_INTR_MASK__MASK 0x00000004L +-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF3_FLR_INTR_MASK__MASK 0x00000008L +-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF4_FLR_INTR_MASK__MASK 0x00000010L +-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF5_FLR_INTR_MASK__MASK 0x00000020L +-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF6_FLR_INTR_MASK__MASK 0x00000040L +-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF7_FLR_INTR_MASK__MASK 0x00000080L +-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF8_FLR_INTR_MASK__MASK 0x00000100L +-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF9_FLR_INTR_MASK__MASK 0x00000200L +-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF10_FLR_INTR_MASK__MASK 0x00000400L +-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF11_FLR_INTR_MASK__MASK 0x00000800L +-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF12_FLR_INTR_MASK__MASK 0x00001000L +-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF13_FLR_INTR_MASK__MASK 0x00002000L +-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF14_FLR_INTR_MASK__MASK 0x00004000L +-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF15_FLR_INTR_MASK__MASK 0x00008000L +-#define BIF_PF0_VF_FLR_INTR_MASK__PF0_SOFTPF_FLR_INTR_MASK__MASK 0x80000000L +-//BIF_PF_FLR_RST +-#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST__MASK 0x00000001L +-#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST__MASK 0x00000002L +-#define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST__MASK 0x00000004L +-#define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST__MASK 0x00000008L +-#define BIF_PF_FLR_RST__DEV0_PF4_FLR_RST__MASK 0x00000010L +-#define BIF_PF_FLR_RST__DEV0_PF5_FLR_RST__MASK 0x00000020L +-#define BIF_PF_FLR_RST__DEV0_PF6_FLR_RST__MASK 0x00000040L +-#define BIF_PF_FLR_RST__DEV0_PF7_FLR_RST__MASK 0x00000080L +-//BIF_PF0_VF_FLR_RST +-#define BIF_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__MASK 0x00000001L +-#define BIF_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__MASK 0x00000002L +-#define BIF_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__MASK 0x00000004L +-#define BIF_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__MASK 0x00000008L +-#define BIF_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__MASK 0x00000010L +-#define BIF_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__MASK 0x00000020L +-#define BIF_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__MASK 0x00000040L +-#define BIF_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__MASK 0x00000080L +-#define BIF_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__MASK 0x00000100L +-#define BIF_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__MASK 0x00000200L +-#define BIF_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__MASK 0x00000400L +-#define BIF_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__MASK 0x00000800L +-#define BIF_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__MASK 0x00001000L +-#define BIF_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__MASK 0x00002000L +-#define BIF_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__MASK 0x00004000L +-#define BIF_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__MASK 0x00008000L +-#define BIF_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__MASK 0x80000000L +-//BIF_DEV0_PF0_DSTATE_VALUE +-#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE__MASK 0x00000003L +-#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L +-#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE__MASK 0x00030000L +-//BIF_DEV0_PF1_DSTATE_VALUE +-#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE__MASK 0x00000003L +-#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L +-#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE__MASK 0x00030000L +-//BIF_DEV0_PF2_DSTATE_VALUE +-#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE__MASK 0x00000003L +-#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L +-#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE__MASK 0x00030000L +-//BIF_DEV0_PF3_DSTATE_VALUE +-#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE__MASK 0x00000003L +-#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L +-#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE__MASK 0x00030000L +-//BIF_DEV0_PF4_DSTATE_VALUE +-#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE__MASK 0x00000003L +-#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L +-#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE__MASK 0x00030000L +-//BIF_DEV0_PF5_DSTATE_VALUE +-#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE__MASK 0x00000003L +-#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L +-#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE__MASK 0x00030000L +-//BIF_DEV0_PF6_DSTATE_VALUE +-#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE__MASK 0x00000003L +-#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L +-#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE__MASK 0x00030000L +-//BIF_DEV0_PF7_DSTATE_VALUE +-#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE__MASK 0x00000003L +-#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L +-#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE__MASK 0x00030000L +-//DEV0_PF0_D3HOTD0_RST_CTRL +-#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L +-#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L +-#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L +-#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L +-#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L +-//DEV0_PF1_D3HOTD0_RST_CTRL +-#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L +-#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L +-#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L +-#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L +-#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L +-//DEV0_PF2_D3HOTD0_RST_CTRL +-#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L +-#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L +-#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L +-#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L +-#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L +-//DEV0_PF3_D3HOTD0_RST_CTRL +-#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L +-#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L +-#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L +-#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L +-#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L +-//DEV0_PF4_D3HOTD0_RST_CTRL +-#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L +-#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L +-#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L +-#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L +-#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L +-//DEV0_PF5_D3HOTD0_RST_CTRL +-#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L +-#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L +-#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L +-#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L +-#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L +-//DEV0_PF6_D3HOTD0_RST_CTRL +-#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L +-#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L +-#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L +-#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L +-#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L +-//DEV0_PF7_D3HOTD0_RST_CTRL +-#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L +-#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L +-#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L +-#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L +-#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L +-//BIF_PORT0_DSTATE_VALUE +-#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE__MASK 0x00000003L +-#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE__MASK 0x00030000L +- +- +-// addressBlock: bif_misc_bif_misc_regblk +-//MISC_SCRATCH +-#define MISC_SCRATCH__MISC_SCRATCH0__MASK 0xFFFFFFFFL +-//INTR_LINE_POLARITY +-#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0__MASK 0x000000FFL +-//INTR_LINE_ENABLE +-#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0__MASK 0x000000FFL +-//OUTSTANDING_VC_ALLOC +-#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC__MASK 0x00000003L +-#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC__MASK 0x0000000CL +-#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC__MASK 0x00000030L +-#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC__MASK 0x000000C0L +-#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC__MASK 0x00000300L +-#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC__MASK 0x00000C00L +-#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC__MASK 0x00003000L +-#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC__MASK 0x0000C000L +-#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD__MASK 0x000F0000L +-#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC__MASK 0x03000000L +-#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC__MASK 0x0C000000L +-#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD__MASK 0xF0000000L +-//BIFC_MISC_CTRL0 +-#define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN__MASK 0x00000001L +-#define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN__MASK 0x00000006L +-#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE__MASK 0x00000100L +-#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK__MASK 0x00000200L +-#define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK__MASK 0x00000400L +-#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS__MASK 0x00010000L +-#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL__MASK 0x00020000L +-#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS__MASK 0x01000000L +-#define BIFC_MISC_CTRL0__VC7_DMA_IOCFG_DIS__MASK 0x02000000L +-#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS__MASK 0x04000000L +-#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE__MASK 0x08000000L +-#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE__MASK 0x10000000L +-#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION__MASK 0x80000000L +-//BIFC_MISC_CTRL1 +-#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT__MASK 0x00000001L +-#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT__MASK 0x00000002L +-#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT__MASK 0x00000004L +-#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT__MASK 0x00000008L +-#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS__MASK 0x00000010L +-#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR__MASK 0x00000020L +-#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS__MASK 0x00000040L +-#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL__MASK 0x00000080L +-#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS__MASK 0x00000300L +-#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS__MASK 0x00000C00L +-#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ__MASK 0x00001000L +-#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE__MASK 0x00002000L +-#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE__MASK 0x00004000L +-#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1__MASK 0x00008000L +-#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS__MASK 0x00010000L +-#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS__MASK 0x00020000L +-#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS__MASK 0x00040000L +-#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS__MASK 0x00080000L +-//BIFC_BME_ERR_LOG +-#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F0__MASK 0x00000001L +-#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F1__MASK 0x00000002L +-#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F2__MASK 0x00000004L +-#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F3__MASK 0x00000008L +-#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F4__MASK 0x00000010L +-#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F5__MASK 0x00000020L +-#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F6__MASK 0x00000040L +-#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F7__MASK 0x00000080L +-#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F0__MASK 0x00010000L +-#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F1__MASK 0x00020000L +-#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F2__MASK 0x00040000L +-#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F3__MASK 0x00080000L +-#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F4__MASK 0x00100000L +-#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F5__MASK 0x00200000L +-#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F6__MASK 0x00400000L +-#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F7__MASK 0x00800000L +-//BIFC_RCCBIH_BME_ERR_LOG +-#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F0__MASK 0x00000001L +-#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F1__MASK 0x00000002L +-#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F2__MASK 0x00000004L +-#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F3__MASK 0x00000008L +-#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F4__MASK 0x00000010L +-#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F5__MASK 0x00000020L +-#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F6__MASK 0x00000040L +-#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F7__MASK 0x00000080L +-#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__MASK 0x00010000L +-#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__MASK 0x00020000L +-#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2__MASK 0x00040000L +-#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3__MASK 0x00080000L +-#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4__MASK 0x00100000L +-#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5__MASK 0x00200000L +-#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6__MASK 0x00400000L +-#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7__MASK 0x00800000L +-//BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0__MASK 0x00000003L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0__MASK 0x0000000CL +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0__MASK 0x000000C0L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0__MASK 0x00000300L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0__MASK 0x00000C00L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0__MASK 0x00003000L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1__MASK 0x00030000L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1__MASK 0x000C0000L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1__MASK 0x00C00000L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1__MASK 0x03000000L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1__MASK 0x0C000000L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1__MASK 0x30000000L +-//BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2__MASK 0x00000003L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2__MASK 0x0000000CL +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2__MASK 0x000000C0L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2__MASK 0x00000300L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2__MASK 0x00000C00L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2__MASK 0x00003000L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3__MASK 0x00030000L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3__MASK 0x000C0000L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3__MASK 0x00C00000L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3__MASK 0x03000000L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3__MASK 0x0C000000L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3__MASK 0x30000000L +-//BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4__MASK 0x00000003L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4__MASK 0x0000000CL +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4__MASK 0x000000C0L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4__MASK 0x00000300L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4__MASK 0x00000C00L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4__MASK 0x00003000L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5__MASK 0x00030000L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5__MASK 0x000C0000L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5__MASK 0x00C00000L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5__MASK 0x03000000L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5__MASK 0x0C000000L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5__MASK 0x30000000L +-//BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6__MASK 0x00000003L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6__MASK 0x0000000CL +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6__MASK 0x000000C0L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6__MASK 0x00000300L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6__MASK 0x00000C00L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6__MASK 0x00003000L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7__MASK 0x00030000L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7__MASK 0x000C0000L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7__MASK 0x00C00000L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7__MASK 0x03000000L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7__MASK 0x0C000000L +-#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7__MASK 0x30000000L +-//NBIF_VWIRE_CTRL +-#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT__MASK 0x000000F0L +-#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED__MASK 0x00000100L +-#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT__MASK 0x00F00000L +-#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL__MASK 0x0C000000L +-//NBIF_SMN_VWR_VCHG_DIS_CTRL +-#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS__MASK 0x00000001L +-#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS__MASK 0x00000002L +-#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS__MASK 0x00000004L +-#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS__MASK 0x00000008L +-#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS__MASK 0x00000010L +-#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS__MASK 0x00000020L +-#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS__MASK 0x00000040L +-//NBIF_SMN_VWR_VCHG_RST_CTRL0 +-#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV__MASK 0x00000001L +-#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV__MASK 0x00000002L +-#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV__MASK 0x00000004L +-#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV__MASK 0x00000008L +-#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV__MASK 0x00000010L +-#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV__MASK 0x00000020L +-#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV__MASK 0x00000040L +-//NBIF_SMN_VWR_VCHG_TRIG +-#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG__MASK 0x00000001L +-#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG__MASK 0x00000002L +-#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG__MASK 0x00000004L +-#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG__MASK 0x00000008L +-#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG__MASK 0x00000010L +-#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG__MASK 0x00000020L +-#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG__MASK 0x00000040L +-//NBIF_SMN_VWR_WTRIG_CNTL +-#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS__MASK 0x00000001L +-#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS__MASK 0x00000002L +-#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS__MASK 0x00000004L +-#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS__MASK 0x00000008L +-#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS__MASK 0x00000010L +-#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS__MASK 0x00000020L +-#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS__MASK 0x00000040L +-//NBIF_SMN_VWR_VCHG_DIS_CTRL_1 +-#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV__MASK 0x00000001L +-#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV__MASK 0x00000002L +-#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV__MASK 0x00000004L +-#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV__MASK 0x00000008L +-#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV__MASK 0x00000010L +-#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV__MASK 0x00000020L +-#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV__MASK 0x00000040L +-//NBIF_MGCG_CTRL +-#define NBIF_MGCG_CTRL__NBIF_MGCG_EN__MASK 0x00000001L +-#define NBIF_MGCG_CTRL__NBIF_MGCG_MODE__MASK 0x00000002L +-#define NBIF_MGCG_CTRL__NBIF_MGCG_HYSTERESIS__MASK 0x000003FCL +-//NBIF_DS_CTRL_LCLK +-#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN__MASK 0x00000001L +-#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER__MASK 0xFFFF0000L +-//SMN_MST_CNTL0 +-#define SMN_MST_CNTL0__SMN_ARB_MODE__MASK 0x00000003L +-#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS__MASK 0x00000100L +-#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS__MASK 0x00000200L +-#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS__MASK 0x00000400L +-#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS__MASK 0x00000800L +-#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0__MASK 0x00010000L +-#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0__MASK 0x00100000L +-#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0__MASK 0x01000000L +-#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0__MASK 0x10000000L +-//SMN_MST_EP_CNTL1 +-#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0__MASK 0x00000001L +-#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1__MASK 0x00000002L +-#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2__MASK 0x00000004L +-#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3__MASK 0x00000008L +-#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4__MASK 0x00000010L +-#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5__MASK 0x00000020L +-#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6__MASK 0x00000040L +-#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7__MASK 0x00000080L +-//SMN_MST_EP_CNTL2 +-#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0__MASK 0x00000001L +-#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1__MASK 0x00000002L +-#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2__MASK 0x00000004L +-#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3__MASK 0x00000008L +-#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4__MASK 0x00000010L +-#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5__MASK 0x00000020L +-#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6__MASK 0x00000040L +-#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7__MASK 0x00000080L +-//NBIF_SDP_VWR_VCHG_DIS_CTRL +-#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS__MASK 0x00000001L +-#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS__MASK 0x00000002L +-#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS__MASK 0x00000004L +-#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS__MASK 0x00000008L +-#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS__MASK 0x00000010L +-#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS__MASK 0x00000020L +-#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS__MASK 0x00000040L +-#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS__MASK 0x00000080L +-#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS__MASK 0x01000000L +-//NBIF_SDP_VWR_VCHG_RST_CTRL0 +-#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN__MASK 0x00000001L +-#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN__MASK 0x00000002L +-#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN__MASK 0x00000004L +-#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN__MASK 0x00000008L +-#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN__MASK 0x00000010L +-#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN__MASK 0x00000020L +-#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN__MASK 0x00000040L +-#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN__MASK 0x00000080L +-#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN__MASK 0x01000000L +-//NBIF_SDP_VWR_VCHG_RST_CTRL1 +-#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL__MASK 0x00000001L +-#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL__MASK 0x00000002L +-#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL__MASK 0x00000004L +-#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL__MASK 0x00000008L +-#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL__MASK 0x00000010L +-#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL__MASK 0x00000020L +-#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL__MASK 0x00000040L +-#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL__MASK 0x00000080L +-#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL__MASK 0x01000000L +-//NBIF_SDP_VWR_VCHG_TRIG +-#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG__MASK 0x00000001L +-#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG__MASK 0x00000002L +-#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG__MASK 0x00000004L +-#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG__MASK 0x00000008L +-#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG__MASK 0x00000010L +-#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG__MASK 0x00000020L +-#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG__MASK 0x00000040L +-#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG__MASK 0x00000080L +-#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG__MASK 0x01000000L +-//BME_DUMMY_CNTL_0 +-#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0__MASK 0x00000003L +-#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1__MASK 0x0000000CL +-#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2__MASK 0x00000030L +-#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3__MASK 0x000000C0L +-#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4__MASK 0x00000300L +-#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5__MASK 0x00000C00L +-#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6__MASK 0x00003000L +-#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7__MASK 0x0000C000L +-//BIFC_THT_CNTL +-#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0__MASK 0x0000000FL +-#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0__MASK 0x000000F0L +-#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1__MASK 0x00000F00L +-//BIFC_HSTARB_CNTL +-#define BIFC_HSTARB_CNTL__SLVARB_MODE__MASK 0x00000003L +-//BIFC_GSI_CNTL +-#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE__MASK 0x00000003L +-#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE__MASK 0x0000001CL +-#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN__MASK 0x00000020L +-#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN__MASK 0x00000040L +-#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN__MASK 0x00000080L +-#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN__MASK 0x00000100L +-#define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN__MASK 0x00000200L +-#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE__MASK 0x00000C00L +-#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE__MASK 0x00003000L +-//BIFC_PCIEFUNC_CNTL +-#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC__MASK 0x0000FFFFL +-#define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC__MASK 0x00010000L +-//BIFC_SDP_CNTL_0 +-#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS__MASK 0x0000003FL +-#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS__MASK 0x00000FC0L +-#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS__MASK 0x0003F000L +-#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS__MASK 0x00FC0000L +-//BIFC_PERF_CNTL_0 +-#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN__MASK 0x00000001L +-#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN__MASK 0x00000002L +-#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET__MASK 0x00000100L +-#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET__MASK 0x00000200L +-#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL__MASK 0x001F0000L +-#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL__MASK 0x1F000000L +-//BIFC_PERF_CNTL_1 +-#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN__MASK 0x00000001L +-#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN__MASK 0x00000002L +-#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET__MASK 0x00000100L +-#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET__MASK 0x00000200L +-#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL__MASK 0x003F0000L +-#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL__MASK 0x7F000000L +-//BIFC_PERF_CNT_MMIO_RD +-#define BIFC_PERF_CNT_MMIO_RD__PERF_CNT_MMIO_RD_VALUE__MASK 0xFFFFFFFFL +-//BIFC_PERF_CNT_MMIO_WR +-#define BIFC_PERF_CNT_MMIO_WR__PERF_CNT_MMIO_WR_VALUE__MASK 0xFFFFFFFFL +-//BIFC_PERF_CNT_DMA_RD +-#define BIFC_PERF_CNT_DMA_RD__PERF_CNT_DMA_RD_VALUE__MASK 0xFFFFFFFFL +-//BIFC_PERF_CNT_DMA_WR +-#define BIFC_PERF_CNT_DMA_WR__PERF_CNT_DMA_WR_VALUE__MASK 0xFFFFFFFFL +-//NBIF_REGIF_ERRSET_CTRL +-#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS__MASK 0x00000001L +-//SMN_MST_EP_CNTL3 +-#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0__MASK 0x00000001L +-#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1__MASK 0x00000002L +-#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2__MASK 0x00000004L +-#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3__MASK 0x00000008L +-#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4__MASK 0x00000010L +-#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5__MASK 0x00000020L +-#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6__MASK 0x00000040L +-#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7__MASK 0x00000080L +-//SMN_MST_EP_CNTL4 +-#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0__MASK 0x00000001L +-#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1__MASK 0x00000002L +-#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2__MASK 0x00000004L +-#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3__MASK 0x00000008L +-#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4__MASK 0x00000010L +-#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5__MASK 0x00000020L +-#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6__MASK 0x00000040L +-#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7__MASK 0x00000080L +-//BIF_SELFRING_BUFFER_VID +-#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID__MASK 0x000000FFL +-#define BIF_SELFRING_BUFFER_VID__IOHUB_RAS_INTR_CID__MASK 0x0000FF00L +-//BIF_SELFRING_VECTOR_CNTL +-#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS__MASK 0x00000001L +- +- +-// addressBlock: bif_ras_bif_ras_regblk +-//BIF_RAS_LEAF0_CTRL +-#define BIF_RAS_LEAF0_CTRL__POISON_DET_EN__MASK 0x00000001L +-#define BIF_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L +-#define BIF_RAS_LEAF0_CTRL__POISON_STALL_EN__MASK 0x00000004L +-#define BIF_RAS_LEAF0_CTRL__PARITY_DET_EN__MASK 0x00000010L +-#define BIF_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L +-#define BIF_RAS_LEAF0_CTRL__PARITY_STALL_EN__MASK 0x00000040L +-#define BIF_RAS_LEAF0_CTRL__ERR_EVENT_RECV__MASK 0x00010000L +-#define BIF_RAS_LEAF0_CTRL__LINK_DIS_RECV__MASK 0x00020000L +-#define BIF_RAS_LEAF0_CTRL__POISON_ERR_DET__MASK 0x00040000L +-#define BIF_RAS_LEAF0_CTRL__PARITY_ERR_DET__MASK 0x00080000L +-#define BIF_RAS_LEAF0_CTRL__ERR_EVENT_SENT__MASK 0x00100000L +-#define BIF_RAS_LEAF0_CTRL__EGRESS_STALLED__MASK 0x00200000L +-//BIF_RAS_LEAF1_CTRL +-#define BIF_RAS_LEAF1_CTRL__POISON_DET_EN__MASK 0x00000001L +-#define BIF_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L +-#define BIF_RAS_LEAF1_CTRL__POISON_STALL_EN__MASK 0x00000004L +-#define BIF_RAS_LEAF1_CTRL__PARITY_DET_EN__MASK 0x00000010L +-#define BIF_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L +-#define BIF_RAS_LEAF1_CTRL__PARITY_STALL_EN__MASK 0x00000040L +-#define BIF_RAS_LEAF1_CTRL__ERR_EVENT_RECV__MASK 0x00010000L +-#define BIF_RAS_LEAF1_CTRL__LINK_DIS_RECV__MASK 0x00020000L +-#define BIF_RAS_LEAF1_CTRL__POISON_ERR_DET__MASK 0x00040000L +-#define BIF_RAS_LEAF1_CTRL__PARITY_ERR_DET__MASK 0x00080000L +-#define BIF_RAS_LEAF1_CTRL__ERR_EVENT_SENT__MASK 0x00100000L +-#define BIF_RAS_LEAF1_CTRL__EGRESS_STALLED__MASK 0x00200000L +-//BIF_RAS_LEAF2_CTRL +-#define BIF_RAS_LEAF2_CTRL__POISON_DET_EN__MASK 0x00000001L +-#define BIF_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L +-#define BIF_RAS_LEAF2_CTRL__POISON_STALL_EN__MASK 0x00000004L +-#define BIF_RAS_LEAF2_CTRL__PARITY_DET_EN__MASK 0x00000010L +-#define BIF_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L +-#define BIF_RAS_LEAF2_CTRL__PARITY_STALL_EN__MASK 0x00000040L +-#define BIF_RAS_LEAF2_CTRL__ERR_EVENT_RECV__MASK 0x00010000L +-#define BIF_RAS_LEAF2_CTRL__LINK_DIS_RECV__MASK 0x00020000L +-#define BIF_RAS_LEAF2_CTRL__POISON_ERR_DET__MASK 0x00040000L +-#define BIF_RAS_LEAF2_CTRL__PARITY_ERR_DET__MASK 0x00080000L +-#define BIF_RAS_LEAF2_CTRL__ERR_EVENT_SENT__MASK 0x00100000L +-#define BIF_RAS_LEAF2_CTRL__EGRESS_STALLED__MASK 0x00200000L +-//BIF_RAS_MISC_CTRL +-#define BIF_RAS_MISC_CTRL__LINKDIS_TRIG_ERREVENT_EN__MASK 0x00000001L +-//BIF_IOHUB_RAS_IH_CNTL +-#define BIF_IOHUB_RAS_IH_CNTL__RAS_IH_INTR_EN__MASK 0x00000001L +-//BIF_RAS_VWR_FROM_IOHUB +-#define BIF_RAS_VWR_FROM_IOHUB__RAS_IH_INTR_TRIG__MASK 0x00000001L +- +- +-// addressBlock: rcc_pfc_amdgfx_RCCPFCDEC +-//RCC_PFC_LTR_CNTL +-#define RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__MASK 0x000003FFL +-#define RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__MASK 0x00001C00L +-#define RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__MASK 0x00008000L +-#define RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__MASK 0x03FF0000L +-#define RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__MASK 0x1C000000L +-#define RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__MASK 0x80000000L +-//RCC_PFC_PME_RESTORE +-#define RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__MASK 0x00000001L +-#define RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__MASK 0x00000100L +-//RCC_PFC_STICKY_RESTORE_0 +-#define RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__MASK 0x00000001L +-#define RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__MASK 0x00000002L +-#define RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__MASK 0x00000004L +-#define RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__MASK 0x00000008L +-#define RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__MASK 0x00000010L +-#define RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__MASK 0x00000020L +-#define RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__MASK 0x00000040L +-#define RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__MASK 0x00000080L +-//RCC_PFC_STICKY_RESTORE_1 +-#define RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__MASK 0xFFFFFFFFL +-//RCC_PFC_STICKY_RESTORE_2 +-#define RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__MASK 0xFFFFFFFFL +-//RCC_PFC_STICKY_RESTORE_3 +-#define RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__MASK 0xFFFFFFFFL +-//RCC_PFC_STICKY_RESTORE_4 +-#define RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__MASK 0xFFFFFFFFL +-//RCC_PFC_STICKY_RESTORE_5 +-#define RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__MASK 0xFFFFFFFFL +-//RCC_PFC_AUXPWR_CNTL +-#define RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__MASK 0x00000007L +-#define RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__MASK 0x00000008L +- +- +-// addressBlock: rcc_pfc_amdgfxaz_RCCPFCDEC +-//RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL +-#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__MASK 0x000003FFL +-#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__MASK 0x00001C00L +-#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__MASK 0x00008000L +-#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__MASK 0x03FF0000L +-#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__MASK 0x1C000000L +-#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__MASK 0x80000000L +-//RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE +-#define RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__MASK 0x00000001L +-#define RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__MASK 0x00000100L +-//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0 +-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__MASK 0x00000001L +-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__MASK 0x00000002L +-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__MASK 0x00000004L +-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__MASK 0x00000008L +-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__MASK 0x00000010L +-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__MASK 0x00000020L +-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__MASK 0x00000040L +-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__MASK 0x00000080L +-//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1 +-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__MASK 0xFFFFFFFFL +-//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2 +-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__MASK 0xFFFFFFFFL +-//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3 +-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__MASK 0xFFFFFFFFL +-//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4 +-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__MASK 0xFFFFFFFFL +-//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5 +-#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__MASK 0xFFFFFFFFL +-//RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL +-#define RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__MASK 0x00000007L +-#define RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__MASK 0x00000008L +- +- +-// addressBlock: pciemsix_amdgfx_MSIXTDEC +-//PCIEMSIX_VECT0_ADDR_LO +-#define PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL +-//PCIEMSIX_VECT0_ADDR_HI +-#define PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT0_MSG_DATA +-#define PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT0_CONTROL +-#define PCIEMSIX_VECT0_CONTROL__MASK_BIT__MASK 0x00000001L +-//PCIEMSIX_VECT1_ADDR_LO +-#define PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL +-//PCIEMSIX_VECT1_ADDR_HI +-#define PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT1_MSG_DATA +-#define PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT1_CONTROL +-#define PCIEMSIX_VECT1_CONTROL__MASK_BIT__MASK 0x00000001L +-//PCIEMSIX_VECT2_ADDR_LO +-#define PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL +-//PCIEMSIX_VECT2_ADDR_HI +-#define PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT2_MSG_DATA +-#define PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT2_CONTROL +-#define PCIEMSIX_VECT2_CONTROL__MASK_BIT__MASK 0x00000001L +-//PCIEMSIX_VECT3_ADDR_LO +-#define PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL +-//PCIEMSIX_VECT3_ADDR_HI +-#define PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT3_MSG_DATA +-#define PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT3_CONTROL +-#define PCIEMSIX_VECT3_CONTROL__MASK_BIT__MASK 0x00000001L +-//PCIEMSIX_VECT4_ADDR_LO +-#define PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL +-//PCIEMSIX_VECT4_ADDR_HI +-#define PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT4_MSG_DATA +-#define PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT4_CONTROL +-#define PCIEMSIX_VECT4_CONTROL__MASK_BIT__MASK 0x00000001L +-//PCIEMSIX_VECT5_ADDR_LO +-#define PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL +-//PCIEMSIX_VECT5_ADDR_HI +-#define PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT5_MSG_DATA +-#define PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT5_CONTROL +-#define PCIEMSIX_VECT5_CONTROL__MASK_BIT__MASK 0x00000001L +-//PCIEMSIX_VECT6_ADDR_LO +-#define PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL +-//PCIEMSIX_VECT6_ADDR_HI +-#define PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT6_MSG_DATA +-#define PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT6_CONTROL +-#define PCIEMSIX_VECT6_CONTROL__MASK_BIT__MASK 0x00000001L +-//PCIEMSIX_VECT7_ADDR_LO +-#define PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL +-//PCIEMSIX_VECT7_ADDR_HI +-#define PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT7_MSG_DATA +-#define PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT7_CONTROL +-#define PCIEMSIX_VECT7_CONTROL__MASK_BIT__MASK 0x00000001L +-//PCIEMSIX_VECT8_ADDR_LO +-#define PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL +-//PCIEMSIX_VECT8_ADDR_HI +-#define PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT8_MSG_DATA +-#define PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT8_CONTROL +-#define PCIEMSIX_VECT8_CONTROL__MASK_BIT__MASK 0x00000001L +-//PCIEMSIX_VECT9_ADDR_LO +-#define PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL +-//PCIEMSIX_VECT9_ADDR_HI +-#define PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT9_MSG_DATA +-#define PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT9_CONTROL +-#define PCIEMSIX_VECT9_CONTROL__MASK_BIT__MASK 0x00000001L +-//PCIEMSIX_VECT10_ADDR_LO +-#define PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL +-//PCIEMSIX_VECT10_ADDR_HI +-#define PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT10_MSG_DATA +-#define PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT10_CONTROL +-#define PCIEMSIX_VECT10_CONTROL__MASK_BIT__MASK 0x00000001L +-//PCIEMSIX_VECT11_ADDR_LO +-#define PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL +-//PCIEMSIX_VECT11_ADDR_HI +-#define PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT11_MSG_DATA +-#define PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT11_CONTROL +-#define PCIEMSIX_VECT11_CONTROL__MASK_BIT__MASK 0x00000001L +-//PCIEMSIX_VECT12_ADDR_LO +-#define PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL +-//PCIEMSIX_VECT12_ADDR_HI +-#define PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT12_MSG_DATA +-#define PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT12_CONTROL +-#define PCIEMSIX_VECT12_CONTROL__MASK_BIT__MASK 0x00000001L +-//PCIEMSIX_VECT13_ADDR_LO +-#define PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL +-//PCIEMSIX_VECT13_ADDR_HI +-#define PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT13_MSG_DATA +-#define PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT13_CONTROL +-#define PCIEMSIX_VECT13_CONTROL__MASK_BIT__MASK 0x00000001L +-//PCIEMSIX_VECT14_ADDR_LO +-#define PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL +-//PCIEMSIX_VECT14_ADDR_HI +-#define PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT14_MSG_DATA +-#define PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT14_CONTROL +-#define PCIEMSIX_VECT14_CONTROL__MASK_BIT__MASK 0x00000001L +-//PCIEMSIX_VECT15_ADDR_LO +-#define PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL +-//PCIEMSIX_VECT15_ADDR_HI +-#define PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT15_MSG_DATA +-#define PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT15_CONTROL +-#define PCIEMSIX_VECT15_CONTROL__MASK_BIT__MASK 0x00000001L +-//PCIEMSIX_VECT16_ADDR_LO +-#define PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL +-//PCIEMSIX_VECT16_ADDR_HI +-#define PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT16_MSG_DATA +-#define PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT16_CONTROL +-#define PCIEMSIX_VECT16_CONTROL__MASK_BIT__MASK 0x00000001L +-//PCIEMSIX_VECT17_ADDR_LO +-#define PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL +-//PCIEMSIX_VECT17_ADDR_HI +-#define PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT17_MSG_DATA +-#define PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT17_CONTROL +-#define PCIEMSIX_VECT17_CONTROL__MASK_BIT__MASK 0x00000001L +-//PCIEMSIX_VECT18_ADDR_LO +-#define PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL +-//PCIEMSIX_VECT18_ADDR_HI +-#define PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT18_MSG_DATA +-#define PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT18_CONTROL +-#define PCIEMSIX_VECT18_CONTROL__MASK_BIT__MASK 0x00000001L +-//PCIEMSIX_VECT19_ADDR_LO +-#define PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL +-//PCIEMSIX_VECT19_ADDR_HI +-#define PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT19_MSG_DATA +-#define PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT19_CONTROL +-#define PCIEMSIX_VECT19_CONTROL__MASK_BIT__MASK 0x00000001L +-//PCIEMSIX_VECT20_ADDR_LO +-#define PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL +-//PCIEMSIX_VECT20_ADDR_HI +-#define PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT20_MSG_DATA +-#define PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT20_CONTROL +-#define PCIEMSIX_VECT20_CONTROL__MASK_BIT__MASK 0x00000001L +-//PCIEMSIX_VECT21_ADDR_LO +-#define PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL +-//PCIEMSIX_VECT21_ADDR_HI +-#define PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT21_MSG_DATA +-#define PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT21_CONTROL +-#define PCIEMSIX_VECT21_CONTROL__MASK_BIT__MASK 0x00000001L +-//PCIEMSIX_VECT22_ADDR_LO +-#define PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL +-//PCIEMSIX_VECT22_ADDR_HI +-#define PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT22_MSG_DATA +-#define PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT22_CONTROL +-#define PCIEMSIX_VECT22_CONTROL__MASK_BIT__MASK 0x00000001L +-//PCIEMSIX_VECT23_ADDR_LO +-#define PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL +-//PCIEMSIX_VECT23_ADDR_HI +-#define PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT23_MSG_DATA +-#define PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT23_CONTROL +-#define PCIEMSIX_VECT23_CONTROL__MASK_BIT__MASK 0x00000001L +-//PCIEMSIX_VECT24_ADDR_LO +-#define PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL +-//PCIEMSIX_VECT24_ADDR_HI +-#define PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT24_MSG_DATA +-#define PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT24_CONTROL +-#define PCIEMSIX_VECT24_CONTROL__MASK_BIT__MASK 0x00000001L +-//PCIEMSIX_VECT25_ADDR_LO +-#define PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL +-//PCIEMSIX_VECT25_ADDR_HI +-#define PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT25_MSG_DATA +-#define PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT25_CONTROL +-#define PCIEMSIX_VECT25_CONTROL__MASK_BIT__MASK 0x00000001L +-//PCIEMSIX_VECT26_ADDR_LO +-#define PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL +-//PCIEMSIX_VECT26_ADDR_HI +-#define PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT26_MSG_DATA +-#define PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT26_CONTROL +-#define PCIEMSIX_VECT26_CONTROL__MASK_BIT__MASK 0x00000001L +-//PCIEMSIX_VECT27_ADDR_LO +-#define PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL +-//PCIEMSIX_VECT27_ADDR_HI +-#define PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT27_MSG_DATA +-#define PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT27_CONTROL +-#define PCIEMSIX_VECT27_CONTROL__MASK_BIT__MASK 0x00000001L +-//PCIEMSIX_VECT28_ADDR_LO +-#define PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL +-//PCIEMSIX_VECT28_ADDR_HI +-#define PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT28_MSG_DATA +-#define PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT28_CONTROL +-#define PCIEMSIX_VECT28_CONTROL__MASK_BIT__MASK 0x00000001L +-//PCIEMSIX_VECT29_ADDR_LO +-#define PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL +-//PCIEMSIX_VECT29_ADDR_HI +-#define PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT29_MSG_DATA +-#define PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT29_CONTROL +-#define PCIEMSIX_VECT29_CONTROL__MASK_BIT__MASK 0x00000001L +-//PCIEMSIX_VECT30_ADDR_LO +-#define PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL +-//PCIEMSIX_VECT30_ADDR_HI +-#define PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT30_MSG_DATA +-#define PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT30_CONTROL +-#define PCIEMSIX_VECT30_CONTROL__MASK_BIT__MASK 0x00000001L +-//PCIEMSIX_VECT31_ADDR_LO +-#define PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL +-//PCIEMSIX_VECT31_ADDR_HI +-#define PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT31_MSG_DATA +-#define PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL +-//PCIEMSIX_VECT31_CONTROL +-#define PCIEMSIX_VECT31_CONTROL__MASK_BIT__MASK 0x00000001L +- +- +-// addressBlock: pciemsix_amdgfx_MSIXPDEC +-//PCIEMSIX_PBA +-#define PCIEMSIX_PBA__MSIX_PENDING_BITS__MASK 0xFFFFFFFFL +- +- +-// addressBlock: syshub_mmreg_ind_syshubind +-//SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000001L +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000002L +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000004L +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000008L +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000010L +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000020L +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000040L +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000080L +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00010000L +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00020000L +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00040000L +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00080000L +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00100000L +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00200000L +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00400000L +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00800000L +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x10000000L +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__MASK 0x80000000L +-//SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__MASK 0x0000FFFFL +-//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK +-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en__MASK 0x00000001L +-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en__MASK 0x00000002L +-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__MASK 0x00008000L +-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en__MASK 0x00010000L +-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en__MASK 0x00020000L +-//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK +-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en__MASK 0x00000001L +-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en__MASK 0x00000002L +-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__MASK 0x00008000L +-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en__MASK 0x00010000L +-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en__MASK 0x00020000L +-//SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L +-//SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL +-#define SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L +-#define SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL +-#define SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L +-//SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L +-//SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L +-//SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L +-//SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L +-//SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L +-//SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L +-#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L +-//SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL +-#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L +-#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L +-#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L +-#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L +-#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L +-#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L +-//SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL +-#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L +-#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L +-#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L +-#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L +-#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L +-#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L +-//SYSHUBMMREGIND_SYSHUB_CG_CNTL +-#define SYSHUBMMREGIND_SYSHUB_CG_CNTL__SYSHUB_CG_EN__MASK 0x00000001L +-#define SYSHUBMMREGIND_SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER__MASK 0x0000FF00L +-#define SYSHUBMMREGIND_SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER__MASK 0x00FF0000L +-//SYSHUBMMREGIND_SYSHUB_TRANS_IDLE +-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0__MASK 0x00000001L +-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1__MASK 0x00000002L +-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2__MASK 0x00000004L +-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3__MASK 0x00000008L +-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4__MASK 0x00000010L +-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5__MASK 0x00000020L +-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6__MASK 0x00000040L +-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7__MASK 0x00000080L +-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8__MASK 0x00000100L +-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9__MASK 0x00000200L +-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10__MASK 0x00000400L +-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11__MASK 0x00000800L +-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12__MASK 0x00001000L +-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13__MASK 0x00002000L +-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14__MASK 0x00004000L +-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15__MASK 0x00008000L +-#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF__MASK 0x00010000L +-//SYSHUBMMREGIND_SYSHUB_HP_TIMER +-#define SYSHUBMMREGIND_SYSHUB_HP_TIMER__SYSHUB_HP_TIMER__MASK 0xFFFFFFFFL +-//SYSHUBMMREGIND_SYSHUB_SCRATCH +-#define SYSHUBMMREGIND_SYSHUB_SCRATCH__SCRATCH__MASK 0xFFFFFFFFL +-//SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000001L +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000002L +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000004L +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000008L +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000010L +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000020L +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000040L +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000080L +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00010000L +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00020000L +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00040000L +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00080000L +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00100000L +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00200000L +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00400000L +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00800000L +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x10000000L +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN__MASK 0x80000000L +-//SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK +-#define SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER__MASK 0x0000FFFFL +-//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK +-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en__MASK 0x00008000L +-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en__MASK 0x00010000L +-//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK +-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en__MASK 0x00008000L +-#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en__MASK 0x00010000L +-//SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L +-//SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L +-//SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L +-//SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L +-//SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L +-//SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L +-//SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L +-#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L +-//SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L +-//SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L +-//SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L +-//SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L +-//SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L +-#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L +- +-#endif +-- +2.7.4 + |