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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2254-drm-amd-include-cleanup-vega10-vce-header-files.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2254-drm-amd-include-cleanup-vega10-vce-header-files.patch1735
1 files changed, 1735 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2254-drm-amd-include-cleanup-vega10-vce-header-files.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2254-drm-amd-include-cleanup-vega10-vce-header-files.patch
new file mode 100644
index 00000000..2f8c44fd
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2254-drm-amd-include-cleanup-vega10-vce-header-files.patch
@@ -0,0 +1,1735 @@
+From 76519d6077d772f368c8b497d30e5adbc57aa2b5 Mon Sep 17 00:00:00 2001
+From: Feifei Xu <Feifei.Xu@amd.com>
+Date: Thu, 23 Nov 2017 14:08:34 +0800
+Subject: [PATCH 2254/4131] drm/amd/include:cleanup vega10 vce header files.
+
+Cleanup asic_reg/vega10/VCE folder.
+
+Change-Id: I60d71f93eecf4ecb3957d8ac18305641fe66b7f1
+Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 6 +-
+ drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 6 +-
+ .../drm/amd/include/asic_reg/vce/vce_4_0_default.h | 122 ++++++
+ .../drm/amd/include/asic_reg/vce/vce_4_0_offset.h | 208 +++++++++
+ .../drm/amd/include/asic_reg/vce/vce_4_0_sh_mask.h | 488 +++++++++++++++++++++
+ .../include/asic_reg/vega10/VCE/vce_4_0_default.h | 122 ------
+ .../include/asic_reg/vega10/VCE/vce_4_0_offset.h | 208 ---------
+ .../include/asic_reg/vega10/VCE/vce_4_0_sh_mask.h | 488 ---------------------
+ 8 files changed, 824 insertions(+), 824 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_default.h
+ create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_offset.h
+ create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_sh_mask.h
+ delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_default.h
+ delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_offset.h
+ delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_sh_mask.h
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+index 83e26ca..c122e95 100644
+--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+@@ -32,9 +32,9 @@
+ #include "vega10/soc15ip.h"
+ #include "uvd/uvd_7_0_offset.h"
+ #include "uvd/uvd_7_0_sh_mask.h"
+-#include "vega10/VCE/vce_4_0_offset.h"
+-#include "vega10/VCE/vce_4_0_default.h"
+-#include "vega10/VCE/vce_4_0_sh_mask.h"
++#include "vce/vce_4_0_offset.h"
++#include "vce/vce_4_0_default.h"
++#include "vce/vce_4_0_sh_mask.h"
+ #include "vega10/NBIF/nbif_6_1_offset.h"
+ #include "hdp/hdp_4_0_offset.h"
+ #include "vega10/MMHUB/mmhub_1_0_offset.h"
+diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+index 4a92530..d8bbc9b 100755
+--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
++++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+@@ -33,9 +33,9 @@
+ #include "mmsch_v1_0.h"
+
+ #include "vega10/soc15ip.h"
+-#include "vega10/VCE/vce_4_0_offset.h"
+-#include "vega10/VCE/vce_4_0_default.h"
+-#include "vega10/VCE/vce_4_0_sh_mask.h"
++#include "vce/vce_4_0_offset.h"
++#include "vce/vce_4_0_default.h"
++#include "vce/vce_4_0_sh_mask.h"
+ #include "vega10/MMHUB/mmhub_1_0_offset.h"
+ #include "vega10/MMHUB/mmhub_1_0_sh_mask.h"
+
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_default.h
+new file mode 100644
+index 0000000..c2a46c7
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_default.h
+@@ -0,0 +1,122 @@
++/*
++ * Copyright (C) 2017 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++#ifndef _vce_4_0_DEFAULT_HEADER
++#define _vce_4_0_DEFAULT_HEADER
++
++
++// addressBlock: vce0_vce_dec
++#define mmVCE_STATUS_DEFAULT 0x00000000
++#define mmVCE_VCPU_CNTL_DEFAULT 0x00200000
++#define mmVCE_VCPU_CACHE_OFFSET0_DEFAULT 0x00000000
++#define mmVCE_VCPU_CACHE_SIZE0_DEFAULT 0x00000000
++#define mmVCE_VCPU_CACHE_OFFSET1_DEFAULT 0x00000000
++#define mmVCE_VCPU_CACHE_SIZE1_DEFAULT 0x00000000
++#define mmVCE_VCPU_CACHE_OFFSET2_DEFAULT 0x00000000
++#define mmVCE_VCPU_CACHE_SIZE2_DEFAULT 0x00000000
++#define mmVCE_VCPU_CACHE_OFFSET3_DEFAULT 0x00000000
++#define mmVCE_VCPU_CACHE_SIZE3_DEFAULT 0x00000000
++#define mmVCE_VCPU_CACHE_OFFSET4_DEFAULT 0x00000000
++#define mmVCE_VCPU_CACHE_SIZE4_DEFAULT 0x00000000
++#define mmVCE_VCPU_CACHE_OFFSET5_DEFAULT 0x00000000
++#define mmVCE_VCPU_CACHE_SIZE5_DEFAULT 0x00000000
++#define mmVCE_VCPU_CACHE_OFFSET6_DEFAULT 0x00000000
++#define mmVCE_VCPU_CACHE_SIZE6_DEFAULT 0x00000000
++#define mmVCE_VCPU_CACHE_OFFSET7_DEFAULT 0x00000000
++#define mmVCE_VCPU_CACHE_SIZE7_DEFAULT 0x00000000
++#define mmVCE_VCPU_CACHE_OFFSET8_DEFAULT 0x00000000
++#define mmVCE_VCPU_CACHE_SIZE8_DEFAULT 0x00000000
++#define mmVCE_SOFT_RESET_DEFAULT 0x00000001
++#define mmVCE_RB_BASE_LO2_DEFAULT 0x00000000
++#define mmVCE_RB_BASE_HI2_DEFAULT 0x00000000
++#define mmVCE_RB_SIZE2_DEFAULT 0x00000000
++#define mmVCE_RB_RPTR2_DEFAULT 0x00000000
++#define mmVCE_RB_WPTR2_DEFAULT 0x00000000
++#define mmVCE_RB_BASE_LO_DEFAULT 0x00000000
++#define mmVCE_RB_BASE_HI_DEFAULT 0x00000000
++#define mmVCE_RB_SIZE_DEFAULT 0x00000000
++#define mmVCE_RB_RPTR_DEFAULT 0x00000000
++#define mmVCE_RB_WPTR_DEFAULT 0x00000000
++#define mmVCE_RB_ARB_CTRL_DEFAULT 0x00010000
++#define mmVCE_CLOCK_GATING_A_DEFAULT 0x00000040
++#define mmVCE_CLOCK_GATING_B_DEFAULT 0x01ef0100
++#define mmVCE_RB_BASE_LO3_DEFAULT 0x00000000
++#define mmVCE_RB_BASE_HI3_DEFAULT 0x00000000
++#define mmVCE_RB_SIZE3_DEFAULT 0x00000000
++#define mmVCE_RB_RPTR3_DEFAULT 0x00000000
++#define mmVCE_RB_WPTR3_DEFAULT 0x00000000
++#define mmVCE_SYS_INT_EN_DEFAULT 0x00000000
++#define mmVCE_SYS_INT_ACK_DEFAULT 0x00000000
++#define mmVCE_SYS_INT_STATUS_DEFAULT 0x00000000
++
++
++// addressBlock: vce0_ctl_dec
++#define mmVCE_UENC_CLOCK_GATING_DEFAULT 0xffc00040
++#define mmVCE_UENC_REG_CLOCK_GATING_DEFAULT 0x000007ff
++#define mmVCE_UENC_CLOCK_GATING_2_DEFAULT 0x00010000
++
++
++// addressBlock: vce0_vce_sclk_dec
++#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR_DEFAULT 0x00000000
++#define mmVCE_LMI_CTRL2_DEFAULT 0x00000000
++#define mmVCE_LMI_SWAP_CNTL3_DEFAULT 0x00000000
++#define mmVCE_LMI_CTRL_DEFAULT 0x00104000
++#define mmVCE_LMI_STATUS_DEFAULT 0x00003f7f
++#define mmVCE_LMI_VM_CTRL_DEFAULT 0x00000000
++#define mmVCE_LMI_SWAP_CNTL_DEFAULT 0x00000000
++#define mmVCE_LMI_SWAP_CNTL1_DEFAULT 0x00000000
++#define mmVCE_LMI_SWAP_CNTL2_DEFAULT 0x00000000
++#define mmVCE_LMI_CACHE_CTRL_DEFAULT 0x00000000
++#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR0_DEFAULT 0x00000000
++#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR1_DEFAULT 0x00000000
++#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR2_DEFAULT 0x00000000
++#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR3_DEFAULT 0x00000000
++#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR4_DEFAULT 0x00000000
++#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR5_DEFAULT 0x00000000
++#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR6_DEFAULT 0x00000000
++#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR7_DEFAULT 0x00000000
++#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0_DEFAULT 0x00000000
++#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1_DEFAULT 0x00000000
++#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2_DEFAULT 0x00000000
++#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR3_DEFAULT 0x00000000
++#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR4_DEFAULT 0x00000000
++#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR5_DEFAULT 0x00000000
++#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR6_DEFAULT 0x00000000
++#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR7_DEFAULT 0x00000000
++
++
++// addressBlock: vce0_mmsch_dec
++#define mmVCE_MMSCH_VF_VMID_DEFAULT 0x00000000
++#define mmVCE_MMSCH_VF_CTX_ADDR_LO_DEFAULT 0x00000000
++#define mmVCE_MMSCH_VF_CTX_ADDR_HI_DEFAULT 0x00000000
++#define mmVCE_MMSCH_VF_CTX_SIZE_DEFAULT 0x00000000
++#define mmVCE_MMSCH_VF_GPCOM_ADDR_LO_DEFAULT 0x00000000
++#define mmVCE_MMSCH_VF_GPCOM_ADDR_HI_DEFAULT 0x00000000
++#define mmVCE_MMSCH_VF_GPCOM_SIZE_DEFAULT 0x00000000
++#define mmVCE_MMSCH_VF_MAILBOX_HOST_DEFAULT 0x00000000
++#define mmVCE_MMSCH_VF_MAILBOX_RESP_DEFAULT 0x00000000
++
++
++// addressBlock: vce0_vce_rb_pg_dec
++#define mmVCE_HW_VERSION_DEFAULT 0x00000000
++
++
++
++#endif
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_offset.h
+new file mode 100644
+index 0000000..109303e
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_offset.h
+@@ -0,0 +1,208 @@
++/*
++ * Copyright (C) 2017 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++#ifndef _vce_4_0_OFFSET_HEADER
++#define _vce_4_0_OFFSET_HEADER
++
++
++
++// addressBlock: vce0_vce_dec
++// base address: 0x22000
++#define mmVCE_STATUS 0x0a01
++#define mmVCE_STATUS_BASE_IDX 0
++#define mmVCE_VCPU_CNTL 0x0a05
++#define mmVCE_VCPU_CNTL_BASE_IDX 0
++#define mmVCE_VCPU_CACHE_OFFSET0 0x0a09
++#define mmVCE_VCPU_CACHE_OFFSET0_BASE_IDX 0
++#define mmVCE_VCPU_CACHE_SIZE0 0x0a0a
++#define mmVCE_VCPU_CACHE_SIZE0_BASE_IDX 0
++#define mmVCE_VCPU_CACHE_OFFSET1 0x0a0b
++#define mmVCE_VCPU_CACHE_OFFSET1_BASE_IDX 0
++#define mmVCE_VCPU_CACHE_SIZE1 0x0a0c
++#define mmVCE_VCPU_CACHE_SIZE1_BASE_IDX 0
++#define mmVCE_VCPU_CACHE_OFFSET2 0x0a0d
++#define mmVCE_VCPU_CACHE_OFFSET2_BASE_IDX 0
++#define mmVCE_VCPU_CACHE_SIZE2 0x0a0e
++#define mmVCE_VCPU_CACHE_SIZE2_BASE_IDX 0
++#define mmVCE_VCPU_CACHE_OFFSET3 0x0a0f
++#define mmVCE_VCPU_CACHE_OFFSET3_BASE_IDX 0
++#define mmVCE_VCPU_CACHE_SIZE3 0x0a10
++#define mmVCE_VCPU_CACHE_SIZE3_BASE_IDX 0
++#define mmVCE_VCPU_CACHE_OFFSET4 0x0a11
++#define mmVCE_VCPU_CACHE_OFFSET4_BASE_IDX 0
++#define mmVCE_VCPU_CACHE_SIZE4 0x0a12
++#define mmVCE_VCPU_CACHE_SIZE4_BASE_IDX 0
++#define mmVCE_VCPU_CACHE_OFFSET5 0x0a13
++#define mmVCE_VCPU_CACHE_OFFSET5_BASE_IDX 0
++#define mmVCE_VCPU_CACHE_SIZE5 0x0a14
++#define mmVCE_VCPU_CACHE_SIZE5_BASE_IDX 0
++#define mmVCE_VCPU_CACHE_OFFSET6 0x0a15
++#define mmVCE_VCPU_CACHE_OFFSET6_BASE_IDX 0
++#define mmVCE_VCPU_CACHE_SIZE6 0x0a16
++#define mmVCE_VCPU_CACHE_SIZE6_BASE_IDX 0
++#define mmVCE_VCPU_CACHE_OFFSET7 0x0a17
++#define mmVCE_VCPU_CACHE_OFFSET7_BASE_IDX 0
++#define mmVCE_VCPU_CACHE_SIZE7 0x0a18
++#define mmVCE_VCPU_CACHE_SIZE7_BASE_IDX 0
++#define mmVCE_VCPU_CACHE_OFFSET8 0x0a19
++#define mmVCE_VCPU_CACHE_OFFSET8_BASE_IDX 0
++#define mmVCE_VCPU_CACHE_SIZE8 0x0a1a
++#define mmVCE_VCPU_CACHE_SIZE8_BASE_IDX 0
++#define mmVCE_SOFT_RESET 0x0a48
++#define mmVCE_SOFT_RESET_BASE_IDX 0
++#define mmVCE_RB_BASE_LO2 0x0a5b
++#define mmVCE_RB_BASE_LO2_BASE_IDX 0
++#define mmVCE_RB_BASE_HI2 0x0a5c
++#define mmVCE_RB_BASE_HI2_BASE_IDX 0
++#define mmVCE_RB_SIZE2 0x0a5d
++#define mmVCE_RB_SIZE2_BASE_IDX 0
++#define mmVCE_RB_RPTR2 0x0a5e
++#define mmVCE_RB_RPTR2_BASE_IDX 0
++#define mmVCE_RB_WPTR2 0x0a5f
++#define mmVCE_RB_WPTR2_BASE_IDX 0
++#define mmVCE_RB_BASE_LO 0x0a60
++#define mmVCE_RB_BASE_LO_BASE_IDX 0
++#define mmVCE_RB_BASE_HI 0x0a61
++#define mmVCE_RB_BASE_HI_BASE_IDX 0
++#define mmVCE_RB_SIZE 0x0a62
++#define mmVCE_RB_SIZE_BASE_IDX 0
++#define mmVCE_RB_RPTR 0x0a63
++#define mmVCE_RB_RPTR_BASE_IDX 0
++#define mmVCE_RB_WPTR 0x0a64
++#define mmVCE_RB_WPTR_BASE_IDX 0
++#define mmVCE_RB_ARB_CTRL 0x0a9f
++#define mmVCE_RB_ARB_CTRL_BASE_IDX 0
++#define mmVCE_CLOCK_GATING_A 0x0abe
++#define mmVCE_CLOCK_GATING_A_BASE_IDX 0
++#define mmVCE_CLOCK_GATING_B 0x0abf
++#define mmVCE_CLOCK_GATING_B_BASE_IDX 0
++#define mmVCE_RB_BASE_LO3 0x0ad4
++#define mmVCE_RB_BASE_LO3_BASE_IDX 0
++#define mmVCE_RB_BASE_HI3 0x0ad5
++#define mmVCE_RB_BASE_HI3_BASE_IDX 0
++#define mmVCE_RB_SIZE3 0x0ad6
++#define mmVCE_RB_SIZE3_BASE_IDX 0
++#define mmVCE_RB_RPTR3 0x0ad7
++#define mmVCE_RB_RPTR3_BASE_IDX 0
++#define mmVCE_RB_WPTR3 0x0ad8
++#define mmVCE_RB_WPTR3_BASE_IDX 0
++#define mmVCE_SYS_INT_EN 0x0b00
++#define mmVCE_SYS_INT_EN_BASE_IDX 0
++#define mmVCE_SYS_INT_ACK 0x0b01
++#define mmVCE_SYS_INT_ACK_BASE_IDX 0
++#define mmVCE_SYS_INT_STATUS 0x0b01
++#define mmVCE_SYS_INT_STATUS_BASE_IDX 0
++
++
++// addressBlock: vce0_ctl_dec
++// base address: 0x22780
++#define mmVCE_UENC_CLOCK_GATING 0x0bef
++#define mmVCE_UENC_CLOCK_GATING_BASE_IDX 0
++#define mmVCE_UENC_REG_CLOCK_GATING 0x0bf0
++#define mmVCE_UENC_REG_CLOCK_GATING_BASE_IDX 0
++#define mmVCE_UENC_CLOCK_GATING_2 0x0c10
++#define mmVCE_UENC_CLOCK_GATING_2_BASE_IDX 0
++
++
++// addressBlock: vce0_vce_sclk_dec
++// base address: 0x23700
++#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR 0x0fcc
++#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR_BASE_IDX 0
++#define mmVCE_LMI_CTRL2 0x0fcf
++#define mmVCE_LMI_CTRL2_BASE_IDX 0
++#define mmVCE_LMI_SWAP_CNTL3 0x0fd0
++#define mmVCE_LMI_SWAP_CNTL3_BASE_IDX 0
++#define mmVCE_LMI_CTRL 0x0fd6
++#define mmVCE_LMI_CTRL_BASE_IDX 0
++#define mmVCE_LMI_STATUS 0x0fd7
++#define mmVCE_LMI_STATUS_BASE_IDX 0
++#define mmVCE_LMI_VM_CTRL 0x0fd8
++#define mmVCE_LMI_VM_CTRL_BASE_IDX 0
++#define mmVCE_LMI_SWAP_CNTL 0x0fdd
++#define mmVCE_LMI_SWAP_CNTL_BASE_IDX 0
++#define mmVCE_LMI_SWAP_CNTL1 0x0fde
++#define mmVCE_LMI_SWAP_CNTL1_BASE_IDX 0
++#define mmVCE_LMI_SWAP_CNTL2 0x0fe2
++#define mmVCE_LMI_SWAP_CNTL2_BASE_IDX 0
++#define mmVCE_LMI_CACHE_CTRL 0x0fec
++#define mmVCE_LMI_CACHE_CTRL_BASE_IDX 0
++#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR0 0x1086
++#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR0_BASE_IDX 0
++#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR1 0x1087
++#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR1_BASE_IDX 0
++#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR2 0x1088
++#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR2_BASE_IDX 0
++#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR3 0x1089
++#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR3_BASE_IDX 0
++#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR4 0x108a
++#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR4_BASE_IDX 0
++#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR5 0x108b
++#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR5_BASE_IDX 0
++#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR6 0x108c
++#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR6_BASE_IDX 0
++#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR7 0x108d
++#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR7_BASE_IDX 0
++#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0 0x1096
++#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0_BASE_IDX 0
++#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1 0x1097
++#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1_BASE_IDX 0
++#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2 0x1098
++#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2_BASE_IDX 0
++#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR3 0x1099
++#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR3_BASE_IDX 0
++#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR4 0x109a
++#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR4_BASE_IDX 0
++#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR5 0x109b
++#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR5_BASE_IDX 0
++#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR6 0x109c
++#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR6_BASE_IDX 0
++#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR7 0x109d
++#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR7_BASE_IDX 0
++
++
++// addressBlock: vce0_mmsch_dec
++// base address: 0x23b00
++#define mmVCE_MMSCH_VF_VMID 0x10cb
++#define mmVCE_MMSCH_VF_VMID_BASE_IDX 0
++#define mmVCE_MMSCH_VF_CTX_ADDR_LO 0x10cc
++#define mmVCE_MMSCH_VF_CTX_ADDR_LO_BASE_IDX 0
++#define mmVCE_MMSCH_VF_CTX_ADDR_HI 0x10cd
++#define mmVCE_MMSCH_VF_CTX_ADDR_HI_BASE_IDX 0
++#define mmVCE_MMSCH_VF_CTX_SIZE 0x10ce
++#define mmVCE_MMSCH_VF_CTX_SIZE_BASE_IDX 0
++#define mmVCE_MMSCH_VF_GPCOM_ADDR_LO 0x10cf
++#define mmVCE_MMSCH_VF_GPCOM_ADDR_LO_BASE_IDX 0
++#define mmVCE_MMSCH_VF_GPCOM_ADDR_HI 0x10d0
++#define mmVCE_MMSCH_VF_GPCOM_ADDR_HI_BASE_IDX 0
++#define mmVCE_MMSCH_VF_GPCOM_SIZE 0x10d1
++#define mmVCE_MMSCH_VF_GPCOM_SIZE_BASE_IDX 0
++#define mmVCE_MMSCH_VF_MAILBOX_HOST 0x10d2
++#define mmVCE_MMSCH_VF_MAILBOX_HOST_BASE_IDX 0
++#define mmVCE_MMSCH_VF_MAILBOX_RESP 0x10d3
++#define mmVCE_MMSCH_VF_MAILBOX_RESP_BASE_IDX 0
++
++
++// addressBlock: vce0_vce_rb_pg_dec
++// base address: 0x23fa0
++#define mmVCE_HW_VERSION 0x11e8
++#define mmVCE_HW_VERSION_BASE_IDX 0
++
++
++#endif
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_sh_mask.h
+new file mode 100644
+index 0000000..4cf6e44
+--- /dev/null
++++ b/drivers/gpu/drm/amd/include/asic_reg/vce/vce_4_0_sh_mask.h
+@@ -0,0 +1,488 @@
++/*
++ * Copyright (C) 2017 Advanced Micro Devices, Inc.
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
++ */
++#ifndef _vce_4_0_SH_MASK_HEADER
++#define _vce_4_0_SH_MASK_HEADER
++
++
++// addressBlock: vce0_vce_dec
++//VCE_STATUS
++#define VCE_STATUS__JOB_BUSY__SHIFT 0x0
++#define VCE_STATUS__VCPU_REPORT__SHIFT 0x1
++#define VCE_STATUS__UENC_BUSY__SHIFT 0x8
++#define VCE_STATUS__VCE_CONFIGURATION__SHIFT 0x16
++#define VCE_STATUS__VCE_INSTANCE_ID__SHIFT 0x18
++#define VCE_STATUS__JOB_BUSY_MASK 0x00000001L
++#define VCE_STATUS__VCPU_REPORT_MASK 0x000000FEL
++#define VCE_STATUS__UENC_BUSY_MASK 0x00000100L
++#define VCE_STATUS__VCE_CONFIGURATION_MASK 0x00C00000L
++#define VCE_STATUS__VCE_INSTANCE_ID_MASK 0x03000000L
++//VCE_VCPU_CNTL
++#define VCE_VCPU_CNTL__CLK_EN__SHIFT 0x0
++#define VCE_VCPU_CNTL__ED_ENABLE__SHIFT 0x1
++#define VCE_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x12
++#define VCE_VCPU_CNTL__ONE_CACHE_SURFACE_EN__SHIFT 0x15
++#define VCE_VCPU_CNTL__CLK_EN_MASK 0x00000001L
++#define VCE_VCPU_CNTL__ED_ENABLE_MASK 0x00000002L
++#define VCE_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x00040000L
++#define VCE_VCPU_CNTL__ONE_CACHE_SURFACE_EN_MASK 0x00200000L
++//VCE_VCPU_CACHE_OFFSET0
++#define VCE_VCPU_CACHE_OFFSET0__OFFSET__SHIFT 0x0
++#define VCE_VCPU_CACHE_OFFSET0__OFFSET_MASK 0x0FFFFFFFL
++//VCE_VCPU_CACHE_SIZE0
++#define VCE_VCPU_CACHE_SIZE0__SIZE__SHIFT 0x0
++#define VCE_VCPU_CACHE_SIZE0__SIZE_MASK 0x00FFFFFFL
++//VCE_VCPU_CACHE_OFFSET1
++#define VCE_VCPU_CACHE_OFFSET1__OFFSET__SHIFT 0x0
++#define VCE_VCPU_CACHE_OFFSET1__OFFSET_MASK 0x0FFFFFFFL
++//VCE_VCPU_CACHE_SIZE1
++#define VCE_VCPU_CACHE_SIZE1__SIZE__SHIFT 0x0
++#define VCE_VCPU_CACHE_SIZE1__SIZE_MASK 0x00FFFFFFL
++//VCE_VCPU_CACHE_OFFSET2
++#define VCE_VCPU_CACHE_OFFSET2__OFFSET__SHIFT 0x0
++#define VCE_VCPU_CACHE_OFFSET2__OFFSET_MASK 0x0FFFFFFFL
++//VCE_VCPU_CACHE_SIZE2
++#define VCE_VCPU_CACHE_SIZE2__SIZE__SHIFT 0x0
++#define VCE_VCPU_CACHE_SIZE2__SIZE_MASK 0x00FFFFFFL
++//VCE_VCPU_CACHE_OFFSET3
++#define VCE_VCPU_CACHE_OFFSET3__OFFSET__SHIFT 0x0
++#define VCE_VCPU_CACHE_OFFSET3__OFFSET_MASK 0x0FFFFFFFL
++//VCE_VCPU_CACHE_SIZE3
++#define VCE_VCPU_CACHE_SIZE3__SIZE__SHIFT 0x0
++#define VCE_VCPU_CACHE_SIZE3__SIZE_MASK 0x00FFFFFFL
++//VCE_VCPU_CACHE_OFFSET4
++#define VCE_VCPU_CACHE_OFFSET4__OFFSET__SHIFT 0x0
++#define VCE_VCPU_CACHE_OFFSET4__OFFSET_MASK 0x0FFFFFFFL
++//VCE_VCPU_CACHE_SIZE4
++#define VCE_VCPU_CACHE_SIZE4__SIZE__SHIFT 0x0
++#define VCE_VCPU_CACHE_SIZE4__SIZE_MASK 0x00FFFFFFL
++//VCE_VCPU_CACHE_OFFSET5
++#define VCE_VCPU_CACHE_OFFSET5__OFFSET__SHIFT 0x0
++#define VCE_VCPU_CACHE_OFFSET5__OFFSET_MASK 0x0FFFFFFFL
++//VCE_VCPU_CACHE_SIZE5
++#define VCE_VCPU_CACHE_SIZE5__SIZE__SHIFT 0x0
++#define VCE_VCPU_CACHE_SIZE5__SIZE_MASK 0x00FFFFFFL
++//VCE_VCPU_CACHE_OFFSET6
++#define VCE_VCPU_CACHE_OFFSET6__OFFSET__SHIFT 0x0
++#define VCE_VCPU_CACHE_OFFSET6__OFFSET_MASK 0x0FFFFFFFL
++//VCE_VCPU_CACHE_SIZE6
++#define VCE_VCPU_CACHE_SIZE6__SIZE__SHIFT 0x0
++#define VCE_VCPU_CACHE_SIZE6__SIZE_MASK 0x00FFFFFFL
++//VCE_VCPU_CACHE_OFFSET7
++#define VCE_VCPU_CACHE_OFFSET7__OFFSET__SHIFT 0x0
++#define VCE_VCPU_CACHE_OFFSET7__OFFSET_MASK 0x0FFFFFFFL
++//VCE_VCPU_CACHE_SIZE7
++#define VCE_VCPU_CACHE_SIZE7__SIZE__SHIFT 0x0
++#define VCE_VCPU_CACHE_SIZE7__SIZE_MASK 0x00FFFFFFL
++//VCE_VCPU_CACHE_OFFSET8
++#define VCE_VCPU_CACHE_OFFSET8__OFFSET__SHIFT 0x0
++#define VCE_VCPU_CACHE_OFFSET8__OFFSET_MASK 0x0FFFFFFFL
++//VCE_VCPU_CACHE_SIZE8
++#define VCE_VCPU_CACHE_SIZE8__SIZE__SHIFT 0x0
++#define VCE_VCPU_CACHE_SIZE8__SIZE_MASK 0x00FFFFFFL
++//VCE_SOFT_RESET
++#define VCE_SOFT_RESET__ECPU_SOFT_RESET__SHIFT 0x0
++#define VCE_SOFT_RESET__UENC_SOFT_RESET__SHIFT 0x1
++#define VCE_SOFT_RESET__FME_SOFT_RESET__SHIFT 0x2
++#define VCE_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0x3
++#define VCE_SOFT_RESET__DBF_SOFT_RESET__SHIFT 0x4
++#define VCE_SOFT_RESET__ENT_SOFT_RESET__SHIFT 0x5
++#define VCE_SOFT_RESET__TBE_SOFT_RESET__SHIFT 0x6
++#define VCE_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x7
++#define VCE_SOFT_RESET__CTL_SOFT_RESET__SHIFT 0x8
++#define VCE_SOFT_RESET__IME_SOFT_RESET__SHIFT 0x9
++#define VCE_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa
++#define VCE_SOFT_RESET__SEM_SOFT_RESET__SHIFT 0xb
++#define VCE_SOFT_RESET__DCAP_SOFT_RESET__SHIFT 0xc
++#define VCE_SOFT_RESET__ACAP_SOFT_RESET__SHIFT 0xd
++#define VCE_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0xe
++#define VCE_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0xf
++#define VCE_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0x10
++#define VCE_SOFT_RESET__AVMUX_SOFT_RESET__SHIFT 0x13
++#define VCE_SOFT_RESET__VREG_SOFT_RESET__SHIFT 0x14
++#define VCE_SOFT_RESET__DCAP_FSM_SOFT_RESET__SHIFT 0x15
++#define VCE_SOFT_RESET__VEP_SOFT_RESET__SHIFT 0x16
++#define VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK 0x00000001L
++#define VCE_SOFT_RESET__UENC_SOFT_RESET_MASK 0x00000002L
++#define VCE_SOFT_RESET__FME_SOFT_RESET_MASK 0x00000004L
++#define VCE_SOFT_RESET__MIF_SOFT_RESET_MASK 0x00000008L
++#define VCE_SOFT_RESET__DBF_SOFT_RESET_MASK 0x00000010L
++#define VCE_SOFT_RESET__ENT_SOFT_RESET_MASK 0x00000020L
++#define VCE_SOFT_RESET__TBE_SOFT_RESET_MASK 0x00000040L
++#define VCE_SOFT_RESET__LCM_SOFT_RESET_MASK 0x00000080L
++#define VCE_SOFT_RESET__CTL_SOFT_RESET_MASK 0x00000100L
++#define VCE_SOFT_RESET__IME_SOFT_RESET_MASK 0x00000200L
++#define VCE_SOFT_RESET__IH_SOFT_RESET_MASK 0x00000400L
++#define VCE_SOFT_RESET__SEM_SOFT_RESET_MASK 0x00000800L
++#define VCE_SOFT_RESET__DCAP_SOFT_RESET_MASK 0x00001000L
++#define VCE_SOFT_RESET__ACAP_SOFT_RESET_MASK 0x00002000L
++#define VCE_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00004000L
++#define VCE_SOFT_RESET__LMI_SOFT_RESET_MASK 0x00008000L
++#define VCE_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x00010000L
++#define VCE_SOFT_RESET__AVMUX_SOFT_RESET_MASK 0x00080000L
++#define VCE_SOFT_RESET__VREG_SOFT_RESET_MASK 0x00100000L
++#define VCE_SOFT_RESET__DCAP_FSM_SOFT_RESET_MASK 0x00200000L
++#define VCE_SOFT_RESET__VEP_SOFT_RESET_MASK 0x00400000L
++//VCE_RB_BASE_LO2
++#define VCE_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6
++#define VCE_RB_BASE_LO2__RB_BASE_LO_MASK 0xFFFFFFC0L
++//VCE_RB_BASE_HI2
++#define VCE_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0
++#define VCE_RB_BASE_HI2__RB_BASE_HI_MASK 0xFFFFFFFFL
++//VCE_RB_SIZE2
++#define VCE_RB_SIZE2__RB_SIZE__SHIFT 0x4
++#define VCE_RB_SIZE2__RB_SIZE_MASK 0x007FFFF0L
++//VCE_RB_RPTR2
++#define VCE_RB_RPTR2__RB_RPTR__SHIFT 0x4
++#define VCE_RB_RPTR2__RB_RPTR_MASK 0x007FFFF0L
++//VCE_RB_WPTR2
++#define VCE_RB_WPTR2__RB_WPTR__SHIFT 0x4
++#define VCE_RB_WPTR2__RB_WPTR_MASK 0x007FFFF0L
++//VCE_RB_BASE_LO
++#define VCE_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6
++#define VCE_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L
++//VCE_RB_BASE_HI
++#define VCE_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0
++#define VCE_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL
++//VCE_RB_SIZE
++#define VCE_RB_SIZE__RB_SIZE__SHIFT 0x4
++#define VCE_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L
++//VCE_RB_RPTR
++#define VCE_RB_RPTR__RB_RPTR__SHIFT 0x4
++#define VCE_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L
++//VCE_RB_WPTR
++#define VCE_RB_WPTR__RB_WPTR__SHIFT 0x4
++#define VCE_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L
++//VCE_RB_ARB_CTRL
++#define VCE_RB_ARB_CTRL__RB_ARB_CTRL__SHIFT 0x0
++#define VCE_RB_ARB_CTRL__VCE_CGTT_OVERRIDE__SHIFT 0x10
++#define VCE_RB_ARB_CTRL__RB_ARB_CTRL_MASK 0x000001FFL
++#define VCE_RB_ARB_CTRL__VCE_CGTT_OVERRIDE_MASK 0x00010000L
++//VCE_CLOCK_GATING_A
++#define VCE_CLOCK_GATING_A__CGC_CLK_ON_DELAY__SHIFT 0x0
++#define VCE_CLOCK_GATING_A__CGC_CLK_OFF_DELAY__SHIFT 0x4
++#define VCE_CLOCK_GATING_A__CGC_REG_AWAKE__SHIFT 0x11
++#define VCE_CLOCK_GATING_A__CGC_CLK_ON_DELAY_MASK 0x0000000FL
++#define VCE_CLOCK_GATING_A__CGC_CLK_OFF_DELAY_MASK 0x00000FF0L
++#define VCE_CLOCK_GATING_A__CGC_REG_AWAKE_MASK 0x00020000L
++//VCE_CLOCK_GATING_B
++#define VCE_CLOCK_GATING_B__CGC_SYS_CLK_FORCE_ON__SHIFT 0x0
++#define VCE_CLOCK_GATING_B__CGC_LMI_MC_CLK_FORCE_ON__SHIFT 0x1
++#define VCE_CLOCK_GATING_B__CGC_LMI_UMC_CLK_FORCE_ON__SHIFT 0x2
++#define VCE_CLOCK_GATING_B__CGC_UENC_CLK_FORCE_ON__SHIFT 0x3
++#define VCE_CLOCK_GATING_B__CGC_VREG_CLK_FORCE_ON__SHIFT 0x4
++#define VCE_CLOCK_GATING_B__CGC_ECPU_CLK_FORCE_ON__SHIFT 0x5
++#define VCE_CLOCK_GATING_B__CGC_IH_CLK_FORCE_ON__SHIFT 0x6
++#define VCE_CLOCK_GATING_B__CGC_SEM_CLK_FORCE_ON__SHIFT 0x7
++#define VCE_CLOCK_GATING_B__CGC_CTLREG_CLK_FORCE_ON__SHIFT 0x8
++#define VCE_CLOCK_GATING_B__CGC_MMSCH_CLK_FORCE_ON__SHIFT 0x9
++#define VCE_CLOCK_GATING_B__CGC_SYS_CLK_FORCE_OFF__SHIFT 0x10
++#define VCE_CLOCK_GATING_B__CGC_LMI_MC_CLK_FORCE_OFF__SHIFT 0x11
++#define VCE_CLOCK_GATING_B__CGC_LMI_UMC_CLK_FORCE_OFF__SHIFT 0x12
++#define VCE_CLOCK_GATING_B__CGC_UENC_CLK_FORCE_OFF__SHIFT 0x13
++#define VCE_CLOCK_GATING_B__CGC_ECPU_CLK_FORCE_OFF__SHIFT 0x15
++#define VCE_CLOCK_GATING_B__CGC_IH_CLK_FORCE_OFF__SHIFT 0x16
++#define VCE_CLOCK_GATING_B__CGC_SEM_CLK_FORCE_OFF__SHIFT 0x17
++#define VCE_CLOCK_GATING_B__CGC_MMSCH_CLK_FORCE_OFF__SHIFT 0x18
++#define VCE_CLOCK_GATING_B__CGC_SYS_CLK_FORCE_ON_MASK 0x00000001L
++#define VCE_CLOCK_GATING_B__CGC_LMI_MC_CLK_FORCE_ON_MASK 0x00000002L
++#define VCE_CLOCK_GATING_B__CGC_LMI_UMC_CLK_FORCE_ON_MASK 0x00000004L
++#define VCE_CLOCK_GATING_B__CGC_UENC_CLK_FORCE_ON_MASK 0x00000008L
++#define VCE_CLOCK_GATING_B__CGC_VREG_CLK_FORCE_ON_MASK 0x00000010L
++#define VCE_CLOCK_GATING_B__CGC_ECPU_CLK_FORCE_ON_MASK 0x00000020L
++#define VCE_CLOCK_GATING_B__CGC_IH_CLK_FORCE_ON_MASK 0x00000040L
++#define VCE_CLOCK_GATING_B__CGC_SEM_CLK_FORCE_ON_MASK 0x00000080L
++#define VCE_CLOCK_GATING_B__CGC_CTLREG_CLK_FORCE_ON_MASK 0x00000100L
++#define VCE_CLOCK_GATING_B__CGC_MMSCH_CLK_FORCE_ON_MASK 0x00000200L
++#define VCE_CLOCK_GATING_B__CGC_SYS_CLK_FORCE_OFF_MASK 0x00010000L
++#define VCE_CLOCK_GATING_B__CGC_LMI_MC_CLK_FORCE_OFF_MASK 0x00020000L
++#define VCE_CLOCK_GATING_B__CGC_LMI_UMC_CLK_FORCE_OFF_MASK 0x00040000L
++#define VCE_CLOCK_GATING_B__CGC_UENC_CLK_FORCE_OFF_MASK 0x00080000L
++#define VCE_CLOCK_GATING_B__CGC_ECPU_CLK_FORCE_OFF_MASK 0x00200000L
++#define VCE_CLOCK_GATING_B__CGC_IH_CLK_FORCE_OFF_MASK 0x00400000L
++#define VCE_CLOCK_GATING_B__CGC_SEM_CLK_FORCE_OFF_MASK 0x00800000L
++#define VCE_CLOCK_GATING_B__CGC_MMSCH_CLK_FORCE_OFF_MASK 0x01000000L
++//VCE_RB_BASE_LO3
++#define VCE_RB_BASE_LO3__RB_BASE_LO__SHIFT 0x6
++#define VCE_RB_BASE_LO3__RB_BASE_LO_MASK 0xFFFFFFC0L
++//VCE_RB_BASE_HI3
++#define VCE_RB_BASE_HI3__RB_BASE_HI__SHIFT 0x0
++#define VCE_RB_BASE_HI3__RB_BASE_HI_MASK 0xFFFFFFFFL
++//VCE_RB_SIZE3
++#define VCE_RB_SIZE3__RB_SIZE__SHIFT 0x4
++#define VCE_RB_SIZE3__RB_SIZE_MASK 0x007FFFF0L
++//VCE_RB_RPTR3
++#define VCE_RB_RPTR3__RB_RPTR__SHIFT 0x4
++#define VCE_RB_RPTR3__RB_RPTR_MASK 0x007FFFF0L
++//VCE_RB_WPTR3
++#define VCE_RB_WPTR3__RB_WPTR__SHIFT 0x4
++#define VCE_RB_WPTR3__RB_WPTR_MASK 0x007FFFF0L
++//VCE_SYS_INT_EN
++#define VCE_SYS_INT_EN__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_EN__SHIFT 0x0
++#define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN__SHIFT 0x3
++#define VCE_SYS_INT_EN__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_EN_MASK 0x00000001L
++#define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK 0x00000008L
++//VCE_SYS_INT_ACK
++#define VCE_SYS_INT_ACK__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_ACK__SHIFT 0x0
++#define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK__SHIFT 0x3
++#define VCE_SYS_INT_ACK__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_ACK_MASK 0x00000001L
++#define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK_MASK 0x00000008L
++//VCE_SYS_INT_STATUS
++#define VCE_SYS_INT_STATUS__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_INT__SHIFT 0x0
++#define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT__SHIFT 0x3
++#define VCE_SYS_INT_STATUS__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_INT_MASK 0x00000001L
++#define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK 0x00000008L
++
++
++// addressBlock: vce0_ctl_dec
++//VCE_UENC_CLOCK_GATING
++#define VCE_UENC_CLOCK_GATING__CLOCK_ON_DELAY__SHIFT 0x0
++#define VCE_UENC_CLOCK_GATING__CLOCK_OFF_DELAY__SHIFT 0x4
++#define VCE_UENC_CLOCK_GATING__VEPCLK_FORCE_ON__SHIFT 0xc
++#define VCE_UENC_CLOCK_GATING__IMECLK_FORCE_ON__SHIFT 0xd
++#define VCE_UENC_CLOCK_GATING__FMECLK_FORCE_ON__SHIFT 0xe
++#define VCE_UENC_CLOCK_GATING__TBECLK_FORCE_ON__SHIFT 0xf
++#define VCE_UENC_CLOCK_GATING__DBFCLK_FORCE_ON__SHIFT 0x10
++#define VCE_UENC_CLOCK_GATING__ENTCLK_FORCE_ON__SHIFT 0x11
++#define VCE_UENC_CLOCK_GATING__LCMCLK_FORCE_ON__SHIFT 0x12
++#define VCE_UENC_CLOCK_GATING__AVMCLK_FORCE_ON__SHIFT 0x13
++#define VCE_UENC_CLOCK_GATING__DCAPCLK_FORCE_ON__SHIFT 0x14
++#define VCE_UENC_CLOCK_GATING__ACAPCLK_FORCE_ON__SHIFT 0x15
++#define VCE_UENC_CLOCK_GATING__ACAPCLK_FORCE_OFF__SHIFT 0x16
++#define VCE_UENC_CLOCK_GATING__VEPCLK_FORCE_OFF__SHIFT 0x17
++#define VCE_UENC_CLOCK_GATING__IMECLK_FORCE_OFF__SHIFT 0x18
++#define VCE_UENC_CLOCK_GATING__FMECLK_FORCE_OFF__SHIFT 0x19
++#define VCE_UENC_CLOCK_GATING__TBECLK_FORCE_OFF__SHIFT 0x1a
++#define VCE_UENC_CLOCK_GATING__DBFCLK_FORCE_OFF__SHIFT 0x1b
++#define VCE_UENC_CLOCK_GATING__ENTCLK_FORCE_OFF__SHIFT 0x1c
++#define VCE_UENC_CLOCK_GATING__LCMCLK_FORCE_OFF__SHIFT 0x1d
++#define VCE_UENC_CLOCK_GATING__AVMCLK_FORCE_OFF__SHIFT 0x1e
++#define VCE_UENC_CLOCK_GATING__DCAPCLK_FORCE_OFF__SHIFT 0x1f
++#define VCE_UENC_CLOCK_GATING__CLOCK_ON_DELAY_MASK 0x0000000FL
++#define VCE_UENC_CLOCK_GATING__CLOCK_OFF_DELAY_MASK 0x00000FF0L
++#define VCE_UENC_CLOCK_GATING__VEPCLK_FORCE_ON_MASK 0x00001000L
++#define VCE_UENC_CLOCK_GATING__IMECLK_FORCE_ON_MASK 0x00002000L
++#define VCE_UENC_CLOCK_GATING__FMECLK_FORCE_ON_MASK 0x00004000L
++#define VCE_UENC_CLOCK_GATING__TBECLK_FORCE_ON_MASK 0x00008000L
++#define VCE_UENC_CLOCK_GATING__DBFCLK_FORCE_ON_MASK 0x00010000L
++#define VCE_UENC_CLOCK_GATING__ENTCLK_FORCE_ON_MASK 0x00020000L
++#define VCE_UENC_CLOCK_GATING__LCMCLK_FORCE_ON_MASK 0x00040000L
++#define VCE_UENC_CLOCK_GATING__AVMCLK_FORCE_ON_MASK 0x00080000L
++#define VCE_UENC_CLOCK_GATING__DCAPCLK_FORCE_ON_MASK 0x00100000L
++#define VCE_UENC_CLOCK_GATING__ACAPCLK_FORCE_ON_MASK 0x00200000L
++#define VCE_UENC_CLOCK_GATING__ACAPCLK_FORCE_OFF_MASK 0x00400000L
++#define VCE_UENC_CLOCK_GATING__VEPCLK_FORCE_OFF_MASK 0x00800000L
++#define VCE_UENC_CLOCK_GATING__IMECLK_FORCE_OFF_MASK 0x01000000L
++#define VCE_UENC_CLOCK_GATING__FMECLK_FORCE_OFF_MASK 0x02000000L
++#define VCE_UENC_CLOCK_GATING__TBECLK_FORCE_OFF_MASK 0x04000000L
++#define VCE_UENC_CLOCK_GATING__DBFCLK_FORCE_OFF_MASK 0x08000000L
++#define VCE_UENC_CLOCK_GATING__ENTCLK_FORCE_OFF_MASK 0x10000000L
++#define VCE_UENC_CLOCK_GATING__LCMCLK_FORCE_OFF_MASK 0x20000000L
++#define VCE_UENC_CLOCK_GATING__AVMCLK_FORCE_OFF_MASK 0x40000000L
++#define VCE_UENC_CLOCK_GATING__DCAPCLK_FORCE_OFF_MASK 0x80000000L
++//VCE_UENC_REG_CLOCK_GATING
++#define VCE_UENC_REG_CLOCK_GATING__MIFREGCLK_FORCE_ON__SHIFT 0x0
++#define VCE_UENC_REG_CLOCK_GATING__IMEREGCLK_FORCE_ON__SHIFT 0x1
++#define VCE_UENC_REG_CLOCK_GATING__FMEREGCLK_FORCE_ON__SHIFT 0x2
++#define VCE_UENC_REG_CLOCK_GATING__TBEREGCLK_FORCE_ON__SHIFT 0x3
++#define VCE_UENC_REG_CLOCK_GATING__DBFREGCLK_FORCE_ON__SHIFT 0x4
++#define VCE_UENC_REG_CLOCK_GATING__ENTREGCLK_FORCE_ON__SHIFT 0x5
++#define VCE_UENC_REG_CLOCK_GATING__LCMREGCLK_FORCE_ON__SHIFT 0x6
++#define VCE_UENC_REG_CLOCK_GATING__RESERVED__SHIFT 0x7
++#define VCE_UENC_REG_CLOCK_GATING__AVMREGCLK_FORCE_ON__SHIFT 0x8
++#define VCE_UENC_REG_CLOCK_GATING__DCAPREGCLK_FORCE_ON__SHIFT 0x9
++#define VCE_UENC_REG_CLOCK_GATING__VEPREGCLK_FORCE_ON__SHIFT 0xa
++#define VCE_UENC_REG_CLOCK_GATING__MIFREGCLK_FORCE_ON_MASK 0x00000001L
++#define VCE_UENC_REG_CLOCK_GATING__IMEREGCLK_FORCE_ON_MASK 0x00000002L
++#define VCE_UENC_REG_CLOCK_GATING__FMEREGCLK_FORCE_ON_MASK 0x00000004L
++#define VCE_UENC_REG_CLOCK_GATING__TBEREGCLK_FORCE_ON_MASK 0x00000008L
++#define VCE_UENC_REG_CLOCK_GATING__DBFREGCLK_FORCE_ON_MASK 0x00000010L
++#define VCE_UENC_REG_CLOCK_GATING__ENTREGCLK_FORCE_ON_MASK 0x00000020L
++#define VCE_UENC_REG_CLOCK_GATING__LCMREGCLK_FORCE_ON_MASK 0x00000040L
++#define VCE_UENC_REG_CLOCK_GATING__RESERVED_MASK 0x00000080L
++#define VCE_UENC_REG_CLOCK_GATING__AVMREGCLK_FORCE_ON_MASK 0x00000100L
++#define VCE_UENC_REG_CLOCK_GATING__DCAPREGCLK_FORCE_ON_MASK 0x00000200L
++#define VCE_UENC_REG_CLOCK_GATING__VEPREGCLK_FORCE_ON_MASK 0x00000400L
++//VCE_UENC_CLOCK_GATING_2
++#define VCE_UENC_CLOCK_GATING_2__DBF2CLK_FORCE_ON__SHIFT 0x1
++#define VCE_UENC_CLOCK_GATING_2__DBF2CLK_FORCE_OFF__SHIFT 0x10
++#define VCE_UENC_CLOCK_GATING_2__DBF2CLK_FORCE_ON_MASK 0x00000002L
++#define VCE_UENC_CLOCK_GATING_2__DBF2CLK_FORCE_OFF_MASK 0x00010000L
++
++
++// addressBlock: vce0_vce_sclk_dec
++//VCE_LMI_VCPU_CACHE_40BIT_BAR
++#define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR__SHIFT 0x0
++#define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR_MASK 0xFFFFFFFFL
++//VCE_LMI_CTRL2
++#define VCE_LMI_CTRL2__STALL_ARB__SHIFT 0x1
++#define VCE_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2
++#define VCE_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3
++#define VCE_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8
++#define VCE_LMI_CTRL2__STALL_ARB_MASK 0x00000002L
++#define VCE_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L
++#define VCE_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x00000008L
++#define VCE_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L
++//VCE_LMI_SWAP_CNTL3
++#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_SWAP__SHIFT 0x0
++#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_TRAN__SHIFT 0x14
++#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_URG__SHIFT 0x1a
++#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_SWAP_MASK 0x00000003L
++#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_TRAN_MASK 0x00100000L
++#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_URG_MASK 0x04000000L
++//VCE_LMI_CTRL
++#define VCE_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb
++#define VCE_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc
++#define VCE_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd
++#define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15
++#define VCE_LMI_CTRL__MIF_DATA_COHERENCY_EN__SHIFT 0x16
++#define VCE_LMI_CTRL__VCPU_RD_CACHE_MISS_COUNT_EN__SHIFT 0x17
++#define VCE_LMI_CTRL__VCPU_RD_CACHE_MISS_COUNT_RESET__SHIFT 0x18
++#define VCE_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000800L
++#define VCE_LMI_CTRL__MASK_MC_URGENT_MASK 0x00001000L
++#define VCE_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x00002000L
++#define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L
++#define VCE_LMI_CTRL__MIF_DATA_COHERENCY_EN_MASK 0x00400000L
++#define VCE_LMI_CTRL__VCPU_RD_CACHE_MISS_COUNT_EN_MASK 0x00800000L
++#define VCE_LMI_CTRL__VCPU_RD_CACHE_MISS_COUNT_RESET_MASK 0x01000000L
++//VCE_LMI_SWAP_CNTL
++#define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x0
++#define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP__SHIFT 0x2
++#define VCE_LMI_SWAP_CNTL__WR_MC_CID_TRAN__SHIFT 0x14
++#define VCE_LMI_SWAP_CNTL__WR_MC_CID_URG__SHIFT 0x1a
++#define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x00000003L
++#define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP_MASK 0x00003FFCL
++#define VCE_LMI_SWAP_CNTL__WR_MC_CID_TRAN_MASK 0x03F00000L
++#define VCE_LMI_SWAP_CNTL__WR_MC_CID_URG_MASK 0xFC000000L
++//VCE_LMI_SWAP_CNTL1
++#define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP__SHIFT 0x0
++#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP__SHIFT 0x2
++#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_TRAN__SHIFT 0x14
++#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_URG__SHIFT 0x1a
++#define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP_MASK 0x00000003L
++#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP_MASK 0x00003FFCL
++#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_TRAN_MASK 0x03F00000L
++#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_URG_MASK 0xFC000000L
++//VCE_LMI_SWAP_CNTL2
++#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_SWAP__SHIFT 0x0
++#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_TRAN__SHIFT 0x14
++#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_URG__SHIFT 0x1a
++#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_SWAP_MASK 0x000000FFL
++#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_TRAN_MASK 0x00F00000L
++#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_URG_MASK 0x3C000000L
++//VCE_LMI_CACHE_CTRL
++#define VCE_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x0
++#define VCE_LMI_CACHE_CTRL__VCPU_FLUSH__SHIFT 0x1
++#define VCE_LMI_CACHE_CTRL__VCPU_EN_MASK 0x00000001L
++#define VCE_LMI_CACHE_CTRL__VCPU_FLUSH_MASK 0x00000002L
++//VCE_LMI_VCPU_CACHE_64BIT_BAR0
++#define VCE_LMI_VCPU_CACHE_64BIT_BAR0__BAR__SHIFT 0x0
++#define VCE_LMI_VCPU_CACHE_64BIT_BAR0__BAR_MASK 0x000000FFL
++//VCE_LMI_VCPU_CACHE_64BIT_BAR1
++#define VCE_LMI_VCPU_CACHE_64BIT_BAR1__BAR__SHIFT 0x0
++#define VCE_LMI_VCPU_CACHE_64BIT_BAR1__BAR_MASK 0x000000FFL
++//VCE_LMI_VCPU_CACHE_64BIT_BAR2
++#define VCE_LMI_VCPU_CACHE_64BIT_BAR2__BAR__SHIFT 0x0
++#define VCE_LMI_VCPU_CACHE_64BIT_BAR2__BAR_MASK 0x000000FFL
++//VCE_LMI_VCPU_CACHE_64BIT_BAR3
++#define VCE_LMI_VCPU_CACHE_64BIT_BAR3__BAR__SHIFT 0x0
++#define VCE_LMI_VCPU_CACHE_64BIT_BAR3__BAR_MASK 0x000000FFL
++//VCE_LMI_VCPU_CACHE_64BIT_BAR4
++#define VCE_LMI_VCPU_CACHE_64BIT_BAR4__BAR__SHIFT 0x0
++#define VCE_LMI_VCPU_CACHE_64BIT_BAR4__BAR_MASK 0x000000FFL
++//VCE_LMI_VCPU_CACHE_64BIT_BAR5
++#define VCE_LMI_VCPU_CACHE_64BIT_BAR5__BAR__SHIFT 0x0
++#define VCE_LMI_VCPU_CACHE_64BIT_BAR5__BAR_MASK 0x000000FFL
++//VCE_LMI_VCPU_CACHE_64BIT_BAR6
++#define VCE_LMI_VCPU_CACHE_64BIT_BAR6__BAR__SHIFT 0x0
++#define VCE_LMI_VCPU_CACHE_64BIT_BAR6__BAR_MASK 0x000000FFL
++//VCE_LMI_VCPU_CACHE_64BIT_BAR7
++#define VCE_LMI_VCPU_CACHE_64BIT_BAR7__BAR__SHIFT 0x0
++#define VCE_LMI_VCPU_CACHE_64BIT_BAR7__BAR_MASK 0x000000FFL
++//VCE_LMI_VCPU_CACHE_40BIT_BAR0
++#define VCE_LMI_VCPU_CACHE_40BIT_BAR0__BAR__SHIFT 0x0
++#define VCE_LMI_VCPU_CACHE_40BIT_BAR0__BAR_MASK 0xFFFFFFFFL
++//VCE_LMI_VCPU_CACHE_40BIT_BAR1
++#define VCE_LMI_VCPU_CACHE_40BIT_BAR1__BAR__SHIFT 0x0
++#define VCE_LMI_VCPU_CACHE_40BIT_BAR1__BAR_MASK 0xFFFFFFFFL
++//VCE_LMI_VCPU_CACHE_40BIT_BAR2
++#define VCE_LMI_VCPU_CACHE_40BIT_BAR2__BAR__SHIFT 0x0
++#define VCE_LMI_VCPU_CACHE_40BIT_BAR2__BAR_MASK 0xFFFFFFFFL
++//VCE_LMI_VCPU_CACHE_40BIT_BAR3
++#define VCE_LMI_VCPU_CACHE_40BIT_BAR3__BAR__SHIFT 0x0
++#define VCE_LMI_VCPU_CACHE_40BIT_BAR3__BAR_MASK 0xFFFFFFFFL
++//VCE_LMI_VCPU_CACHE_40BIT_BAR4
++#define VCE_LMI_VCPU_CACHE_40BIT_BAR4__BAR__SHIFT 0x0
++#define VCE_LMI_VCPU_CACHE_40BIT_BAR4__BAR_MASK 0xFFFFFFFFL
++//VCE_LMI_VCPU_CACHE_40BIT_BAR5
++#define VCE_LMI_VCPU_CACHE_40BIT_BAR5__BAR__SHIFT 0x0
++#define VCE_LMI_VCPU_CACHE_40BIT_BAR5__BAR_MASK 0xFFFFFFFFL
++//VCE_LMI_VCPU_CACHE_40BIT_BAR6
++#define VCE_LMI_VCPU_CACHE_40BIT_BAR6__BAR__SHIFT 0x0
++#define VCE_LMI_VCPU_CACHE_40BIT_BAR6__BAR_MASK 0xFFFFFFFFL
++//VCE_LMI_VCPU_CACHE_40BIT_BAR7
++#define VCE_LMI_VCPU_CACHE_40BIT_BAR7__BAR__SHIFT 0x0
++#define VCE_LMI_VCPU_CACHE_40BIT_BAR7__BAR_MASK 0xFFFFFFFFL
++
++
++// addressBlock: vce0_mmsch_dec
++//VCE_MMSCH_VF_VMID
++#define VCE_MMSCH_VF_VMID__VF_CTX_VMID__SHIFT 0x0
++#define VCE_MMSCH_VF_VMID__VF_GPCOM_VMID__SHIFT 0x4
++#define VCE_MMSCH_VF_VMID__VF_CTX_VMID_MASK 0x0000000FL
++#define VCE_MMSCH_VF_VMID__VF_GPCOM_VMID_MASK 0x000000F0L
++//VCE_MMSCH_VF_CTX_ADDR_LO
++#define VCE_MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO__SHIFT 0x6
++#define VCE_MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO_MASK 0xFFFFFFC0L
++//VCE_MMSCH_VF_CTX_ADDR_HI
++#define VCE_MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI__SHIFT 0x0
++#define VCE_MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI_MASK 0xFFFFFFFFL
++//VCE_MMSCH_VF_CTX_SIZE
++#define VCE_MMSCH_VF_CTX_SIZE__VF_CTX_SIZE__SHIFT 0x0
++#define VCE_MMSCH_VF_CTX_SIZE__VF_CTX_SIZE_MASK 0xFFFFFFFFL
++//VCE_MMSCH_VF_GPCOM_ADDR_LO
++#define VCE_MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO__SHIFT 0x6
++#define VCE_MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO_MASK 0xFFFFFFC0L
++//VCE_MMSCH_VF_GPCOM_ADDR_HI
++#define VCE_MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI__SHIFT 0x0
++#define VCE_MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI_MASK 0xFFFFFFFFL
++//VCE_MMSCH_VF_GPCOM_SIZE
++#define VCE_MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE__SHIFT 0x0
++#define VCE_MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE_MASK 0xFFFFFFFFL
++//VCE_MMSCH_VF_MAILBOX_HOST
++#define VCE_MMSCH_VF_MAILBOX_HOST__DATA__SHIFT 0x0
++#define VCE_MMSCH_VF_MAILBOX_HOST__DATA_MASK 0xFFFFFFFFL
++//VCE_MMSCH_VF_MAILBOX_RESP
++#define VCE_MMSCH_VF_MAILBOX_RESP__RESP__SHIFT 0x0
++#define VCE_MMSCH_VF_MAILBOX_RESP__RESP_MASK 0xFFFFFFFFL
++
++
++// addressBlock: vce0_vce_rb_pg_dec
++//VCE_HW_VERSION
++#define VCE_HW_VERSION__VCE_VERSION__SHIFT 0x0
++#define VCE_HW_VERSION__VCE_CONFIGURATION__SHIFT 0x8
++#define VCE_HW_VERSION__VCE_INSTANCE_ID__SHIFT 0xa
++#define VCE_HW_VERSION__VCE_VERSION_MASK 0x000000FFL
++#define VCE_HW_VERSION__VCE_CONFIGURATION_MASK 0x00000300L
++#define VCE_HW_VERSION__VCE_INSTANCE_ID_MASK 0x00000C00L
++
++
++
++#endif
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_default.h
+deleted file mode 100644
+index c2a46c7..0000000
+--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_default.h
++++ /dev/null
+@@ -1,122 +0,0 @@
+-/*
+- * Copyright (C) 2017 Advanced Micro Devices, Inc.
+- *
+- * Permission is hereby granted, free of charge, to any person obtaining a
+- * copy of this software and associated documentation files (the "Software"),
+- * to deal in the Software without restriction, including without limitation
+- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+- * and/or sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following conditions:
+- *
+- * The above copyright notice and this permission notice shall be included
+- * in all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+- */
+-#ifndef _vce_4_0_DEFAULT_HEADER
+-#define _vce_4_0_DEFAULT_HEADER
+-
+-
+-// addressBlock: vce0_vce_dec
+-#define mmVCE_STATUS_DEFAULT 0x00000000
+-#define mmVCE_VCPU_CNTL_DEFAULT 0x00200000
+-#define mmVCE_VCPU_CACHE_OFFSET0_DEFAULT 0x00000000
+-#define mmVCE_VCPU_CACHE_SIZE0_DEFAULT 0x00000000
+-#define mmVCE_VCPU_CACHE_OFFSET1_DEFAULT 0x00000000
+-#define mmVCE_VCPU_CACHE_SIZE1_DEFAULT 0x00000000
+-#define mmVCE_VCPU_CACHE_OFFSET2_DEFAULT 0x00000000
+-#define mmVCE_VCPU_CACHE_SIZE2_DEFAULT 0x00000000
+-#define mmVCE_VCPU_CACHE_OFFSET3_DEFAULT 0x00000000
+-#define mmVCE_VCPU_CACHE_SIZE3_DEFAULT 0x00000000
+-#define mmVCE_VCPU_CACHE_OFFSET4_DEFAULT 0x00000000
+-#define mmVCE_VCPU_CACHE_SIZE4_DEFAULT 0x00000000
+-#define mmVCE_VCPU_CACHE_OFFSET5_DEFAULT 0x00000000
+-#define mmVCE_VCPU_CACHE_SIZE5_DEFAULT 0x00000000
+-#define mmVCE_VCPU_CACHE_OFFSET6_DEFAULT 0x00000000
+-#define mmVCE_VCPU_CACHE_SIZE6_DEFAULT 0x00000000
+-#define mmVCE_VCPU_CACHE_OFFSET7_DEFAULT 0x00000000
+-#define mmVCE_VCPU_CACHE_SIZE7_DEFAULT 0x00000000
+-#define mmVCE_VCPU_CACHE_OFFSET8_DEFAULT 0x00000000
+-#define mmVCE_VCPU_CACHE_SIZE8_DEFAULT 0x00000000
+-#define mmVCE_SOFT_RESET_DEFAULT 0x00000001
+-#define mmVCE_RB_BASE_LO2_DEFAULT 0x00000000
+-#define mmVCE_RB_BASE_HI2_DEFAULT 0x00000000
+-#define mmVCE_RB_SIZE2_DEFAULT 0x00000000
+-#define mmVCE_RB_RPTR2_DEFAULT 0x00000000
+-#define mmVCE_RB_WPTR2_DEFAULT 0x00000000
+-#define mmVCE_RB_BASE_LO_DEFAULT 0x00000000
+-#define mmVCE_RB_BASE_HI_DEFAULT 0x00000000
+-#define mmVCE_RB_SIZE_DEFAULT 0x00000000
+-#define mmVCE_RB_RPTR_DEFAULT 0x00000000
+-#define mmVCE_RB_WPTR_DEFAULT 0x00000000
+-#define mmVCE_RB_ARB_CTRL_DEFAULT 0x00010000
+-#define mmVCE_CLOCK_GATING_A_DEFAULT 0x00000040
+-#define mmVCE_CLOCK_GATING_B_DEFAULT 0x01ef0100
+-#define mmVCE_RB_BASE_LO3_DEFAULT 0x00000000
+-#define mmVCE_RB_BASE_HI3_DEFAULT 0x00000000
+-#define mmVCE_RB_SIZE3_DEFAULT 0x00000000
+-#define mmVCE_RB_RPTR3_DEFAULT 0x00000000
+-#define mmVCE_RB_WPTR3_DEFAULT 0x00000000
+-#define mmVCE_SYS_INT_EN_DEFAULT 0x00000000
+-#define mmVCE_SYS_INT_ACK_DEFAULT 0x00000000
+-#define mmVCE_SYS_INT_STATUS_DEFAULT 0x00000000
+-
+-
+-// addressBlock: vce0_ctl_dec
+-#define mmVCE_UENC_CLOCK_GATING_DEFAULT 0xffc00040
+-#define mmVCE_UENC_REG_CLOCK_GATING_DEFAULT 0x000007ff
+-#define mmVCE_UENC_CLOCK_GATING_2_DEFAULT 0x00010000
+-
+-
+-// addressBlock: vce0_vce_sclk_dec
+-#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR_DEFAULT 0x00000000
+-#define mmVCE_LMI_CTRL2_DEFAULT 0x00000000
+-#define mmVCE_LMI_SWAP_CNTL3_DEFAULT 0x00000000
+-#define mmVCE_LMI_CTRL_DEFAULT 0x00104000
+-#define mmVCE_LMI_STATUS_DEFAULT 0x00003f7f
+-#define mmVCE_LMI_VM_CTRL_DEFAULT 0x00000000
+-#define mmVCE_LMI_SWAP_CNTL_DEFAULT 0x00000000
+-#define mmVCE_LMI_SWAP_CNTL1_DEFAULT 0x00000000
+-#define mmVCE_LMI_SWAP_CNTL2_DEFAULT 0x00000000
+-#define mmVCE_LMI_CACHE_CTRL_DEFAULT 0x00000000
+-#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR0_DEFAULT 0x00000000
+-#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR1_DEFAULT 0x00000000
+-#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR2_DEFAULT 0x00000000
+-#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR3_DEFAULT 0x00000000
+-#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR4_DEFAULT 0x00000000
+-#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR5_DEFAULT 0x00000000
+-#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR6_DEFAULT 0x00000000
+-#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR7_DEFAULT 0x00000000
+-#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0_DEFAULT 0x00000000
+-#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1_DEFAULT 0x00000000
+-#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2_DEFAULT 0x00000000
+-#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR3_DEFAULT 0x00000000
+-#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR4_DEFAULT 0x00000000
+-#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR5_DEFAULT 0x00000000
+-#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR6_DEFAULT 0x00000000
+-#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR7_DEFAULT 0x00000000
+-
+-
+-// addressBlock: vce0_mmsch_dec
+-#define mmVCE_MMSCH_VF_VMID_DEFAULT 0x00000000
+-#define mmVCE_MMSCH_VF_CTX_ADDR_LO_DEFAULT 0x00000000
+-#define mmVCE_MMSCH_VF_CTX_ADDR_HI_DEFAULT 0x00000000
+-#define mmVCE_MMSCH_VF_CTX_SIZE_DEFAULT 0x00000000
+-#define mmVCE_MMSCH_VF_GPCOM_ADDR_LO_DEFAULT 0x00000000
+-#define mmVCE_MMSCH_VF_GPCOM_ADDR_HI_DEFAULT 0x00000000
+-#define mmVCE_MMSCH_VF_GPCOM_SIZE_DEFAULT 0x00000000
+-#define mmVCE_MMSCH_VF_MAILBOX_HOST_DEFAULT 0x00000000
+-#define mmVCE_MMSCH_VF_MAILBOX_RESP_DEFAULT 0x00000000
+-
+-
+-// addressBlock: vce0_vce_rb_pg_dec
+-#define mmVCE_HW_VERSION_DEFAULT 0x00000000
+-
+-
+-
+-#endif
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_offset.h
+deleted file mode 100644
+index 109303e..0000000
+--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_offset.h
++++ /dev/null
+@@ -1,208 +0,0 @@
+-/*
+- * Copyright (C) 2017 Advanced Micro Devices, Inc.
+- *
+- * Permission is hereby granted, free of charge, to any person obtaining a
+- * copy of this software and associated documentation files (the "Software"),
+- * to deal in the Software without restriction, including without limitation
+- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+- * and/or sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following conditions:
+- *
+- * The above copyright notice and this permission notice shall be included
+- * in all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+- */
+-#ifndef _vce_4_0_OFFSET_HEADER
+-#define _vce_4_0_OFFSET_HEADER
+-
+-
+-
+-// addressBlock: vce0_vce_dec
+-// base address: 0x22000
+-#define mmVCE_STATUS 0x0a01
+-#define mmVCE_STATUS_BASE_IDX 0
+-#define mmVCE_VCPU_CNTL 0x0a05
+-#define mmVCE_VCPU_CNTL_BASE_IDX 0
+-#define mmVCE_VCPU_CACHE_OFFSET0 0x0a09
+-#define mmVCE_VCPU_CACHE_OFFSET0_BASE_IDX 0
+-#define mmVCE_VCPU_CACHE_SIZE0 0x0a0a
+-#define mmVCE_VCPU_CACHE_SIZE0_BASE_IDX 0
+-#define mmVCE_VCPU_CACHE_OFFSET1 0x0a0b
+-#define mmVCE_VCPU_CACHE_OFFSET1_BASE_IDX 0
+-#define mmVCE_VCPU_CACHE_SIZE1 0x0a0c
+-#define mmVCE_VCPU_CACHE_SIZE1_BASE_IDX 0
+-#define mmVCE_VCPU_CACHE_OFFSET2 0x0a0d
+-#define mmVCE_VCPU_CACHE_OFFSET2_BASE_IDX 0
+-#define mmVCE_VCPU_CACHE_SIZE2 0x0a0e
+-#define mmVCE_VCPU_CACHE_SIZE2_BASE_IDX 0
+-#define mmVCE_VCPU_CACHE_OFFSET3 0x0a0f
+-#define mmVCE_VCPU_CACHE_OFFSET3_BASE_IDX 0
+-#define mmVCE_VCPU_CACHE_SIZE3 0x0a10
+-#define mmVCE_VCPU_CACHE_SIZE3_BASE_IDX 0
+-#define mmVCE_VCPU_CACHE_OFFSET4 0x0a11
+-#define mmVCE_VCPU_CACHE_OFFSET4_BASE_IDX 0
+-#define mmVCE_VCPU_CACHE_SIZE4 0x0a12
+-#define mmVCE_VCPU_CACHE_SIZE4_BASE_IDX 0
+-#define mmVCE_VCPU_CACHE_OFFSET5 0x0a13
+-#define mmVCE_VCPU_CACHE_OFFSET5_BASE_IDX 0
+-#define mmVCE_VCPU_CACHE_SIZE5 0x0a14
+-#define mmVCE_VCPU_CACHE_SIZE5_BASE_IDX 0
+-#define mmVCE_VCPU_CACHE_OFFSET6 0x0a15
+-#define mmVCE_VCPU_CACHE_OFFSET6_BASE_IDX 0
+-#define mmVCE_VCPU_CACHE_SIZE6 0x0a16
+-#define mmVCE_VCPU_CACHE_SIZE6_BASE_IDX 0
+-#define mmVCE_VCPU_CACHE_OFFSET7 0x0a17
+-#define mmVCE_VCPU_CACHE_OFFSET7_BASE_IDX 0
+-#define mmVCE_VCPU_CACHE_SIZE7 0x0a18
+-#define mmVCE_VCPU_CACHE_SIZE7_BASE_IDX 0
+-#define mmVCE_VCPU_CACHE_OFFSET8 0x0a19
+-#define mmVCE_VCPU_CACHE_OFFSET8_BASE_IDX 0
+-#define mmVCE_VCPU_CACHE_SIZE8 0x0a1a
+-#define mmVCE_VCPU_CACHE_SIZE8_BASE_IDX 0
+-#define mmVCE_SOFT_RESET 0x0a48
+-#define mmVCE_SOFT_RESET_BASE_IDX 0
+-#define mmVCE_RB_BASE_LO2 0x0a5b
+-#define mmVCE_RB_BASE_LO2_BASE_IDX 0
+-#define mmVCE_RB_BASE_HI2 0x0a5c
+-#define mmVCE_RB_BASE_HI2_BASE_IDX 0
+-#define mmVCE_RB_SIZE2 0x0a5d
+-#define mmVCE_RB_SIZE2_BASE_IDX 0
+-#define mmVCE_RB_RPTR2 0x0a5e
+-#define mmVCE_RB_RPTR2_BASE_IDX 0
+-#define mmVCE_RB_WPTR2 0x0a5f
+-#define mmVCE_RB_WPTR2_BASE_IDX 0
+-#define mmVCE_RB_BASE_LO 0x0a60
+-#define mmVCE_RB_BASE_LO_BASE_IDX 0
+-#define mmVCE_RB_BASE_HI 0x0a61
+-#define mmVCE_RB_BASE_HI_BASE_IDX 0
+-#define mmVCE_RB_SIZE 0x0a62
+-#define mmVCE_RB_SIZE_BASE_IDX 0
+-#define mmVCE_RB_RPTR 0x0a63
+-#define mmVCE_RB_RPTR_BASE_IDX 0
+-#define mmVCE_RB_WPTR 0x0a64
+-#define mmVCE_RB_WPTR_BASE_IDX 0
+-#define mmVCE_RB_ARB_CTRL 0x0a9f
+-#define mmVCE_RB_ARB_CTRL_BASE_IDX 0
+-#define mmVCE_CLOCK_GATING_A 0x0abe
+-#define mmVCE_CLOCK_GATING_A_BASE_IDX 0
+-#define mmVCE_CLOCK_GATING_B 0x0abf
+-#define mmVCE_CLOCK_GATING_B_BASE_IDX 0
+-#define mmVCE_RB_BASE_LO3 0x0ad4
+-#define mmVCE_RB_BASE_LO3_BASE_IDX 0
+-#define mmVCE_RB_BASE_HI3 0x0ad5
+-#define mmVCE_RB_BASE_HI3_BASE_IDX 0
+-#define mmVCE_RB_SIZE3 0x0ad6
+-#define mmVCE_RB_SIZE3_BASE_IDX 0
+-#define mmVCE_RB_RPTR3 0x0ad7
+-#define mmVCE_RB_RPTR3_BASE_IDX 0
+-#define mmVCE_RB_WPTR3 0x0ad8
+-#define mmVCE_RB_WPTR3_BASE_IDX 0
+-#define mmVCE_SYS_INT_EN 0x0b00
+-#define mmVCE_SYS_INT_EN_BASE_IDX 0
+-#define mmVCE_SYS_INT_ACK 0x0b01
+-#define mmVCE_SYS_INT_ACK_BASE_IDX 0
+-#define mmVCE_SYS_INT_STATUS 0x0b01
+-#define mmVCE_SYS_INT_STATUS_BASE_IDX 0
+-
+-
+-// addressBlock: vce0_ctl_dec
+-// base address: 0x22780
+-#define mmVCE_UENC_CLOCK_GATING 0x0bef
+-#define mmVCE_UENC_CLOCK_GATING_BASE_IDX 0
+-#define mmVCE_UENC_REG_CLOCK_GATING 0x0bf0
+-#define mmVCE_UENC_REG_CLOCK_GATING_BASE_IDX 0
+-#define mmVCE_UENC_CLOCK_GATING_2 0x0c10
+-#define mmVCE_UENC_CLOCK_GATING_2_BASE_IDX 0
+-
+-
+-// addressBlock: vce0_vce_sclk_dec
+-// base address: 0x23700
+-#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR 0x0fcc
+-#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR_BASE_IDX 0
+-#define mmVCE_LMI_CTRL2 0x0fcf
+-#define mmVCE_LMI_CTRL2_BASE_IDX 0
+-#define mmVCE_LMI_SWAP_CNTL3 0x0fd0
+-#define mmVCE_LMI_SWAP_CNTL3_BASE_IDX 0
+-#define mmVCE_LMI_CTRL 0x0fd6
+-#define mmVCE_LMI_CTRL_BASE_IDX 0
+-#define mmVCE_LMI_STATUS 0x0fd7
+-#define mmVCE_LMI_STATUS_BASE_IDX 0
+-#define mmVCE_LMI_VM_CTRL 0x0fd8
+-#define mmVCE_LMI_VM_CTRL_BASE_IDX 0
+-#define mmVCE_LMI_SWAP_CNTL 0x0fdd
+-#define mmVCE_LMI_SWAP_CNTL_BASE_IDX 0
+-#define mmVCE_LMI_SWAP_CNTL1 0x0fde
+-#define mmVCE_LMI_SWAP_CNTL1_BASE_IDX 0
+-#define mmVCE_LMI_SWAP_CNTL2 0x0fe2
+-#define mmVCE_LMI_SWAP_CNTL2_BASE_IDX 0
+-#define mmVCE_LMI_CACHE_CTRL 0x0fec
+-#define mmVCE_LMI_CACHE_CTRL_BASE_IDX 0
+-#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR0 0x1086
+-#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR0_BASE_IDX 0
+-#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR1 0x1087
+-#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR1_BASE_IDX 0
+-#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR2 0x1088
+-#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR2_BASE_IDX 0
+-#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR3 0x1089
+-#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR3_BASE_IDX 0
+-#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR4 0x108a
+-#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR4_BASE_IDX 0
+-#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR5 0x108b
+-#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR5_BASE_IDX 0
+-#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR6 0x108c
+-#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR6_BASE_IDX 0
+-#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR7 0x108d
+-#define mmVCE_LMI_VCPU_CACHE_64BIT_BAR7_BASE_IDX 0
+-#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0 0x1096
+-#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR0_BASE_IDX 0
+-#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1 0x1097
+-#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR1_BASE_IDX 0
+-#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2 0x1098
+-#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR2_BASE_IDX 0
+-#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR3 0x1099
+-#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR3_BASE_IDX 0
+-#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR4 0x109a
+-#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR4_BASE_IDX 0
+-#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR5 0x109b
+-#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR5_BASE_IDX 0
+-#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR6 0x109c
+-#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR6_BASE_IDX 0
+-#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR7 0x109d
+-#define mmVCE_LMI_VCPU_CACHE_40BIT_BAR7_BASE_IDX 0
+-
+-
+-// addressBlock: vce0_mmsch_dec
+-// base address: 0x23b00
+-#define mmVCE_MMSCH_VF_VMID 0x10cb
+-#define mmVCE_MMSCH_VF_VMID_BASE_IDX 0
+-#define mmVCE_MMSCH_VF_CTX_ADDR_LO 0x10cc
+-#define mmVCE_MMSCH_VF_CTX_ADDR_LO_BASE_IDX 0
+-#define mmVCE_MMSCH_VF_CTX_ADDR_HI 0x10cd
+-#define mmVCE_MMSCH_VF_CTX_ADDR_HI_BASE_IDX 0
+-#define mmVCE_MMSCH_VF_CTX_SIZE 0x10ce
+-#define mmVCE_MMSCH_VF_CTX_SIZE_BASE_IDX 0
+-#define mmVCE_MMSCH_VF_GPCOM_ADDR_LO 0x10cf
+-#define mmVCE_MMSCH_VF_GPCOM_ADDR_LO_BASE_IDX 0
+-#define mmVCE_MMSCH_VF_GPCOM_ADDR_HI 0x10d0
+-#define mmVCE_MMSCH_VF_GPCOM_ADDR_HI_BASE_IDX 0
+-#define mmVCE_MMSCH_VF_GPCOM_SIZE 0x10d1
+-#define mmVCE_MMSCH_VF_GPCOM_SIZE_BASE_IDX 0
+-#define mmVCE_MMSCH_VF_MAILBOX_HOST 0x10d2
+-#define mmVCE_MMSCH_VF_MAILBOX_HOST_BASE_IDX 0
+-#define mmVCE_MMSCH_VF_MAILBOX_RESP 0x10d3
+-#define mmVCE_MMSCH_VF_MAILBOX_RESP_BASE_IDX 0
+-
+-
+-// addressBlock: vce0_vce_rb_pg_dec
+-// base address: 0x23fa0
+-#define mmVCE_HW_VERSION 0x11e8
+-#define mmVCE_HW_VERSION_BASE_IDX 0
+-
+-
+-#endif
+diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_sh_mask.h
+deleted file mode 100644
+index 4cf6e44..0000000
+--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_sh_mask.h
++++ /dev/null
+@@ -1,488 +0,0 @@
+-/*
+- * Copyright (C) 2017 Advanced Micro Devices, Inc.
+- *
+- * Permission is hereby granted, free of charge, to any person obtaining a
+- * copy of this software and associated documentation files (the "Software"),
+- * to deal in the Software without restriction, including without limitation
+- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+- * and/or sell copies of the Software, and to permit persons to whom the
+- * Software is furnished to do so, subject to the following conditions:
+- *
+- * The above copyright notice and this permission notice shall be included
+- * in all copies or substantial portions of the Software.
+- *
+- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+- */
+-#ifndef _vce_4_0_SH_MASK_HEADER
+-#define _vce_4_0_SH_MASK_HEADER
+-
+-
+-// addressBlock: vce0_vce_dec
+-//VCE_STATUS
+-#define VCE_STATUS__JOB_BUSY__SHIFT 0x0
+-#define VCE_STATUS__VCPU_REPORT__SHIFT 0x1
+-#define VCE_STATUS__UENC_BUSY__SHIFT 0x8
+-#define VCE_STATUS__VCE_CONFIGURATION__SHIFT 0x16
+-#define VCE_STATUS__VCE_INSTANCE_ID__SHIFT 0x18
+-#define VCE_STATUS__JOB_BUSY_MASK 0x00000001L
+-#define VCE_STATUS__VCPU_REPORT_MASK 0x000000FEL
+-#define VCE_STATUS__UENC_BUSY_MASK 0x00000100L
+-#define VCE_STATUS__VCE_CONFIGURATION_MASK 0x00C00000L
+-#define VCE_STATUS__VCE_INSTANCE_ID_MASK 0x03000000L
+-//VCE_VCPU_CNTL
+-#define VCE_VCPU_CNTL__CLK_EN__SHIFT 0x0
+-#define VCE_VCPU_CNTL__ED_ENABLE__SHIFT 0x1
+-#define VCE_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x12
+-#define VCE_VCPU_CNTL__ONE_CACHE_SURFACE_EN__SHIFT 0x15
+-#define VCE_VCPU_CNTL__CLK_EN_MASK 0x00000001L
+-#define VCE_VCPU_CNTL__ED_ENABLE_MASK 0x00000002L
+-#define VCE_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x00040000L
+-#define VCE_VCPU_CNTL__ONE_CACHE_SURFACE_EN_MASK 0x00200000L
+-//VCE_VCPU_CACHE_OFFSET0
+-#define VCE_VCPU_CACHE_OFFSET0__OFFSET__SHIFT 0x0
+-#define VCE_VCPU_CACHE_OFFSET0__OFFSET_MASK 0x0FFFFFFFL
+-//VCE_VCPU_CACHE_SIZE0
+-#define VCE_VCPU_CACHE_SIZE0__SIZE__SHIFT 0x0
+-#define VCE_VCPU_CACHE_SIZE0__SIZE_MASK 0x00FFFFFFL
+-//VCE_VCPU_CACHE_OFFSET1
+-#define VCE_VCPU_CACHE_OFFSET1__OFFSET__SHIFT 0x0
+-#define VCE_VCPU_CACHE_OFFSET1__OFFSET_MASK 0x0FFFFFFFL
+-//VCE_VCPU_CACHE_SIZE1
+-#define VCE_VCPU_CACHE_SIZE1__SIZE__SHIFT 0x0
+-#define VCE_VCPU_CACHE_SIZE1__SIZE_MASK 0x00FFFFFFL
+-//VCE_VCPU_CACHE_OFFSET2
+-#define VCE_VCPU_CACHE_OFFSET2__OFFSET__SHIFT 0x0
+-#define VCE_VCPU_CACHE_OFFSET2__OFFSET_MASK 0x0FFFFFFFL
+-//VCE_VCPU_CACHE_SIZE2
+-#define VCE_VCPU_CACHE_SIZE2__SIZE__SHIFT 0x0
+-#define VCE_VCPU_CACHE_SIZE2__SIZE_MASK 0x00FFFFFFL
+-//VCE_VCPU_CACHE_OFFSET3
+-#define VCE_VCPU_CACHE_OFFSET3__OFFSET__SHIFT 0x0
+-#define VCE_VCPU_CACHE_OFFSET3__OFFSET_MASK 0x0FFFFFFFL
+-//VCE_VCPU_CACHE_SIZE3
+-#define VCE_VCPU_CACHE_SIZE3__SIZE__SHIFT 0x0
+-#define VCE_VCPU_CACHE_SIZE3__SIZE_MASK 0x00FFFFFFL
+-//VCE_VCPU_CACHE_OFFSET4
+-#define VCE_VCPU_CACHE_OFFSET4__OFFSET__SHIFT 0x0
+-#define VCE_VCPU_CACHE_OFFSET4__OFFSET_MASK 0x0FFFFFFFL
+-//VCE_VCPU_CACHE_SIZE4
+-#define VCE_VCPU_CACHE_SIZE4__SIZE__SHIFT 0x0
+-#define VCE_VCPU_CACHE_SIZE4__SIZE_MASK 0x00FFFFFFL
+-//VCE_VCPU_CACHE_OFFSET5
+-#define VCE_VCPU_CACHE_OFFSET5__OFFSET__SHIFT 0x0
+-#define VCE_VCPU_CACHE_OFFSET5__OFFSET_MASK 0x0FFFFFFFL
+-//VCE_VCPU_CACHE_SIZE5
+-#define VCE_VCPU_CACHE_SIZE5__SIZE__SHIFT 0x0
+-#define VCE_VCPU_CACHE_SIZE5__SIZE_MASK 0x00FFFFFFL
+-//VCE_VCPU_CACHE_OFFSET6
+-#define VCE_VCPU_CACHE_OFFSET6__OFFSET__SHIFT 0x0
+-#define VCE_VCPU_CACHE_OFFSET6__OFFSET_MASK 0x0FFFFFFFL
+-//VCE_VCPU_CACHE_SIZE6
+-#define VCE_VCPU_CACHE_SIZE6__SIZE__SHIFT 0x0
+-#define VCE_VCPU_CACHE_SIZE6__SIZE_MASK 0x00FFFFFFL
+-//VCE_VCPU_CACHE_OFFSET7
+-#define VCE_VCPU_CACHE_OFFSET7__OFFSET__SHIFT 0x0
+-#define VCE_VCPU_CACHE_OFFSET7__OFFSET_MASK 0x0FFFFFFFL
+-//VCE_VCPU_CACHE_SIZE7
+-#define VCE_VCPU_CACHE_SIZE7__SIZE__SHIFT 0x0
+-#define VCE_VCPU_CACHE_SIZE7__SIZE_MASK 0x00FFFFFFL
+-//VCE_VCPU_CACHE_OFFSET8
+-#define VCE_VCPU_CACHE_OFFSET8__OFFSET__SHIFT 0x0
+-#define VCE_VCPU_CACHE_OFFSET8__OFFSET_MASK 0x0FFFFFFFL
+-//VCE_VCPU_CACHE_SIZE8
+-#define VCE_VCPU_CACHE_SIZE8__SIZE__SHIFT 0x0
+-#define VCE_VCPU_CACHE_SIZE8__SIZE_MASK 0x00FFFFFFL
+-//VCE_SOFT_RESET
+-#define VCE_SOFT_RESET__ECPU_SOFT_RESET__SHIFT 0x0
+-#define VCE_SOFT_RESET__UENC_SOFT_RESET__SHIFT 0x1
+-#define VCE_SOFT_RESET__FME_SOFT_RESET__SHIFT 0x2
+-#define VCE_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0x3
+-#define VCE_SOFT_RESET__DBF_SOFT_RESET__SHIFT 0x4
+-#define VCE_SOFT_RESET__ENT_SOFT_RESET__SHIFT 0x5
+-#define VCE_SOFT_RESET__TBE_SOFT_RESET__SHIFT 0x6
+-#define VCE_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x7
+-#define VCE_SOFT_RESET__CTL_SOFT_RESET__SHIFT 0x8
+-#define VCE_SOFT_RESET__IME_SOFT_RESET__SHIFT 0x9
+-#define VCE_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa
+-#define VCE_SOFT_RESET__SEM_SOFT_RESET__SHIFT 0xb
+-#define VCE_SOFT_RESET__DCAP_SOFT_RESET__SHIFT 0xc
+-#define VCE_SOFT_RESET__ACAP_SOFT_RESET__SHIFT 0xd
+-#define VCE_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0xe
+-#define VCE_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0xf
+-#define VCE_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0x10
+-#define VCE_SOFT_RESET__AVMUX_SOFT_RESET__SHIFT 0x13
+-#define VCE_SOFT_RESET__VREG_SOFT_RESET__SHIFT 0x14
+-#define VCE_SOFT_RESET__DCAP_FSM_SOFT_RESET__SHIFT 0x15
+-#define VCE_SOFT_RESET__VEP_SOFT_RESET__SHIFT 0x16
+-#define VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK 0x00000001L
+-#define VCE_SOFT_RESET__UENC_SOFT_RESET_MASK 0x00000002L
+-#define VCE_SOFT_RESET__FME_SOFT_RESET_MASK 0x00000004L
+-#define VCE_SOFT_RESET__MIF_SOFT_RESET_MASK 0x00000008L
+-#define VCE_SOFT_RESET__DBF_SOFT_RESET_MASK 0x00000010L
+-#define VCE_SOFT_RESET__ENT_SOFT_RESET_MASK 0x00000020L
+-#define VCE_SOFT_RESET__TBE_SOFT_RESET_MASK 0x00000040L
+-#define VCE_SOFT_RESET__LCM_SOFT_RESET_MASK 0x00000080L
+-#define VCE_SOFT_RESET__CTL_SOFT_RESET_MASK 0x00000100L
+-#define VCE_SOFT_RESET__IME_SOFT_RESET_MASK 0x00000200L
+-#define VCE_SOFT_RESET__IH_SOFT_RESET_MASK 0x00000400L
+-#define VCE_SOFT_RESET__SEM_SOFT_RESET_MASK 0x00000800L
+-#define VCE_SOFT_RESET__DCAP_SOFT_RESET_MASK 0x00001000L
+-#define VCE_SOFT_RESET__ACAP_SOFT_RESET_MASK 0x00002000L
+-#define VCE_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00004000L
+-#define VCE_SOFT_RESET__LMI_SOFT_RESET_MASK 0x00008000L
+-#define VCE_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x00010000L
+-#define VCE_SOFT_RESET__AVMUX_SOFT_RESET_MASK 0x00080000L
+-#define VCE_SOFT_RESET__VREG_SOFT_RESET_MASK 0x00100000L
+-#define VCE_SOFT_RESET__DCAP_FSM_SOFT_RESET_MASK 0x00200000L
+-#define VCE_SOFT_RESET__VEP_SOFT_RESET_MASK 0x00400000L
+-//VCE_RB_BASE_LO2
+-#define VCE_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6
+-#define VCE_RB_BASE_LO2__RB_BASE_LO_MASK 0xFFFFFFC0L
+-//VCE_RB_BASE_HI2
+-#define VCE_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0
+-#define VCE_RB_BASE_HI2__RB_BASE_HI_MASK 0xFFFFFFFFL
+-//VCE_RB_SIZE2
+-#define VCE_RB_SIZE2__RB_SIZE__SHIFT 0x4
+-#define VCE_RB_SIZE2__RB_SIZE_MASK 0x007FFFF0L
+-//VCE_RB_RPTR2
+-#define VCE_RB_RPTR2__RB_RPTR__SHIFT 0x4
+-#define VCE_RB_RPTR2__RB_RPTR_MASK 0x007FFFF0L
+-//VCE_RB_WPTR2
+-#define VCE_RB_WPTR2__RB_WPTR__SHIFT 0x4
+-#define VCE_RB_WPTR2__RB_WPTR_MASK 0x007FFFF0L
+-//VCE_RB_BASE_LO
+-#define VCE_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6
+-#define VCE_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L
+-//VCE_RB_BASE_HI
+-#define VCE_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0
+-#define VCE_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL
+-//VCE_RB_SIZE
+-#define VCE_RB_SIZE__RB_SIZE__SHIFT 0x4
+-#define VCE_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L
+-//VCE_RB_RPTR
+-#define VCE_RB_RPTR__RB_RPTR__SHIFT 0x4
+-#define VCE_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L
+-//VCE_RB_WPTR
+-#define VCE_RB_WPTR__RB_WPTR__SHIFT 0x4
+-#define VCE_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L
+-//VCE_RB_ARB_CTRL
+-#define VCE_RB_ARB_CTRL__RB_ARB_CTRL__SHIFT 0x0
+-#define VCE_RB_ARB_CTRL__VCE_CGTT_OVERRIDE__SHIFT 0x10
+-#define VCE_RB_ARB_CTRL__RB_ARB_CTRL_MASK 0x000001FFL
+-#define VCE_RB_ARB_CTRL__VCE_CGTT_OVERRIDE_MASK 0x00010000L
+-//VCE_CLOCK_GATING_A
+-#define VCE_CLOCK_GATING_A__CGC_CLK_ON_DELAY__SHIFT 0x0
+-#define VCE_CLOCK_GATING_A__CGC_CLK_OFF_DELAY__SHIFT 0x4
+-#define VCE_CLOCK_GATING_A__CGC_REG_AWAKE__SHIFT 0x11
+-#define VCE_CLOCK_GATING_A__CGC_CLK_ON_DELAY_MASK 0x0000000FL
+-#define VCE_CLOCK_GATING_A__CGC_CLK_OFF_DELAY_MASK 0x00000FF0L
+-#define VCE_CLOCK_GATING_A__CGC_REG_AWAKE_MASK 0x00020000L
+-//VCE_CLOCK_GATING_B
+-#define VCE_CLOCK_GATING_B__CGC_SYS_CLK_FORCE_ON__SHIFT 0x0
+-#define VCE_CLOCK_GATING_B__CGC_LMI_MC_CLK_FORCE_ON__SHIFT 0x1
+-#define VCE_CLOCK_GATING_B__CGC_LMI_UMC_CLK_FORCE_ON__SHIFT 0x2
+-#define VCE_CLOCK_GATING_B__CGC_UENC_CLK_FORCE_ON__SHIFT 0x3
+-#define VCE_CLOCK_GATING_B__CGC_VREG_CLK_FORCE_ON__SHIFT 0x4
+-#define VCE_CLOCK_GATING_B__CGC_ECPU_CLK_FORCE_ON__SHIFT 0x5
+-#define VCE_CLOCK_GATING_B__CGC_IH_CLK_FORCE_ON__SHIFT 0x6
+-#define VCE_CLOCK_GATING_B__CGC_SEM_CLK_FORCE_ON__SHIFT 0x7
+-#define VCE_CLOCK_GATING_B__CGC_CTLREG_CLK_FORCE_ON__SHIFT 0x8
+-#define VCE_CLOCK_GATING_B__CGC_MMSCH_CLK_FORCE_ON__SHIFT 0x9
+-#define VCE_CLOCK_GATING_B__CGC_SYS_CLK_FORCE_OFF__SHIFT 0x10
+-#define VCE_CLOCK_GATING_B__CGC_LMI_MC_CLK_FORCE_OFF__SHIFT 0x11
+-#define VCE_CLOCK_GATING_B__CGC_LMI_UMC_CLK_FORCE_OFF__SHIFT 0x12
+-#define VCE_CLOCK_GATING_B__CGC_UENC_CLK_FORCE_OFF__SHIFT 0x13
+-#define VCE_CLOCK_GATING_B__CGC_ECPU_CLK_FORCE_OFF__SHIFT 0x15
+-#define VCE_CLOCK_GATING_B__CGC_IH_CLK_FORCE_OFF__SHIFT 0x16
+-#define VCE_CLOCK_GATING_B__CGC_SEM_CLK_FORCE_OFF__SHIFT 0x17
+-#define VCE_CLOCK_GATING_B__CGC_MMSCH_CLK_FORCE_OFF__SHIFT 0x18
+-#define VCE_CLOCK_GATING_B__CGC_SYS_CLK_FORCE_ON_MASK 0x00000001L
+-#define VCE_CLOCK_GATING_B__CGC_LMI_MC_CLK_FORCE_ON_MASK 0x00000002L
+-#define VCE_CLOCK_GATING_B__CGC_LMI_UMC_CLK_FORCE_ON_MASK 0x00000004L
+-#define VCE_CLOCK_GATING_B__CGC_UENC_CLK_FORCE_ON_MASK 0x00000008L
+-#define VCE_CLOCK_GATING_B__CGC_VREG_CLK_FORCE_ON_MASK 0x00000010L
+-#define VCE_CLOCK_GATING_B__CGC_ECPU_CLK_FORCE_ON_MASK 0x00000020L
+-#define VCE_CLOCK_GATING_B__CGC_IH_CLK_FORCE_ON_MASK 0x00000040L
+-#define VCE_CLOCK_GATING_B__CGC_SEM_CLK_FORCE_ON_MASK 0x00000080L
+-#define VCE_CLOCK_GATING_B__CGC_CTLREG_CLK_FORCE_ON_MASK 0x00000100L
+-#define VCE_CLOCK_GATING_B__CGC_MMSCH_CLK_FORCE_ON_MASK 0x00000200L
+-#define VCE_CLOCK_GATING_B__CGC_SYS_CLK_FORCE_OFF_MASK 0x00010000L
+-#define VCE_CLOCK_GATING_B__CGC_LMI_MC_CLK_FORCE_OFF_MASK 0x00020000L
+-#define VCE_CLOCK_GATING_B__CGC_LMI_UMC_CLK_FORCE_OFF_MASK 0x00040000L
+-#define VCE_CLOCK_GATING_B__CGC_UENC_CLK_FORCE_OFF_MASK 0x00080000L
+-#define VCE_CLOCK_GATING_B__CGC_ECPU_CLK_FORCE_OFF_MASK 0x00200000L
+-#define VCE_CLOCK_GATING_B__CGC_IH_CLK_FORCE_OFF_MASK 0x00400000L
+-#define VCE_CLOCK_GATING_B__CGC_SEM_CLK_FORCE_OFF_MASK 0x00800000L
+-#define VCE_CLOCK_GATING_B__CGC_MMSCH_CLK_FORCE_OFF_MASK 0x01000000L
+-//VCE_RB_BASE_LO3
+-#define VCE_RB_BASE_LO3__RB_BASE_LO__SHIFT 0x6
+-#define VCE_RB_BASE_LO3__RB_BASE_LO_MASK 0xFFFFFFC0L
+-//VCE_RB_BASE_HI3
+-#define VCE_RB_BASE_HI3__RB_BASE_HI__SHIFT 0x0
+-#define VCE_RB_BASE_HI3__RB_BASE_HI_MASK 0xFFFFFFFFL
+-//VCE_RB_SIZE3
+-#define VCE_RB_SIZE3__RB_SIZE__SHIFT 0x4
+-#define VCE_RB_SIZE3__RB_SIZE_MASK 0x007FFFF0L
+-//VCE_RB_RPTR3
+-#define VCE_RB_RPTR3__RB_RPTR__SHIFT 0x4
+-#define VCE_RB_RPTR3__RB_RPTR_MASK 0x007FFFF0L
+-//VCE_RB_WPTR3
+-#define VCE_RB_WPTR3__RB_WPTR__SHIFT 0x4
+-#define VCE_RB_WPTR3__RB_WPTR_MASK 0x007FFFF0L
+-//VCE_SYS_INT_EN
+-#define VCE_SYS_INT_EN__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_EN__SHIFT 0x0
+-#define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN__SHIFT 0x3
+-#define VCE_SYS_INT_EN__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_EN_MASK 0x00000001L
+-#define VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK 0x00000008L
+-//VCE_SYS_INT_ACK
+-#define VCE_SYS_INT_ACK__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_ACK__SHIFT 0x0
+-#define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK__SHIFT 0x3
+-#define VCE_SYS_INT_ACK__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_ACK_MASK 0x00000001L
+-#define VCE_SYS_INT_ACK__VCE_SYS_INT_TRAP_INTERRUPT_ACK_MASK 0x00000008L
+-//VCE_SYS_INT_STATUS
+-#define VCE_SYS_INT_STATUS__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_INT__SHIFT 0x0
+-#define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT__SHIFT 0x3
+-#define VCE_SYS_INT_STATUS__VCE_SYS_INT_SEMA_WAIT_FAIL_TIMEOUT_INT_MASK 0x00000001L
+-#define VCE_SYS_INT_STATUS__VCE_SYS_INT_TRAP_INTERRUPT_INT_MASK 0x00000008L
+-
+-
+-// addressBlock: vce0_ctl_dec
+-//VCE_UENC_CLOCK_GATING
+-#define VCE_UENC_CLOCK_GATING__CLOCK_ON_DELAY__SHIFT 0x0
+-#define VCE_UENC_CLOCK_GATING__CLOCK_OFF_DELAY__SHIFT 0x4
+-#define VCE_UENC_CLOCK_GATING__VEPCLK_FORCE_ON__SHIFT 0xc
+-#define VCE_UENC_CLOCK_GATING__IMECLK_FORCE_ON__SHIFT 0xd
+-#define VCE_UENC_CLOCK_GATING__FMECLK_FORCE_ON__SHIFT 0xe
+-#define VCE_UENC_CLOCK_GATING__TBECLK_FORCE_ON__SHIFT 0xf
+-#define VCE_UENC_CLOCK_GATING__DBFCLK_FORCE_ON__SHIFT 0x10
+-#define VCE_UENC_CLOCK_GATING__ENTCLK_FORCE_ON__SHIFT 0x11
+-#define VCE_UENC_CLOCK_GATING__LCMCLK_FORCE_ON__SHIFT 0x12
+-#define VCE_UENC_CLOCK_GATING__AVMCLK_FORCE_ON__SHIFT 0x13
+-#define VCE_UENC_CLOCK_GATING__DCAPCLK_FORCE_ON__SHIFT 0x14
+-#define VCE_UENC_CLOCK_GATING__ACAPCLK_FORCE_ON__SHIFT 0x15
+-#define VCE_UENC_CLOCK_GATING__ACAPCLK_FORCE_OFF__SHIFT 0x16
+-#define VCE_UENC_CLOCK_GATING__VEPCLK_FORCE_OFF__SHIFT 0x17
+-#define VCE_UENC_CLOCK_GATING__IMECLK_FORCE_OFF__SHIFT 0x18
+-#define VCE_UENC_CLOCK_GATING__FMECLK_FORCE_OFF__SHIFT 0x19
+-#define VCE_UENC_CLOCK_GATING__TBECLK_FORCE_OFF__SHIFT 0x1a
+-#define VCE_UENC_CLOCK_GATING__DBFCLK_FORCE_OFF__SHIFT 0x1b
+-#define VCE_UENC_CLOCK_GATING__ENTCLK_FORCE_OFF__SHIFT 0x1c
+-#define VCE_UENC_CLOCK_GATING__LCMCLK_FORCE_OFF__SHIFT 0x1d
+-#define VCE_UENC_CLOCK_GATING__AVMCLK_FORCE_OFF__SHIFT 0x1e
+-#define VCE_UENC_CLOCK_GATING__DCAPCLK_FORCE_OFF__SHIFT 0x1f
+-#define VCE_UENC_CLOCK_GATING__CLOCK_ON_DELAY_MASK 0x0000000FL
+-#define VCE_UENC_CLOCK_GATING__CLOCK_OFF_DELAY_MASK 0x00000FF0L
+-#define VCE_UENC_CLOCK_GATING__VEPCLK_FORCE_ON_MASK 0x00001000L
+-#define VCE_UENC_CLOCK_GATING__IMECLK_FORCE_ON_MASK 0x00002000L
+-#define VCE_UENC_CLOCK_GATING__FMECLK_FORCE_ON_MASK 0x00004000L
+-#define VCE_UENC_CLOCK_GATING__TBECLK_FORCE_ON_MASK 0x00008000L
+-#define VCE_UENC_CLOCK_GATING__DBFCLK_FORCE_ON_MASK 0x00010000L
+-#define VCE_UENC_CLOCK_GATING__ENTCLK_FORCE_ON_MASK 0x00020000L
+-#define VCE_UENC_CLOCK_GATING__LCMCLK_FORCE_ON_MASK 0x00040000L
+-#define VCE_UENC_CLOCK_GATING__AVMCLK_FORCE_ON_MASK 0x00080000L
+-#define VCE_UENC_CLOCK_GATING__DCAPCLK_FORCE_ON_MASK 0x00100000L
+-#define VCE_UENC_CLOCK_GATING__ACAPCLK_FORCE_ON_MASK 0x00200000L
+-#define VCE_UENC_CLOCK_GATING__ACAPCLK_FORCE_OFF_MASK 0x00400000L
+-#define VCE_UENC_CLOCK_GATING__VEPCLK_FORCE_OFF_MASK 0x00800000L
+-#define VCE_UENC_CLOCK_GATING__IMECLK_FORCE_OFF_MASK 0x01000000L
+-#define VCE_UENC_CLOCK_GATING__FMECLK_FORCE_OFF_MASK 0x02000000L
+-#define VCE_UENC_CLOCK_GATING__TBECLK_FORCE_OFF_MASK 0x04000000L
+-#define VCE_UENC_CLOCK_GATING__DBFCLK_FORCE_OFF_MASK 0x08000000L
+-#define VCE_UENC_CLOCK_GATING__ENTCLK_FORCE_OFF_MASK 0x10000000L
+-#define VCE_UENC_CLOCK_GATING__LCMCLK_FORCE_OFF_MASK 0x20000000L
+-#define VCE_UENC_CLOCK_GATING__AVMCLK_FORCE_OFF_MASK 0x40000000L
+-#define VCE_UENC_CLOCK_GATING__DCAPCLK_FORCE_OFF_MASK 0x80000000L
+-//VCE_UENC_REG_CLOCK_GATING
+-#define VCE_UENC_REG_CLOCK_GATING__MIFREGCLK_FORCE_ON__SHIFT 0x0
+-#define VCE_UENC_REG_CLOCK_GATING__IMEREGCLK_FORCE_ON__SHIFT 0x1
+-#define VCE_UENC_REG_CLOCK_GATING__FMEREGCLK_FORCE_ON__SHIFT 0x2
+-#define VCE_UENC_REG_CLOCK_GATING__TBEREGCLK_FORCE_ON__SHIFT 0x3
+-#define VCE_UENC_REG_CLOCK_GATING__DBFREGCLK_FORCE_ON__SHIFT 0x4
+-#define VCE_UENC_REG_CLOCK_GATING__ENTREGCLK_FORCE_ON__SHIFT 0x5
+-#define VCE_UENC_REG_CLOCK_GATING__LCMREGCLK_FORCE_ON__SHIFT 0x6
+-#define VCE_UENC_REG_CLOCK_GATING__RESERVED__SHIFT 0x7
+-#define VCE_UENC_REG_CLOCK_GATING__AVMREGCLK_FORCE_ON__SHIFT 0x8
+-#define VCE_UENC_REG_CLOCK_GATING__DCAPREGCLK_FORCE_ON__SHIFT 0x9
+-#define VCE_UENC_REG_CLOCK_GATING__VEPREGCLK_FORCE_ON__SHIFT 0xa
+-#define VCE_UENC_REG_CLOCK_GATING__MIFREGCLK_FORCE_ON_MASK 0x00000001L
+-#define VCE_UENC_REG_CLOCK_GATING__IMEREGCLK_FORCE_ON_MASK 0x00000002L
+-#define VCE_UENC_REG_CLOCK_GATING__FMEREGCLK_FORCE_ON_MASK 0x00000004L
+-#define VCE_UENC_REG_CLOCK_GATING__TBEREGCLK_FORCE_ON_MASK 0x00000008L
+-#define VCE_UENC_REG_CLOCK_GATING__DBFREGCLK_FORCE_ON_MASK 0x00000010L
+-#define VCE_UENC_REG_CLOCK_GATING__ENTREGCLK_FORCE_ON_MASK 0x00000020L
+-#define VCE_UENC_REG_CLOCK_GATING__LCMREGCLK_FORCE_ON_MASK 0x00000040L
+-#define VCE_UENC_REG_CLOCK_GATING__RESERVED_MASK 0x00000080L
+-#define VCE_UENC_REG_CLOCK_GATING__AVMREGCLK_FORCE_ON_MASK 0x00000100L
+-#define VCE_UENC_REG_CLOCK_GATING__DCAPREGCLK_FORCE_ON_MASK 0x00000200L
+-#define VCE_UENC_REG_CLOCK_GATING__VEPREGCLK_FORCE_ON_MASK 0x00000400L
+-//VCE_UENC_CLOCK_GATING_2
+-#define VCE_UENC_CLOCK_GATING_2__DBF2CLK_FORCE_ON__SHIFT 0x1
+-#define VCE_UENC_CLOCK_GATING_2__DBF2CLK_FORCE_OFF__SHIFT 0x10
+-#define VCE_UENC_CLOCK_GATING_2__DBF2CLK_FORCE_ON_MASK 0x00000002L
+-#define VCE_UENC_CLOCK_GATING_2__DBF2CLK_FORCE_OFF_MASK 0x00010000L
+-
+-
+-// addressBlock: vce0_vce_sclk_dec
+-//VCE_LMI_VCPU_CACHE_40BIT_BAR
+-#define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR__SHIFT 0x0
+-#define VCE_LMI_VCPU_CACHE_40BIT_BAR__BAR_MASK 0xFFFFFFFFL
+-//VCE_LMI_CTRL2
+-#define VCE_LMI_CTRL2__STALL_ARB__SHIFT 0x1
+-#define VCE_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2
+-#define VCE_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3
+-#define VCE_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8
+-#define VCE_LMI_CTRL2__STALL_ARB_MASK 0x00000002L
+-#define VCE_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L
+-#define VCE_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x00000008L
+-#define VCE_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L
+-//VCE_LMI_SWAP_CNTL3
+-#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_SWAP__SHIFT 0x0
+-#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_TRAN__SHIFT 0x14
+-#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_URG__SHIFT 0x1a
+-#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_SWAP_MASK 0x00000003L
+-#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_TRAN_MASK 0x00100000L
+-#define VCE_LMI_SWAP_CNTL3__RD_MC_CID_URG_MASK 0x04000000L
+-//VCE_LMI_CTRL
+-#define VCE_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb
+-#define VCE_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc
+-#define VCE_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd
+-#define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15
+-#define VCE_LMI_CTRL__MIF_DATA_COHERENCY_EN__SHIFT 0x16
+-#define VCE_LMI_CTRL__VCPU_RD_CACHE_MISS_COUNT_EN__SHIFT 0x17
+-#define VCE_LMI_CTRL__VCPU_RD_CACHE_MISS_COUNT_RESET__SHIFT 0x18
+-#define VCE_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000800L
+-#define VCE_LMI_CTRL__MASK_MC_URGENT_MASK 0x00001000L
+-#define VCE_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x00002000L
+-#define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L
+-#define VCE_LMI_CTRL__MIF_DATA_COHERENCY_EN_MASK 0x00400000L
+-#define VCE_LMI_CTRL__VCPU_RD_CACHE_MISS_COUNT_EN_MASK 0x00800000L
+-#define VCE_LMI_CTRL__VCPU_RD_CACHE_MISS_COUNT_RESET_MASK 0x01000000L
+-//VCE_LMI_SWAP_CNTL
+-#define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x0
+-#define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP__SHIFT 0x2
+-#define VCE_LMI_SWAP_CNTL__WR_MC_CID_TRAN__SHIFT 0x14
+-#define VCE_LMI_SWAP_CNTL__WR_MC_CID_URG__SHIFT 0x1a
+-#define VCE_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x00000003L
+-#define VCE_LMI_SWAP_CNTL__WR_MC_CID_SWAP_MASK 0x00003FFCL
+-#define VCE_LMI_SWAP_CNTL__WR_MC_CID_TRAN_MASK 0x03F00000L
+-#define VCE_LMI_SWAP_CNTL__WR_MC_CID_URG_MASK 0xFC000000L
+-//VCE_LMI_SWAP_CNTL1
+-#define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP__SHIFT 0x0
+-#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP__SHIFT 0x2
+-#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_TRAN__SHIFT 0x14
+-#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_URG__SHIFT 0x1a
+-#define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP_MASK 0x00000003L
+-#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP_MASK 0x00003FFCL
+-#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_TRAN_MASK 0x03F00000L
+-#define VCE_LMI_SWAP_CNTL1__RD_MC_CID_URG_MASK 0xFC000000L
+-//VCE_LMI_SWAP_CNTL2
+-#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_SWAP__SHIFT 0x0
+-#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_TRAN__SHIFT 0x14
+-#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_URG__SHIFT 0x1a
+-#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_SWAP_MASK 0x000000FFL
+-#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_TRAN_MASK 0x00F00000L
+-#define VCE_LMI_SWAP_CNTL2__WR_MC_CID_URG_MASK 0x3C000000L
+-//VCE_LMI_CACHE_CTRL
+-#define VCE_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x0
+-#define VCE_LMI_CACHE_CTRL__VCPU_FLUSH__SHIFT 0x1
+-#define VCE_LMI_CACHE_CTRL__VCPU_EN_MASK 0x00000001L
+-#define VCE_LMI_CACHE_CTRL__VCPU_FLUSH_MASK 0x00000002L
+-//VCE_LMI_VCPU_CACHE_64BIT_BAR0
+-#define VCE_LMI_VCPU_CACHE_64BIT_BAR0__BAR__SHIFT 0x0
+-#define VCE_LMI_VCPU_CACHE_64BIT_BAR0__BAR_MASK 0x000000FFL
+-//VCE_LMI_VCPU_CACHE_64BIT_BAR1
+-#define VCE_LMI_VCPU_CACHE_64BIT_BAR1__BAR__SHIFT 0x0
+-#define VCE_LMI_VCPU_CACHE_64BIT_BAR1__BAR_MASK 0x000000FFL
+-//VCE_LMI_VCPU_CACHE_64BIT_BAR2
+-#define VCE_LMI_VCPU_CACHE_64BIT_BAR2__BAR__SHIFT 0x0
+-#define VCE_LMI_VCPU_CACHE_64BIT_BAR2__BAR_MASK 0x000000FFL
+-//VCE_LMI_VCPU_CACHE_64BIT_BAR3
+-#define VCE_LMI_VCPU_CACHE_64BIT_BAR3__BAR__SHIFT 0x0
+-#define VCE_LMI_VCPU_CACHE_64BIT_BAR3__BAR_MASK 0x000000FFL
+-//VCE_LMI_VCPU_CACHE_64BIT_BAR4
+-#define VCE_LMI_VCPU_CACHE_64BIT_BAR4__BAR__SHIFT 0x0
+-#define VCE_LMI_VCPU_CACHE_64BIT_BAR4__BAR_MASK 0x000000FFL
+-//VCE_LMI_VCPU_CACHE_64BIT_BAR5
+-#define VCE_LMI_VCPU_CACHE_64BIT_BAR5__BAR__SHIFT 0x0
+-#define VCE_LMI_VCPU_CACHE_64BIT_BAR5__BAR_MASK 0x000000FFL
+-//VCE_LMI_VCPU_CACHE_64BIT_BAR6
+-#define VCE_LMI_VCPU_CACHE_64BIT_BAR6__BAR__SHIFT 0x0
+-#define VCE_LMI_VCPU_CACHE_64BIT_BAR6__BAR_MASK 0x000000FFL
+-//VCE_LMI_VCPU_CACHE_64BIT_BAR7
+-#define VCE_LMI_VCPU_CACHE_64BIT_BAR7__BAR__SHIFT 0x0
+-#define VCE_LMI_VCPU_CACHE_64BIT_BAR7__BAR_MASK 0x000000FFL
+-//VCE_LMI_VCPU_CACHE_40BIT_BAR0
+-#define VCE_LMI_VCPU_CACHE_40BIT_BAR0__BAR__SHIFT 0x0
+-#define VCE_LMI_VCPU_CACHE_40BIT_BAR0__BAR_MASK 0xFFFFFFFFL
+-//VCE_LMI_VCPU_CACHE_40BIT_BAR1
+-#define VCE_LMI_VCPU_CACHE_40BIT_BAR1__BAR__SHIFT 0x0
+-#define VCE_LMI_VCPU_CACHE_40BIT_BAR1__BAR_MASK 0xFFFFFFFFL
+-//VCE_LMI_VCPU_CACHE_40BIT_BAR2
+-#define VCE_LMI_VCPU_CACHE_40BIT_BAR2__BAR__SHIFT 0x0
+-#define VCE_LMI_VCPU_CACHE_40BIT_BAR2__BAR_MASK 0xFFFFFFFFL
+-//VCE_LMI_VCPU_CACHE_40BIT_BAR3
+-#define VCE_LMI_VCPU_CACHE_40BIT_BAR3__BAR__SHIFT 0x0
+-#define VCE_LMI_VCPU_CACHE_40BIT_BAR3__BAR_MASK 0xFFFFFFFFL
+-//VCE_LMI_VCPU_CACHE_40BIT_BAR4
+-#define VCE_LMI_VCPU_CACHE_40BIT_BAR4__BAR__SHIFT 0x0
+-#define VCE_LMI_VCPU_CACHE_40BIT_BAR4__BAR_MASK 0xFFFFFFFFL
+-//VCE_LMI_VCPU_CACHE_40BIT_BAR5
+-#define VCE_LMI_VCPU_CACHE_40BIT_BAR5__BAR__SHIFT 0x0
+-#define VCE_LMI_VCPU_CACHE_40BIT_BAR5__BAR_MASK 0xFFFFFFFFL
+-//VCE_LMI_VCPU_CACHE_40BIT_BAR6
+-#define VCE_LMI_VCPU_CACHE_40BIT_BAR6__BAR__SHIFT 0x0
+-#define VCE_LMI_VCPU_CACHE_40BIT_BAR6__BAR_MASK 0xFFFFFFFFL
+-//VCE_LMI_VCPU_CACHE_40BIT_BAR7
+-#define VCE_LMI_VCPU_CACHE_40BIT_BAR7__BAR__SHIFT 0x0
+-#define VCE_LMI_VCPU_CACHE_40BIT_BAR7__BAR_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: vce0_mmsch_dec
+-//VCE_MMSCH_VF_VMID
+-#define VCE_MMSCH_VF_VMID__VF_CTX_VMID__SHIFT 0x0
+-#define VCE_MMSCH_VF_VMID__VF_GPCOM_VMID__SHIFT 0x4
+-#define VCE_MMSCH_VF_VMID__VF_CTX_VMID_MASK 0x0000000FL
+-#define VCE_MMSCH_VF_VMID__VF_GPCOM_VMID_MASK 0x000000F0L
+-//VCE_MMSCH_VF_CTX_ADDR_LO
+-#define VCE_MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO__SHIFT 0x6
+-#define VCE_MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO_MASK 0xFFFFFFC0L
+-//VCE_MMSCH_VF_CTX_ADDR_HI
+-#define VCE_MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI__SHIFT 0x0
+-#define VCE_MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI_MASK 0xFFFFFFFFL
+-//VCE_MMSCH_VF_CTX_SIZE
+-#define VCE_MMSCH_VF_CTX_SIZE__VF_CTX_SIZE__SHIFT 0x0
+-#define VCE_MMSCH_VF_CTX_SIZE__VF_CTX_SIZE_MASK 0xFFFFFFFFL
+-//VCE_MMSCH_VF_GPCOM_ADDR_LO
+-#define VCE_MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO__SHIFT 0x6
+-#define VCE_MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO_MASK 0xFFFFFFC0L
+-//VCE_MMSCH_VF_GPCOM_ADDR_HI
+-#define VCE_MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI__SHIFT 0x0
+-#define VCE_MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI_MASK 0xFFFFFFFFL
+-//VCE_MMSCH_VF_GPCOM_SIZE
+-#define VCE_MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE__SHIFT 0x0
+-#define VCE_MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE_MASK 0xFFFFFFFFL
+-//VCE_MMSCH_VF_MAILBOX_HOST
+-#define VCE_MMSCH_VF_MAILBOX_HOST__DATA__SHIFT 0x0
+-#define VCE_MMSCH_VF_MAILBOX_HOST__DATA_MASK 0xFFFFFFFFL
+-//VCE_MMSCH_VF_MAILBOX_RESP
+-#define VCE_MMSCH_VF_MAILBOX_RESP__RESP__SHIFT 0x0
+-#define VCE_MMSCH_VF_MAILBOX_RESP__RESP_MASK 0xFFFFFFFFL
+-
+-
+-// addressBlock: vce0_vce_rb_pg_dec
+-//VCE_HW_VERSION
+-#define VCE_HW_VERSION__VCE_VERSION__SHIFT 0x0
+-#define VCE_HW_VERSION__VCE_CONFIGURATION__SHIFT 0x8
+-#define VCE_HW_VERSION__VCE_INSTANCE_ID__SHIFT 0xa
+-#define VCE_HW_VERSION__VCE_VERSION_MASK 0x000000FFL
+-#define VCE_HW_VERSION__VCE_CONFIGURATION_MASK 0x00000300L
+-#define VCE_HW_VERSION__VCE_INSTANCE_ID_MASK 0x00000C00L
+-
+-
+-
+-#endif
+--
+2.7.4
+