diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2251-drm-amd-include-cleanup-vega10-umc-header-files.patch')
| -rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2251-drm-amd-include-cleanup-vega10-umc-header-files.patch | 315 |
1 files changed, 315 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2251-drm-amd-include-cleanup-vega10-umc-header-files.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2251-drm-amd-include-cleanup-vega10-umc-header-files.patch new file mode 100644 index 00000000..2333a5a5 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2251-drm-amd-include-cleanup-vega10-umc-header-files.patch @@ -0,0 +1,315 @@ +From ad852b0886aa315ffc482be439634db99910428c Mon Sep 17 00:00:00 2001 +From: Feifei Xu <Feifei.Xu@amd.com> +Date: Wed, 22 Nov 2017 15:23:20 +0800 +Subject: [PATCH 2251/4131] drm/amd/include: cleanup vega10 umc header files. + +Remove asic/vega10/UMC folder. + +Change-Id: Ic99f95e957c24cac3d5cb8768fa63452c8d1e505 +Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +- + .../drm/amd/include/asic_reg/umc/umc_6_0_default.h | 31 +++++++++++++ + .../drm/amd/include/asic_reg/umc/umc_6_0_offset.h | 52 ++++++++++++++++++++++ + .../drm/amd/include/asic_reg/umc/umc_6_0_sh_mask.h | 36 +++++++++++++++ + .../include/asic_reg/vega10/UMC/umc_6_0_default.h | 31 ------------- + .../include/asic_reg/vega10/UMC/umc_6_0_offset.h | 52 ---------------------- + .../include/asic_reg/vega10/UMC/umc_6_0_sh_mask.h | 36 --------------- + 7 files changed, 120 insertions(+), 120 deletions(-) + create mode 100644 drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_default.h + create mode 100644 drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_offset.h + create mode 100644 drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_sh_mask.h + delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_default.h + delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_offset.h + delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_sh_mask.h + +diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +index 34ba6d6..432c3da 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +@@ -36,7 +36,7 @@ + #include "athub/athub_1_0_offset.h" + + #include "soc15_common.h" +-#include "vega10/UMC/umc_6_0_sh_mask.h" ++#include "umc/umc_6_0_sh_mask.h" + + #include "nbio_v6_1.h" + #include "nbio_v7_0.h" +diff --git a/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_default.h +new file mode 100644 +index 0000000..128a18f +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_default.h +@@ -0,0 +1,31 @@ ++/* ++ * Copyright (C) 2017 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#ifndef _umc_6_0_DEFAULT_HEADER ++#define _umc_6_0_DEFAULT_HEADER ++ ++#define mmUMCCH0_0_EccCtrl_DEFAULT 0x00000000 ++ ++#define mmUMCCH0_0_UMC_CONFIG_DEFAULT 0x00000203 ++ ++#define mmUMCCH0_0_UmcLocalCap_DEFAULT 0x00000000 ++ ++#endif +diff --git a/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_offset.h +new file mode 100644 +index 0000000..6985dbb +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_offset.h +@@ -0,0 +1,52 @@ ++/* ++ * Copyright (C) 2017 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#ifndef _umc_6_0_OFFSET_H_ ++#define _umc_6_0_OFFSET_H_ ++ ++#define mmUMCCH0_0_EccCtrl 0x0053 ++#define mmUMCCH0_0_EccCtrl_BASE_IDX 0 ++#define mmUMCCH1_0_EccCtrl 0x0853 ++#define mmUMCCH1_0_EccCtrl_BASE_IDX 0 ++#define mmUMCCH2_0_EccCtrl 0x1053 ++#define mmUMCCH2_0_EccCtrl_BASE_IDX 0 ++#define mmUMCCH3_0_EccCtrl 0x1853 ++#define mmUMCCH3_0_EccCtrl_BASE_IDX 0 ++ ++#define mmUMCCH0_0_UMC_CONFIG 0x0040 ++#define mmUMCCH0_0_UMC_CONFIG_BASE_IDX 0 ++#define mmUMCCH1_0_UMC_CONFIG 0x0840 ++#define mmUMCCH1_0_UMC_CONFIG_BASE_IDX 0 ++#define mmUMCCH2_0_UMC_CONFIG 0x1040 ++#define mmUMCCH2_0_UMC_CONFIG_BASE_IDX 0 ++#define mmUMCCH3_0_UMC_CONFIG 0x1840 ++#define mmUMCCH3_0_UMC_CONFIG_BASE_IDX 0 ++ ++#define mmUMCCH0_0_UmcLocalCap 0x0306 ++#define mmUMCCH0_0_UmcLocalCap_BASE_IDX 0 ++#define mmUMCCH1_0_UmcLocalCap 0x0b06 ++#define mmUMCCH1_0_UmcLocalCap_BASE_IDX 0 ++#define mmUMCCH2_0_UmcLocalCap 0x1306 ++#define mmUMCCH2_0_UmcLocalCap_BASE_IDX 0 ++#define mmUMCCH3_0_UmcLocalCap 0x1b06 ++#define mmUMCCH3_0_UmcLocalCap_BASE_IDX 0 ++ ++#endif +diff --git a/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_sh_mask.h +new file mode 100644 +index 0000000..3e857d1 +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/asic_reg/umc/umc_6_0_sh_mask.h +@@ -0,0 +1,36 @@ ++/* ++ * Copyright (C) 2017 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#ifndef _umc_6_0_SH_MASK_HEADER ++#define _umc_6_0_SH_MASK_HEADER ++ ++#define UMCCH0_0_EccCtrl__RdEccEn_MASK 0x00000400L ++#define UMCCH0_0_EccCtrl__RdEccEn__SHIFT 0xa ++#define UMCCH0_0_EccCtrl__WrEccEn_MASK 0x00000001L ++#define UMCCH0_0_EccCtrl__WrEccEn__SHIFT 0x0 ++ ++#define UMCCH0_0_UMC_CONFIG__DramReady_MASK 0x80000000L ++#define UMCCH0_0_UMC_CONFIG__DramReady__SHIFT 0x1f ++ ++#define UMCCH0_0_UmcLocalCap__EccDis_MASK 0x00000001L ++#define UMCCH0_0_UmcLocalCap__EccDis__SHIFT 0x0 ++ ++#endif +diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_default.h +deleted file mode 100644 +index 128a18f..0000000 +--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_default.h ++++ /dev/null +@@ -1,31 +0,0 @@ +-/* +- * Copyright (C) 2017 Advanced Micro Devices, Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included +- * in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#ifndef _umc_6_0_DEFAULT_HEADER +-#define _umc_6_0_DEFAULT_HEADER +- +-#define mmUMCCH0_0_EccCtrl_DEFAULT 0x00000000 +- +-#define mmUMCCH0_0_UMC_CONFIG_DEFAULT 0x00000203 +- +-#define mmUMCCH0_0_UmcLocalCap_DEFAULT 0x00000000 +- +-#endif +diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_offset.h +deleted file mode 100644 +index 6985dbb..0000000 +--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_offset.h ++++ /dev/null +@@ -1,52 +0,0 @@ +-/* +- * Copyright (C) 2017 Advanced Micro Devices, Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included +- * in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#ifndef _umc_6_0_OFFSET_H_ +-#define _umc_6_0_OFFSET_H_ +- +-#define mmUMCCH0_0_EccCtrl 0x0053 +-#define mmUMCCH0_0_EccCtrl_BASE_IDX 0 +-#define mmUMCCH1_0_EccCtrl 0x0853 +-#define mmUMCCH1_0_EccCtrl_BASE_IDX 0 +-#define mmUMCCH2_0_EccCtrl 0x1053 +-#define mmUMCCH2_0_EccCtrl_BASE_IDX 0 +-#define mmUMCCH3_0_EccCtrl 0x1853 +-#define mmUMCCH3_0_EccCtrl_BASE_IDX 0 +- +-#define mmUMCCH0_0_UMC_CONFIG 0x0040 +-#define mmUMCCH0_0_UMC_CONFIG_BASE_IDX 0 +-#define mmUMCCH1_0_UMC_CONFIG 0x0840 +-#define mmUMCCH1_0_UMC_CONFIG_BASE_IDX 0 +-#define mmUMCCH2_0_UMC_CONFIG 0x1040 +-#define mmUMCCH2_0_UMC_CONFIG_BASE_IDX 0 +-#define mmUMCCH3_0_UMC_CONFIG 0x1840 +-#define mmUMCCH3_0_UMC_CONFIG_BASE_IDX 0 +- +-#define mmUMCCH0_0_UmcLocalCap 0x0306 +-#define mmUMCCH0_0_UmcLocalCap_BASE_IDX 0 +-#define mmUMCCH1_0_UmcLocalCap 0x0b06 +-#define mmUMCCH1_0_UmcLocalCap_BASE_IDX 0 +-#define mmUMCCH2_0_UmcLocalCap 0x1306 +-#define mmUMCCH2_0_UmcLocalCap_BASE_IDX 0 +-#define mmUMCCH3_0_UmcLocalCap 0x1b06 +-#define mmUMCCH3_0_UmcLocalCap_BASE_IDX 0 +- +-#endif +diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_sh_mask.h +deleted file mode 100644 +index 3e857d1..0000000 +--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/UMC/umc_6_0_sh_mask.h ++++ /dev/null +@@ -1,36 +0,0 @@ +-/* +- * Copyright (C) 2017 Advanced Micro Devices, Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included +- * in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#ifndef _umc_6_0_SH_MASK_HEADER +-#define _umc_6_0_SH_MASK_HEADER +- +-#define UMCCH0_0_EccCtrl__RdEccEn_MASK 0x00000400L +-#define UMCCH0_0_EccCtrl__RdEccEn__SHIFT 0xa +-#define UMCCH0_0_EccCtrl__WrEccEn_MASK 0x00000001L +-#define UMCCH0_0_EccCtrl__WrEccEn__SHIFT 0x0 +- +-#define UMCCH0_0_UMC_CONFIG__DramReady_MASK 0x80000000L +-#define UMCCH0_0_UMC_CONFIG__DramReady__SHIFT 0x1f +- +-#define UMCCH0_0_UmcLocalCap__EccDis_MASK 0x00000001L +-#define UMCCH0_0_UmcLocalCap__EccDis__SHIFT 0x0 +- +-#endif +-- +2.7.4 + |