diff options
Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2248-drm-amd-include-cleanup-vega10-mp-header-files.patch')
-rw-r--r-- | meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2248-drm-amd-include-cleanup-vega10-mp-header-files.patch | 4123 |
1 files changed, 4123 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2248-drm-amd-include-cleanup-vega10-mp-header-files.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2248-drm-amd-include-cleanup-vega10-mp-header-files.patch new file mode 100644 index 00000000..89e35ea3 --- /dev/null +++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2248-drm-amd-include-cleanup-vega10-mp-header-files.patch @@ -0,0 +1,4123 @@ +From 1aeff8e9fa357609ab9129bb11c058558b11760a Mon Sep 17 00:00:00 2001 +From: Feifei Xu <Feifei.Xu@amd.com> +Date: Wed, 15 Nov 2017 18:39:21 +0800 +Subject: [PATCH 2248/4131] drm/amd/include:cleanup vega10 mp header files. + +To remove include/asic_reg/vega10 folder, this patch cleanup +asic_reg/vega10/MP folder, and remove unused mp_9_0_default.h. + +Change-Id: Id53e6ab7a8bc78ff61457836b1b3ce499b158610 +Signed-off-by: Feifei Xu <Feifei.Xu@amd.com> +--- + drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 4 +- + drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +- + .../drm/amd/include/asic_reg/mp/mp_9_0_offset.h | 375 +++++ + .../drm/amd/include/asic_reg/mp/mp_9_0_sh_mask.h | 1463 ++++++++++++++++++++ + .../include/asic_reg/vega10/MP/mp_9_0_default.h | 342 ----- + .../amd/include/asic_reg/vega10/MP/mp_9_0_offset.h | 375 ----- + .../include/asic_reg/vega10/MP/mp_9_0_sh_mask.h | 1463 -------------------- + drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h | 5 +- + 8 files changed, 1844 insertions(+), 2187 deletions(-) + create mode 100644 drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_offset.h + create mode 100644 drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_sh_mask.h + delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_default.h + delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_offset.h + delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_sh_mask.h + +diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c +index b855964..53df744 100644 +--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c ++++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c +@@ -32,8 +32,8 @@ + #include "psp_v3_1.h" + + #include "vega10/soc15ip.h" +-#include "vega10/MP/mp_9_0_offset.h" +-#include "vega10/MP/mp_9_0_sh_mask.h" ++#include "mp/mp_9_0_offset.h" ++#include "mp/mp_9_0_sh_mask.h" + #include "vega10/GC/gc_9_0_offset.h" + #include "sdma0/sdma0_4_0_offset.h" + #include "vega10/NBIO/nbio_6_1_offset.h" +diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c +index a3f67cf..8b270f0 100644 +--- a/drivers/gpu/drm/amd/amdgpu/soc15.c ++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c +@@ -42,8 +42,8 @@ + #include "sdma1/sdma1_4_0_offset.h" + #include "hdp/hdp_4_0_offset.h" + #include "hdp/hdp_4_0_sh_mask.h" +-#include "vega10/MP/mp_9_0_offset.h" +-#include "vega10/MP/mp_9_0_sh_mask.h" ++#include "mp/mp_9_0_offset.h" ++#include "mp/mp_9_0_sh_mask.h" + #include "vega10/SMUIO/smuio_9_0_offset.h" + #include "vega10/SMUIO/smuio_9_0_sh_mask.h" + +diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_offset.h +new file mode 100644 +index 0000000..621e880 +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_offset.h +@@ -0,0 +1,375 @@ ++/* ++ * Copyright (C) 2017 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#ifndef _mp_9_0_OFFSET_HEADER ++#define _mp_9_0_OFFSET_HEADER ++ ++ ++ ++// addressBlock: mp_SmuMp0_SmnDec ++// base address: 0x0 ++#define mmMP0_SMN_C2PMSG_32 0x0060 ++#define mmMP0_SMN_C2PMSG_32_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_33 0x0061 ++#define mmMP0_SMN_C2PMSG_33_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_34 0x0062 ++#define mmMP0_SMN_C2PMSG_34_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_35 0x0063 ++#define mmMP0_SMN_C2PMSG_35_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_36 0x0064 ++#define mmMP0_SMN_C2PMSG_36_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_37 0x0065 ++#define mmMP0_SMN_C2PMSG_37_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_38 0x0066 ++#define mmMP0_SMN_C2PMSG_38_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_39 0x0067 ++#define mmMP0_SMN_C2PMSG_39_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_40 0x0068 ++#define mmMP0_SMN_C2PMSG_40_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_41 0x0069 ++#define mmMP0_SMN_C2PMSG_41_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_42 0x006a ++#define mmMP0_SMN_C2PMSG_42_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_43 0x006b ++#define mmMP0_SMN_C2PMSG_43_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_44 0x006c ++#define mmMP0_SMN_C2PMSG_44_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_45 0x006d ++#define mmMP0_SMN_C2PMSG_45_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_46 0x006e ++#define mmMP0_SMN_C2PMSG_46_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_47 0x006f ++#define mmMP0_SMN_C2PMSG_47_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_48 0x0070 ++#define mmMP0_SMN_C2PMSG_48_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_49 0x0071 ++#define mmMP0_SMN_C2PMSG_49_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_50 0x0072 ++#define mmMP0_SMN_C2PMSG_50_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_51 0x0073 ++#define mmMP0_SMN_C2PMSG_51_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_52 0x0074 ++#define mmMP0_SMN_C2PMSG_52_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_53 0x0075 ++#define mmMP0_SMN_C2PMSG_53_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_54 0x0076 ++#define mmMP0_SMN_C2PMSG_54_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_55 0x0077 ++#define mmMP0_SMN_C2PMSG_55_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_56 0x0078 ++#define mmMP0_SMN_C2PMSG_56_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_57 0x0079 ++#define mmMP0_SMN_C2PMSG_57_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_58 0x007a ++#define mmMP0_SMN_C2PMSG_58_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_59 0x007b ++#define mmMP0_SMN_C2PMSG_59_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_60 0x007c ++#define mmMP0_SMN_C2PMSG_60_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_61 0x007d ++#define mmMP0_SMN_C2PMSG_61_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_62 0x007e ++#define mmMP0_SMN_C2PMSG_62_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_63 0x007f ++#define mmMP0_SMN_C2PMSG_63_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_64 0x0080 ++#define mmMP0_SMN_C2PMSG_64_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_65 0x0081 ++#define mmMP0_SMN_C2PMSG_65_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_66 0x0082 ++#define mmMP0_SMN_C2PMSG_66_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_67 0x0083 ++#define mmMP0_SMN_C2PMSG_67_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_68 0x0084 ++#define mmMP0_SMN_C2PMSG_68_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_69 0x0085 ++#define mmMP0_SMN_C2PMSG_69_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_70 0x0086 ++#define mmMP0_SMN_C2PMSG_70_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_71 0x0087 ++#define mmMP0_SMN_C2PMSG_71_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_72 0x0088 ++#define mmMP0_SMN_C2PMSG_72_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_73 0x0089 ++#define mmMP0_SMN_C2PMSG_73_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_74 0x008a ++#define mmMP0_SMN_C2PMSG_74_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_75 0x008b ++#define mmMP0_SMN_C2PMSG_75_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_76 0x008c ++#define mmMP0_SMN_C2PMSG_76_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_77 0x008d ++#define mmMP0_SMN_C2PMSG_77_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_78 0x008e ++#define mmMP0_SMN_C2PMSG_78_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_79 0x008f ++#define mmMP0_SMN_C2PMSG_79_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_80 0x0090 ++#define mmMP0_SMN_C2PMSG_80_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_81 0x0091 ++#define mmMP0_SMN_C2PMSG_81_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_82 0x0092 ++#define mmMP0_SMN_C2PMSG_82_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_83 0x0093 ++#define mmMP0_SMN_C2PMSG_83_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_84 0x0094 ++#define mmMP0_SMN_C2PMSG_84_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_85 0x0095 ++#define mmMP0_SMN_C2PMSG_85_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_86 0x0096 ++#define mmMP0_SMN_C2PMSG_86_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_87 0x0097 ++#define mmMP0_SMN_C2PMSG_87_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_88 0x0098 ++#define mmMP0_SMN_C2PMSG_88_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_89 0x0099 ++#define mmMP0_SMN_C2PMSG_89_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_90 0x009a ++#define mmMP0_SMN_C2PMSG_90_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_91 0x009b ++#define mmMP0_SMN_C2PMSG_91_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_92 0x009c ++#define mmMP0_SMN_C2PMSG_92_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_93 0x009d ++#define mmMP0_SMN_C2PMSG_93_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_94 0x009e ++#define mmMP0_SMN_C2PMSG_94_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_95 0x009f ++#define mmMP0_SMN_C2PMSG_95_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_96 0x00a0 ++#define mmMP0_SMN_C2PMSG_96_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_97 0x00a1 ++#define mmMP0_SMN_C2PMSG_97_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_98 0x00a2 ++#define mmMP0_SMN_C2PMSG_98_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_99 0x00a3 ++#define mmMP0_SMN_C2PMSG_99_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_100 0x00a4 ++#define mmMP0_SMN_C2PMSG_100_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_101 0x00a5 ++#define mmMP0_SMN_C2PMSG_101_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_102 0x00a6 ++#define mmMP0_SMN_C2PMSG_102_BASE_IDX 0 ++#define mmMP0_SMN_C2PMSG_103 0x00a7 ++#define mmMP0_SMN_C2PMSG_103_BASE_IDX 0 ++#define mmMP0_SMN_ACTIVE_FCN_ID 0x00c0 ++#define mmMP0_SMN_ACTIVE_FCN_ID_BASE_IDX 0 ++#define mmMP0_SMN_IH_CREDIT 0x00c1 ++#define mmMP0_SMN_IH_CREDIT_BASE_IDX 0 ++#define mmMP0_SMN_IH_SW_INT 0x00c2 ++#define mmMP0_SMN_IH_SW_INT_BASE_IDX 0 ++#define mmMP0_SMN_IH_SW_INT_CTRL 0x00c3 ++#define mmMP0_SMN_IH_SW_INT_CTRL_BASE_IDX 0 ++ ++ ++// addressBlock: mp_SmuMp1_SmnDec ++// base address: 0x0 ++#define mmMP1_SMN_ACP2MP_RESP 0x0240 ++#define mmMP1_SMN_ACP2MP_RESP_BASE_IDX 0 ++#define mmMP1_SMN_DC2MP_RESP 0x0241 ++#define mmMP1_SMN_DC2MP_RESP_BASE_IDX 0 ++#define mmMP1_SMN_UVD2MP_RESP 0x0242 ++#define mmMP1_SMN_UVD2MP_RESP_BASE_IDX 0 ++#define mmMP1_SMN_VCE2MP_RESP 0x0243 ++#define mmMP1_SMN_VCE2MP_RESP_BASE_IDX 0 ++#define mmMP1_SMN_RLC2MP_RESP 0x0244 ++#define mmMP1_SMN_RLC2MP_RESP_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_32 0x0260 ++#define mmMP1_SMN_C2PMSG_32_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_33 0x0261 ++#define mmMP1_SMN_C2PMSG_33_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_34 0x0262 ++#define mmMP1_SMN_C2PMSG_34_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_35 0x0263 ++#define mmMP1_SMN_C2PMSG_35_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_36 0x0264 ++#define mmMP1_SMN_C2PMSG_36_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_37 0x0265 ++#define mmMP1_SMN_C2PMSG_37_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_38 0x0266 ++#define mmMP1_SMN_C2PMSG_38_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_39 0x0267 ++#define mmMP1_SMN_C2PMSG_39_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_40 0x0268 ++#define mmMP1_SMN_C2PMSG_40_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_41 0x0269 ++#define mmMP1_SMN_C2PMSG_41_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_42 0x026a ++#define mmMP1_SMN_C2PMSG_42_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_43 0x026b ++#define mmMP1_SMN_C2PMSG_43_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_44 0x026c ++#define mmMP1_SMN_C2PMSG_44_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_45 0x026d ++#define mmMP1_SMN_C2PMSG_45_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_46 0x026e ++#define mmMP1_SMN_C2PMSG_46_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_47 0x026f ++#define mmMP1_SMN_C2PMSG_47_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_48 0x0270 ++#define mmMP1_SMN_C2PMSG_48_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_49 0x0271 ++#define mmMP1_SMN_C2PMSG_49_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_50 0x0272 ++#define mmMP1_SMN_C2PMSG_50_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_51 0x0273 ++#define mmMP1_SMN_C2PMSG_51_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_52 0x0274 ++#define mmMP1_SMN_C2PMSG_52_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_53 0x0275 ++#define mmMP1_SMN_C2PMSG_53_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_54 0x0276 ++#define mmMP1_SMN_C2PMSG_54_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_55 0x0277 ++#define mmMP1_SMN_C2PMSG_55_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_56 0x0278 ++#define mmMP1_SMN_C2PMSG_56_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_57 0x0279 ++#define mmMP1_SMN_C2PMSG_57_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_58 0x027a ++#define mmMP1_SMN_C2PMSG_58_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_59 0x027b ++#define mmMP1_SMN_C2PMSG_59_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_60 0x027c ++#define mmMP1_SMN_C2PMSG_60_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_61 0x027d ++#define mmMP1_SMN_C2PMSG_61_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_62 0x027e ++#define mmMP1_SMN_C2PMSG_62_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_63 0x027f ++#define mmMP1_SMN_C2PMSG_63_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_64 0x0280 ++#define mmMP1_SMN_C2PMSG_64_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_65 0x0281 ++#define mmMP1_SMN_C2PMSG_65_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_66 0x0282 ++#define mmMP1_SMN_C2PMSG_66_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_67 0x0283 ++#define mmMP1_SMN_C2PMSG_67_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_68 0x0284 ++#define mmMP1_SMN_C2PMSG_68_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_69 0x0285 ++#define mmMP1_SMN_C2PMSG_69_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_70 0x0286 ++#define mmMP1_SMN_C2PMSG_70_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_71 0x0287 ++#define mmMP1_SMN_C2PMSG_71_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_72 0x0288 ++#define mmMP1_SMN_C2PMSG_72_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_73 0x0289 ++#define mmMP1_SMN_C2PMSG_73_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_74 0x028a ++#define mmMP1_SMN_C2PMSG_74_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_75 0x028b ++#define mmMP1_SMN_C2PMSG_75_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_76 0x028c ++#define mmMP1_SMN_C2PMSG_76_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_77 0x028d ++#define mmMP1_SMN_C2PMSG_77_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_78 0x028e ++#define mmMP1_SMN_C2PMSG_78_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_79 0x028f ++#define mmMP1_SMN_C2PMSG_79_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_80 0x0290 ++#define mmMP1_SMN_C2PMSG_80_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_81 0x0291 ++#define mmMP1_SMN_C2PMSG_81_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_82 0x0292 ++#define mmMP1_SMN_C2PMSG_82_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_83 0x0293 ++#define mmMP1_SMN_C2PMSG_83_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_84 0x0294 ++#define mmMP1_SMN_C2PMSG_84_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_85 0x0295 ++#define mmMP1_SMN_C2PMSG_85_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_86 0x0296 ++#define mmMP1_SMN_C2PMSG_86_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_87 0x0297 ++#define mmMP1_SMN_C2PMSG_87_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_88 0x0298 ++#define mmMP1_SMN_C2PMSG_88_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_89 0x0299 ++#define mmMP1_SMN_C2PMSG_89_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_90 0x029a ++#define mmMP1_SMN_C2PMSG_90_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_91 0x029b ++#define mmMP1_SMN_C2PMSG_91_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_92 0x029c ++#define mmMP1_SMN_C2PMSG_92_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_93 0x029d ++#define mmMP1_SMN_C2PMSG_93_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_94 0x029e ++#define mmMP1_SMN_C2PMSG_94_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_95 0x029f ++#define mmMP1_SMN_C2PMSG_95_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_96 0x02a0 ++#define mmMP1_SMN_C2PMSG_96_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_97 0x02a1 ++#define mmMP1_SMN_C2PMSG_97_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_98 0x02a2 ++#define mmMP1_SMN_C2PMSG_98_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_99 0x02a3 ++#define mmMP1_SMN_C2PMSG_99_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_100 0x02a4 ++#define mmMP1_SMN_C2PMSG_100_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_101 0x02a5 ++#define mmMP1_SMN_C2PMSG_101_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_102 0x02a6 ++#define mmMP1_SMN_C2PMSG_102_BASE_IDX 0 ++#define mmMP1_SMN_C2PMSG_103 0x02a7 ++#define mmMP1_SMN_C2PMSG_103_BASE_IDX 0 ++#define mmMP1_SMN_ACTIVE_FCN_ID 0x02c0 ++#define mmMP1_SMN_ACTIVE_FCN_ID_BASE_IDX 0 ++#define mmMP1_SMN_IH_CREDIT 0x02c1 ++#define mmMP1_SMN_IH_CREDIT_BASE_IDX 0 ++#define mmMP1_SMN_IH_SW_INT 0x02c2 ++#define mmMP1_SMN_IH_SW_INT_BASE_IDX 0 ++#define mmMP1_SMN_IH_SW_INT_CTRL 0x02c3 ++#define mmMP1_SMN_IH_SW_INT_CTRL_BASE_IDX 0 ++#define mmMP1_SMN_FPS_CNT 0x02c4 ++#define mmMP1_SMN_FPS_CNT_BASE_IDX 0 ++#define mmMP1_SMN_EXT_SCRATCH0 0x03c0 ++#define mmMP1_SMN_EXT_SCRATCH0_BASE_IDX 0 ++#define mmMP1_SMN_EXT_SCRATCH1 0x03c1 ++#define mmMP1_SMN_EXT_SCRATCH1_BASE_IDX 0 ++#define mmMP1_SMN_EXT_SCRATCH2 0x03c2 ++#define mmMP1_SMN_EXT_SCRATCH2_BASE_IDX 0 ++#define mmMP1_SMN_EXT_SCRATCH3 0x03c3 ++#define mmMP1_SMN_EXT_SCRATCH3_BASE_IDX 0 ++#define mmMP1_SMN_EXT_SCRATCH4 0x03c4 ++#define mmMP1_SMN_EXT_SCRATCH4_BASE_IDX 0 ++#define mmMP1_SMN_EXT_SCRATCH5 0x03c5 ++#define mmMP1_SMN_EXT_SCRATCH5_BASE_IDX 0 ++#define mmMP1_SMN_EXT_SCRATCH6 0x03c6 ++#define mmMP1_SMN_EXT_SCRATCH6_BASE_IDX 0 ++#define mmMP1_SMN_EXT_SCRATCH7 0x03c7 ++#define mmMP1_SMN_EXT_SCRATCH7_BASE_IDX 0 ++#define mmMP1_SMN_EXT_SCRATCH8 0x03c8 ++#define mmMP1_SMN_EXT_SCRATCH8_BASE_IDX 0 ++ ++ ++// addressBlock: mp_SmuMp1Pub_CruDec ++// base address: 0x0 ++#define mmMP1_SMN_PUB_CTRL 0x02c5 ++#define mmMP1_SMN_PUB_CTRL_BASE_IDX 0 ++ ++ ++ ++#endif +diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_sh_mask.h +new file mode 100644 +index 0000000..ae7b518 +--- /dev/null ++++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_sh_mask.h +@@ -0,0 +1,1463 @@ ++/* ++ * Copyright (C) 2017 Advanced Micro Devices, Inc. ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included ++ * in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS ++ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL ++ * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN ++ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN ++ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ */ ++#ifndef _mp_9_0_SH_MASK_HEADER ++#define _mp_9_0_SH_MASK_HEADER ++ ++ ++// addressBlock: mp_SmuMp0_SmnDec ++//MP0_SMN_C2PMSG_32 ++#define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_33 ++#define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_34 ++#define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_35 ++#define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_36 ++#define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_37 ++#define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_38 ++#define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_39 ++#define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_40 ++#define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_41 ++#define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_42 ++#define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_43 ++#define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_44 ++#define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_45 ++#define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_46 ++#define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_47 ++#define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_48 ++#define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_49 ++#define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_50 ++#define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_51 ++#define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_52 ++#define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_53 ++#define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_54 ++#define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_55 ++#define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_56 ++#define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_57 ++#define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_58 ++#define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_59 ++#define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_60 ++#define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_61 ++#define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_62 ++#define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_63 ++#define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_64 ++#define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_65 ++#define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_66 ++#define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_67 ++#define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_68 ++#define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_69 ++#define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_70 ++#define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_71 ++#define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_72 ++#define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_73 ++#define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_74 ++#define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_75 ++#define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_76 ++#define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_77 ++#define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_78 ++#define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_79 ++#define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_80 ++#define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_81 ++#define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_82 ++#define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_83 ++#define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_84 ++#define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_85 ++#define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_86 ++#define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_87 ++#define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_88 ++#define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_89 ++#define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_90 ++#define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_91 ++#define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_92 ++#define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_93 ++#define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_94 ++#define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_95 ++#define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_96 ++#define MP0_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_97 ++#define MP0_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_98 ++#define MP0_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_99 ++#define MP0_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_100 ++#define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_101 ++#define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_102 ++#define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_C2PMSG_103 ++#define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 ++#define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL ++//MP0_SMN_ACTIVE_FCN_ID ++#define MP0_SMN_ACTIVE_FCN_ID__VFID__SHIFT 0x0 ++#define MP0_SMN_ACTIVE_FCN_ID__VF__SHIFT 0x1f ++#define MP0_SMN_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL ++#define MP0_SMN_ACTIVE_FCN_ID__VF_MASK 0x80000000L ++//MP0_SMN_IH_CREDIT ++#define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 ++#define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 ++#define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L ++#define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L ++//MP0_SMN_IH_SW_INT ++#define MP0_SMN_IH_SW_INT__VALID__SHIFT 0x0 ++#define MP0_SMN_IH_SW_INT__ID__SHIFT 0x1 ++#define MP0_SMN_IH_SW_INT__VALID_MASK 0x00000001L ++#define MP0_SMN_IH_SW_INT__ID_MASK 0x000001FEL ++//MP0_SMN_IH_SW_INT_CTRL ++#define MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK__SHIFT 0x0 ++#define MP0_SMN_IH_SW_INT_CTRL__SW_INT_ACK__SHIFT 0x8 ++#define MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK 0x00000001L ++#define MP0_SMN_IH_SW_INT_CTRL__SW_INT_ACK_MASK 0x00000100L ++ ++ ++// addressBlock: mp_SmuMp1_SmnDec ++//MP1_SMN_ACP2MP_RESP ++#define MP1_SMN_ACP2MP_RESP__CONTENT__SHIFT 0x0 ++#define MP1_SMN_ACP2MP_RESP__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_DC2MP_RESP ++#define MP1_SMN_DC2MP_RESP__CONTENT__SHIFT 0x0 ++#define MP1_SMN_DC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_UVD2MP_RESP ++#define MP1_SMN_UVD2MP_RESP__CONTENT__SHIFT 0x0 ++#define MP1_SMN_UVD2MP_RESP__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_VCE2MP_RESP ++#define MP1_SMN_VCE2MP_RESP__CONTENT__SHIFT 0x0 ++#define MP1_SMN_VCE2MP_RESP__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_RLC2MP_RESP ++#define MP1_SMN_RLC2MP_RESP__CONTENT__SHIFT 0x0 ++#define MP1_SMN_RLC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_32 ++#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_33 ++#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_34 ++#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_35 ++#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_36 ++#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_37 ++#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_38 ++#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_39 ++#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_40 ++#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_41 ++#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_42 ++#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_43 ++#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_44 ++#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_45 ++#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_46 ++#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_47 ++#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_48 ++#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_49 ++#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_50 ++#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_51 ++#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_52 ++#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_53 ++#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_54 ++#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_55 ++#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_56 ++#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_57 ++#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_58 ++#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_59 ++#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_60 ++#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_61 ++#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_62 ++#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_63 ++#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_64 ++#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_65 ++#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_66 ++#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_67 ++#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_68 ++#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_69 ++#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_70 ++#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_71 ++#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_72 ++#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_73 ++#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_74 ++#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_75 ++#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_76 ++#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_77 ++#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_78 ++#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_79 ++#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_80 ++#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_81 ++#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_82 ++#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_83 ++#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_84 ++#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_85 ++#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_86 ++#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_87 ++#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_88 ++#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_89 ++#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_90 ++#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_91 ++#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_92 ++#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_93 ++#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_94 ++#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_95 ++#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_96 ++#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_97 ++#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_98 ++#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_99 ++#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_100 ++#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_101 ++#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_102 ++#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_C2PMSG_103 ++#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 ++#define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL ++//MP1_SMN_ACTIVE_FCN_ID ++#define MP1_SMN_ACTIVE_FCN_ID__VFID__SHIFT 0x0 ++#define MP1_SMN_ACTIVE_FCN_ID__VF__SHIFT 0x1f ++#define MP1_SMN_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL ++#define MP1_SMN_ACTIVE_FCN_ID__VF_MASK 0x80000000L ++//MP1_SMN_IH_CREDIT ++#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 ++#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 ++#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L ++#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L ++//MP1_SMN_IH_SW_INT ++#define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x0 ++#define MP1_SMN_IH_SW_INT__ID__SHIFT 0x1 ++#define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000001L ++#define MP1_SMN_IH_SW_INT__ID_MASK 0x000001FEL ++//MP1_SMN_IH_SW_INT_CTRL ++#define MP1_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK__SHIFT 0x0 ++#define MP1_SMN_IH_SW_INT_CTRL__SW_INT_ACK__SHIFT 0x8 ++#define MP1_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK 0x00000001L ++#define MP1_SMN_IH_SW_INT_CTRL__SW_INT_ACK_MASK 0x00000100L ++//MP1_SMN_FPS_CNT ++#define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0 ++#define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL ++//MP1_SMN_EXT_SCRATCH0 ++#define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0 ++#define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL ++//MP1_SMN_EXT_SCRATCH1 ++#define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0 ++#define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL ++//MP1_SMN_EXT_SCRATCH2 ++#define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0 ++#define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL ++//MP1_SMN_EXT_SCRATCH3 ++#define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0 ++#define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL ++//MP1_SMN_EXT_SCRATCH4 ++#define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0 ++#define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL ++//MP1_SMN_EXT_SCRATCH5 ++#define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0 ++#define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL ++//MP1_SMN_EXT_SCRATCH6 ++#define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0 ++#define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL ++//MP1_SMN_EXT_SCRATCH7 ++#define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0 ++#define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL ++//MP1_SMN_EXT_SCRATCH8 ++#define MP1_SMN_EXT_SCRATCH8__DATA__SHIFT 0x0 ++#define MP1_SMN_EXT_SCRATCH8__DATA_MASK 0xFFFFFFFFL ++ ++ ++ ++ ++// addressBlock: mp_SmuMp0Pub_CruDec ++//MP0_SOC_INFO ++#define MP0_SOC_INFO__SOC_DIE_ID__SHIFT 0x0 ++#define MP0_SOC_INFO__SOC_PKG_TYPE__SHIFT 0x2 ++#define MP0_SOC_INFO__SOC_DIE_ID_MASK 0x00000003L ++#define MP0_SOC_INFO__SOC_PKG_TYPE_MASK 0x0000001CL ++//MP0_PUB_SCRATCH0 ++#define MP0_PUB_SCRATCH0__DATA__SHIFT 0x0 ++#define MP0_PUB_SCRATCH0__DATA_MASK 0xFFFFFFFFL ++//MP0_PUB_SCRATCH1 ++#define MP0_PUB_SCRATCH1__DATA__SHIFT 0x0 ++#define MP0_PUB_SCRATCH1__DATA_MASK 0xFFFFFFFFL ++//MP0_PUB_SCRATCH2 ++#define MP0_PUB_SCRATCH2__DATA__SHIFT 0x0 ++#define MP0_PUB_SCRATCH2__DATA_MASK 0xFFFFFFFFL ++//MP0_PUB_SCRATCH3 ++#define MP0_PUB_SCRATCH3__DATA__SHIFT 0x0 ++#define MP0_PUB_SCRATCH3__DATA_MASK 0xFFFFFFFFL ++//MP0_FW_INTF ++#define MP0_FW_INTF__SS_SECURE__SHIFT 0x13 ++#define MP0_FW_INTF__SS_SECURE_MASK 0x00080000L ++//MP0_C2PMSG_0 ++#define MP0_C2PMSG_0__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_1 ++#define MP0_C2PMSG_1__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_2 ++#define MP0_C2PMSG_2__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_3 ++#define MP0_C2PMSG_3__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_4 ++#define MP0_C2PMSG_4__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_5 ++#define MP0_C2PMSG_5__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_6 ++#define MP0_C2PMSG_6__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_7 ++#define MP0_C2PMSG_7__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_8 ++#define MP0_C2PMSG_8__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_9 ++#define MP0_C2PMSG_9__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_10 ++#define MP0_C2PMSG_10__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_11 ++#define MP0_C2PMSG_11__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_12 ++#define MP0_C2PMSG_12__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_13 ++#define MP0_C2PMSG_13__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_14 ++#define MP0_C2PMSG_14__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_15 ++#define MP0_C2PMSG_15__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_16 ++#define MP0_C2PMSG_16__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_17 ++#define MP0_C2PMSG_17__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_18 ++#define MP0_C2PMSG_18__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_19 ++#define MP0_C2PMSG_19__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_20 ++#define MP0_C2PMSG_20__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_21 ++#define MP0_C2PMSG_21__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_22 ++#define MP0_C2PMSG_22__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_23 ++#define MP0_C2PMSG_23__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_24 ++#define MP0_C2PMSG_24__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_25 ++#define MP0_C2PMSG_25__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_26 ++#define MP0_C2PMSG_26__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_27 ++#define MP0_C2PMSG_27__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_28 ++#define MP0_C2PMSG_28__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_29 ++#define MP0_C2PMSG_29__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_30 ++#define MP0_C2PMSG_30__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_31 ++#define MP0_C2PMSG_31__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL ++//MP0_P2CMSG_0 ++#define MP0_P2CMSG_0__CONTENT__SHIFT 0x0 ++#define MP0_P2CMSG_0__CONTENT_MASK 0xFFFFFFFFL ++//MP0_P2CMSG_1 ++#define MP0_P2CMSG_1__CONTENT__SHIFT 0x0 ++#define MP0_P2CMSG_1__CONTENT_MASK 0xFFFFFFFFL ++//MP0_P2CMSG_2 ++#define MP0_P2CMSG_2__CONTENT__SHIFT 0x0 ++#define MP0_P2CMSG_2__CONTENT_MASK 0xFFFFFFFFL ++//MP0_P2CMSG_3 ++#define MP0_P2CMSG_3__CONTENT__SHIFT 0x0 ++#define MP0_P2CMSG_3__CONTENT_MASK 0xFFFFFFFFL ++//MP0_P2CMSG_INTEN ++#define MP0_P2CMSG_INTEN__INTEN__SHIFT 0x0 ++#define MP0_P2CMSG_INTEN__INTEN_MASK 0x0000000FL ++//MP0_P2CMSG_INTSTS ++#define MP0_P2CMSG_INTSTS__INTSTS0__SHIFT 0x0 ++#define MP0_P2CMSG_INTSTS__INTSTS1__SHIFT 0x1 ++#define MP0_P2CMSG_INTSTS__INTSTS2__SHIFT 0x2 ++#define MP0_P2CMSG_INTSTS__INTSTS3__SHIFT 0x3 ++#define MP0_P2CMSG_INTSTS__INTSTS0_MASK 0x00000001L ++#define MP0_P2CMSG_INTSTS__INTSTS1_MASK 0x00000002L ++#define MP0_P2CMSG_INTSTS__INTSTS2_MASK 0x00000004L ++#define MP0_P2CMSG_INTSTS__INTSTS3_MASK 0x00000008L ++//MP0_C2PMSG_ATTR_0 ++#define MP0_C2PMSG_ATTR_0__MSG_ATTR__SHIFT 0x0 ++#define MP0_C2PMSG_ATTR_0__MSG_ATTR_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_ATTR_1 ++#define MP0_C2PMSG_ATTR_1__MSG_ATTR__SHIFT 0x0 ++#define MP0_C2PMSG_ATTR_1__MSG_ATTR_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_ATTR_2 ++#define MP0_C2PMSG_ATTR_2__MSG_ATTR__SHIFT 0x0 ++#define MP0_C2PMSG_ATTR_2__MSG_ATTR_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_ATTR_3 ++#define MP0_C2PMSG_ATTR_3__MSG_ATTR__SHIFT 0x0 ++#define MP0_C2PMSG_ATTR_3__MSG_ATTR_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_ATTR_4 ++#define MP0_C2PMSG_ATTR_4__MSG_ATTR__SHIFT 0x0 ++#define MP0_C2PMSG_ATTR_4__MSG_ATTR_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_ATTR_5 ++#define MP0_C2PMSG_ATTR_5__MSG_ATTR__SHIFT 0x0 ++#define MP0_C2PMSG_ATTR_5__MSG_ATTR_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_ATTR_6 ++#define MP0_C2PMSG_ATTR_6__MSG_ATTR__SHIFT 0x0 ++#define MP0_C2PMSG_ATTR_6__MSG_ATTR_MASK 0x0000FFFFL ++//MP0_P2CMSG_ATTR ++#define MP0_P2CMSG_ATTR__MSG_ATTR__SHIFT 0x0 ++#define MP0_P2CMSG_ATTR__MSG_ATTR_MASK 0x000000FFL ++//MP0_P2SMSG_0 ++#define MP0_P2SMSG_0__CONTENT__SHIFT 0x0 ++#define MP0_P2SMSG_0__CONTENT_MASK 0xFFFFFFFFL ++//MP0_P2SMSG_1 ++#define MP0_P2SMSG_1__CONTENT__SHIFT 0x0 ++#define MP0_P2SMSG_1__CONTENT_MASK 0xFFFFFFFFL ++//MP0_P2SMSG_2 ++#define MP0_P2SMSG_2__CONTENT__SHIFT 0x0 ++#define MP0_P2SMSG_2__CONTENT_MASK 0xFFFFFFFFL ++//MP0_P2SMSG_3 ++#define MP0_P2SMSG_3__CONTENT__SHIFT 0x0 ++#define MP0_P2SMSG_3__CONTENT_MASK 0xFFFFFFFFL ++//MP0_P2SMSG_ATTR ++#define MP0_P2SMSG_ATTR__MSG_ATTR__SHIFT 0x0 ++#define MP0_P2SMSG_ATTR__MSG_ATTR_MASK 0x000000FFL ++//MP0_S2PMSG_ATTR ++#define MP0_S2PMSG_ATTR__MSG_ATTR__SHIFT 0x0 ++#define MP0_S2PMSG_ATTR__MSG_ATTR_MASK 0x00000003L ++//MP0_P2SMSG_INTSTS ++#define MP0_P2SMSG_INTSTS__INTSTS0__SHIFT 0x0 ++#define MP0_P2SMSG_INTSTS__INTSTS1__SHIFT 0x1 ++#define MP0_P2SMSG_INTSTS__INTSTS2__SHIFT 0x2 ++#define MP0_P2SMSG_INTSTS__INTSTS3__SHIFT 0x3 ++#define MP0_P2SMSG_INTSTS__INTSTS0_MASK 0x00000001L ++#define MP0_P2SMSG_INTSTS__INTSTS1_MASK 0x00000002L ++#define MP0_P2SMSG_INTSTS__INTSTS2_MASK 0x00000004L ++#define MP0_P2SMSG_INTSTS__INTSTS3_MASK 0x00000008L ++//MP0_S2PMSG_0 ++#define MP0_S2PMSG_0__CONTENT__SHIFT 0x0 ++#define MP0_S2PMSG_0__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_32 ++#define MP0_C2PMSG_32__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_33 ++#define MP0_C2PMSG_33__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_34 ++#define MP0_C2PMSG_34__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_35 ++#define MP0_C2PMSG_35__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_36 ++#define MP0_C2PMSG_36__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_37 ++#define MP0_C2PMSG_37__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_38 ++#define MP0_C2PMSG_38__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_39 ++#define MP0_C2PMSG_39__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_40 ++#define MP0_C2PMSG_40__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_41 ++#define MP0_C2PMSG_41__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_42 ++#define MP0_C2PMSG_42__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_43 ++#define MP0_C2PMSG_43__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_44 ++#define MP0_C2PMSG_44__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_45 ++#define MP0_C2PMSG_45__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_46 ++#define MP0_C2PMSG_46__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_47 ++#define MP0_C2PMSG_47__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_48 ++#define MP0_C2PMSG_48__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_49 ++#define MP0_C2PMSG_49__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_50 ++#define MP0_C2PMSG_50__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_51 ++#define MP0_C2PMSG_51__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_52 ++#define MP0_C2PMSG_52__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_53 ++#define MP0_C2PMSG_53__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_54 ++#define MP0_C2PMSG_54__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_55 ++#define MP0_C2PMSG_55__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_56 ++#define MP0_C2PMSG_56__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_57 ++#define MP0_C2PMSG_57__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_58 ++#define MP0_C2PMSG_58__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_59 ++#define MP0_C2PMSG_59__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_60 ++#define MP0_C2PMSG_60__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_61 ++#define MP0_C2PMSG_61__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_62 ++#define MP0_C2PMSG_62__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_63 ++#define MP0_C2PMSG_63__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_64 ++#define MP0_C2PMSG_64__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_65 ++#define MP0_C2PMSG_65__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_66 ++#define MP0_C2PMSG_66__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_67 ++#define MP0_C2PMSG_67__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_68 ++#define MP0_C2PMSG_68__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_69 ++#define MP0_C2PMSG_69__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_70 ++#define MP0_C2PMSG_70__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_71 ++#define MP0_C2PMSG_71__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_72 ++#define MP0_C2PMSG_72__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_73 ++#define MP0_C2PMSG_73__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_74 ++#define MP0_C2PMSG_74__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_75 ++#define MP0_C2PMSG_75__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_76 ++#define MP0_C2PMSG_76__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_77 ++#define MP0_C2PMSG_77__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_78 ++#define MP0_C2PMSG_78__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_79 ++#define MP0_C2PMSG_79__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_80 ++#define MP0_C2PMSG_80__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_81 ++#define MP0_C2PMSG_81__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_82 ++#define MP0_C2PMSG_82__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_83 ++#define MP0_C2PMSG_83__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_84 ++#define MP0_C2PMSG_84__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_85 ++#define MP0_C2PMSG_85__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_86 ++#define MP0_C2PMSG_86__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_87 ++#define MP0_C2PMSG_87__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_88 ++#define MP0_C2PMSG_88__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_89 ++#define MP0_C2PMSG_89__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_90 ++#define MP0_C2PMSG_90__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_91 ++#define MP0_C2PMSG_91__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_92 ++#define MP0_C2PMSG_92__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_93 ++#define MP0_C2PMSG_93__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_94 ++#define MP0_C2PMSG_94__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_95 ++#define MP0_C2PMSG_95__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_96 ++#define MP0_C2PMSG_96__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_97 ++#define MP0_C2PMSG_97__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_98 ++#define MP0_C2PMSG_98__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_99 ++#define MP0_C2PMSG_99__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_100 ++#define MP0_C2PMSG_100__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_101 ++#define MP0_C2PMSG_101__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_102 ++#define MP0_C2PMSG_102__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL ++//MP0_C2PMSG_103 ++#define MP0_C2PMSG_103__CONTENT__SHIFT 0x0 ++#define MP0_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL ++//MP0_ACTIVE_FCN_ID ++#define MP0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 ++#define MP0_ACTIVE_FCN_ID__VF__SHIFT 0x1f ++#define MP0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL ++#define MP0_ACTIVE_FCN_ID__VF_MASK 0x80000000L ++//MP0_IH_CREDIT ++#define MP0_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 ++#define MP0_IH_CREDIT__CLIENT_ID__SHIFT 0x10 ++#define MP0_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L ++#define MP0_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L ++//MP0_IH_SW_INT ++#define MP0_IH_SW_INT__ID__SHIFT 0x0 ++#define MP0_IH_SW_INT__VALID__SHIFT 0x8 ++#define MP0_IH_SW_INT__ID_MASK 0x000000FFL ++#define MP0_IH_SW_INT__VALID_MASK 0x00000100L ++//MP0_IH_SW_INT_CTRL ++#define MP0_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 ++#define MP0_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 ++#define MP0_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L ++#define MP0_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L ++ ++ ++//CGTT_DRM_CLK_CTRL0 ++#define CGTT_DRM_CLK_CTRL0__ON_DELAY__SHIFT 0x0 ++#define CGTT_DRM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 ++#define CGTT_DRM_CLK_CTRL0__DIV_ID__SHIFT 0xc ++#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_0__SHIFT 0x15 ++#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_REG__SHIFT 0x16 ++#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18 ++#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19 ++#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a ++#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b ++#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c ++#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d ++#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e ++#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f ++#define CGTT_DRM_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL ++#define CGTT_DRM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L ++#define CGTT_DRM_CLK_CTRL0__DIV_ID_MASK 0x00007000L ++#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_0_MASK 0x00200000L ++#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_REG_MASK 0x00400000L ++#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L ++#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L ++#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L ++#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L ++#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L ++#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L ++#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L ++#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L ++//DRM_LIGHT_SLEEP_CTRL ++#define DRM_LIGHT_SLEEP_CTRL__MEM_LIGHT_SLEEP_EN__SHIFT 0x0 ++#define DRM_LIGHT_SLEEP_CTRL__MEM_LIGHT_SLEEP_EN_MASK 0x00000001L ++ ++ ++// addressBlock: mp_SmuMp1Pub_CruDec ++//MP1_SMN_PUB_CTRL ++#define MP1_SMN_PUB_CTRL__RESET__SHIFT 0x0 ++#define MP1_SMN_PUB_CTRL__RESET_MASK 0x00000001L ++//MP1_FIRMWARE_FLAGS ++#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 ++#define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 ++#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L ++#define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL ++//MP1_PUB_SCRATCH0 ++#define MP1_PUB_SCRATCH0__DATA__SHIFT 0x0 ++#define MP1_PUB_SCRATCH0__DATA_MASK 0xFFFFFFFFL ++//MP1_PUB_SCRATCH1 ++#define MP1_PUB_SCRATCH1__DATA__SHIFT 0x0 ++#define MP1_PUB_SCRATCH1__DATA_MASK 0xFFFFFFFFL ++//MP1_PUB_SCRATCH2 ++#define MP1_PUB_SCRATCH2__DATA__SHIFT 0x0 ++#define MP1_PUB_SCRATCH2__DATA_MASK 0xFFFFFFFFL ++//MP1_PUB_SCRATCH3 ++#define MP1_PUB_SCRATCH3__DATA__SHIFT 0x0 ++#define MP1_PUB_SCRATCH3__DATA_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_0 ++#define MP1_C2PMSG_0__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_1 ++#define MP1_C2PMSG_1__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_2 ++#define MP1_C2PMSG_2__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_3 ++#define MP1_C2PMSG_3__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_4 ++#define MP1_C2PMSG_4__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_5 ++#define MP1_C2PMSG_5__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_6 ++#define MP1_C2PMSG_6__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_7 ++#define MP1_C2PMSG_7__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_8 ++#define MP1_C2PMSG_8__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_9 ++#define MP1_C2PMSG_9__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_10 ++#define MP1_C2PMSG_10__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_11 ++#define MP1_C2PMSG_11__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_12 ++#define MP1_C2PMSG_12__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_13 ++#define MP1_C2PMSG_13__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_14 ++#define MP1_C2PMSG_14__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_15 ++#define MP1_C2PMSG_15__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_16 ++#define MP1_C2PMSG_16__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_17 ++#define MP1_C2PMSG_17__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_18 ++#define MP1_C2PMSG_18__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_19 ++#define MP1_C2PMSG_19__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_20 ++#define MP1_C2PMSG_20__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_21 ++#define MP1_C2PMSG_21__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_22 ++#define MP1_C2PMSG_22__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_23 ++#define MP1_C2PMSG_23__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_24 ++#define MP1_C2PMSG_24__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_25 ++#define MP1_C2PMSG_25__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_26 ++#define MP1_C2PMSG_26__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_27 ++#define MP1_C2PMSG_27__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_28 ++#define MP1_C2PMSG_28__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_29 ++#define MP1_C2PMSG_29__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_30 ++#define MP1_C2PMSG_30__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_31 ++#define MP1_C2PMSG_31__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL ++//MP1_P2CMSG_0 ++#define MP1_P2CMSG_0__CONTENT__SHIFT 0x0 ++#define MP1_P2CMSG_0__CONTENT_MASK 0xFFFFFFFFL ++//MP1_P2CMSG_1 ++#define MP1_P2CMSG_1__CONTENT__SHIFT 0x0 ++#define MP1_P2CMSG_1__CONTENT_MASK 0xFFFFFFFFL ++//MP1_P2CMSG_2 ++#define MP1_P2CMSG_2__CONTENT__SHIFT 0x0 ++#define MP1_P2CMSG_2__CONTENT_MASK 0xFFFFFFFFL ++//MP1_P2CMSG_3 ++#define MP1_P2CMSG_3__CONTENT__SHIFT 0x0 ++#define MP1_P2CMSG_3__CONTENT_MASK 0xFFFFFFFFL ++//MP1_P2CMSG_INTEN ++#define MP1_P2CMSG_INTEN__INTEN__SHIFT 0x0 ++#define MP1_P2CMSG_INTEN__INTEN_MASK 0x0000000FL ++//MP1_P2CMSG_INTSTS ++#define MP1_P2CMSG_INTSTS__INTSTS0__SHIFT 0x0 ++#define MP1_P2CMSG_INTSTS__INTSTS1__SHIFT 0x1 ++#define MP1_P2CMSG_INTSTS__INTSTS2__SHIFT 0x2 ++#define MP1_P2CMSG_INTSTS__INTSTS3__SHIFT 0x3 ++#define MP1_P2CMSG_INTSTS__INTSTS0_MASK 0x00000001L ++#define MP1_P2CMSG_INTSTS__INTSTS1_MASK 0x00000002L ++#define MP1_P2CMSG_INTSTS__INTSTS2_MASK 0x00000004L ++#define MP1_P2CMSG_INTSTS__INTSTS3_MASK 0x00000008L ++//MP1_P2SMSG_0 ++#define MP1_P2SMSG_0__CONTENT__SHIFT 0x0 ++#define MP1_P2SMSG_0__CONTENT_MASK 0xFFFFFFFFL ++//MP1_P2SMSG_1 ++#define MP1_P2SMSG_1__CONTENT__SHIFT 0x0 ++#define MP1_P2SMSG_1__CONTENT_MASK 0xFFFFFFFFL ++//MP1_P2SMSG_2 ++#define MP1_P2SMSG_2__CONTENT__SHIFT 0x0 ++#define MP1_P2SMSG_2__CONTENT_MASK 0xFFFFFFFFL ++//MP1_P2SMSG_3 ++#define MP1_P2SMSG_3__CONTENT__SHIFT 0x0 ++#define MP1_P2SMSG_3__CONTENT_MASK 0xFFFFFFFFL ++//MP1_P2SMSG_INTSTS ++#define MP1_P2SMSG_INTSTS__INTSTS0__SHIFT 0x0 ++#define MP1_P2SMSG_INTSTS__INTSTS1__SHIFT 0x1 ++#define MP1_P2SMSG_INTSTS__INTSTS2__SHIFT 0x2 ++#define MP1_P2SMSG_INTSTS__INTSTS3__SHIFT 0x3 ++#define MP1_P2SMSG_INTSTS__INTSTS0_MASK 0x00000001L ++#define MP1_P2SMSG_INTSTS__INTSTS1_MASK 0x00000002L ++#define MP1_P2SMSG_INTSTS__INTSTS2_MASK 0x00000004L ++#define MP1_P2SMSG_INTSTS__INTSTS3_MASK 0x00000008L ++//MP1_S2PMSG_0 ++#define MP1_S2PMSG_0__CONTENT__SHIFT 0x0 ++#define MP1_S2PMSG_0__CONTENT_MASK 0xFFFFFFFFL ++//MP1_ACP2MP_RESP ++#define MP1_ACP2MP_RESP__CONTENT__SHIFT 0x0 ++#define MP1_ACP2MP_RESP__CONTENT_MASK 0xFFFFFFFFL ++//MP1_DC2MP_RESP ++#define MP1_DC2MP_RESP__CONTENT__SHIFT 0x0 ++#define MP1_DC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL ++//MP1_UVD2MP_RESP ++#define MP1_UVD2MP_RESP__CONTENT__SHIFT 0x0 ++#define MP1_UVD2MP_RESP__CONTENT_MASK 0xFFFFFFFFL ++//MP1_VCE2MP_RESP ++#define MP1_VCE2MP_RESP__CONTENT__SHIFT 0x0 ++#define MP1_VCE2MP_RESP__CONTENT_MASK 0xFFFFFFFFL ++//MP1_RLC2MP_RESP ++#define MP1_RLC2MP_RESP__CONTENT__SHIFT 0x0 ++#define MP1_RLC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_32 ++#define MP1_C2PMSG_32__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_33 ++#define MP1_C2PMSG_33__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_34 ++#define MP1_C2PMSG_34__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_35 ++#define MP1_C2PMSG_35__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_36 ++#define MP1_C2PMSG_36__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_37 ++#define MP1_C2PMSG_37__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_38 ++#define MP1_C2PMSG_38__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_39 ++#define MP1_C2PMSG_39__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_40 ++#define MP1_C2PMSG_40__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_41 ++#define MP1_C2PMSG_41__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_42 ++#define MP1_C2PMSG_42__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_43 ++#define MP1_C2PMSG_43__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_44 ++#define MP1_C2PMSG_44__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_45 ++#define MP1_C2PMSG_45__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_46 ++#define MP1_C2PMSG_46__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_47 ++#define MP1_C2PMSG_47__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_48 ++#define MP1_C2PMSG_48__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_49 ++#define MP1_C2PMSG_49__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_50 ++#define MP1_C2PMSG_50__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_51 ++#define MP1_C2PMSG_51__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_52 ++#define MP1_C2PMSG_52__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_53 ++#define MP1_C2PMSG_53__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_54 ++#define MP1_C2PMSG_54__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_55 ++#define MP1_C2PMSG_55__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_56 ++#define MP1_C2PMSG_56__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_57 ++#define MP1_C2PMSG_57__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_58 ++#define MP1_C2PMSG_58__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_59 ++#define MP1_C2PMSG_59__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_60 ++#define MP1_C2PMSG_60__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_61 ++#define MP1_C2PMSG_61__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_62 ++#define MP1_C2PMSG_62__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_63 ++#define MP1_C2PMSG_63__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_64 ++#define MP1_C2PMSG_64__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_65 ++#define MP1_C2PMSG_65__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_66 ++#define MP1_C2PMSG_66__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_67 ++#define MP1_C2PMSG_67__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_68 ++#define MP1_C2PMSG_68__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_69 ++#define MP1_C2PMSG_69__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_70 ++#define MP1_C2PMSG_70__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_71 ++#define MP1_C2PMSG_71__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_72 ++#define MP1_C2PMSG_72__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_73 ++#define MP1_C2PMSG_73__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_74 ++#define MP1_C2PMSG_74__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_75 ++#define MP1_C2PMSG_75__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_76 ++#define MP1_C2PMSG_76__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_77 ++#define MP1_C2PMSG_77__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_78 ++#define MP1_C2PMSG_78__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_79 ++#define MP1_C2PMSG_79__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_80 ++#define MP1_C2PMSG_80__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_81 ++#define MP1_C2PMSG_81__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_82 ++#define MP1_C2PMSG_82__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_83 ++#define MP1_C2PMSG_83__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_84 ++#define MP1_C2PMSG_84__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_85 ++#define MP1_C2PMSG_85__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_86 ++#define MP1_C2PMSG_86__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_87 ++#define MP1_C2PMSG_87__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_88 ++#define MP1_C2PMSG_88__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_89 ++#define MP1_C2PMSG_89__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_90 ++#define MP1_C2PMSG_90__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_91 ++#define MP1_C2PMSG_91__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_92 ++#define MP1_C2PMSG_92__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_93 ++#define MP1_C2PMSG_93__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_94 ++#define MP1_C2PMSG_94__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_95 ++#define MP1_C2PMSG_95__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_96 ++#define MP1_C2PMSG_96__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_97 ++#define MP1_C2PMSG_97__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_98 ++#define MP1_C2PMSG_98__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_99 ++#define MP1_C2PMSG_99__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_100 ++#define MP1_C2PMSG_100__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_101 ++#define MP1_C2PMSG_101__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_102 ++#define MP1_C2PMSG_102__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL ++//MP1_C2PMSG_103 ++#define MP1_C2PMSG_103__CONTENT__SHIFT 0x0 ++#define MP1_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL ++//MP1_ACTIVE_FCN_ID ++#define MP1_ACTIVE_FCN_ID__VFID__SHIFT 0x0 ++#define MP1_ACTIVE_FCN_ID__VF__SHIFT 0x1f ++#define MP1_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL ++#define MP1_ACTIVE_FCN_ID__VF_MASK 0x80000000L ++//MP1_IH_CREDIT ++#define MP1_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 ++#define MP1_IH_CREDIT__CLIENT_ID__SHIFT 0x10 ++#define MP1_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L ++#define MP1_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L ++//MP1_IH_SW_INT ++#define MP1_IH_SW_INT__ID__SHIFT 0x0 ++#define MP1_IH_SW_INT__VALID__SHIFT 0x8 ++#define MP1_IH_SW_INT__ID_MASK 0x000000FFL ++#define MP1_IH_SW_INT__VALID_MASK 0x00000100L ++//MP1_IH_SW_INT_CTRL ++#define MP1_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 ++#define MP1_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 ++#define MP1_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L ++#define MP1_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L ++//MP1_FPS_CNT ++#define MP1_FPS_CNT__COUNT__SHIFT 0x0 ++#define MP1_FPS_CNT__COUNT_MASK 0xFFFFFFFFL ++//MP1_PUB_CTRL ++#define MP1_PUB_CTRL__RESET__SHIFT 0x0 ++#define MP1_PUB_CTRL__RESET_MASK 0x00000001L ++//MP1_EXT_SCRATCH0 ++#define MP1_EXT_SCRATCH0__DATA__SHIFT 0x0 ++#define MP1_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL ++//MP1_EXT_SCRATCH1 ++#define MP1_EXT_SCRATCH1__DATA__SHIFT 0x0 ++#define MP1_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL ++//MP1_EXT_SCRATCH2 ++#define MP1_EXT_SCRATCH2__DATA__SHIFT 0x0 ++#define MP1_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL ++//MP1_EXT_SCRATCH3 ++#define MP1_EXT_SCRATCH3__DATA__SHIFT 0x0 ++#define MP1_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL ++//MP1_EXT_SCRATCH4 ++#define MP1_EXT_SCRATCH4__DATA__SHIFT 0x0 ++#define MP1_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL ++//MP1_EXT_SCRATCH5 ++#define MP1_EXT_SCRATCH5__DATA__SHIFT 0x0 ++#define MP1_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL ++//MP1_EXT_SCRATCH6 ++#define MP1_EXT_SCRATCH6__DATA__SHIFT 0x0 ++#define MP1_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL ++//MP1_EXT_SCRATCH7 ++#define MP1_EXT_SCRATCH7__DATA__SHIFT 0x0 ++#define MP1_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL ++ ++ ++#endif +diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_default.h +deleted file mode 100644 +index 98ba7d8..0000000 +--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_default.h ++++ /dev/null +@@ -1,342 +0,0 @@ +-/* +- * Copyright (C) 2017 Advanced Micro Devices, Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included +- * in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- */ +-#ifndef _mp_9_0_DEFAULT_HEADER +-#define _mp_9_0_DEFAULT_HEADER +- +- +-// addressBlock: mp_SmuMp0_SmnDec +-#define mmMP0_SMN_C2PMSG_32_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_33_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_34_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_35_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_36_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_37_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_38_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_39_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_40_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_41_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_42_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_43_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_44_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_45_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_46_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_47_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_48_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_49_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_50_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_51_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_52_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_53_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_54_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_55_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_56_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_57_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_58_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_59_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_60_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_61_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_62_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_63_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_64_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_65_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_66_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_67_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_68_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_69_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_70_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_71_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_72_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_73_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_74_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_75_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_76_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_77_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_78_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_79_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_80_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_81_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_82_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_83_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_84_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_85_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_86_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_87_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_88_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_89_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_90_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_91_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_92_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_93_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_94_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_95_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_96_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_97_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_98_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_99_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_100_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_101_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_102_DEFAULT 0x00000000 +-#define mmMP0_SMN_C2PMSG_103_DEFAULT 0x00000000 +-#define mmMP0_SMN_ACTIVE_FCN_ID_DEFAULT 0x00000000 +-#define mmMP0_SMN_IH_CREDIT_DEFAULT 0x00000000 +-#define mmMP0_SMN_IH_SW_INT_DEFAULT 0x00000000 +-#define mmMP0_SMN_IH_SW_INT_CTRL_DEFAULT 0x00000000 +- +- +-// addressBlock: mp_SmuMp1_SmnDec +-#define mmMP1_SMN_ACP2MP_RESP_DEFAULT 0x00000000 +-#define mmMP1_SMN_DC2MP_RESP_DEFAULT 0x00000000 +-#define mmMP1_SMN_UVD2MP_RESP_DEFAULT 0x00000000 +-#define mmMP1_SMN_VCE2MP_RESP_DEFAULT 0x00000000 +-#define mmMP1_SMN_RLC2MP_RESP_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_32_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_33_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_34_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_35_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_36_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_37_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_38_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_39_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_40_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_41_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_42_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_43_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_44_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_45_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_46_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_47_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_48_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_49_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_50_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_51_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_52_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_53_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_54_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_55_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_56_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_57_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_58_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_59_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_60_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_61_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_62_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_63_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_64_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_65_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_66_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_67_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_68_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_69_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_70_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_71_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_72_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_73_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_74_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_75_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_76_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_77_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_78_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_79_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_80_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_81_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_82_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_83_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_84_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_85_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_86_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_87_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_88_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_89_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_90_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_91_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_92_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_93_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_94_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_95_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_96_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_97_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_98_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_99_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_100_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_101_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_102_DEFAULT 0x00000000 +-#define mmMP1_SMN_C2PMSG_103_DEFAULT 0x00000000 +-#define mmMP1_SMN_ACTIVE_FCN_ID_DEFAULT 0x00000000 +-#define mmMP1_SMN_IH_CREDIT_DEFAULT 0x00000000 +-#define mmMP1_SMN_IH_SW_INT_DEFAULT 0x00000000 +-#define mmMP1_SMN_IH_SW_INT_CTRL_DEFAULT 0x00000000 +-#define mmMP1_SMN_FPS_CNT_DEFAULT 0x00000000 +-#define mmMP1_SMN_EXT_SCRATCH0_DEFAULT 0x00000000 +-#define mmMP1_SMN_EXT_SCRATCH1_DEFAULT 0x00000000 +-#define mmMP1_SMN_EXT_SCRATCH2_DEFAULT 0x00000000 +-#define mmMP1_SMN_EXT_SCRATCH3_DEFAULT 0x00000000 +-#define mmMP1_SMN_EXT_SCRATCH4_DEFAULT 0x00000000 +-#define mmMP1_SMN_EXT_SCRATCH5_DEFAULT 0x00000000 +-#define mmMP1_SMN_EXT_SCRATCH6_DEFAULT 0x00000000 +-#define mmMP1_SMN_EXT_SCRATCH7_DEFAULT 0x00000000 +-#define mmMP1_SMN_EXT_SCRATCH8_DEFAULT 0x00000000 +- +- +-// addressBlock: mp_SmuMp1Pub_CruDec +-#define mmMP1_SMN_PUB_CTRL_DEFAULT 0x00000001 +-#define smnMP1_FIRMWARE_FLAGS_DEFAULT 0x00000000 +-#define smnMP1_PUB_SCRATCH0_DEFAULT 0x00000000 +-#define smnMP1_PUB_SCRATCH1_DEFAULT 0x00000000 +-#define smnMP1_PUB_SCRATCH2_DEFAULT 0x00000000 +-#define smnMP1_PUB_SCRATCH3_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_0_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_1_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_2_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_3_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_4_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_5_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_6_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_7_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_8_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_9_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_10_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_11_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_12_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_13_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_14_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_15_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_16_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_17_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_18_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_19_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_20_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_21_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_22_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_23_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_24_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_25_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_26_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_27_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_28_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_29_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_30_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_31_DEFAULT 0x00000000 +-#define smnMP1_P2CMSG_0_DEFAULT 0x00000000 +-#define smnMP1_P2CMSG_1_DEFAULT 0x00000000 +-#define smnMP1_P2CMSG_2_DEFAULT 0x00000000 +-#define smnMP1_P2CMSG_3_DEFAULT 0x00000000 +-#define smnMP1_P2CMSG_INTEN_DEFAULT 0x00000000 +-#define smnMP1_P2CMSG_INTSTS_DEFAULT 0x00000000 +-#define smnMP1_P2SMSG_0_DEFAULT 0x00000000 +-#define smnMP1_P2SMSG_1_DEFAULT 0x00000000 +-#define smnMP1_P2SMSG_2_DEFAULT 0x00000000 +-#define smnMP1_P2SMSG_3_DEFAULT 0x00000000 +-#define smnMP1_P2SMSG_INTSTS_DEFAULT 0x00000000 +-#define smnMP1_S2PMSG_0_DEFAULT 0x00000000 +-#define smnMP1_ACP2MP_RESP_DEFAULT 0x00000000 +-#define smnMP1_DC2MP_RESP_DEFAULT 0x00000000 +-#define smnMP1_UVD2MP_RESP_DEFAULT 0x00000000 +-#define smnMP1_VCE2MP_RESP_DEFAULT 0x00000000 +-#define smnMP1_RLC2MP_RESP_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_32_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_33_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_34_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_35_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_36_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_37_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_38_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_39_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_40_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_41_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_42_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_43_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_44_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_45_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_46_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_47_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_48_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_49_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_50_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_51_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_52_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_53_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_54_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_55_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_56_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_57_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_58_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_59_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_60_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_61_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_62_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_63_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_64_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_65_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_66_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_67_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_68_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_69_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_70_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_71_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_72_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_73_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_74_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_75_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_76_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_77_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_78_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_79_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_80_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_81_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_82_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_83_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_84_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_85_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_86_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_87_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_88_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_89_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_90_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_91_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_92_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_93_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_94_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_95_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_96_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_97_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_98_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_99_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_100_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_101_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_102_DEFAULT 0x00000000 +-#define smnMP1_C2PMSG_103_DEFAULT 0x00000000 +-#define smnMP1_ACTIVE_FCN_ID_DEFAULT 0x00000000 +-#define smnMP1_IH_CREDIT_DEFAULT 0x00000000 +-#define smnMP1_IH_SW_INT_DEFAULT 0x00000000 +-#define smnMP1_IH_SW_INT_CTRL_DEFAULT 0x00000000 +-#define smnMP1_FPS_CNT_DEFAULT 0x00000000 +-#define smnMP1_PUB_CTRL_DEFAULT 0x00000001 +-#define smnMP1_EXT_SCRATCH0_DEFAULT 0x00000000 +-#define smnMP1_EXT_SCRATCH1_DEFAULT 0x00000000 +-#define smnMP1_EXT_SCRATCH2_DEFAULT 0x00000000 +-#define smnMP1_EXT_SCRATCH3_DEFAULT 0x00000000 +-#define smnMP1_EXT_SCRATCH4_DEFAULT 0x00000000 +-#define smnMP1_EXT_SCRATCH5_DEFAULT 0x00000000 +-#define smnMP1_EXT_SCRATCH6_DEFAULT 0x00000000 +-#define smnMP1_EXT_SCRATCH7_DEFAULT 0x00000000 +- +- +-#endif +diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_offset.h +deleted file mode 100644 +index 621e880..0000000 +--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_offset.h ++++ /dev/null +@@ -1,375 +0,0 @@ +-/* +- * Copyright (C) 2017 Advanced Micro Devices, Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included +- * in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- */ +-#ifndef _mp_9_0_OFFSET_HEADER +-#define _mp_9_0_OFFSET_HEADER +- +- +- +-// addressBlock: mp_SmuMp0_SmnDec +-// base address: 0x0 +-#define mmMP0_SMN_C2PMSG_32 0x0060 +-#define mmMP0_SMN_C2PMSG_32_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_33 0x0061 +-#define mmMP0_SMN_C2PMSG_33_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_34 0x0062 +-#define mmMP0_SMN_C2PMSG_34_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_35 0x0063 +-#define mmMP0_SMN_C2PMSG_35_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_36 0x0064 +-#define mmMP0_SMN_C2PMSG_36_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_37 0x0065 +-#define mmMP0_SMN_C2PMSG_37_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_38 0x0066 +-#define mmMP0_SMN_C2PMSG_38_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_39 0x0067 +-#define mmMP0_SMN_C2PMSG_39_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_40 0x0068 +-#define mmMP0_SMN_C2PMSG_40_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_41 0x0069 +-#define mmMP0_SMN_C2PMSG_41_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_42 0x006a +-#define mmMP0_SMN_C2PMSG_42_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_43 0x006b +-#define mmMP0_SMN_C2PMSG_43_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_44 0x006c +-#define mmMP0_SMN_C2PMSG_44_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_45 0x006d +-#define mmMP0_SMN_C2PMSG_45_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_46 0x006e +-#define mmMP0_SMN_C2PMSG_46_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_47 0x006f +-#define mmMP0_SMN_C2PMSG_47_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_48 0x0070 +-#define mmMP0_SMN_C2PMSG_48_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_49 0x0071 +-#define mmMP0_SMN_C2PMSG_49_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_50 0x0072 +-#define mmMP0_SMN_C2PMSG_50_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_51 0x0073 +-#define mmMP0_SMN_C2PMSG_51_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_52 0x0074 +-#define mmMP0_SMN_C2PMSG_52_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_53 0x0075 +-#define mmMP0_SMN_C2PMSG_53_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_54 0x0076 +-#define mmMP0_SMN_C2PMSG_54_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_55 0x0077 +-#define mmMP0_SMN_C2PMSG_55_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_56 0x0078 +-#define mmMP0_SMN_C2PMSG_56_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_57 0x0079 +-#define mmMP0_SMN_C2PMSG_57_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_58 0x007a +-#define mmMP0_SMN_C2PMSG_58_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_59 0x007b +-#define mmMP0_SMN_C2PMSG_59_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_60 0x007c +-#define mmMP0_SMN_C2PMSG_60_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_61 0x007d +-#define mmMP0_SMN_C2PMSG_61_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_62 0x007e +-#define mmMP0_SMN_C2PMSG_62_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_63 0x007f +-#define mmMP0_SMN_C2PMSG_63_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_64 0x0080 +-#define mmMP0_SMN_C2PMSG_64_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_65 0x0081 +-#define mmMP0_SMN_C2PMSG_65_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_66 0x0082 +-#define mmMP0_SMN_C2PMSG_66_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_67 0x0083 +-#define mmMP0_SMN_C2PMSG_67_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_68 0x0084 +-#define mmMP0_SMN_C2PMSG_68_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_69 0x0085 +-#define mmMP0_SMN_C2PMSG_69_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_70 0x0086 +-#define mmMP0_SMN_C2PMSG_70_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_71 0x0087 +-#define mmMP0_SMN_C2PMSG_71_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_72 0x0088 +-#define mmMP0_SMN_C2PMSG_72_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_73 0x0089 +-#define mmMP0_SMN_C2PMSG_73_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_74 0x008a +-#define mmMP0_SMN_C2PMSG_74_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_75 0x008b +-#define mmMP0_SMN_C2PMSG_75_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_76 0x008c +-#define mmMP0_SMN_C2PMSG_76_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_77 0x008d +-#define mmMP0_SMN_C2PMSG_77_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_78 0x008e +-#define mmMP0_SMN_C2PMSG_78_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_79 0x008f +-#define mmMP0_SMN_C2PMSG_79_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_80 0x0090 +-#define mmMP0_SMN_C2PMSG_80_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_81 0x0091 +-#define mmMP0_SMN_C2PMSG_81_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_82 0x0092 +-#define mmMP0_SMN_C2PMSG_82_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_83 0x0093 +-#define mmMP0_SMN_C2PMSG_83_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_84 0x0094 +-#define mmMP0_SMN_C2PMSG_84_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_85 0x0095 +-#define mmMP0_SMN_C2PMSG_85_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_86 0x0096 +-#define mmMP0_SMN_C2PMSG_86_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_87 0x0097 +-#define mmMP0_SMN_C2PMSG_87_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_88 0x0098 +-#define mmMP0_SMN_C2PMSG_88_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_89 0x0099 +-#define mmMP0_SMN_C2PMSG_89_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_90 0x009a +-#define mmMP0_SMN_C2PMSG_90_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_91 0x009b +-#define mmMP0_SMN_C2PMSG_91_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_92 0x009c +-#define mmMP0_SMN_C2PMSG_92_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_93 0x009d +-#define mmMP0_SMN_C2PMSG_93_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_94 0x009e +-#define mmMP0_SMN_C2PMSG_94_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_95 0x009f +-#define mmMP0_SMN_C2PMSG_95_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_96 0x00a0 +-#define mmMP0_SMN_C2PMSG_96_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_97 0x00a1 +-#define mmMP0_SMN_C2PMSG_97_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_98 0x00a2 +-#define mmMP0_SMN_C2PMSG_98_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_99 0x00a3 +-#define mmMP0_SMN_C2PMSG_99_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_100 0x00a4 +-#define mmMP0_SMN_C2PMSG_100_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_101 0x00a5 +-#define mmMP0_SMN_C2PMSG_101_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_102 0x00a6 +-#define mmMP0_SMN_C2PMSG_102_BASE_IDX 0 +-#define mmMP0_SMN_C2PMSG_103 0x00a7 +-#define mmMP0_SMN_C2PMSG_103_BASE_IDX 0 +-#define mmMP0_SMN_ACTIVE_FCN_ID 0x00c0 +-#define mmMP0_SMN_ACTIVE_FCN_ID_BASE_IDX 0 +-#define mmMP0_SMN_IH_CREDIT 0x00c1 +-#define mmMP0_SMN_IH_CREDIT_BASE_IDX 0 +-#define mmMP0_SMN_IH_SW_INT 0x00c2 +-#define mmMP0_SMN_IH_SW_INT_BASE_IDX 0 +-#define mmMP0_SMN_IH_SW_INT_CTRL 0x00c3 +-#define mmMP0_SMN_IH_SW_INT_CTRL_BASE_IDX 0 +- +- +-// addressBlock: mp_SmuMp1_SmnDec +-// base address: 0x0 +-#define mmMP1_SMN_ACP2MP_RESP 0x0240 +-#define mmMP1_SMN_ACP2MP_RESP_BASE_IDX 0 +-#define mmMP1_SMN_DC2MP_RESP 0x0241 +-#define mmMP1_SMN_DC2MP_RESP_BASE_IDX 0 +-#define mmMP1_SMN_UVD2MP_RESP 0x0242 +-#define mmMP1_SMN_UVD2MP_RESP_BASE_IDX 0 +-#define mmMP1_SMN_VCE2MP_RESP 0x0243 +-#define mmMP1_SMN_VCE2MP_RESP_BASE_IDX 0 +-#define mmMP1_SMN_RLC2MP_RESP 0x0244 +-#define mmMP1_SMN_RLC2MP_RESP_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_32 0x0260 +-#define mmMP1_SMN_C2PMSG_32_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_33 0x0261 +-#define mmMP1_SMN_C2PMSG_33_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_34 0x0262 +-#define mmMP1_SMN_C2PMSG_34_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_35 0x0263 +-#define mmMP1_SMN_C2PMSG_35_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_36 0x0264 +-#define mmMP1_SMN_C2PMSG_36_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_37 0x0265 +-#define mmMP1_SMN_C2PMSG_37_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_38 0x0266 +-#define mmMP1_SMN_C2PMSG_38_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_39 0x0267 +-#define mmMP1_SMN_C2PMSG_39_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_40 0x0268 +-#define mmMP1_SMN_C2PMSG_40_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_41 0x0269 +-#define mmMP1_SMN_C2PMSG_41_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_42 0x026a +-#define mmMP1_SMN_C2PMSG_42_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_43 0x026b +-#define mmMP1_SMN_C2PMSG_43_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_44 0x026c +-#define mmMP1_SMN_C2PMSG_44_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_45 0x026d +-#define mmMP1_SMN_C2PMSG_45_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_46 0x026e +-#define mmMP1_SMN_C2PMSG_46_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_47 0x026f +-#define mmMP1_SMN_C2PMSG_47_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_48 0x0270 +-#define mmMP1_SMN_C2PMSG_48_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_49 0x0271 +-#define mmMP1_SMN_C2PMSG_49_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_50 0x0272 +-#define mmMP1_SMN_C2PMSG_50_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_51 0x0273 +-#define mmMP1_SMN_C2PMSG_51_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_52 0x0274 +-#define mmMP1_SMN_C2PMSG_52_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_53 0x0275 +-#define mmMP1_SMN_C2PMSG_53_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_54 0x0276 +-#define mmMP1_SMN_C2PMSG_54_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_55 0x0277 +-#define mmMP1_SMN_C2PMSG_55_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_56 0x0278 +-#define mmMP1_SMN_C2PMSG_56_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_57 0x0279 +-#define mmMP1_SMN_C2PMSG_57_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_58 0x027a +-#define mmMP1_SMN_C2PMSG_58_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_59 0x027b +-#define mmMP1_SMN_C2PMSG_59_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_60 0x027c +-#define mmMP1_SMN_C2PMSG_60_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_61 0x027d +-#define mmMP1_SMN_C2PMSG_61_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_62 0x027e +-#define mmMP1_SMN_C2PMSG_62_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_63 0x027f +-#define mmMP1_SMN_C2PMSG_63_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_64 0x0280 +-#define mmMP1_SMN_C2PMSG_64_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_65 0x0281 +-#define mmMP1_SMN_C2PMSG_65_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_66 0x0282 +-#define mmMP1_SMN_C2PMSG_66_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_67 0x0283 +-#define mmMP1_SMN_C2PMSG_67_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_68 0x0284 +-#define mmMP1_SMN_C2PMSG_68_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_69 0x0285 +-#define mmMP1_SMN_C2PMSG_69_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_70 0x0286 +-#define mmMP1_SMN_C2PMSG_70_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_71 0x0287 +-#define mmMP1_SMN_C2PMSG_71_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_72 0x0288 +-#define mmMP1_SMN_C2PMSG_72_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_73 0x0289 +-#define mmMP1_SMN_C2PMSG_73_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_74 0x028a +-#define mmMP1_SMN_C2PMSG_74_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_75 0x028b +-#define mmMP1_SMN_C2PMSG_75_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_76 0x028c +-#define mmMP1_SMN_C2PMSG_76_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_77 0x028d +-#define mmMP1_SMN_C2PMSG_77_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_78 0x028e +-#define mmMP1_SMN_C2PMSG_78_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_79 0x028f +-#define mmMP1_SMN_C2PMSG_79_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_80 0x0290 +-#define mmMP1_SMN_C2PMSG_80_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_81 0x0291 +-#define mmMP1_SMN_C2PMSG_81_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_82 0x0292 +-#define mmMP1_SMN_C2PMSG_82_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_83 0x0293 +-#define mmMP1_SMN_C2PMSG_83_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_84 0x0294 +-#define mmMP1_SMN_C2PMSG_84_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_85 0x0295 +-#define mmMP1_SMN_C2PMSG_85_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_86 0x0296 +-#define mmMP1_SMN_C2PMSG_86_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_87 0x0297 +-#define mmMP1_SMN_C2PMSG_87_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_88 0x0298 +-#define mmMP1_SMN_C2PMSG_88_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_89 0x0299 +-#define mmMP1_SMN_C2PMSG_89_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_90 0x029a +-#define mmMP1_SMN_C2PMSG_90_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_91 0x029b +-#define mmMP1_SMN_C2PMSG_91_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_92 0x029c +-#define mmMP1_SMN_C2PMSG_92_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_93 0x029d +-#define mmMP1_SMN_C2PMSG_93_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_94 0x029e +-#define mmMP1_SMN_C2PMSG_94_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_95 0x029f +-#define mmMP1_SMN_C2PMSG_95_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_96 0x02a0 +-#define mmMP1_SMN_C2PMSG_96_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_97 0x02a1 +-#define mmMP1_SMN_C2PMSG_97_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_98 0x02a2 +-#define mmMP1_SMN_C2PMSG_98_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_99 0x02a3 +-#define mmMP1_SMN_C2PMSG_99_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_100 0x02a4 +-#define mmMP1_SMN_C2PMSG_100_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_101 0x02a5 +-#define mmMP1_SMN_C2PMSG_101_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_102 0x02a6 +-#define mmMP1_SMN_C2PMSG_102_BASE_IDX 0 +-#define mmMP1_SMN_C2PMSG_103 0x02a7 +-#define mmMP1_SMN_C2PMSG_103_BASE_IDX 0 +-#define mmMP1_SMN_ACTIVE_FCN_ID 0x02c0 +-#define mmMP1_SMN_ACTIVE_FCN_ID_BASE_IDX 0 +-#define mmMP1_SMN_IH_CREDIT 0x02c1 +-#define mmMP1_SMN_IH_CREDIT_BASE_IDX 0 +-#define mmMP1_SMN_IH_SW_INT 0x02c2 +-#define mmMP1_SMN_IH_SW_INT_BASE_IDX 0 +-#define mmMP1_SMN_IH_SW_INT_CTRL 0x02c3 +-#define mmMP1_SMN_IH_SW_INT_CTRL_BASE_IDX 0 +-#define mmMP1_SMN_FPS_CNT 0x02c4 +-#define mmMP1_SMN_FPS_CNT_BASE_IDX 0 +-#define mmMP1_SMN_EXT_SCRATCH0 0x03c0 +-#define mmMP1_SMN_EXT_SCRATCH0_BASE_IDX 0 +-#define mmMP1_SMN_EXT_SCRATCH1 0x03c1 +-#define mmMP1_SMN_EXT_SCRATCH1_BASE_IDX 0 +-#define mmMP1_SMN_EXT_SCRATCH2 0x03c2 +-#define mmMP1_SMN_EXT_SCRATCH2_BASE_IDX 0 +-#define mmMP1_SMN_EXT_SCRATCH3 0x03c3 +-#define mmMP1_SMN_EXT_SCRATCH3_BASE_IDX 0 +-#define mmMP1_SMN_EXT_SCRATCH4 0x03c4 +-#define mmMP1_SMN_EXT_SCRATCH4_BASE_IDX 0 +-#define mmMP1_SMN_EXT_SCRATCH5 0x03c5 +-#define mmMP1_SMN_EXT_SCRATCH5_BASE_IDX 0 +-#define mmMP1_SMN_EXT_SCRATCH6 0x03c6 +-#define mmMP1_SMN_EXT_SCRATCH6_BASE_IDX 0 +-#define mmMP1_SMN_EXT_SCRATCH7 0x03c7 +-#define mmMP1_SMN_EXT_SCRATCH7_BASE_IDX 0 +-#define mmMP1_SMN_EXT_SCRATCH8 0x03c8 +-#define mmMP1_SMN_EXT_SCRATCH8_BASE_IDX 0 +- +- +-// addressBlock: mp_SmuMp1Pub_CruDec +-// base address: 0x0 +-#define mmMP1_SMN_PUB_CTRL 0x02c5 +-#define mmMP1_SMN_PUB_CTRL_BASE_IDX 0 +- +- +- +-#endif +diff --git a/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_sh_mask.h +deleted file mode 100644 +index ae7b518..0000000 +--- a/drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_sh_mask.h ++++ /dev/null +@@ -1,1463 +0,0 @@ +-/* +- * Copyright (C) 2017 Advanced Micro Devices, Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included +- * in all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +- * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- */ +-#ifndef _mp_9_0_SH_MASK_HEADER +-#define _mp_9_0_SH_MASK_HEADER +- +- +-// addressBlock: mp_SmuMp0_SmnDec +-//MP0_SMN_C2PMSG_32 +-#define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_33 +-#define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_34 +-#define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_35 +-#define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_36 +-#define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_37 +-#define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_38 +-#define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_39 +-#define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_40 +-#define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_41 +-#define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_42 +-#define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_43 +-#define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_44 +-#define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_45 +-#define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_46 +-#define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_47 +-#define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_48 +-#define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_49 +-#define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_50 +-#define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_51 +-#define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_52 +-#define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_53 +-#define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_54 +-#define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_55 +-#define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_56 +-#define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_57 +-#define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_58 +-#define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_59 +-#define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_60 +-#define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_61 +-#define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_62 +-#define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_63 +-#define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_64 +-#define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_65 +-#define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_66 +-#define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_67 +-#define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_68 +-#define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_69 +-#define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_70 +-#define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_71 +-#define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_72 +-#define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_73 +-#define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_74 +-#define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_75 +-#define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_76 +-#define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_77 +-#define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_78 +-#define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_79 +-#define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_80 +-#define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_81 +-#define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_82 +-#define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_83 +-#define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_84 +-#define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_85 +-#define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_86 +-#define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_87 +-#define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_88 +-#define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_89 +-#define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_90 +-#define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_91 +-#define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_92 +-#define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_93 +-#define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_94 +-#define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_95 +-#define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_96 +-#define MP0_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_97 +-#define MP0_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_98 +-#define MP0_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_99 +-#define MP0_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_100 +-#define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_101 +-#define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_102 +-#define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_C2PMSG_103 +-#define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 +-#define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL +-//MP0_SMN_ACTIVE_FCN_ID +-#define MP0_SMN_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +-#define MP0_SMN_ACTIVE_FCN_ID__VF__SHIFT 0x1f +-#define MP0_SMN_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +-#define MP0_SMN_ACTIVE_FCN_ID__VF_MASK 0x80000000L +-//MP0_SMN_IH_CREDIT +-#define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +-#define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 +-#define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +-#define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L +-//MP0_SMN_IH_SW_INT +-#define MP0_SMN_IH_SW_INT__VALID__SHIFT 0x0 +-#define MP0_SMN_IH_SW_INT__ID__SHIFT 0x1 +-#define MP0_SMN_IH_SW_INT__VALID_MASK 0x00000001L +-#define MP0_SMN_IH_SW_INT__ID_MASK 0x000001FEL +-//MP0_SMN_IH_SW_INT_CTRL +-#define MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK__SHIFT 0x0 +-#define MP0_SMN_IH_SW_INT_CTRL__SW_INT_ACK__SHIFT 0x8 +-#define MP0_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK 0x00000001L +-#define MP0_SMN_IH_SW_INT_CTRL__SW_INT_ACK_MASK 0x00000100L +- +- +-// addressBlock: mp_SmuMp1_SmnDec +-//MP1_SMN_ACP2MP_RESP +-#define MP1_SMN_ACP2MP_RESP__CONTENT__SHIFT 0x0 +-#define MP1_SMN_ACP2MP_RESP__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_DC2MP_RESP +-#define MP1_SMN_DC2MP_RESP__CONTENT__SHIFT 0x0 +-#define MP1_SMN_DC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_UVD2MP_RESP +-#define MP1_SMN_UVD2MP_RESP__CONTENT__SHIFT 0x0 +-#define MP1_SMN_UVD2MP_RESP__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_VCE2MP_RESP +-#define MP1_SMN_VCE2MP_RESP__CONTENT__SHIFT 0x0 +-#define MP1_SMN_VCE2MP_RESP__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_RLC2MP_RESP +-#define MP1_SMN_RLC2MP_RESP__CONTENT__SHIFT 0x0 +-#define MP1_SMN_RLC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_32 +-#define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_33 +-#define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_34 +-#define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_35 +-#define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_36 +-#define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_37 +-#define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_38 +-#define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_39 +-#define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_40 +-#define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_41 +-#define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_42 +-#define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_43 +-#define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_44 +-#define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_45 +-#define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_46 +-#define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_47 +-#define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_48 +-#define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_49 +-#define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_50 +-#define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_51 +-#define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_52 +-#define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_53 +-#define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_54 +-#define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_55 +-#define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_56 +-#define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_57 +-#define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_58 +-#define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_59 +-#define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_60 +-#define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_61 +-#define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_62 +-#define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_63 +-#define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_64 +-#define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_65 +-#define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_66 +-#define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_67 +-#define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_68 +-#define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_69 +-#define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_70 +-#define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_71 +-#define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_72 +-#define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_73 +-#define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_74 +-#define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_75 +-#define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_76 +-#define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_77 +-#define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_78 +-#define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_79 +-#define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_80 +-#define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_81 +-#define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_82 +-#define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_83 +-#define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_84 +-#define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_85 +-#define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_86 +-#define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_87 +-#define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_88 +-#define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_89 +-#define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_90 +-#define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_91 +-#define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_92 +-#define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_93 +-#define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_94 +-#define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_95 +-#define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_96 +-#define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_97 +-#define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_98 +-#define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_99 +-#define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_100 +-#define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_101 +-#define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_102 +-#define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_C2PMSG_103 +-#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 +-#define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL +-//MP1_SMN_ACTIVE_FCN_ID +-#define MP1_SMN_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +-#define MP1_SMN_ACTIVE_FCN_ID__VF__SHIFT 0x1f +-#define MP1_SMN_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +-#define MP1_SMN_ACTIVE_FCN_ID__VF_MASK 0x80000000L +-//MP1_SMN_IH_CREDIT +-#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +-#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 +-#define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +-#define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L +-//MP1_SMN_IH_SW_INT +-#define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x0 +-#define MP1_SMN_IH_SW_INT__ID__SHIFT 0x1 +-#define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000001L +-#define MP1_SMN_IH_SW_INT__ID_MASK 0x000001FEL +-//MP1_SMN_IH_SW_INT_CTRL +-#define MP1_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK__SHIFT 0x0 +-#define MP1_SMN_IH_SW_INT_CTRL__SW_INT_ACK__SHIFT 0x8 +-#define MP1_SMN_IH_SW_INT_CTRL__SW_TRIG_MASK_MASK 0x00000001L +-#define MP1_SMN_IH_SW_INT_CTRL__SW_INT_ACK_MASK 0x00000100L +-//MP1_SMN_FPS_CNT +-#define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0 +-#define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL +-//MP1_SMN_EXT_SCRATCH0 +-#define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0 +-#define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL +-//MP1_SMN_EXT_SCRATCH1 +-#define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0 +-#define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL +-//MP1_SMN_EXT_SCRATCH2 +-#define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0 +-#define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL +-//MP1_SMN_EXT_SCRATCH3 +-#define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0 +-#define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL +-//MP1_SMN_EXT_SCRATCH4 +-#define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0 +-#define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL +-//MP1_SMN_EXT_SCRATCH5 +-#define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0 +-#define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL +-//MP1_SMN_EXT_SCRATCH6 +-#define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0 +-#define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL +-//MP1_SMN_EXT_SCRATCH7 +-#define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0 +-#define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL +-//MP1_SMN_EXT_SCRATCH8 +-#define MP1_SMN_EXT_SCRATCH8__DATA__SHIFT 0x0 +-#define MP1_SMN_EXT_SCRATCH8__DATA_MASK 0xFFFFFFFFL +- +- +- +- +-// addressBlock: mp_SmuMp0Pub_CruDec +-//MP0_SOC_INFO +-#define MP0_SOC_INFO__SOC_DIE_ID__SHIFT 0x0 +-#define MP0_SOC_INFO__SOC_PKG_TYPE__SHIFT 0x2 +-#define MP0_SOC_INFO__SOC_DIE_ID_MASK 0x00000003L +-#define MP0_SOC_INFO__SOC_PKG_TYPE_MASK 0x0000001CL +-//MP0_PUB_SCRATCH0 +-#define MP0_PUB_SCRATCH0__DATA__SHIFT 0x0 +-#define MP0_PUB_SCRATCH0__DATA_MASK 0xFFFFFFFFL +-//MP0_PUB_SCRATCH1 +-#define MP0_PUB_SCRATCH1__DATA__SHIFT 0x0 +-#define MP0_PUB_SCRATCH1__DATA_MASK 0xFFFFFFFFL +-//MP0_PUB_SCRATCH2 +-#define MP0_PUB_SCRATCH2__DATA__SHIFT 0x0 +-#define MP0_PUB_SCRATCH2__DATA_MASK 0xFFFFFFFFL +-//MP0_PUB_SCRATCH3 +-#define MP0_PUB_SCRATCH3__DATA__SHIFT 0x0 +-#define MP0_PUB_SCRATCH3__DATA_MASK 0xFFFFFFFFL +-//MP0_FW_INTF +-#define MP0_FW_INTF__SS_SECURE__SHIFT 0x13 +-#define MP0_FW_INTF__SS_SECURE_MASK 0x00080000L +-//MP0_C2PMSG_0 +-#define MP0_C2PMSG_0__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_1 +-#define MP0_C2PMSG_1__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_2 +-#define MP0_C2PMSG_2__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_3 +-#define MP0_C2PMSG_3__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_4 +-#define MP0_C2PMSG_4__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_5 +-#define MP0_C2PMSG_5__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_6 +-#define MP0_C2PMSG_6__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_7 +-#define MP0_C2PMSG_7__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_8 +-#define MP0_C2PMSG_8__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_9 +-#define MP0_C2PMSG_9__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_10 +-#define MP0_C2PMSG_10__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_11 +-#define MP0_C2PMSG_11__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_12 +-#define MP0_C2PMSG_12__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_13 +-#define MP0_C2PMSG_13__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_14 +-#define MP0_C2PMSG_14__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_15 +-#define MP0_C2PMSG_15__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_16 +-#define MP0_C2PMSG_16__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_17 +-#define MP0_C2PMSG_17__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_18 +-#define MP0_C2PMSG_18__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_19 +-#define MP0_C2PMSG_19__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_20 +-#define MP0_C2PMSG_20__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_21 +-#define MP0_C2PMSG_21__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_22 +-#define MP0_C2PMSG_22__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_23 +-#define MP0_C2PMSG_23__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_24 +-#define MP0_C2PMSG_24__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_25 +-#define MP0_C2PMSG_25__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_26 +-#define MP0_C2PMSG_26__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_27 +-#define MP0_C2PMSG_27__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_28 +-#define MP0_C2PMSG_28__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_29 +-#define MP0_C2PMSG_29__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_30 +-#define MP0_C2PMSG_30__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_31 +-#define MP0_C2PMSG_31__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL +-//MP0_P2CMSG_0 +-#define MP0_P2CMSG_0__CONTENT__SHIFT 0x0 +-#define MP0_P2CMSG_0__CONTENT_MASK 0xFFFFFFFFL +-//MP0_P2CMSG_1 +-#define MP0_P2CMSG_1__CONTENT__SHIFT 0x0 +-#define MP0_P2CMSG_1__CONTENT_MASK 0xFFFFFFFFL +-//MP0_P2CMSG_2 +-#define MP0_P2CMSG_2__CONTENT__SHIFT 0x0 +-#define MP0_P2CMSG_2__CONTENT_MASK 0xFFFFFFFFL +-//MP0_P2CMSG_3 +-#define MP0_P2CMSG_3__CONTENT__SHIFT 0x0 +-#define MP0_P2CMSG_3__CONTENT_MASK 0xFFFFFFFFL +-//MP0_P2CMSG_INTEN +-#define MP0_P2CMSG_INTEN__INTEN__SHIFT 0x0 +-#define MP0_P2CMSG_INTEN__INTEN_MASK 0x0000000FL +-//MP0_P2CMSG_INTSTS +-#define MP0_P2CMSG_INTSTS__INTSTS0__SHIFT 0x0 +-#define MP0_P2CMSG_INTSTS__INTSTS1__SHIFT 0x1 +-#define MP0_P2CMSG_INTSTS__INTSTS2__SHIFT 0x2 +-#define MP0_P2CMSG_INTSTS__INTSTS3__SHIFT 0x3 +-#define MP0_P2CMSG_INTSTS__INTSTS0_MASK 0x00000001L +-#define MP0_P2CMSG_INTSTS__INTSTS1_MASK 0x00000002L +-#define MP0_P2CMSG_INTSTS__INTSTS2_MASK 0x00000004L +-#define MP0_P2CMSG_INTSTS__INTSTS3_MASK 0x00000008L +-//MP0_C2PMSG_ATTR_0 +-#define MP0_C2PMSG_ATTR_0__MSG_ATTR__SHIFT 0x0 +-#define MP0_C2PMSG_ATTR_0__MSG_ATTR_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_ATTR_1 +-#define MP0_C2PMSG_ATTR_1__MSG_ATTR__SHIFT 0x0 +-#define MP0_C2PMSG_ATTR_1__MSG_ATTR_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_ATTR_2 +-#define MP0_C2PMSG_ATTR_2__MSG_ATTR__SHIFT 0x0 +-#define MP0_C2PMSG_ATTR_2__MSG_ATTR_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_ATTR_3 +-#define MP0_C2PMSG_ATTR_3__MSG_ATTR__SHIFT 0x0 +-#define MP0_C2PMSG_ATTR_3__MSG_ATTR_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_ATTR_4 +-#define MP0_C2PMSG_ATTR_4__MSG_ATTR__SHIFT 0x0 +-#define MP0_C2PMSG_ATTR_4__MSG_ATTR_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_ATTR_5 +-#define MP0_C2PMSG_ATTR_5__MSG_ATTR__SHIFT 0x0 +-#define MP0_C2PMSG_ATTR_5__MSG_ATTR_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_ATTR_6 +-#define MP0_C2PMSG_ATTR_6__MSG_ATTR__SHIFT 0x0 +-#define MP0_C2PMSG_ATTR_6__MSG_ATTR_MASK 0x0000FFFFL +-//MP0_P2CMSG_ATTR +-#define MP0_P2CMSG_ATTR__MSG_ATTR__SHIFT 0x0 +-#define MP0_P2CMSG_ATTR__MSG_ATTR_MASK 0x000000FFL +-//MP0_P2SMSG_0 +-#define MP0_P2SMSG_0__CONTENT__SHIFT 0x0 +-#define MP0_P2SMSG_0__CONTENT_MASK 0xFFFFFFFFL +-//MP0_P2SMSG_1 +-#define MP0_P2SMSG_1__CONTENT__SHIFT 0x0 +-#define MP0_P2SMSG_1__CONTENT_MASK 0xFFFFFFFFL +-//MP0_P2SMSG_2 +-#define MP0_P2SMSG_2__CONTENT__SHIFT 0x0 +-#define MP0_P2SMSG_2__CONTENT_MASK 0xFFFFFFFFL +-//MP0_P2SMSG_3 +-#define MP0_P2SMSG_3__CONTENT__SHIFT 0x0 +-#define MP0_P2SMSG_3__CONTENT_MASK 0xFFFFFFFFL +-//MP0_P2SMSG_ATTR +-#define MP0_P2SMSG_ATTR__MSG_ATTR__SHIFT 0x0 +-#define MP0_P2SMSG_ATTR__MSG_ATTR_MASK 0x000000FFL +-//MP0_S2PMSG_ATTR +-#define MP0_S2PMSG_ATTR__MSG_ATTR__SHIFT 0x0 +-#define MP0_S2PMSG_ATTR__MSG_ATTR_MASK 0x00000003L +-//MP0_P2SMSG_INTSTS +-#define MP0_P2SMSG_INTSTS__INTSTS0__SHIFT 0x0 +-#define MP0_P2SMSG_INTSTS__INTSTS1__SHIFT 0x1 +-#define MP0_P2SMSG_INTSTS__INTSTS2__SHIFT 0x2 +-#define MP0_P2SMSG_INTSTS__INTSTS3__SHIFT 0x3 +-#define MP0_P2SMSG_INTSTS__INTSTS0_MASK 0x00000001L +-#define MP0_P2SMSG_INTSTS__INTSTS1_MASK 0x00000002L +-#define MP0_P2SMSG_INTSTS__INTSTS2_MASK 0x00000004L +-#define MP0_P2SMSG_INTSTS__INTSTS3_MASK 0x00000008L +-//MP0_S2PMSG_0 +-#define MP0_S2PMSG_0__CONTENT__SHIFT 0x0 +-#define MP0_S2PMSG_0__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_32 +-#define MP0_C2PMSG_32__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_33 +-#define MP0_C2PMSG_33__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_34 +-#define MP0_C2PMSG_34__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_35 +-#define MP0_C2PMSG_35__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_36 +-#define MP0_C2PMSG_36__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_37 +-#define MP0_C2PMSG_37__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_38 +-#define MP0_C2PMSG_38__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_39 +-#define MP0_C2PMSG_39__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_40 +-#define MP0_C2PMSG_40__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_41 +-#define MP0_C2PMSG_41__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_42 +-#define MP0_C2PMSG_42__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_43 +-#define MP0_C2PMSG_43__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_44 +-#define MP0_C2PMSG_44__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_45 +-#define MP0_C2PMSG_45__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_46 +-#define MP0_C2PMSG_46__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_47 +-#define MP0_C2PMSG_47__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_48 +-#define MP0_C2PMSG_48__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_49 +-#define MP0_C2PMSG_49__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_50 +-#define MP0_C2PMSG_50__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_51 +-#define MP0_C2PMSG_51__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_52 +-#define MP0_C2PMSG_52__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_53 +-#define MP0_C2PMSG_53__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_54 +-#define MP0_C2PMSG_54__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_55 +-#define MP0_C2PMSG_55__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_56 +-#define MP0_C2PMSG_56__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_57 +-#define MP0_C2PMSG_57__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_58 +-#define MP0_C2PMSG_58__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_59 +-#define MP0_C2PMSG_59__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_60 +-#define MP0_C2PMSG_60__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_61 +-#define MP0_C2PMSG_61__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_62 +-#define MP0_C2PMSG_62__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_63 +-#define MP0_C2PMSG_63__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_64 +-#define MP0_C2PMSG_64__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_65 +-#define MP0_C2PMSG_65__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_66 +-#define MP0_C2PMSG_66__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_67 +-#define MP0_C2PMSG_67__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_68 +-#define MP0_C2PMSG_68__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_69 +-#define MP0_C2PMSG_69__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_70 +-#define MP0_C2PMSG_70__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_71 +-#define MP0_C2PMSG_71__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_72 +-#define MP0_C2PMSG_72__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_73 +-#define MP0_C2PMSG_73__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_74 +-#define MP0_C2PMSG_74__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_75 +-#define MP0_C2PMSG_75__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_76 +-#define MP0_C2PMSG_76__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_77 +-#define MP0_C2PMSG_77__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_78 +-#define MP0_C2PMSG_78__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_79 +-#define MP0_C2PMSG_79__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_80 +-#define MP0_C2PMSG_80__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_81 +-#define MP0_C2PMSG_81__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_82 +-#define MP0_C2PMSG_82__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_83 +-#define MP0_C2PMSG_83__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_84 +-#define MP0_C2PMSG_84__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_85 +-#define MP0_C2PMSG_85__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_86 +-#define MP0_C2PMSG_86__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_87 +-#define MP0_C2PMSG_87__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_88 +-#define MP0_C2PMSG_88__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_89 +-#define MP0_C2PMSG_89__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_90 +-#define MP0_C2PMSG_90__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_91 +-#define MP0_C2PMSG_91__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_92 +-#define MP0_C2PMSG_92__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_93 +-#define MP0_C2PMSG_93__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_94 +-#define MP0_C2PMSG_94__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_95 +-#define MP0_C2PMSG_95__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_96 +-#define MP0_C2PMSG_96__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_97 +-#define MP0_C2PMSG_97__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_98 +-#define MP0_C2PMSG_98__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_99 +-#define MP0_C2PMSG_99__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_100 +-#define MP0_C2PMSG_100__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_101 +-#define MP0_C2PMSG_101__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_102 +-#define MP0_C2PMSG_102__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL +-//MP0_C2PMSG_103 +-#define MP0_C2PMSG_103__CONTENT__SHIFT 0x0 +-#define MP0_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL +-//MP0_ACTIVE_FCN_ID +-#define MP0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +-#define MP0_ACTIVE_FCN_ID__VF__SHIFT 0x1f +-#define MP0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +-#define MP0_ACTIVE_FCN_ID__VF_MASK 0x80000000L +-//MP0_IH_CREDIT +-#define MP0_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +-#define MP0_IH_CREDIT__CLIENT_ID__SHIFT 0x10 +-#define MP0_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +-#define MP0_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L +-//MP0_IH_SW_INT +-#define MP0_IH_SW_INT__ID__SHIFT 0x0 +-#define MP0_IH_SW_INT__VALID__SHIFT 0x8 +-#define MP0_IH_SW_INT__ID_MASK 0x000000FFL +-#define MP0_IH_SW_INT__VALID_MASK 0x00000100L +-//MP0_IH_SW_INT_CTRL +-#define MP0_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 +-#define MP0_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 +-#define MP0_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L +-#define MP0_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L +- +- +-//CGTT_DRM_CLK_CTRL0 +-#define CGTT_DRM_CLK_CTRL0__ON_DELAY__SHIFT 0x0 +-#define CGTT_DRM_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 +-#define CGTT_DRM_CLK_CTRL0__DIV_ID__SHIFT 0xc +-#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_0__SHIFT 0x15 +-#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_REG__SHIFT 0x16 +-#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18 +-#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19 +-#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a +-#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b +-#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c +-#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d +-#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e +-#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f +-#define CGTT_DRM_CLK_CTRL0__ON_DELAY_MASK 0x0000000FL +-#define CGTT_DRM_CLK_CTRL0__OFF_HYSTERESIS_MASK 0x00000FF0L +-#define CGTT_DRM_CLK_CTRL0__DIV_ID_MASK 0x00007000L +-#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_0_MASK 0x00200000L +-#define CGTT_DRM_CLK_CTRL0__RAMP_DIS_CLK_REG_MASK 0x00400000L +-#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x01000000L +-#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x02000000L +-#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x04000000L +-#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x08000000L +-#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000L +-#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000L +-#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000L +-#define CGTT_DRM_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000L +-//DRM_LIGHT_SLEEP_CTRL +-#define DRM_LIGHT_SLEEP_CTRL__MEM_LIGHT_SLEEP_EN__SHIFT 0x0 +-#define DRM_LIGHT_SLEEP_CTRL__MEM_LIGHT_SLEEP_EN_MASK 0x00000001L +- +- +-// addressBlock: mp_SmuMp1Pub_CruDec +-//MP1_SMN_PUB_CTRL +-#define MP1_SMN_PUB_CTRL__RESET__SHIFT 0x0 +-#define MP1_SMN_PUB_CTRL__RESET_MASK 0x00000001L +-//MP1_FIRMWARE_FLAGS +-#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 +-#define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 +-#define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L +-#define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL +-//MP1_PUB_SCRATCH0 +-#define MP1_PUB_SCRATCH0__DATA__SHIFT 0x0 +-#define MP1_PUB_SCRATCH0__DATA_MASK 0xFFFFFFFFL +-//MP1_PUB_SCRATCH1 +-#define MP1_PUB_SCRATCH1__DATA__SHIFT 0x0 +-#define MP1_PUB_SCRATCH1__DATA_MASK 0xFFFFFFFFL +-//MP1_PUB_SCRATCH2 +-#define MP1_PUB_SCRATCH2__DATA__SHIFT 0x0 +-#define MP1_PUB_SCRATCH2__DATA_MASK 0xFFFFFFFFL +-//MP1_PUB_SCRATCH3 +-#define MP1_PUB_SCRATCH3__DATA__SHIFT 0x0 +-#define MP1_PUB_SCRATCH3__DATA_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_0 +-#define MP1_C2PMSG_0__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_1 +-#define MP1_C2PMSG_1__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_2 +-#define MP1_C2PMSG_2__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_3 +-#define MP1_C2PMSG_3__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_4 +-#define MP1_C2PMSG_4__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_5 +-#define MP1_C2PMSG_5__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_6 +-#define MP1_C2PMSG_6__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_7 +-#define MP1_C2PMSG_7__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_8 +-#define MP1_C2PMSG_8__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_9 +-#define MP1_C2PMSG_9__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_10 +-#define MP1_C2PMSG_10__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_11 +-#define MP1_C2PMSG_11__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_12 +-#define MP1_C2PMSG_12__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_13 +-#define MP1_C2PMSG_13__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_14 +-#define MP1_C2PMSG_14__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_15 +-#define MP1_C2PMSG_15__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_16 +-#define MP1_C2PMSG_16__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_17 +-#define MP1_C2PMSG_17__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_18 +-#define MP1_C2PMSG_18__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_19 +-#define MP1_C2PMSG_19__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_20 +-#define MP1_C2PMSG_20__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_21 +-#define MP1_C2PMSG_21__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_22 +-#define MP1_C2PMSG_22__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_23 +-#define MP1_C2PMSG_23__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_24 +-#define MP1_C2PMSG_24__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_25 +-#define MP1_C2PMSG_25__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_26 +-#define MP1_C2PMSG_26__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_27 +-#define MP1_C2PMSG_27__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_28 +-#define MP1_C2PMSG_28__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_29 +-#define MP1_C2PMSG_29__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_30 +-#define MP1_C2PMSG_30__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_31 +-#define MP1_C2PMSG_31__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL +-//MP1_P2CMSG_0 +-#define MP1_P2CMSG_0__CONTENT__SHIFT 0x0 +-#define MP1_P2CMSG_0__CONTENT_MASK 0xFFFFFFFFL +-//MP1_P2CMSG_1 +-#define MP1_P2CMSG_1__CONTENT__SHIFT 0x0 +-#define MP1_P2CMSG_1__CONTENT_MASK 0xFFFFFFFFL +-//MP1_P2CMSG_2 +-#define MP1_P2CMSG_2__CONTENT__SHIFT 0x0 +-#define MP1_P2CMSG_2__CONTENT_MASK 0xFFFFFFFFL +-//MP1_P2CMSG_3 +-#define MP1_P2CMSG_3__CONTENT__SHIFT 0x0 +-#define MP1_P2CMSG_3__CONTENT_MASK 0xFFFFFFFFL +-//MP1_P2CMSG_INTEN +-#define MP1_P2CMSG_INTEN__INTEN__SHIFT 0x0 +-#define MP1_P2CMSG_INTEN__INTEN_MASK 0x0000000FL +-//MP1_P2CMSG_INTSTS +-#define MP1_P2CMSG_INTSTS__INTSTS0__SHIFT 0x0 +-#define MP1_P2CMSG_INTSTS__INTSTS1__SHIFT 0x1 +-#define MP1_P2CMSG_INTSTS__INTSTS2__SHIFT 0x2 +-#define MP1_P2CMSG_INTSTS__INTSTS3__SHIFT 0x3 +-#define MP1_P2CMSG_INTSTS__INTSTS0_MASK 0x00000001L +-#define MP1_P2CMSG_INTSTS__INTSTS1_MASK 0x00000002L +-#define MP1_P2CMSG_INTSTS__INTSTS2_MASK 0x00000004L +-#define MP1_P2CMSG_INTSTS__INTSTS3_MASK 0x00000008L +-//MP1_P2SMSG_0 +-#define MP1_P2SMSG_0__CONTENT__SHIFT 0x0 +-#define MP1_P2SMSG_0__CONTENT_MASK 0xFFFFFFFFL +-//MP1_P2SMSG_1 +-#define MP1_P2SMSG_1__CONTENT__SHIFT 0x0 +-#define MP1_P2SMSG_1__CONTENT_MASK 0xFFFFFFFFL +-//MP1_P2SMSG_2 +-#define MP1_P2SMSG_2__CONTENT__SHIFT 0x0 +-#define MP1_P2SMSG_2__CONTENT_MASK 0xFFFFFFFFL +-//MP1_P2SMSG_3 +-#define MP1_P2SMSG_3__CONTENT__SHIFT 0x0 +-#define MP1_P2SMSG_3__CONTENT_MASK 0xFFFFFFFFL +-//MP1_P2SMSG_INTSTS +-#define MP1_P2SMSG_INTSTS__INTSTS0__SHIFT 0x0 +-#define MP1_P2SMSG_INTSTS__INTSTS1__SHIFT 0x1 +-#define MP1_P2SMSG_INTSTS__INTSTS2__SHIFT 0x2 +-#define MP1_P2SMSG_INTSTS__INTSTS3__SHIFT 0x3 +-#define MP1_P2SMSG_INTSTS__INTSTS0_MASK 0x00000001L +-#define MP1_P2SMSG_INTSTS__INTSTS1_MASK 0x00000002L +-#define MP1_P2SMSG_INTSTS__INTSTS2_MASK 0x00000004L +-#define MP1_P2SMSG_INTSTS__INTSTS3_MASK 0x00000008L +-//MP1_S2PMSG_0 +-#define MP1_S2PMSG_0__CONTENT__SHIFT 0x0 +-#define MP1_S2PMSG_0__CONTENT_MASK 0xFFFFFFFFL +-//MP1_ACP2MP_RESP +-#define MP1_ACP2MP_RESP__CONTENT__SHIFT 0x0 +-#define MP1_ACP2MP_RESP__CONTENT_MASK 0xFFFFFFFFL +-//MP1_DC2MP_RESP +-#define MP1_DC2MP_RESP__CONTENT__SHIFT 0x0 +-#define MP1_DC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL +-//MP1_UVD2MP_RESP +-#define MP1_UVD2MP_RESP__CONTENT__SHIFT 0x0 +-#define MP1_UVD2MP_RESP__CONTENT_MASK 0xFFFFFFFFL +-//MP1_VCE2MP_RESP +-#define MP1_VCE2MP_RESP__CONTENT__SHIFT 0x0 +-#define MP1_VCE2MP_RESP__CONTENT_MASK 0xFFFFFFFFL +-//MP1_RLC2MP_RESP +-#define MP1_RLC2MP_RESP__CONTENT__SHIFT 0x0 +-#define MP1_RLC2MP_RESP__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_32 +-#define MP1_C2PMSG_32__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_33 +-#define MP1_C2PMSG_33__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_34 +-#define MP1_C2PMSG_34__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_35 +-#define MP1_C2PMSG_35__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_36 +-#define MP1_C2PMSG_36__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_37 +-#define MP1_C2PMSG_37__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_38 +-#define MP1_C2PMSG_38__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_39 +-#define MP1_C2PMSG_39__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_40 +-#define MP1_C2PMSG_40__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_41 +-#define MP1_C2PMSG_41__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_42 +-#define MP1_C2PMSG_42__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_43 +-#define MP1_C2PMSG_43__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_44 +-#define MP1_C2PMSG_44__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_45 +-#define MP1_C2PMSG_45__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_46 +-#define MP1_C2PMSG_46__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_47 +-#define MP1_C2PMSG_47__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_48 +-#define MP1_C2PMSG_48__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_49 +-#define MP1_C2PMSG_49__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_50 +-#define MP1_C2PMSG_50__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_51 +-#define MP1_C2PMSG_51__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_52 +-#define MP1_C2PMSG_52__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_53 +-#define MP1_C2PMSG_53__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_54 +-#define MP1_C2PMSG_54__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_55 +-#define MP1_C2PMSG_55__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_56 +-#define MP1_C2PMSG_56__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_57 +-#define MP1_C2PMSG_57__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_58 +-#define MP1_C2PMSG_58__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_59 +-#define MP1_C2PMSG_59__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_60 +-#define MP1_C2PMSG_60__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_61 +-#define MP1_C2PMSG_61__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_62 +-#define MP1_C2PMSG_62__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_63 +-#define MP1_C2PMSG_63__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_64 +-#define MP1_C2PMSG_64__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_65 +-#define MP1_C2PMSG_65__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_66 +-#define MP1_C2PMSG_66__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_67 +-#define MP1_C2PMSG_67__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_68 +-#define MP1_C2PMSG_68__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_69 +-#define MP1_C2PMSG_69__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_70 +-#define MP1_C2PMSG_70__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_71 +-#define MP1_C2PMSG_71__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_72 +-#define MP1_C2PMSG_72__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_73 +-#define MP1_C2PMSG_73__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_74 +-#define MP1_C2PMSG_74__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_75 +-#define MP1_C2PMSG_75__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_76 +-#define MP1_C2PMSG_76__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_77 +-#define MP1_C2PMSG_77__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_78 +-#define MP1_C2PMSG_78__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_79 +-#define MP1_C2PMSG_79__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_80 +-#define MP1_C2PMSG_80__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_81 +-#define MP1_C2PMSG_81__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_82 +-#define MP1_C2PMSG_82__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_83 +-#define MP1_C2PMSG_83__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_84 +-#define MP1_C2PMSG_84__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_85 +-#define MP1_C2PMSG_85__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_86 +-#define MP1_C2PMSG_86__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_87 +-#define MP1_C2PMSG_87__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_88 +-#define MP1_C2PMSG_88__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_89 +-#define MP1_C2PMSG_89__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_90 +-#define MP1_C2PMSG_90__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_91 +-#define MP1_C2PMSG_91__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_92 +-#define MP1_C2PMSG_92__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_93 +-#define MP1_C2PMSG_93__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_94 +-#define MP1_C2PMSG_94__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_95 +-#define MP1_C2PMSG_95__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_96 +-#define MP1_C2PMSG_96__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_97 +-#define MP1_C2PMSG_97__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_98 +-#define MP1_C2PMSG_98__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_99 +-#define MP1_C2PMSG_99__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_100 +-#define MP1_C2PMSG_100__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_101 +-#define MP1_C2PMSG_101__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_102 +-#define MP1_C2PMSG_102__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL +-//MP1_C2PMSG_103 +-#define MP1_C2PMSG_103__CONTENT__SHIFT 0x0 +-#define MP1_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL +-//MP1_ACTIVE_FCN_ID +-#define MP1_ACTIVE_FCN_ID__VFID__SHIFT 0x0 +-#define MP1_ACTIVE_FCN_ID__VF__SHIFT 0x1f +-#define MP1_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL +-#define MP1_ACTIVE_FCN_ID__VF_MASK 0x80000000L +-//MP1_IH_CREDIT +-#define MP1_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 +-#define MP1_IH_CREDIT__CLIENT_ID__SHIFT 0x10 +-#define MP1_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L +-#define MP1_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L +-//MP1_IH_SW_INT +-#define MP1_IH_SW_INT__ID__SHIFT 0x0 +-#define MP1_IH_SW_INT__VALID__SHIFT 0x8 +-#define MP1_IH_SW_INT__ID_MASK 0x000000FFL +-#define MP1_IH_SW_INT__VALID_MASK 0x00000100L +-//MP1_IH_SW_INT_CTRL +-#define MP1_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 +-#define MP1_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 +-#define MP1_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L +-#define MP1_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L +-//MP1_FPS_CNT +-#define MP1_FPS_CNT__COUNT__SHIFT 0x0 +-#define MP1_FPS_CNT__COUNT_MASK 0xFFFFFFFFL +-//MP1_PUB_CTRL +-#define MP1_PUB_CTRL__RESET__SHIFT 0x0 +-#define MP1_PUB_CTRL__RESET_MASK 0x00000001L +-//MP1_EXT_SCRATCH0 +-#define MP1_EXT_SCRATCH0__DATA__SHIFT 0x0 +-#define MP1_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL +-//MP1_EXT_SCRATCH1 +-#define MP1_EXT_SCRATCH1__DATA__SHIFT 0x0 +-#define MP1_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL +-//MP1_EXT_SCRATCH2 +-#define MP1_EXT_SCRATCH2__DATA__SHIFT 0x0 +-#define MP1_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL +-//MP1_EXT_SCRATCH3 +-#define MP1_EXT_SCRATCH3__DATA__SHIFT 0x0 +-#define MP1_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL +-//MP1_EXT_SCRATCH4 +-#define MP1_EXT_SCRATCH4__DATA__SHIFT 0x0 +-#define MP1_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL +-//MP1_EXT_SCRATCH5 +-#define MP1_EXT_SCRATCH5__DATA__SHIFT 0x0 +-#define MP1_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL +-//MP1_EXT_SCRATCH6 +-#define MP1_EXT_SCRATCH6__DATA__SHIFT 0x0 +-#define MP1_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL +-//MP1_EXT_SCRATCH7 +-#define MP1_EXT_SCRATCH7__DATA__SHIFT 0x0 +-#define MP1_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL +- +- +-#endif +diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h +index 8c55eaa..2573f95 100644 +--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h ++++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h +@@ -28,9 +28,8 @@ + #include "asic_reg/vega10/THM/thm_9_0_offset.h" + #include "asic_reg/vega10/THM/thm_9_0_sh_mask.h" + +-#include "asic_reg/vega10/MP/mp_9_0_default.h" +-#include "asic_reg/vega10/MP/mp_9_0_offset.h" +-#include "asic_reg/vega10/MP/mp_9_0_sh_mask.h" ++#include "asic_reg/mp/mp_9_0_offset.h" ++#include "asic_reg/mp/mp_9_0_sh_mask.h" + + #include "asic_reg/vega10/GC/gc_9_0_default.h" + #include "asic_reg/vega10/GC/gc_9_0_offset.h" +-- +2.7.4 + |