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Diffstat (limited to 'meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2229-drm-amd-powerplay-Followup-fixes-to-mc_reg_address.patch')
-rw-r--r--meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2229-drm-amd-powerplay-Followup-fixes-to-mc_reg_address.patch167
1 files changed, 167 insertions, 0 deletions
diff --git a/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2229-drm-amd-powerplay-Followup-fixes-to-mc_reg_address.patch b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2229-drm-amd-powerplay-Followup-fixes-to-mc_reg_address.patch
new file mode 100644
index 00000000..6c14d55c
--- /dev/null
+++ b/meta-amd-bsp/recipes-kernel/linux/linux-yocto-4.14.71/2229-drm-amd-powerplay-Followup-fixes-to-mc_reg_address.patch
@@ -0,0 +1,167 @@
+From fe961d8a38bbf839b7e6990cb115ae63cb987bc1 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ernst=20Sj=C3=B6strand?= <ernstp@gmail.com>
+Date: Sun, 19 Nov 2017 18:52:46 +0100
+Subject: [PATCH 2229/4131] drm/amd/powerplay: Followup fixes to mc_reg_address
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This is a followup to:
+drm/amd/powerplay: Fix buffer overflows with mc_reg_address
+
+Rework *_set_mc_special_registers for the other architectures to
+use the same logic as the first patch. This allows the last entry
+of the array to be filled without an error message for example.
+This doesn't fix any known problems, perhaps avoided by luck.
+
+Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
+Signed-off-by: Ernst Sjöstrand <ernstp@gmail.com>
+Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
+---
+ drivers/gpu/drm/amd/amdgpu/si_dpm.c | 10 +++-------
+ drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c | 12 ++++--------
+ drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c | 12 ++++--------
+ 3 files changed, 11 insertions(+), 23 deletions(-)
+
+diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+index b8256566..b1a3ca5 100644
+--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
++++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+@@ -5829,9 +5829,9 @@ static int si_set_mc_special_registers(struct amdgpu_device *adev,
+ ((temp_reg & 0xffff0000)) |
+ ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
+ j++;
++
+ if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
+ return -EINVAL;
+-
+ temp_reg = RREG32(MC_PMG_CMD_MRS);
+ table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS;
+ table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP;
+@@ -5843,18 +5843,16 @@ static int si_set_mc_special_registers(struct amdgpu_device *adev,
+ table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
+ }
+ j++;
+- if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
+- return -EINVAL;
+
+ if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
++ if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
++ return -EINVAL;
+ table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD;
+ table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD;
+ for (k = 0; k < table->num_entries; k++)
+ table->mc_reg_table_entry[k].mc_data[j] =
+ (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
+ j++;
+- if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
+- return -EINVAL;
+ }
+ break;
+ case MC_SEQ_RESERVE_M:
+@@ -5866,8 +5864,6 @@ static int si_set_mc_special_registers(struct amdgpu_device *adev,
+ (temp_reg & 0xffff0000) |
+ (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
+ j++;
+- if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
+- return -EINVAL;
+ break;
+ default:
+ break;
+diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
+index 4d672cd..4c30daa 100644
+--- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
++++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
+@@ -2602,9 +2602,9 @@ static int ci_set_mc_special_registers(struct pp_hwmgr *hwmgr,
+ ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
+ }
+ j++;
++
+ PP_ASSERT_WITH_CODE((j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
+ "Invalid VramInfo table.", return -EINVAL);
+-
+ temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
+ table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
+ table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
+@@ -2617,10 +2617,10 @@ static int ci_set_mc_special_registers(struct pp_hwmgr *hwmgr,
+ table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
+ }
+ j++;
+- PP_ASSERT_WITH_CODE((j <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
+- "Invalid VramInfo table.", return -EINVAL);
+
+- if (!data->is_memory_gddr5 && j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE) {
++ if (!data->is_memory_gddr5) {
++ PP_ASSERT_WITH_CODE((j < SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
++ "Invalid VramInfo table.", return -EINVAL);
+ table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
+ table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
+ for (k = 0; k < table->num_entries; k++) {
+@@ -2628,8 +2628,6 @@ static int ci_set_mc_special_registers(struct pp_hwmgr *hwmgr,
+ (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
+ }
+ j++;
+- PP_ASSERT_WITH_CODE((j <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
+- "Invalid VramInfo table.", return -EINVAL);
+ }
+
+ break;
+@@ -2644,8 +2642,6 @@ static int ci_set_mc_special_registers(struct pp_hwmgr *hwmgr,
+ (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
+ }
+ j++;
+- PP_ASSERT_WITH_CODE((j <= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE),
+- "Invalid VramInfo table.", return -EINVAL);
+ break;
+
+ default:
+diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
+index 3412882..a1a1d73 100644
+--- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
++++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
+@@ -2552,9 +2552,9 @@ static int iceland_set_mc_special_registers(struct pp_hwmgr *hwmgr,
+ ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
+ }
+ j++;
++
+ PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
+ "Invalid VramInfo table.", return -EINVAL);
+-
+ temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
+ table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
+ table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
+@@ -2568,10 +2568,10 @@ static int iceland_set_mc_special_registers(struct pp_hwmgr *hwmgr,
+ }
+ }
+ j++;
+- PP_ASSERT_WITH_CODE((j <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
+- "Invalid VramInfo table.", return -EINVAL);
+
+- if (!data->is_memory_gddr5 && j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE) {
++ if (!data->is_memory_gddr5) {
++ PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
++ "Invalid VramInfo table.", return -EINVAL);
+ table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
+ table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
+ for (k = 0; k < table->num_entries; k++) {
+@@ -2579,8 +2579,6 @@ static int iceland_set_mc_special_registers(struct pp_hwmgr *hwmgr,
+ (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
+ }
+ j++;
+- PP_ASSERT_WITH_CODE((j <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
+- "Invalid VramInfo table.", return -EINVAL);
+ }
+
+ break;
+@@ -2595,8 +2593,6 @@ static int iceland_set_mc_special_registers(struct pp_hwmgr *hwmgr,
+ (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
+ }
+ j++;
+- PP_ASSERT_WITH_CODE((j <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
+- "Invalid VramInfo table.", return -EINVAL);
+ break;
+
+ default:
+--
+2.7.4
+
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-05-01 03:16:41 +0000